WO1992015094A1 - Schaltung zum erzeugen eines binärsignals aus einem ternären signal - Google Patents
Schaltung zum erzeugen eines binärsignals aus einem ternären signal Download PDFInfo
- Publication number
- WO1992015094A1 WO1992015094A1 PCT/EP1992/000233 EP9200233W WO9215094A1 WO 1992015094 A1 WO1992015094 A1 WO 1992015094A1 EP 9200233 W EP9200233 W EP 9200233W WO 9215094 A1 WO9215094 A1 WO 9215094A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- comparators
- output
- circuit
- pulses
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/16—Conversion to or from representation by pulses the pulses having three levels
- H03M5/18—Conversion to or from representation by pulses the pulses having three levels two levels being symmetrical with respect to the third level, i.e. balanced bipolar ternary code
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
Definitions
- the invention is based on a circuit according to the preamble of claim 1.
- a three-state ternary signal is sampled from the tape.
- a binary signal with only two states is to be generated from this signal.
- Level evaluators are necessary for the evaluation in order to detect the low and high level of the signal.
- a Schmitt trigger is generally used as the level decider.
- Such circuits require automatic gain control (AGC) in order to maintain the optimal trigger points.
- AGC automatic gain control
- the automatic balancing of the trigger points in known circuits only takes place when the binary signal is free of DC voltage.
- the invention has for its object to provide a circuit for level decision, in which the maintenance of the optimal trigger points on the ternary signal requires neither an automatic gain control (AGC) nor the DC voltage freedom of the binary signal.
- AGC automatic gain control
- This object is achieved in that the signal is applied to oppositely polarized inputs of two comparators, that the same polarized inputs of the comparators are connected to a common bias voltage, that the difference between the two bias voltages is regulated by the mean value of the output voltages of the comparators is that the mean pulse width of the output voltages is approximately constant.
- the output pulses of the two comparators are preferably fed to the two inputs of an RS flip-flop.
- the output pulses of the two comparators are combined with a gate.
- the mean value of the output voltage of the gate is preferably fed as an input voltage to the same inputs of the two comparators as a bias voltage.
- the output pulses of the gate can be fed to a circuit for regenerating the bit clock.
- the pulse width can be changed by setting the preload difference.
- the bias voltage difference and thus the threshold value position are expediently carried out in such a way that the bit error rate is as low as possible.
- Fig. 1 is an overview circuit diagram for recovery
- Fig. 5 shows an inventive circuit
- Fig. 1 shows an arrangement for generating a binary signal from a signal obtained by scanning a binary recording track.
- Fig. 2 shows the associated waveforms.
- the magnetic track contains the bit pattern in binary form, ie in the form of oppositely magnetized areas N (north pole) and S (south pole).
- the playback voltage is induced in the playback head by the flow change between the areas N and S. This voltage represents approximately the differentiated bit pattern.
- the pulses generated by the magnetization changes between the north pole N and the south pole S become in the equalization circuit E narrowed and as far as possible freed from the influences of the neighboring pulses.
- the result is represented by signal A1.
- the signal A2 is obtained by integrating the signal A1.
- a simple zero crossing detector is used as the level decision PE, which is largely independent of the level.
- the binary signal B contains low-frequency spectral components and large runlength values, it is cheaper to evaluate the ternary signal A1 directly with the level decider.
- a Schmitt trigger can be used, which detects the positive and negative pulses alternately.
- Fig. 4 shows the operation of this Heidelbergun ⁇ .
- the circuit contains a comparator K with a binary output. By returning the output signal to one of the inputs, a hysteresis of the trigger point is generated and the threshold value is alternately placed in the level range of the positive and negative pulses.
- the potentiometer P the trigger points can be set so that the bit error rate is as low as possible.
- the disadvantage of this circuit compared to the zero crossing detector is the level dependency.
- an automatic gain control for the ternary signal A1 is required.
- the automatic balancing of the trigger points in the circuit according to FIG. 3 only takes place when the binary signal B is free of DC voltage.
- the ternary signal A1 is inherently DC-free.
- the signal A1 is fed to the circuit via the emitter follower 1.
- the circuit contains two comparators with 2, 3 with binary output.
- the direct inputs (+) of the two comparators 2, 3 receive the bias voltage Uo via the resistors 8, 9.
- the inverting (-) inputs receive the regulated bias voltage U1 via the resistors 10,11.
- the signal A1 is fed to the direct input of the comparator 2 via the capacitor 4 and the inverting input of the comparator 3 via the capacitor 5.
- the other two inputs of the comparators 2, 3 are connected to ground via the capacitors 6 and 7. As shown in FIG. 6, the negative pulses from A1 at the output of the comparator 2 generate the pulse voltage C1 and the positive pulses from A1 the pulse voltage C2 at the output of the comparator 2.
- the pulses C1 and C2 are combined to form the pulse voltage C.
- the mean value of the voltage C is a measure of the position of the threshold value at the inputs of the comparators 2, 3. Since the pulses of the ternary signal A1 have a relatively low slope, the pulses of the voltage C become wider the closer the threshold value is the center line of signal A1. Via the low-pass filter 13, the average value of the voltage C is fed to the amplifier 14, which supplies the bias voltage U1. When the pulses C become wider, the voltage U1 drops. This shifts the threshold value so that the pulses C become narrower again. The control thus ensures that a certain average pulse width of the pulses C is maintained. The greater the amplification of the amplifier 14, the more accurate the pulse width of C is.
- Compliance with the pulse width of C corresponds to compliance with a certain threshold value relative to the pulse height, and is therefore independent of the pulse amplitude.
- the optimum threshold value for example the minimum bit error rate, is set with the potentiometer 15.
- the position of the threshold value also depends on the frequency of the level transitions in the binary signal. However, this is constant by means of a fixed recording signal.
- the time constant of the control loop is chosen so that a sufficiently constant mean value is obtained.
- the original binary signal which corresponds to the magnetization pattern of the recording track or the recording current, is obtained in the circuit according to FIG. 5 in that the Pulse voltages C1 and C2 are supplied to the RS flip-flop formed by gates 16 and 11. 6, the signal B is generated at the output of the flip-flop. With the aid of this signal, the bit clock can be regenerated in a PLL circuit and the signal B can be prepared for further processing by sampling with the bit clock.
- Signal C which contains one pulse for each level transition of signal B, is also suitable for the regeneration of the bit clock.
- the circuit described only generates the signal for the regeneration of the bit clock.
- the bit clock is then used to sample the ternary signal A1 with the aid of an A / D converter.
- the binary signal can then be re-scanned with increased interference immunity by special processing of the sample values.
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Dc Digital Transmission (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Manipulation Of Pulses (AREA)
- Radar Systems Or Details Thereof (AREA)
- Selective Calling Equipment (AREA)
- Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50351592A JP3643589B2 (ja) | 1991-02-15 | 1992-02-04 | 3進信号から2進信号を生成する回路 |
EP92903583A EP0571411B1 (de) | 1991-02-15 | 1992-02-04 | Schaltung zum erzeugen eines binärsignals aus einem ternären signal |
DE59200627T DE59200627D1 (de) | 1991-02-15 | 1992-02-04 | Schaltung zum erzeugen eines binärsignals aus einem ternären signal. |
KR1019930702423A KR100285509B1 (ko) | 1991-02-15 | 1992-02-04 | 3진신호로부터 2진신호를 발생시키기 위한 회로 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DEP4104645.5 | 1991-02-15 | ||
DE4104645A DE4104645A1 (de) | 1991-02-15 | 1991-02-15 | Schaltung zum erzeugen eines binaersignals aus einem ternaeren signal |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1992015094A1 true WO1992015094A1 (de) | 1992-09-03 |
Family
ID=6425101
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP1992/000233 WO1992015094A1 (de) | 1991-02-15 | 1992-02-04 | Schaltung zum erzeugen eines binärsignals aus einem ternären signal |
Country Status (7)
Country | Link |
---|---|
EP (1) | EP0571411B1 (de) |
JP (1) | JP3643589B2 (de) |
KR (1) | KR100285509B1 (de) |
AT (1) | ATE112881T1 (de) |
DE (2) | DE4104645A1 (de) |
ES (1) | ES2064164T3 (de) |
WO (1) | WO1992015094A1 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4343252A1 (de) * | 1993-12-17 | 1995-06-22 | Thomson Brandt Gmbh | Schaltung zum Dekodieren von 2T-vorkodierten Binärsignalen |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3225946A1 (de) * | 1981-07-10 | 1983-02-03 | Victor Company Of Japan, Ltd., Yokohama, Kanagawa | Magnetische wiedergabeanordnung fuer ein digitales signal |
EP0084358A2 (de) * | 1982-01-18 | 1983-07-27 | Tandberg Data A/S | Verfahren und Schaltungsanordnung zum Bewerten von Lesesignalen eines Magnetschichtspeichers |
GB2217957A (en) * | 1988-04-27 | 1989-11-01 | Philips Electronic Associated | Circuit arrangement for producing a binary signal |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4346411A (en) * | 1981-02-17 | 1982-08-24 | International Business Machines Corporation | Amplitude sensitive three-level detector for derivative read back channel of magnetic storage device |
US4837642A (en) * | 1988-01-12 | 1989-06-06 | Ampex Corporation | Threshold tracking system |
DD269964A1 (de) * | 1988-02-29 | 1989-07-12 | Eaw Berlin Treptow Friedrich E | Anordnung zur decodierung eines 3-pegelcodes 3pc in einem 2-pegelcode mit taktrueckgewinnung |
-
1991
- 1991-02-15 DE DE4104645A patent/DE4104645A1/de not_active Withdrawn
-
1992
- 1992-02-04 KR KR1019930702423A patent/KR100285509B1/ko not_active IP Right Cessation
- 1992-02-04 WO PCT/EP1992/000233 patent/WO1992015094A1/de active IP Right Grant
- 1992-02-04 JP JP50351592A patent/JP3643589B2/ja not_active Expired - Fee Related
- 1992-02-04 ES ES92903583T patent/ES2064164T3/es not_active Expired - Lifetime
- 1992-02-04 EP EP92903583A patent/EP0571411B1/de not_active Expired - Lifetime
- 1992-02-04 AT AT92903583T patent/ATE112881T1/de active
- 1992-02-04 DE DE59200627T patent/DE59200627D1/de not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3225946A1 (de) * | 1981-07-10 | 1983-02-03 | Victor Company Of Japan, Ltd., Yokohama, Kanagawa | Magnetische wiedergabeanordnung fuer ein digitales signal |
EP0084358A2 (de) * | 1982-01-18 | 1983-07-27 | Tandberg Data A/S | Verfahren und Schaltungsanordnung zum Bewerten von Lesesignalen eines Magnetschichtspeichers |
GB2217957A (en) * | 1988-04-27 | 1989-11-01 | Philips Electronic Associated | Circuit arrangement for producing a binary signal |
Non-Patent Citations (2)
Title |
---|
IBM Technical Disclosure Bulletin, Band. 15, Nr. 12, Mai 1973 H. H. Ottesen et al: "ADAPTIVE DC RESTORATION ", * |
Patent Abstracts of Japan, Band 12, Nr 245, P729, Zusammenfassung von JP 63- 37867, publ 1988-02-18 * |
Also Published As
Publication number | Publication date |
---|---|
EP0571411B1 (de) | 1994-10-12 |
KR930703677A (ko) | 1993-11-30 |
KR100285509B1 (ko) | 2001-04-02 |
JPH06505111A (ja) | 1994-06-09 |
JP3643589B2 (ja) | 2005-04-27 |
ES2064164T3 (es) | 1995-01-16 |
DE59200627D1 (de) | 1994-11-17 |
EP0571411A1 (de) | 1993-12-01 |
ATE112881T1 (de) | 1994-10-15 |
DE4104645A1 (de) | 1992-08-20 |
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