WO1992005578A1 - Procede de fabrication de dispositifs a semi-conducteur - Google Patents
Procede de fabrication de dispositifs a semi-conducteur Download PDFInfo
- Publication number
- WO1992005578A1 WO1992005578A1 PCT/JP1991/001205 JP9101205W WO9205578A1 WO 1992005578 A1 WO1992005578 A1 WO 1992005578A1 JP 9101205 W JP9101205 W JP 9101205W WO 9205578 A1 WO9205578 A1 WO 9205578A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- wafer
- heat treatment
- initial
- bmd density
- warpage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P36/00—Gettering within semiconductor bodies
- H10P36/20—Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body
Definitions
- the present invention relates to a method for manufacturing a semiconductor device, comprising: an initial oxygen concentration (hereinafter referred to as an initial Oi) of X-ha, a warpage amount of an X-ha in a heat treatment process, and an internal defect density (hereinafter referred to as an internal defect density) And BMD density) to minimize the amount of warpage caused by heat treatment during the device manufacturing process, and to reduce the gettering ability.
- an initial Oi an initial oxygen concentration
- a warpage amount of an X-ha in a heat treatment process and an internal defect density (hereinafter referred to as an internal defect density) And BMD density)
- BMD density internal defect density
- IG Intrinsic gettering
- ⁇ X - c optimum BMD density C is required
- the initial 0i of CZ silicon single crystal silicon commonly used is 12 ⁇ 10 ′′ to 18 ⁇ 10 17 at oms Zcc, and to obtain an optimal BMD density, According to the initial 0i of each substrate wafer, a pre-heat treatment for generating oxygen precipitation nuclei is performed at 600 to 900 ° C.
- BMD density determined by the gettering ability can be generated inside the semiconductor device during the heat treatment in the semiconductor device manufacturing process. Due to the temperature gradient in the plane, thermal stress is generated, dislocations are generated and multiplied by internal defects, and the wafer is deformed, warped, and a series of defects. Will cause a gap. The portion where the slip occurs deteriorates the device characteristics. In addition, the warpage of the wafer also causes a pattern shift in a fine process such as mask alignment, and in any case, lowers the device yield.
- the present invention has been made to solve the above-described problems.
- a single-crystal silicon material to be used as a material is demanded from an element yield and a gettering ability.
- the warp limit value of the 1-ha after passing through the device manufacturing process and the BMD density are specified within a certain range, it is only possible to satisfy the certain range at the same time.
- the wafer having the initial Oi is simultaneously filled with a certain range between the upper limit and the lower limit of the initial Oi and the certain range of the BMD density. It is characterized in that pre-heat treatment is performed using the time that can be added.
- the BMD density in the wafer in the heat treatment in the device manufacturing process or the simulation heat treatment is determined. From this relationship, the warpage limit value (a) and the BMD density range (b) are further restricted by the device yield and gettering ability.
- a certain range (c) between the upper limit (X) and the lower limit (y) of the initial Oi and the BMD density range (b) Is the heat treatment time that intersects the region that simultaneously satisfies and, and the initial O within the range of the upper limit (X) and the lower limit (y)
- the silicon wafer having i is pre-heat treated.
- pre-heat treatment refers to a heat treatment before a device manufacturing process (including a simulation heat treatment).
- Figure 1 shows the relationship between the BMD density in a wafer and the amount of warpage in the wafer.
- Figure 2 shows the relationship between the BMD density in the wafer and the amount of warpage in the wafer at each initial 0i.
- Fig. 3 shows the relationship between the BMD density and the amount of precipitated oxygen in each area of Oi.
- Fig. 4 shows a simulation heat treatment
- Fig. 5 shows the relationship between the initial Oi in B and the BMD density for each pre-heat treatment time.
- FIG. 6 is a diagram showing the relationship between the amount of wafer warpage and the amount of precipitated oxygen.
- the present inventor has investigated this relationship in more detail, and found that even if the BMD density is the same, the wafer after the simulation heat treatment depends on the difference of the initial 0i in the wafer. of It has been found that there is a difference in the amount of warpage. This is shown in Figure 2.
- Fig. 3 shows the amount of precipitated oxygen on the horizontal axis. That is, even with the same BMD density or the same amount of precipitated oxygen, the lower the initial 0 i in the wafer, the smaller the warpage of the wafer after the simulation heat treatment.
- the simulation heat treatment means the heat treatment step shown in FIG. This heat treatment has been most commonly used in the industry as a simulation maturation process for simulating the element manufacturing process.
- the initial Oi in the wafer the lower the initial Oi in the wafer, the lower the warpage of the wafer after the simulation heat treatment. Therefore, in order to minimize the warpage, it is only necessary to select a wafer with the lowest initial O i and use it for production. In practice, however, if the initial O i is too low, the pre-heat treatment time must be extremely long before the simulation heat treatment. Because there is a lower limit. On the other hand, for the initial Oi that is too long, even if the BMD density can be secured by a short-time heat treatment, the wafer warp increases and the wafer itself becomes brittle. Get up, and this also has a reasonable upper limit.
- the amount of warpage and the BMD density in the simulation heat treatment or the heat treatment in the process are determined based on the element yield.
- Tali If requested by the Wing capability and specified in a certain desired range, the range of the initial Oi that satisfies this range is limited.
- the range of the initial oxygen concentration is generally 1 ⁇ 10 17 to 20 ⁇ 10 17 atoms / cc.
- the range of the initial Oi defined in the first stage and the desired BMD density range are calculated. If the pre-heat treatment time for satisfying the conditions is obtained at the same time, the obtained processing time becomes the pre-ripening treatment condition for securing the desired BMD density and keeping the warpage 10 within the desired range. .
- the feature of the present invention is that the wafer selected in the first step and in the initial Oi range is subjected to the pre-heat treatment for the time determined in the second step.
- the initial Oi is plotted on the horizontal axis
- the BMD density is plotted on the vertical axis
- the relationship is graphed for each pre-heat treatment time at 650 ° C.
- Li co down ⁇ E is subjected to the production of DRAM if example bets were, - BMD density range in Ha, generally in 1's 10 6 to 2 Figure 10 6 Ke cm.
- the BMD density range is, for example, 1 ⁇ 10 S to 2 ⁇ 10 S Keno ⁇ , and the amount of warpage is as follows. If less than 50 is required, the range between the vertical and horizontal axes in the figure (the shaded area in Fig. 2) can satisfy the initial Oi of 17 X 10 17 atoms / cc or less. It is clear that it is limited to the noise. It can also be seen that at least an initial Oi of 10 ⁇ 10 17 atoms / cc or more is required.
- the initial Oi is less than 17 X 10 17 atoms / cc of this, more than 10 X 10 17 atoms / cc, were example, chose ⁇ E one Nono of 15.5 X 10 17 atoms / cc and the filtrate come when crossing the shaded minute, when viewed in the horizontal axis, to become a less anti Ri of 50 Lord, as the BMD density range, before Symbol 1's 10 6 to 2 10 6 Ke 011 2 of U Chi, especially 1 XI (! 6 ⁇ 1.3 X 10 6 this to be limited to the Keno crf and GaAkira et al. or to become r Next, referring to FIG.
- Initial 0i is less than 16 ⁇ 10 17 atoms / cc and 12 ⁇ 10 17 atoms / cc or more CZ silicon wafer (diameter 5 ”, crystal axis 100>
- the average number of non-defective devices was 187 and the yield was over 90%.
- the warpage of ⁇ 1 -c is all 50 or less, and the BMD density is in the range of 1 ⁇ 10 s to 2 ⁇ 10 s / cm 2 : That is, in FIG. 2, the relationship fell within the range of the hatched area.
- Initial 0i is, 16 X 10 17 atoms / cc or less, 12 X 10 of 17 atoms / cc or more, a diameter of 05 ", the crystal axis rather 100>, conductivity type P-type, resistivity of 2 ⁇ 6 ⁇ 'of cm, CZ Shi Silicone mirror surface
- a pre-ripening treatment is performed as appropriate so that only the BMD density falls within the range of 1 ⁇ 10 s to 2 ⁇ 10 B cm 2 , and the DRAM elements are formed. The yield was observed for the Z elements.
- the number of non-defective devices was 132 on an average of 25 devices, and the yield was 64%.
- the BMD density was in the range of 1 ⁇ 10 6 to 2 ⁇ 10 s Z cm 2 , but the warpage of the wafer was nearly 50% or more.
- Initial 0i is CZ silicon mirror of 17 x 10 17 atoms / cc or more, diameter 93 ⁇ 45 ", crystal axis ⁇ 100>, conductivity type P, resistivity 2-6 ⁇ .cm.
- an appropriate pre-heat treatment is performed so that only the BMD density falls within the range of 1 ⁇ 10 s to 2 ⁇ 10 s keno cm 2 , and a DRAM element is formed. The yield was observed for 206 elements / piece-,
- the average number of non-defective devices was 25, and the yield was 10%.
- the BMD density was in the range of 1 ⁇ 10 E to 2 ⁇ 10 6 Z cm 2 , but almost all of the wafer warpages were 50 or more.
- FIG. 2 used in the examples shows the relationship between the wafer BMD density and the amount of warpage in the C-M0S simulation, assuming a DRAM.
- Certain BM D required by gettering ability In order to secure the density, it is possible to select as appropriate according to the combination of the initial 0i in the I: -C and the pre-heat treatment conditions.
- the combination of the above-mentioned conditions to minimize the amount and secure the BMD density necessary for achieving the desired gettering ability is determined in a short time without trial and error. , Can be selected efficiently.
- ⁇ : —ha is selected using the initial Oi in the wafer correlated to the occurrence of warpage as an index, and finally the pre-heat treatment time for element manufacturing is determined.
- the yield is improved and the productivity is improved compared to the conventional method.
- the pre-heat treatment time is determined while keeping the pre-heat treatment temperature constant. However, even if the pre-heat treatment temperature changes, the optimum operation time can be determined according to the same operation.
- the present invention is also applicable to a method in which a high-temperature (usually 110 ° C. or higher) heat treatment for outward diffusion of oxygen is added before the pre-heat treatment for forming the oxygen precipitate. It can be applied, and the optimum preheat treatment conditions can be set without trial and error. As shown in Fig. 6, before the pre-heat treatment for oxygen precipitation nucleation, Regardless of whether or not a high-temperature heat treatment step is performed, if the same initial 0i is used, there is no difference in the relationship between the amount of warpage and the amount of precipitated oxygen. This is because it was confirmed during the race.
- the present invention is applied to a semiconductor device.
Landscapes
- Crystals, And After-Treatments Of Crystals (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP91915960A EP0552366B1 (en) | 1990-09-14 | 1991-09-11 | Semiconductor device manufacturing process |
| DE69125498T DE69125498T2 (de) | 1990-09-14 | 1991-09-11 | Halbleiterverrichtungsherstellungsverfahren |
| US08/030,251 US5506154A (en) | 1990-09-14 | 1991-09-11 | Process for preheat treatment of semiconductor wafers |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2/242558 | 1990-09-14 | ||
| JP2242558A JP3011982B2 (ja) | 1990-09-14 | 1990-09-14 | 半導体装置の製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1992005578A1 true WO1992005578A1 (fr) | 1992-04-02 |
Family
ID=17090883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP1991/001205 Ceased WO1992005578A1 (fr) | 1990-09-14 | 1991-09-11 | Procede de fabrication de dispositifs a semi-conducteur |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5506154A (enExample) |
| EP (1) | EP0552366B1 (enExample) |
| JP (1) | JP3011982B2 (enExample) |
| DE (1) | DE69125498T2 (enExample) |
| WO (1) | WO1992005578A1 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002009081A (ja) * | 2000-06-26 | 2002-01-11 | Toshiba Corp | 半導体装置及びその製造方法 |
| JP4667030B2 (ja) * | 2004-12-10 | 2011-04-06 | キヤノン株式会社 | 固体撮像装置用の半導体基板とその製造方法 |
| JP2007287860A (ja) * | 2006-04-14 | 2007-11-01 | Toshiba Corp | 半導体装置の製造方法 |
| US8494817B1 (en) * | 2006-11-30 | 2013-07-23 | Pdf Solutions, Inc. | Methods for yield variability benchmarking, assessment, quantification, and localization |
| JP5934218B2 (ja) | 2010-09-03 | 2016-06-15 | ジーテイーエイテイー・アイピー・ホールデイング・エルエルシーGTAT IP Holding LLC | ガリウム、インジウムまたはアルミニウムでドープされたケイ素の単結晶 |
| JP2015008314A (ja) * | 2014-08-14 | 2015-01-15 | 株式会社Sumco | エピタキシャルウェーハの製造方法及びエピタキシャルウェーハ |
| DE102018203945B4 (de) | 2018-03-15 | 2023-08-10 | Siltronic Ag | Verfahren zur Herstellung von Halbleiterscheiben |
| CN114717643A (zh) * | 2022-03-02 | 2022-07-08 | 扬州方通电子材料科技有限公司 | 一种超大尺寸半导体单晶硅棒生长方法及单晶硅棒 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS618930A (ja) * | 1984-06-20 | 1986-01-16 | インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン | 半導体ウエーハの標準化処理方法 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5617011A (en) * | 1979-07-23 | 1981-02-18 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS5680139A (en) * | 1979-12-05 | 1981-07-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Manufacture of semiconductor device |
| JPS57197827A (en) * | 1981-05-29 | 1982-12-04 | Hitachi Ltd | Semiconductor substrate |
| JPS58159334A (ja) * | 1982-03-17 | 1983-09-21 | Toshiba Corp | 半導体ウエハの処理方法 |
| JPS59127232A (ja) * | 1983-01-11 | 1984-07-23 | Seiko Epson Corp | 磁気記録媒体 |
| JPS60249336A (ja) * | 1984-05-24 | 1985-12-10 | Komatsu Denshi Kinzoku Kk | 半導体シリコン基板の処理方法 |
| EP0165364B1 (fr) * | 1984-06-20 | 1988-09-07 | International Business Machines Corporation | Procédé de standardisation et de stabilisation de tranches semiconductrices |
| JPS6276714A (ja) * | 1985-09-30 | 1987-04-08 | Mitsubishi Metal Corp | シリコンウエハ |
| US4868133A (en) * | 1988-02-11 | 1989-09-19 | Dns Electronic Materials, Inc. | Semiconductor wafer fabrication with improved control of internal gettering sites using RTA |
| US4851358A (en) * | 1988-02-11 | 1989-07-25 | Dns Electronic Materials, Inc. | Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing |
| JPH01208830A (ja) * | 1988-02-17 | 1989-08-22 | Fujitsu Ltd | シリコン・ウェハ |
| JPH0750713B2 (ja) * | 1990-09-21 | 1995-05-31 | コマツ電子金属株式会社 | 半導体ウェーハの熱処理方法 |
| JP3232168B2 (ja) * | 1993-07-02 | 2001-11-26 | 三菱電機株式会社 | 半導体基板およびその製造方法ならびにその半導体基板を用いた半導体装置 |
-
1990
- 1990-09-14 JP JP2242558A patent/JP3011982B2/ja not_active Expired - Lifetime
-
1991
- 1991-09-11 US US08/030,251 patent/US5506154A/en not_active Expired - Lifetime
- 1991-09-11 EP EP91915960A patent/EP0552366B1/en not_active Expired - Lifetime
- 1991-09-11 WO PCT/JP1991/001205 patent/WO1992005578A1/ja not_active Ceased
- 1991-09-11 DE DE69125498T patent/DE69125498T2/de not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS618930A (ja) * | 1984-06-20 | 1986-01-16 | インタ−ナシヨナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン | 半導体ウエーハの標準化処理方法 |
Non-Patent Citations (3)
| Title |
|---|
| Applied Physics, Vol. 49, No. 1, 1980, pages 90-96. * |
| Proceedings of the 12th Conference on Solid State Devices, Tokyo, 1980; Japanese Journal of Applied Physics, Vol. 20, 1981, Supplement 20-1, pages 25-30. * |
| See also references of EP0552366A4 * |
Also Published As
| Publication number | Publication date |
|---|---|
| DE69125498D1 (de) | 1997-05-07 |
| EP0552366A1 (en) | 1993-07-28 |
| EP0552366A4 (enExample) | 1994-02-16 |
| JP3011982B2 (ja) | 2000-02-21 |
| US5506154A (en) | 1996-04-09 |
| DE69125498T2 (de) | 1997-07-17 |
| EP0552366B1 (en) | 1997-04-02 |
| JPH04123435A (ja) | 1992-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6478883B1 (en) | Silicon single crystal wafer, epitaxial silicon wafer, and methods for producing them | |
| US6162708A (en) | Method for producing an epitaxial silicon single crystal wafer and the epitaxial silicon single crystal wafer | |
| JPS6124240A (ja) | 半導体基板 | |
| JP2000044389A (ja) | エピタキシャルシリコン単結晶ウエ―ハの製造方法及びエピタキシャルシリコン単結晶ウエ―ハ | |
| JP3381816B2 (ja) | 半導体基板の製造方法 | |
| WO1992005578A1 (fr) | Procede de fabrication de dispositifs a semi-conducteur | |
| US5385115A (en) | Semiconductor wafer heat treatment method | |
| JPH11314997A (ja) | 半導体シリコン単結晶ウェーハの製造方法 | |
| JPH04163920A (ja) | Si基板の製造方法 | |
| KR20000006046A (ko) | 실리콘에피택셜웨이퍼의제조방법 | |
| JP3022044B2 (ja) | シリコンウエハの製造方法およびシリコンウエハ | |
| JP3080501B2 (ja) | シリコンウェーハの製造方法 | |
| JP3412531B2 (ja) | リンドープシリコン単結晶ウエーハ及びエピタキシャルシリコンウエーハ及びこれらの製造方法 | |
| JPS63198334A (ja) | 半導体シリコンウエ−ハの製造方法 | |
| JPH04298042A (ja) | 半導体の熱処理方法 | |
| JP3294723B2 (ja) | シリコンウェーハの製造方法およびシリコンウェーハ | |
| WO2006022127A1 (ja) | シリコンエピタキシャルウェーハの製造方法 | |
| JPH0119265B2 (enExample) | ||
| JPH09223699A (ja) | シリコンウェーハとその製造方法 | |
| JPS58138034A (ja) | 半導体装置の製造方法 | |
| JPH0324058B2 (enExample) | ||
| TWI901958B (zh) | 矽晶圓及其製造方法 | |
| JP3220961B2 (ja) | エピタキシャル半導体ウエーハの製造方法 | |
| JPS63182815A (ja) | エピタキシアルウエ−ハの製造方法 | |
| JPH0897220A (ja) | シリコンエピタキシャルウェーハの製造方法及びシリコンエピタキシャルウェーハ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A1 Designated state(s): US |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): DE FR GB IT NL |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 1991915960 Country of ref document: EP |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 08030251 Country of ref document: US |
|
| WWP | Wipo information: published in national office |
Ref document number: 1991915960 Country of ref document: EP |
|
| WWG | Wipo information: grant in national office |
Ref document number: 1991915960 Country of ref document: EP |