WO1989005488A3 - Systeme de memoire - Google Patents

Systeme de memoire Download PDF

Info

Publication number
WO1989005488A3
WO1989005488A3 PCT/US1988/004095 US8804095W WO8905488A3 WO 1989005488 A3 WO1989005488 A3 WO 1989005488A3 US 8804095 W US8804095 W US 8804095W WO 8905488 A3 WO8905488 A3 WO 8905488A3
Authority
WO
WIPO (PCT)
Prior art keywords
address
memory banks
memory
transceiver
memory system
Prior art date
Application number
PCT/US1988/004095
Other languages
English (en)
Other versions
WO1989005488A2 (fr
Inventor
Richard G Pechter
Ronald Selkovitch
Quoanh W Tsy
William C Woolf
Original Assignee
Ncr Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ncr Co filed Critical Ncr Co
Priority to DE3887324T priority Critical patent/DE3887324T2/de
Publication of WO1989005488A2 publication Critical patent/WO1989005488A2/fr
Publication of WO1989005488A3 publication Critical patent/WO1989005488A3/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Abstract

L'invention concerne un système de mémoire comprenant des premier et second blocs de mémoire (2, 3) dans lesquels des adresses consécutives sont stockées alternativement. Les blocs de mémoire d'adresses sont adressés sélectivement en utilisant des segments impairs et pairs de l'adresse générée dans un compteur d'adresses. Des données de sortie provenant de chacun des blocs de mémoire d'adresses (2, 3) sont stockées dans un registre émetteur/récepteur respectif (12, 14). En fonctionnement, l'un des registres émetteurs/récepteurs (12, 14) transmet des données reçues pendant un cycle d'adresse de mémoire préalable à un bus processeur (11), tandis que l'autre registre émetteur/récepteur (12, 14) mémorise des donnés représentatives d'une adresse suivante anticipée.
PCT/US1988/004095 1987-12-11 1988-11-18 Systeme de memoire WO1989005488A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE3887324T DE3887324T2 (de) 1987-12-11 1988-11-18 Speicheranordnung.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/131,602 US4918587A (en) 1987-12-11 1987-12-11 Prefetch circuit for a computer memory subject to consecutive addressing
US131,602 1987-12-11

Publications (2)

Publication Number Publication Date
WO1989005488A2 WO1989005488A2 (fr) 1989-06-15
WO1989005488A3 true WO1989005488A3 (fr) 1989-06-29

Family

ID=22450170

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/004095 WO1989005488A2 (fr) 1987-12-11 1988-11-18 Systeme de memoire

Country Status (5)

Country Link
US (1) US4918587A (fr)
EP (1) EP0345325B1 (fr)
JP (1) JP2835757B2 (fr)
DE (1) DE3887324T2 (fr)
WO (1) WO1989005488A2 (fr)

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JP2752076B2 (ja) * 1988-02-23 1998-05-18 株式会社東芝 プログラマブル・コントローラ
US5146578A (en) * 1989-05-01 1992-09-08 Zenith Data Systems Corporation Method of varying the amount of data prefetched to a cache memory in dependence on the history of data requests
DE69123987T2 (de) * 1990-01-31 1997-04-30 Hewlett Packard Co Stossbetrieb für Mikroprozessor mit externem Systemspeicher
EP0440457A3 (en) * 1990-01-31 1992-01-02 Hewlett-Packard Company Burst mode read implementation
JPH03248243A (ja) * 1990-02-26 1991-11-06 Nec Corp 情報処理装置
US5210838A (en) * 1990-05-15 1993-05-11 Sun Microsystems, Inc. Method and apparatus for predicting the effective addresses of future memory load operations in a microprocessor
JPH04293135A (ja) * 1991-03-20 1992-10-16 Yokogawa Hewlett Packard Ltd メモリアクセス方式
US5592348A (en) * 1991-05-17 1997-01-07 Adaptec, Inc. Method and structure for locating and skipping over servo bursts on a magnetic disk
US5289584A (en) * 1991-06-21 1994-02-22 Compaq Computer Corp. Memory system with FIFO data input
US5485589A (en) * 1991-12-31 1996-01-16 Dell Usa, L.P. Predictive addressing architecture
US5659713A (en) * 1992-04-24 1997-08-19 Digital Equipment Corporation Memory stream buffer with variable-size prefetch depending on memory interleaving configuration
US5361391A (en) * 1992-06-22 1994-11-01 Sun Microsystems, Inc. Intelligent cache memory and prefetch method based on CPU data fetching characteristics
JPH0659972A (ja) * 1992-08-05 1994-03-04 Oki Electric Ind Co Ltd メモリ制御装置
KR940009733B1 (ko) * 1992-09-21 1994-10-17 삼성전자 주식회사 디지탈 신호 처리장치
US5566324A (en) * 1992-12-24 1996-10-15 Ncr Corporation Computer apparatus including a main memory prefetch cache and method of operation thereof
EP0691006B1 (fr) * 1993-03-23 1998-01-07 Apple Computer, Inc. Dispositif et procede pour format de fichier readressable
FR2720530B1 (fr) * 1994-05-27 1996-08-23 Sextant Avionique Dispositif pour l'optimisation des performances d'un processeur.
US5696917A (en) * 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
KR0159435B1 (ko) * 1995-12-30 1998-12-15 김광호 디스크 콘트롤러의 프로그래머블 콘트롤 시퀀서와 그의 맵 할당방법
KR0176637B1 (ko) * 1995-12-30 1999-04-15 김광호 디스크 콘트롤러의 프로그래머블 콘트롤 시퀀서와 그의 맵 할당방법
US5761713A (en) * 1996-03-01 1998-06-02 Hewlett-Packard Co. Address aggregation system and method for increasing throughput to a multi-banked data cache from a processor by concurrently forwarding an address to each bank
US5724613A (en) * 1996-05-06 1998-03-03 Vlsi Technology, Inc. System and method for automatically enabling and disabling a prefetching capability
US5958040A (en) * 1997-05-28 1999-09-28 Digital Equipment Corporation Adaptive stream buffers
US5938763A (en) * 1997-08-06 1999-08-17 Zenith Electronics Corporation System for transposing data from column order to row order
US6430680B1 (en) * 1998-03-31 2002-08-06 International Business Machines Corporation Processor and method of prefetching data based upon a detected stride
US6754779B1 (en) * 1999-08-23 2004-06-22 Advanced Micro Devices SDRAM read prefetch from multiple master devices
US6470427B1 (en) 1999-11-09 2002-10-22 International Business Machines Corporation Programmable agent and method for managing prefetch queues
US6718454B1 (en) * 2000-04-29 2004-04-06 Hewlett-Packard Development Company, L.P. Systems and methods for prefetch operations to reduce latency associated with memory access
DE60316197T2 (de) * 2002-04-04 2008-04-10 Infineon Technologies Ag Verfahren und System zum Teilen eines Speichermoduls
US7941794B2 (en) * 2004-08-30 2011-05-10 Sanyo Electric Co., Ltd. Data flow graph processing method and processing apparatus provided with reconfigurable circuit
US7617338B2 (en) * 2005-02-03 2009-11-10 International Business Machines Corporation Memory with combined line and word access
US7469259B2 (en) * 2006-08-10 2008-12-23 Kabushiki Kaisha Toshiba System and method for employing an extended boundary lookup table
US8627022B2 (en) * 2008-01-21 2014-01-07 Freescale Semiconductor, Inc. Contention free parallel access system and a method for contention free parallel access to a group of memory banks
TWI762852B (zh) * 2020-01-03 2022-05-01 瑞昱半導體股份有限公司 記憶體裝置及其操作方法
CN113110878A (zh) * 2020-01-09 2021-07-13 瑞昱半导体股份有限公司 存储器装置及其操作方法
US11733898B2 (en) 2021-04-26 2023-08-22 Microsoft Technology Licensing, Llc Memory array for storing odd and even data bits of data words in alternate sub-banks to reduce multi-bit error rate and related methods

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3931613A (en) * 1974-09-25 1976-01-06 Data General Corporation Data processing system
EP0165822A2 (fr) * 1984-06-21 1985-12-27 Fujitsu Limited Système de commande d'accès en mémoire
US4583162A (en) * 1983-01-13 1986-04-15 The Singer Company Look ahead memory interface
US4621320A (en) * 1983-10-24 1986-11-04 Sperry Corporation Multi-user read-ahead memory

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US4424561A (en) * 1980-12-31 1984-01-03 Honeywell Information Systems Inc. Odd/even bank structure for a cache memory
DE3245939C2 (de) * 1982-12-11 1985-12-19 Fa. Carl Zeiss, 7920 Heidenheim Vorrichtung zur Erzeugung eines Bildes des Augenhintergrundes
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JPS60148537A (ja) * 1984-01-12 1985-08-05 興和株式会社 レ−ザ−光を利用した眼科測定装置
JPS60165822A (ja) * 1984-02-09 1985-08-29 Nec Corp 電子式可変抵抗器
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Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3931613A (en) * 1974-09-25 1976-01-06 Data General Corporation Data processing system
US4583162A (en) * 1983-01-13 1986-04-15 The Singer Company Look ahead memory interface
US4621320A (en) * 1983-10-24 1986-11-04 Sperry Corporation Multi-user read-ahead memory
EP0165822A2 (fr) * 1984-06-21 1985-12-27 Fujitsu Limited Système de commande d'accès en mémoire

Non-Patent Citations (1)

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Title
IBM Technical Disclosure Bulletin, volume 26, no. 7B, December 1983, (New York, US), B.D. Herrman et al.: "Installing an instruction-buffer on a processor memory interface", pages 3941-3944 *

Also Published As

Publication number Publication date
EP0345325A1 (fr) 1989-12-13
DE3887324T2 (de) 1994-09-08
JP2835757B2 (ja) 1998-12-14
WO1989005488A2 (fr) 1989-06-15
DE3887324D1 (de) 1994-03-03
US4918587A (en) 1990-04-17
EP0345325B1 (fr) 1994-01-19
JPH02502495A (ja) 1990-08-09

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