WO1982003948A1 - Metallisation composite de faible resistivite pour des dispositifs semiconducteurs et procede - Google Patents

Metallisation composite de faible resistivite pour des dispositifs semiconducteurs et procede Download PDF

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Publication number
WO1982003948A1
WO1982003948A1 PCT/US1982/000472 US8200472W WO8203948A1 WO 1982003948 A1 WO1982003948 A1 WO 1982003948A1 US 8200472 W US8200472 W US 8200472W WO 8203948 A1 WO8203948 A1 WO 8203948A1
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layer
intermetallic
hole portion
composite
lift
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PCT/US1982/000472
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English (en)
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Inc Motorola
Carlton H Aspin
Wei Jen Lo
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Inc Motorola
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Application filed by Inc Motorola filed Critical Inc Motorola
Priority to DE8282901672T priority Critical patent/DE3268922D1/de
Publication of WO1982003948A1 publication Critical patent/WO1982003948A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention relates to metallization systems for semiconductor devices and, more particularly, to the structure, composition and formation of a composite metallization having low resistivity, good thermal and chemical stability, and protective properties for use with devices and integrated circuits, especially very large scale integrated circuits.
  • a device refers to single devices or multiple devices commonly referred to as inte ⁇ grated circuits.
  • a device may have two or more terminals and consist of semiconductor regions, dielectric regions and/or metal regions.
  • interconnect and contact metallization resistance has now become a significant factor in limiting device and circuit performance in scaled structures.
  • Series "metallization" resistance is particularly a concern where polycrystall ine semiconductor materials are employed for device electrodes and device interconnects, as in very large scale integrated (VLSI) and ultra-high frequency (UHF) structures employing metal-oxide-semiconductor (MOS) devices.
  • VLSI very large scale integrated
  • UHF ultra-high frequency
  • MOS metal-oxide-semiconductor
  • "metallization” refers to the conductive materials employed for contacting or interconnecting semiconductor devices or other circuit elements whether formed from metals, semi- conductors, Inter etallic compounds or combinations or composites thereof.
  • poly refers to polycrystal line materials, typically polycrystalline semiconductors.
  • poly-silicon denotes polycrystalline silicon.
  • intermetallic refers to conductive compounds which have resis ⁇ tivity substantially intermediate between metals and semiconductors and which are formed of one or more substantially metallic elements plus another element.
  • compounds such as metal borides, carbides, nitrides and suicides provide numerous intermetallics. Doped polycrystalline silicon is much used for metallization purposes despite its relatively high resistivity (typically 1000 ⁇ ohm-cm) because of its many other favorable and convenient properties.
  • intermetallic metal suicide such as titanium-sil icide
  • the substances which etch the suicide also etch oxide layers or poly-silicon layers present on the device, making it extremely difficult to achieve uniform delinea ⁇ tion of fine geometries across large wafer areas without damage to other material regions.
  • the suicide layers are in tension so that during subsequent thermal cycles a ridge or "beak" forms at the .edge of the suicide region which is difficult to bridge. This leads to open circuits or short circuits in superposed dielectric and metal layers.
  • most suicides react on exposure to hot oxidizing atmospheres encountered in subsequent device processing and form higher resistivity or insulating layers which can negate the purpose to reduce series and contact resistance.
  • a composite metallization structure comprising an optional but desirable base layer compatible with the underlying device surface, a first superposed conductive intermetallic layer, plus a second superposed conductive and protective intermetallic (cap) layer different from said first layer which facilitates contact to the first layer, inhibits oxidation, provides etch protection, and controls tensile strain.
  • ⁇ 0n silicon semiconductors, poly-silicon is a preferred base layer, titanium suicide a preferred first intermetallic layer and titanium nitride a preferred second intermetallic layer.
  • the present invention further includes a method for fabricating the desired structure by an improved lift-off technique wherein the desired layers are non-uniform in thickness, being thinner where lift-off separation is to occur.
  • FIG. 1 shows a simplified, idealized cross-section of a portion of an MOS integrated circuit.
  • FIG. 2A-C shows a simplified cross-section of the gate region of a single MOS device using a polycrystalline silicon base layer/sil icide composite metallization of the prior art.
  • FIG. 3A-C shows a simplified cross-section of the gate region of a single MOS device using an intermetallic composite metallization of the present invention.
  • FIG. 4A-H shows a simplified cross-section of a single MOS gate composite metallization during several formation steps of the present invention.
  • FIG. 5A-B shows a schematic representation of the deposition geometry for producing non-uniform deposits in resist openings on a semiconductor wafer to facilitate lift-off.
  • FIG. 1 shows an idealized cross-section of portion 10 of an MOS integrated circuit comprising silicon substrate 11 having diffused regions 12, thin (gate) oxide region 13 and field oxide region 14.
  • Composite first metallization layer 15a-c comprises gate region 15a, contact region 15b, and interconnect region 15c.
  • Dielectric region 16 covers first metallization 15a-c and isolates second metallization layer 17 except at through-holes 18 and 21.
  • Passivation dielectric layer 19 seals and protects the overall structure. External connections (not shown) are made to contact pads in layer 17 exposed through holes 20 in passivation layer 19.
  • the composite metallization of the present invention is useful for any or all of metalliza ⁇ tions 15a, 15b, 15c and 17.
  • FIG. 2A-C shows a simplified cross-section of the gate region of a single silicon MOS transistor having a composite poly-silicon plus suicide metallization of the prior art, during various stages of processing.
  • silicon substrate 30 has thereon thin gate oxide layer 31, uniform poly-silicon layer 32, and uniform intermetallic suicide layer 33 which is to be etched by any convenient means to form suicide gate region 34.
  • Poly-silicon base layer 32 provides a well characterized and well controlled interface 39 to thin gate oxide layer 31. Additionally, layer 32 should have sufficient thickness to prevent diffusion of material from inter- metallic suicide layer 34 to interface 39 with the oxide. Typical prior art thickness values for layer 32 are in the range 100-200 n . In FIG.
  • silicide layer 33 and poly-base layer 32 have been preferentially etched so as to form silicide gate region 34 and poly-silicon gate region 35.
  • Under-cut region 36 occurs because poly 32 etches more rapidly than the silicide 33.
  • Use of anisotropic etch techniques such as ion-milling are not practical because they do not stop automatically on reaching oxide layer 31, which is thin (e.g. 30-120 nm) and easily damaged.
  • doped source-drain regions 38 have been formed, typically by ion implantation.
  • the residual tensile stress present in silicide region 34 produces strain in the form of ridges or "beaks" 37.
  • the combination of undercut 36 and beaks 37 are difficult to bridge, so that when dielectric layer 16 and metallization 17 of FIG. 1 are applied, short circuits or discontinuities occur causing device malfunction.
  • FIGURES 3A-C illustrate a preferred embodiment of an improved device structure in accordance with the present invention which avoids the difficulties of the prior art device of FIG. 2.
  • silicon substrate 30 has thereon thin gate oxide layer 31, and optionally, substan ⁇ tially uniform polysilicon base layer 42a to control properties of interface 39 against oxide layer 31.
  • First poly-base layer 42a may be as thin as a few atom layers since it need not act as a diffusion barrier to inter ⁇ metallic 44. This function is accomplished by thicker second polysilicon base layer 42b which is substantially homogeneous with layer 42a. It will be apparent to those of skill in the art that, while the formation (FIG.
  • PoTy base layer 42 has thereon first intermetallic silicide layer 44 chosen for its low conductivity and compatibility to underlying semiconductor or dielectric layers, and second intermetallic protective cap 49 chosen for its conductivity and protective properties, e.g., resistance to etching and oxidation, and ability to control tensile strain.
  • first intermetallic silicide layer 44 chosen for its low conductivity and compatibility to underlying semiconductor or dielectric layers
  • second intermetallic protective cap 49 chosen for its conductivity and protective properties, e.g., resistance to etching and oxidation, and ability to control tensile strain.
  • “protective” refers to the ability of the second intermetallic layer to protect underlying films against oxidizing a bients and etching ambients encountered during subsequent processing of the device or semiconductor wafer being treated by inhibiting these oxidizing or etching reactions, and the ability to control strain to avoid formation of "beaks" and other stress induced surface asperities, whether these effects occur singly or in combination.
  • Titanium silicide is the preferred choice of material for conductive intermetallic layer 44.
  • inter ⁇ metallic suicides of Zr, Hf, V, Nb, Ta, Cr, Mo, W, Fe, Co, Ni , Pt, and Pd are also useful.
  • Ti , Ta, Mo, and W form suicides having resistivity less than doped poly-
  • Titanium nitride is the preferred choice of material for conductive and protective intermetallic layer 49, although other materials such as tantalum nitride or zirconium nitride can also serve. Titanium nitride has the advantages of being reasonably conductive (approximately 22 yohm-cm) and not readily attacked by buffered HF, HC1 , H2O2-H2SO4, or halogen bearing liquids or gases. It is also stable with respect to the preferred titanium-silicide up to 1200°C in an oxidizing atmosphere and not degraded by an oxidizing ambient up to 1200°C. Further it is able to provide a diffusion barrier between first intermetallic layer 44 and any subsequent metallization which may be superposed, as for example, aluminum metal as layer 17 of FIG. 1.
  • FIG. 3B shows the structure following removal of uniform first poly-base layer 42a.
  • Any convenient etching method may be used, such as wet chemical etching, plasma etching, sputtering, ion-milling, or reactive ion etching. It is desirable to choose a preferential etch such as a chlorine compound which attacks the poly-silicon more rapidly than nitride cap 49 or oxide layer 31. Suitable etchant means are well known in the art.
  • Undercut 46 is minimized (FIG. 2B) by keeping layer 42a thin, or avoided (FIG. 2C) by omitting layer 42a.
  • FIG. 3C illustrates the structure obtained by forming base layer 42 in a single step, omitting uniform first poly-base layer 42a. This substantially eliminates undercutting since cap 49 covers sides 51-52 of first intermetallic 44 and poly-base layer 42. It will be apparent to those of skill in the art that other layers can be added to the structure of FIGS. 3B-C to provide a completed device, as in FIG. 1.
  • FIG. 2 The prior art structure of FIG. 2 has not proven practical for reducing contact and interconnection resis- tance on semiconductor devices because it has not been possible to find a single intermetallic (e.g. silicide) or poly-base layer plus intermetallic composite with the needed combination of resistivity, etch resistance or selectivity, thermal and chemical stability (e.g. oxidation resistance), mechanical properties (e.g. thermal expan ⁇ sion), and co patibilty with the sensitive surfaces and materials inherent in the device structure.
  • intermetallic e.g. silicide
  • poly-base layer plus intermetallic composite with the needed combination of resistivity, etch resistance or selectivity, thermal and chemical stability (e.g. oxidation resistance), mechanical properties (e.g. thermal expan ⁇ sion), and co patibilty with the sensitive surfaces and materials inherent in the device structure.
  • the base layer and first intermetallic are chosen to optimize the interface compatibility with the device and to reduce series resistance
  • the second intermetallic protec ⁇ tive cap is chosen to optimize interactions with subsequent processing steps (etching, oxidation, heat treatment, etc.) and coupling to the external contacts.
  • the two intermetallics must be mutually compatible metallur- gically, chemically, mechanically, and electrically. It has been discovered that for silicon based systems, titanium-sil icides and titanium-nitrides form a compatible and preferred set of materials for the first and second intermetallic respectively.
  • FIG. 4A-H illustrates a preferred method of fabrica ⁇ tion of the invented structure for the case of a gate region of a silicon based MOS device.
  • FIG. 3 and FIG. 4 are intended as non-limiting examples. It will be apparent to those of skill in the art that the invented structure and method are useful for forming other contact and interconnect regions and for other semiconductor material combinations.
  • silicon semiconductor wafer 60 has prepared thereon silicon dioxide dielectric layer 61.
  • layer 61 acts as the gate insulator of an MOS device.
  • Layer 61 is typically 15-150 nm thick, the particular value being chosen by well known methods to give particular electrical characteristics. It is preferred that a cleaning step be performed to insure that oxide interface 65 is free from contaminants.
  • Thin substantially uniform first polycrystalline semiconductor (e.g. silicon) base layer 62a is coated (formed) on oxide layer 61.
  • the thickness of first base layer portion 62a is usually in the range from a few atom layers (0.5-1.0 nm) to several hundred nanometers, preferably in the range 20-30 nm.
  • Layer 62a serves to stabilize interface 65, and may be doped n or p-type to yield specific device characteristics. While first base layer 62a is preferred for the sake of cleanliness, it is not essential and may be omitted.
  • Pattern forming layer 63 is applied (FIG. 4C) to cover the wafer surface.
  • the wafer surface can include semiconductor regions, oxide or other dielectric regions, metallized regions or combinations thereof.
  • an oVganic resist having a thickness in the range 0.5 to
  • open region (hole portion) 64 and protected regions (lift-off portion) 66 are applied and patterned to give open region (hole portion) 64 and protected regions (lift-off portion) 66.
  • the hole portion open regions penetrate to the underlying wafer surface and correspond in size and shape substantially to the circuit, device or interconnect areas where metallization is desired to be formed.
  • Width 68 of hole portion 64 substantially deter ⁇ mines the width of the finished metallization pattern.
  • side wall faces 67 of opening 64 be vertical or slope outward, away from the opening. Inward sloping (toward,the opening) of faces 67 by more than 10-15° with respect to the surface normal should be avoided.
  • Techniques for forming dielectric layer 61, uniform fi st poly-base layer 62a and resist layer 63, for cleaning interface 65, and for patterning resist layer 63 to form open regions (hole portion) 64 and closed regions (lift-off portion) 66 are well known per se in the art.
  • Conventional positive photoresist gives faces 67 which typically have an inward sloping angle of 10-15° with respect to the surface normal.
  • second poly base layer portion 62b is applied over the wafer, covering resist regions 66 (lift-off portion) and also forming on the surfaces exposed in opening 64 (hole portion). Thickness in the range 0-200 nm is useful, while 20-30 nm is preferred.
  • the layer may be doped n or p type to yield specific device charac ⁇ teristics.
  • the deposit formed in opening 64 is thinner adjacent to side walls 67, taperin-g toward substantially zero thickness.
  • Combined polycrystalline base layer 62 formed of first base layer 62a and second base layer 62b in opening 64 should be of sufficient total thickness, in the range less than 300 nm to stabilize interface 65 and inhibit diffusion of other elements from superposed inter ⁇ metallic layers 69 and 70 during subsequent processing (heating) steps. It has been found that 15 to 60 nm gives good results and is preferred. While it is convenient in maintaining interface cleanliness to form layer 62 in two steps to give layers 62a and 62b, this is not essential.
  • Base layer 62 may be formed entirely of uniform first base layer 62a, entirely of patterned second base layer 62b, or a combination of 62a and 62b.
  • poly base layer 62 is desirably present in MOS gate regions because the properties of poly-silicon are well known and controlled, it is not essential.
  • Useful devices, contacts and/or interconnects can be obtained when poly layer 62 is omitted or converted partially or wholly to an intermetallic during subsequent process steps.
  • First and second intermetallic layer 69 and 70 are deposited over the wafer surface, covering poly base layer 62b (if present) on resist lift-off portions 66 and also forming on the surface exposed in opening (hole portion) 64.
  • the deposits applied, established and/or formed in opening 64 taper toward zero thickness adjacent to side walls 67, so that layer 70 conformally coats layers 69 and 62b in hole portion 64.
  • the thickness of layer 69 is chosen, based on the measured resistivity, to give the desired series resistance. The thicker the layer, the lower the resistance. There is little benefit in using a thickness greater than that required to give the desired resistance in the completed metallization, since thicker layers make formation of fine line geometry more difficult.
  • Titanium silicide is preferred for first intermetallic layer 69, but silicides of other materials (e.g. Zr, Hf, V, Nb, Ta, Cr, Mo, W, Fe, Co, Ni , Pt and Pd) can also serve. However, some (e.g. Ni , Pt, Pd) will have restricted temperature ranges.
  • the titanium silicide is generally silicon rich with an average composition TiSi x , with x in the range one to five, but the range 2.5 to 3.5 is preferred. For x less than or equal to two, the oxidation resistance was observed to degrade, and for x greater than or equal to four, the sheet resistance increases. Titanium silicide layers having thicknesses in the range 50-500 nm are useful, and 200-400 nm are preferred.
  • Titanium nitride (TiN y is the preferred material for second intermetallic protective cap layer 70.
  • a minimum thickness of approximately 20 nm is found to give useful etch resistance, oxidation resistance, and inhibit "beak" formation. Typical thicknesses are in the range 60-80 nm for protective cap 70, but little advantage, is gained by increases beyond about 100 nm.
  • a total thickness of layers 62, 69 and 70 in the range 300-600 nm is a useful compromise between the requirements for reasonable sheet resistance, for example, approximately one ohm per square, and the ability to achieve sub-micron line widths.
  • a typical structure utilizing approximately 50 nm of poly-silicon as the base layer, 300 nm of titanium silicide as the first intermetallic layer and 60 nm of titanium nitride as the second intermetallic layer gave composite metallization sheet resistance values of 0.9 to 1.2 ohms per square. This is substantially improved over the values of 20 to 25 ohms per square typically obtained for comparable (total) thicknesses of doped poly alone.
  • Vacuum deposition is the preferred method of establishing polycrystal1 ine base layer 62b and forming first intermetallic layer 69.
  • Both layers can be prepared during a single pump-down by energizing a silicon source to deposit poly-base layer 62b (if desired) and then co-energizing a titanium source to co-deposit titanium and silicon to form the silicide.
  • This method is particularly flexible and permits the deposition ratio x in the compound TiSi x to be easily controlled and varied.
  • Other deposi- tion methods such as sputtering may also be used, provided the substrate temperature remains sufficiently low to avoid thermal damage to resist lift-off portion 66 present on the wafer.
  • layers 62b, 69, and 70 are important since improved lift-off characteristics and protective properties of the structure are obtained by arranging for layers 62b and 69 in opening 64 to be generally convex in shape, tapering toward zero thickness adjacent to side wall faces 67 of resist regions 66. This is accomplished by carrying out the formation of layers 62b and 69 in a vacuum deposition system where the evaporation sources are not fixed coaxially with respect to the axis of the surface normal extending from the center of opening 64.
  • FIG. 5A illustrates a desired geometrical arrangement of a substantially point source 80, wafer substrate 81, and relative motion 82 during evaporation to obtain a tapered deposit in region 64 as a result of the shadowing of evaporation source 80 by the side walls 67 of resist regions 66.
  • relative motion exist between source 80 and substrate 81 so that central portion 84 of opening 64 is substantially constantly exposed to source 80, while side portions 86 are shadowed by side walls 67 during a part of the evaporation step.
  • the rela- tive motion may be rotary, translatory or a combination.
  • a substantially point source is desirable but not essential.
  • a planetary system for rotating substrate 81 relative to source 80 gave satisfactory results.
  • FIG. 5B shows schematically profile 85a-c of a cross section of a resulting deposit at different stages of growth or after deposition of successive layers 85a, 85b, and 85c.
  • the cross section tapers toward zero thickness from the central region toward the edges of the layer near side walls 67.
  • Film thickness values given herein for films produced according to the methods of this invention or used in the invented structure correspond to the "central thickness", i.e., the thickness of central region 85a-c of the layers. Ordinarily the thickness of regions 87a-c and central regions 85a-c will be the same. While evaportion is preferred, sputtering can also produce tapered deposits because of wall shadowing. Because of the tapered deposits, layer 70 of FIG.
  • the tapered structure also provides (FIG. 5B) an easy break line between deposits 87a-c on lift-off portion resist regions 66 and deposits 85a-c in hole portion opening 64 so that lift-off is effected cleanly. This improves manufacturing yield. While a planetary evaporation system was found to give satisfactory results, it will be recognized by those of skill in the art that a wide variety of source-substrate geometries exist, with or without relative motion, that will give deposits having a break or thin region in the deposit on or adjacent to side walls 67, and varying amounts of taper on deposits 85a-c within region 64. Following formation (FIG.
  • FIG. 4D shows the structure after * removing portions 74 lying under lift-off portion 66.
  • Portions 74 of layer 62a may be removed by etching using methods well known in the art. No separate masking operation is required since cap layer 70 substantially protects the top and sides of layers 69 and 62b of composite metallization 71. Undercutting into region 75 of layer 62a located under region 62b of metallization 71 is minimized since layer 62a can be made thinner than in the prior art.
  • region 74 of layer 62a may be removed by converting regions 74 to oxide (e.g. Si ⁇ 2) regions 76 by, for example, heating the device structure in an oxidizing atmosphere (see FIG. 4G).
  • Intermetallic protective cap layer 70 substantially protects the top and sides of layers 69 and 62b of composite metallization 71 and inhibits oxidation thereon. There is no significant oxidation of region 75 of layer 62a underlying region 62b of FIG. 4G. Oxidation extends substantially to boundary 77 of region 75 underlying surface 78 of region 70.
  • a 50 nm poly-silicon layer is readily oxidized at 900°C in one hour in dry oxygen. Other oxidation means well known in the art can also be used.
  • Oxide regions 76 may be retained as a convenience for use in subsequent processing steps or selectively removed by methods well known in the art, for example, by using a preferential etchant which does not attack the poly-silicon. With this approach there is substantially no undercutting into region 75 of layer 62a in metallization 71.
  • the structure obtained by forming portion 62b alone is illustrated in FIG. 4H.
  • Source-drain diffusions 72 are typically provided by ion implantation using composite metallization 71 as an implant mask, however other means can be used. There is further illustrated in FIG.
  • dielectric insulating layer 90 formed in conjunction with or subse ⁇ quent to layer 70 by the same general technique used to form layers 62b, 69 or 70 in FIG. 4A-G.
  • means and materials for implementing layer 90 are plasma activated chemical vapor deposition or evaporation or sputtering of Si ⁇ 2» reactive sputtering of silicon in oxygen or nitrogen to produce Si ⁇ £ or or evaporation of silicon followed by oxidation to Si ⁇ « Insulating layer 90 is convenient in subsequent processing steps to avoid shorts to source-drain contacts of MOS devices. S ⁇ O2 is a preferred material. The formation and presence of layer 90 does not interfere with the removal of regions 76 previously described.
  • Composite metallization 71 corresponds to metalliza ⁇ tion regions 15a-c of FIG. 1, some portions (15a) being formed over gate oxide, some portions (15b) being formed directly on the semiconductor and some (15c) being formed on thick oxide. Conventional and well known processing steps are used to provide regions or layers 12, 13, 14, 16, 17 and 19 and contact regions 18, 20 and 21 of FIG. 1. It
  • processing steps for composite metalliza ⁇ tion of titanium silicides and titanium nitrides include a heating cycle in a non-reducing ambient to temperatures up to 1200°C to sinter or anneal the deposited intermetallic materials to reduce their resistance.
  • This sintering or annealing may be performed at any time during the subsequent processing, but where ion implantation is utilized, the post-implant anneal to remove implant damage conveniently serves to sinter or anneal the intermetallic as well. While the sintering or annealing step may be omitted, lower composite metallization sheet resistance is obtained by sintering/annealing.
  • an intermetallic creating layer e.g. Ti
  • a titanium intermetallic creating layer reacts with silicon to form titanium silicides upon heating to temperatures in the range 500-1200°C, with 750-1000°C preferred. Appropriate temperature ranges for other intermetallic creating layers and/or semiconductor combinations can be readily determined.
  • the step of heating to react the intermetallic creating layer to form the corresponding intermetallic may be performed before or after deposition of the second intermetallic layer.
  • a non-oxidizing atmosphere is preferred for reacting prior to deposition of the second intermetallic, and a non-reducing atmosphere is preferred
  • OMPI for reacting after deposition of the second intermetallic.
  • Those portions of the intermetallic creating layer overlying non-reactive dielectric areas e.g. Si ⁇ 2» S ⁇ 3N4 are expected to remain metallic and conductive, and fulfill the same function of providing conductive paths as would the co-deposited intermetallic in those same regions.
  • an organic resist as the pattern forming layer
  • other materials can be used provided that they can be selectively dissolved to accomplish the removal (lift-off step), without significantly attacking those materials desired to be retained on the surface.
  • an improved contact and interconnect metallization structure for semiconductor device and circuits which has lower resistivity to- the flow of electrical current, which has improved resistance to etching and oxidation to facilitate subsequent processing steps, and which avoids formation of ridges or "beaks" of the prior art.
  • an improved process for the formation of a composite intermetallic metallization system for semiconductor devices and circuits particularly by an improved lift-off technique.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Crystallography & Structural Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

Une resistance en serie de faible contact et a metallisation d'interconnexion sur des dispositifs semiconducteurs est obtenue tout en eliminant les problemes d'incompatibilite de materiaux et de procedes de l'art anterieur en utilisant une structure de metallisation composite (42, 44, 49) ayant deux couches intermetalliques superposees (44, 49) ayant des proprietes differentes. La premiere couche intermetallique (44) est choisie pour sa haute conductivite et sa compatibilite avec les interfaces des dispositifs. La seconde intermetallique (49) joue le role 'de chapeau' protecteur conducteur et est choisie pour sa conductivite et sa compatibilite avec les etapes ulterieures du procede. Les deux couches intermetalliques (44, 49) doivent egalement etre compatibles. Pour des dispositifs au silicium, la premiere et la seconde couches intermetalliques preferentielles sont, respectivement, du siliciure de titane riche en silicium et du nitrure de titane, mais d'autres materiaux peuvent egalement etre utilises. Du silicium polycristallin (42) est souhaitable pour une couche de base sous la premiere couche intermetallique (44) dans certaines structures de dispositifs telles que des portes MOS. La metallisation composite est preparee par une technique de decollage.
PCT/US1982/000472 1981-05-04 1982-04-15 Metallisation composite de faible resistivite pour des dispositifs semiconducteurs et procede WO1982003948A1 (fr)

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DE8282901672T DE3268922D1 (en) 1981-05-04 1982-04-15 Low resistivity composite metallization for semiconductor devices and method therefor

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US26066781A 1981-05-04 1981-05-04
US260667810504 1981-05-04

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JP (1) JPS58500680A (fr)
DE (1) DE3268922D1 (fr)
IE (1) IE53237B1 (fr)
IT (1) IT1147876B (fr)
WO (1) WO1982003948A1 (fr)

Cited By (17)

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EP0093971A2 (fr) * 1982-04-28 1983-11-16 Kabushiki Kaisha Toshiba Dispositif semi-conducteur comprenant une couche intermédiaire d'un élément de transition et procédé pour le fabriquer
WO1985004049A1 (fr) * 1984-03-01 1985-09-12 Advanced Micro Devices, Inc. Structure de circuits integres possedant une couche de siliciur e metallique intermediaire et son procede de fabrication
EP0197738A2 (fr) * 1985-03-29 1986-10-15 Kabushiki Kaisha Toshiba Méthode de fabrication d'un dispositif semiconducteur de type LDD
EP0194950A3 (en) * 1985-03-15 1988-08-10 Fairchild Semiconductor Corporation High temperature interconnect system for an integrated circuit
US4792841A (en) * 1980-08-15 1988-12-20 Hitachi, Ltd. Semiconductor devices and a process for producing the same
US4811078A (en) * 1985-05-01 1989-03-07 Texas Instruments Incorporated Integrated circuit device and process with tin capacitors
US4814854A (en) * 1985-05-01 1989-03-21 Texas Instruments Incorporated Integrated circuit device and process with tin-gate transistor
US4821085A (en) * 1985-05-01 1989-04-11 Texas Instruments Incorporated VLSI local interconnect structure
US4890141A (en) * 1985-05-01 1989-12-26 Texas Instruments Incorporated CMOS device with both p+ and n+ gates
US4900257A (en) * 1985-03-30 1990-02-13 Kabushiki Kaisha Toshiba Method of making a polycide gate using a titanium nitride capping layer
US4920071A (en) * 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
US5086016A (en) * 1990-10-31 1992-02-04 International Business Machines Corporation Method of making semiconductor device contact including transition metal-compound dopant source
EP0568108A1 (fr) * 1984-04-13 1993-11-03 Fairchild Semiconductor Corporation Procédé et structure pour l'inhibition de l'exo-diffusion de dopants et/ou de silicium
US5668394A (en) * 1993-06-24 1997-09-16 United Microelectronics Corporation Prevention of fluorine-induced gate oxide degradation in WSi polycide structure
EP0935282A2 (fr) * 1998-02-04 1999-08-11 Nec Corporation Dispositif semi-conducteur comprenant une couche de contact de siliciure riche en silicium, et sa méthode de fabrication
WO2004013922A2 (fr) * 2002-08-06 2004-02-12 Avecia Limited Dispositifs electroniques organiques
WO2009020755A2 (fr) * 2007-08-03 2009-02-12 Micron Technology, Inc. Conducteurs intermétalliques

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JPH0716000B2 (ja) * 1985-10-25 1995-02-22 株式会社日立製作所 半導体集積回路装置の製造方法

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US3632436A (en) * 1969-07-11 1972-01-04 Rca Corp Contact system for semiconductor devices
US3754168A (en) * 1970-03-09 1973-08-21 Texas Instruments Inc Metal contact and interconnection system for nonhermetic enclosed semiconductor devices
US4042953A (en) * 1973-08-01 1977-08-16 Micro Power Systems, Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
US4112196A (en) * 1977-01-24 1978-09-05 National Micronetics, Inc. Beam lead arrangement for microelectronic devices
US4128670A (en) * 1977-11-11 1978-12-05 International Business Machines Corporation Fabrication method for integrated circuits with polysilicon lines having low sheet resistance
US4276557A (en) * 1978-12-29 1981-06-30 Bell Telephone Laboratories, Incorporated Integrated semiconductor circuit structure and method for making it
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
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Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4792841A (en) * 1980-08-15 1988-12-20 Hitachi, Ltd. Semiconductor devices and a process for producing the same
EP0093971A3 (en) * 1982-04-28 1985-01-30 Kabushiki Kaisha Toshiba Semiconductor device having an interstitial transition element layer and method of manufacturing the same
EP0093971A2 (fr) * 1982-04-28 1983-11-16 Kabushiki Kaisha Toshiba Dispositif semi-conducteur comprenant une couche intermédiaire d'un élément de transition et procédé pour le fabriquer
WO1985004049A1 (fr) * 1984-03-01 1985-09-12 Advanced Micro Devices, Inc. Structure de circuits integres possedant une couche de siliciur e metallique intermediaire et son procede de fabrication
EP0568108A1 (fr) * 1984-04-13 1993-11-03 Fairchild Semiconductor Corporation Procédé et structure pour l'inhibition de l'exo-diffusion de dopants et/ou de silicium
US4920071A (en) * 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
EP0194950A3 (en) * 1985-03-15 1988-08-10 Fairchild Semiconductor Corporation High temperature interconnect system for an integrated circuit
US5414301A (en) * 1985-03-15 1995-05-09 National Semiconductor Corporation High temperature interconnect system for an integrated circuit
EP0197738A2 (fr) * 1985-03-29 1986-10-15 Kabushiki Kaisha Toshiba Méthode de fabrication d'un dispositif semiconducteur de type LDD
EP0197738A3 (en) * 1985-03-29 1986-12-30 Kabushiki Kaisha Toshiba Ldd semiconductor device and method for manufacturing thereof
US4900257A (en) * 1985-03-30 1990-02-13 Kabushiki Kaisha Toshiba Method of making a polycide gate using a titanium nitride capping layer
US4890141A (en) * 1985-05-01 1989-12-26 Texas Instruments Incorporated CMOS device with both p+ and n+ gates
US4821085A (en) * 1985-05-01 1989-04-11 Texas Instruments Incorporated VLSI local interconnect structure
US4814854A (en) * 1985-05-01 1989-03-21 Texas Instruments Incorporated Integrated circuit device and process with tin-gate transistor
US5302539A (en) * 1985-05-01 1994-04-12 Texas Instruments Incorporated VLSI interconnect method and structure
US4811078A (en) * 1985-05-01 1989-03-07 Texas Instruments Incorporated Integrated circuit device and process with tin capacitors
US5086016A (en) * 1990-10-31 1992-02-04 International Business Machines Corporation Method of making semiconductor device contact including transition metal-compound dopant source
US5668394A (en) * 1993-06-24 1997-09-16 United Microelectronics Corporation Prevention of fluorine-induced gate oxide degradation in WSi polycide structure
EP0935282A3 (fr) * 1998-02-04 2000-04-05 Nec Corporation Dispositif semi-conducteur comprenant une couche de contact de siliciure riche en silicium, et sa méthode de fabrication
EP0935282A2 (fr) * 1998-02-04 1999-08-11 Nec Corporation Dispositif semi-conducteur comprenant une couche de contact de siliciure riche en silicium, et sa méthode de fabrication
US6288430B1 (en) 1998-02-04 2001-09-11 Nec Corporation Semiconductor device having silicide layer with siliconrich region and method for making the same
US6492264B2 (en) 1998-02-04 2002-12-10 Nec Corporation Semiconductor device having a silicide layer with silicon-rich region and method for making the same
WO2004013922A2 (fr) * 2002-08-06 2004-02-12 Avecia Limited Dispositifs electroniques organiques
WO2004013922A3 (fr) * 2002-08-06 2004-06-10 Avecia Ltd Dispositifs electroniques organiques
US7332369B2 (en) 2002-08-06 2008-02-19 Merck Patent Gmbh Organic electronic devices
WO2009020755A2 (fr) * 2007-08-03 2009-02-12 Micron Technology, Inc. Conducteurs intermétalliques
WO2009020755A3 (fr) * 2007-08-03 2009-04-02 Micron Technology Inc Conducteurs intermétalliques

Also Published As

Publication number Publication date
JPH0244144B2 (fr) 1990-10-02
IE821036L (en) 1982-11-04
JPS58500680A (ja) 1983-04-28
IT8248321A0 (it) 1982-04-30
EP0077813A4 (fr) 1984-02-09
EP0077813A1 (fr) 1983-05-04
IE53237B1 (en) 1988-09-14
IT1147876B (it) 1986-11-26
EP0077813B1 (fr) 1986-02-05
DE3268922D1 (en) 1986-03-20

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