USRE48495E1 - System, device, and method for initializing a plurality of electronic devices using a single packet - Google Patents

System, device, and method for initializing a plurality of electronic devices using a single packet Download PDF

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USRE48495E1
USRE48495E1 US16/512,828 US201016512828A USRE48495E US RE48495 E1 USRE48495 E1 US RE48495E1 US 201016512828 A US201016512828 A US 201016512828A US RE48495 E USRE48495 E US RE48495E
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Prior art keywords
packet
electronic device
initialization
host apparatus
power units
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Akihisa Fujimoto
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Kioxia Corp
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Toshiba Memory Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4405—Initialisation of multiprocessor systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments described herein relate generally to a semiconductor system, a semiconductor device, and an electronic device initializing method.
  • the embodiments relate to a semiconductor system including plural electronic devices.
  • An SDTM card is well known as a memory system in which a NAND type flash memory is used.
  • An SD interface is well known as an interface between the SD card and a host apparatus. In the SD interface, plural devices can be connected to one bus.
  • U.S. Pat. No. 6,820,148 discloses the above-described configuration.
  • FIG. 1 is a block diagram of a semiconductor system according to a first embodiment
  • FIG. 2 is a flowchart illustrating an operation of the semiconductor system of the first embodiment
  • FIG. 3 and FIG. 4 are timing charts of a symbol and a signal of the first embodiment
  • FIG. 5 is a block diagram of the semiconductor system of the first embodiment
  • FIG. 6 is a block diagram of an electronic device of the first embodiment
  • FIG. 7 and FIG. 8 are conceptual views of a frame format of the first embodiment
  • FIG. 9 and FIG. 10 are flowcharts illustrating operations of a host apparatus and the electronic device of the first embodiment
  • FIG. 11 is a block diagram of the semiconductor system of the first embodiment
  • FIG. 12 is a conceptual view of the frame format of the first embodiment
  • FIG. 13 and FIG. 14 are flowcharts illustrating the electronic device of the first embodiment
  • FIGS. 15 to 18 are block diagrams of the semiconductor system of the first embodiment
  • FIG. 19 is a diagram illustrating capability of the electronic device of the first embodiment
  • FIG. 20 is a conceptual view of the frame format of the first embodiment
  • FIG. 21 is a conceptual view of a frame format according to a second embodiment
  • FIG. 22 and FIG. 23 are flowcharts illustrating operations of an electronic device and a host apparatus of the second embodiment
  • FIGS. 24 to 30 are block diagrams of a semiconductor system of the second embodiment
  • FIG. 31 is a conceptual view of the frame format of the second embodiment
  • FIG. 32 is a block diagram of a semiconductor system according to a third embodiment.
  • FIG. 33 is a diagram illustrating a flag and an operation of a host apparatus of the third embodiment.
  • FIG. 34 and FIG. 35 are block diagrams of a semiconductor system according to a fourth embodiment
  • FIG. 36 is a block diagram of a semiconductor system according to a fifth embodiment.
  • FIG. 37 is a block diagram of a semiconductor system according to a sixth embodiment.
  • FIG. 38 is a diagram illustrating allocation of signals to signal pins of an electronic device of the sixth embodiment.
  • a semiconductor system includes plural electronic devices and a host apparatus.
  • the host apparatus initializes plural electronic devices in units of group.
  • FIG. 1 is a block diagram illustrating an example of the semiconductor system of the first embodiment.
  • a semiconductor system 1 includes a host apparatus 2 and a semiconductor devide 3 .
  • the host apparatus 2 includes at least one input port and at least one output port.
  • the host apparatus 2 controls an operation of the semiconductor device 3 through the ports to administer an operation of the semiconductor system 1 .
  • each port is configured as a differential pair according to a LVDS (low voltage differential Signaling) method.
  • a signal output from the output port of the host apparatus 2 is referred to as a signal D 0
  • differential signals of the signal D 0 are referred to as signals D 0 + and D 0 ⁇ .
  • a signal input to the output port of the host apparatus 2 is referred to as a signal D 1
  • differential signals of the signal D 1 are referred to as signals D 1 + and D 1 ⁇ .
  • the host apparatus 2 assembles a packet including a command and data, and the host apparatus 2 transmits the packet to the semiconductor device 3 to control the operation of the semiconductor device 3 .
  • the host apparatus 2 receives the packet transmitted from the semiconductor device 3 to perform the operation according to the received packet.
  • the semiconductor device 3 includes N (N is a natural number more than 1) electronic devices 4 .
  • N electronic devices 4 are referred to as electronic devices 4 -i (i is 1 to N) when distinguished from one another.
  • each of the electronic devices 4 includes an input signal pin 5 , an output signal pin 6 , a packet decoder 7 , a processing unit 8 , a register 9 , and a packet update circuit 10 .
  • the units are referred to as an input signal pin 5 -i, an output signal pin 6 -i, a packet decoder 7 -i, a processing unit 8 -i, register 9 -i, and a packet update circuit 10 -i.
  • the input signal pin 5 including plural signals acts as at least one input port to receive the packet provided from the outside.
  • the input signal pin 5 transfers the received packet to the packet decoder 7 .
  • the packet decoder 7 is configured to be able to analyze the packet transferred from the input signal pin 5 .
  • the packet decoder 7 distinguishes kinds of the packets using a command identifier in a packet header.
  • the packet decoder 7 commands the processing unit 8 to perform a necessary calculation in response to the kind of the packet.
  • the packet decoder 7 commands the packet update circuit 10 to update the received packet if needed.
  • the processing unit 8 is configured to be able to perform necessary processing in response to the command from the packet decoder 7 .
  • Examples of the processing contents include initialization of the device and computation of a device ID.
  • the processing unit 8 causes the register 9 to retain the device ID.
  • the device ID means a number that is unique to each electronic device 4 , and the host apparatus can identify each electronic device 4 using the device ID.
  • the packet decoder 7 compares the device ID that is included as address information in the packet with the device ID in the register 9 , which allows the packet decoder 7 to determine whether the packet is direct to the semiconductor device 3 .
  • the packet update circuit 10 updates contents of a payload of the received packet, and the packet update circuit 10 outputs the packet to the outside from the output signal pin 6 that includes the plural signals to act as at least one output port. For example, the packet update circuit 10 updates the contents of the payload according to calculation result of the processing unit 8 .
  • There are two kinds of timing in which the packet is output from the output signal pin 6 that is, the case in which the received packet is transmitted as soon as possible irrespective of a processing status of the device to the received packet, and the case in which the packet is transmitted after the device performs the processing to the received packet. It depends on the command identifier of the packet and a state of the device.
  • the N electronic devices 4 - 1 to 4 -N having the above-described configuration are ring-connected (or chain-connected) to the host apparatus 2 as illustrated in FIG. 1 . That is, the packet transmitted from the host apparatus 2 is received by the electronic device 4 - 1 , transferred from the electronic device 4 - 1 to the electronic device 4 - 2 , and transferred from the electronic device 4 - 2 to the electronic device 4 - 3 . After that, similar steps are repeated. Then the packet output from the output signal pin 6 -N of the electronic device 4 -N is returned to the host apparatus 2 .
  • the semiconductor device 3 of FIG. 1 includes a configuration in which the semiconductor device 3 includes electronic devices 4 - 1 to 4 -N and a hub (see a fourth embodiment).
  • Almost all the pieces of communication conducted using the ring connection are used in the communication between the host and the electronic device and occasionally used in the communication between the electronic devices. For example, when the electronic device 4 - 2 does not correctly receive data, which is transmitted from electronic device 4 - 1 to the electronic device 4 - 2 , due to a noise, the electronic device 4 - 2 can make a request to transmit the data again. At this point, the electronic device 4 - 1 is notifies of the retransmission request made by the electronic device 4 - 2 through the electronic devices 4 - 3 to 4 -N and the host apparatus 2 , which allows the electronic device 4 - 1 to retransmit the data.
  • FIG. 2 is a flowchart illustrating an operation of the semiconductor system. First an entire flow will roughly be described.
  • Step S 10 interface selection is performed (Step S 10 ).
  • the host apparatus 2 determines whether an interface connected to the semiconductor device 3 can be used, that is, whether the semiconductor device 3 is connected.
  • the interface can be used that is, when the semiconductor device 3 is connected (YES in Step S 11 )
  • one of the electronic devices 4 transmits a boot code to the host apparatus 2 (Step S 12 ).
  • the host apparatus 2 that receives the boot code performs the boot code and performs numbering of the electronic devices 4 (enumeration) (Step S 13 ). That is, the device ID described above is allocated to each electronic device 4 .
  • each electronic device 4 is initialized in response to the command from the host apparatus 2 (Step S 14 ).
  • Each electronic device 4 becomes a ready state by the initialization.
  • the initialization is performed in units of a plurality of the electronic devices 4 in order to shorten a time necessary for the initialization.
  • the host apparatus 2 has a restriction to a power supply current that can be supplied to the electronic device 4 , the number of simultaneously-initialized devices is restricted, and thus the initialization is separately performed.
  • Step S 15 the host apparatus 2 obtains information on each electronic device 4 .
  • Step S 15 the host apparatus 2 determines an operating condition common to the electronic devices 4 based on the capabilities of the host apparatus 2 and electronic device 4 , and the host apparatus 2 collectively sets the operating condition for the host apparatus 2 and the electronic devices 4 (Step S 16 ).
  • the capability set in this step is an item common to the whole system.
  • the host apparatus 2 determines an individual operating condition of the electronic device 4 , and the host apparatus 2 separately sets the individual operating condition for the electronic device 4 (Step S 17 ).
  • a UHS-II card has a hierarchical structure. Therefore, when the semiconductor device 3 is the UHS-II card, the initialization is performed to a physical layer in Step S 14 . For example, the initialization is performed to a layer higher than the physical layer in Step S 16 and Step S 17 B.
  • FIG. 3 is a timing chart illustrating a clock and a symbol, transmitted from the host apparatus 2 to the semiconductor device 3 and a level and a symbol (the state is communicated in synchronization with the clock in the symbol, and the symbol includes plural bits and is encoded by 8b/10b coding), transmitted from the semiconductor device 3 to the host apparatus 2 , immediately after the semiconductor device 3 is connected to the host apparatus 2 .
  • FIG. 4 is a timing chart of the signals D 0 and D 1 immediately after the semiconductor device 3 is connected to the host apparatus 2 .
  • the semiconductor system 1 is in a power-down state.
  • the host apparatus 2 does not generate the clock, and the host apparatus 2 does not transmit the symbol to the semiconductor device 3 .
  • the host apparatus 2 transmits STB to the semiconductor device 3 using one of an “H” level or an “L” level of the differential signal in order to determine usability of the interface.
  • the “H” level is STB. Therefore, a data link state transitions to a wakeup state.
  • the host apparatus 2 outputs a clock RCLK to the semiconductor device 3 .
  • the clock RCLK is supplied to each of the electronic devices 4 - 0 to 4 -n.
  • the electronic device 4 performs the operation in synchronization with the clock RCLK.
  • the level STB is sequentially transferred from the electronic device 4 - 0 to the electronic device 4 -N.
  • the electronic device 4 that receives the level STB returns the level STB to the host apparatus 2 .
  • the level STB is a signal that indicates that the host apparatus 2 and the electronic device 4 are in a standby state before synchronized with each other.
  • the host apparatus 2 transmits the level STB, whereby the D 0 ⁇ changes from the “L” level to the “H” level while the signal D 0 changes to the differential level.
  • the semiconductor device 3 transmits the level STB, whereby the D 1 ⁇ changes from the “L” level to the “H” level while the signal D 0 changes to the differential level.
  • the host apparatus 2 recognizes that the interface can be used by detecting that the signals D 0 and D 1 change to the differential level.
  • processing is performed in order to synchronize the host apparatus 2 and the semiconductor device 3 with each other. That is, the host apparatus 2 transmits a symbol SYN to the semiconductor device 3 , and the semiconductor device 3 returns the symbol SYN to the host apparatus 2 when a PLL is locked.
  • the host apparatus 2 receives the symbol SYN. Because the reception clock of the host apparatus 2 differs from the transmission clock RCLK in a phase, it is necessary to lock another PLL for the reception.
  • the symbol SYN is one that is used for synchronization.
  • the PLL is locked while the symbol SYN is received plural times, which allows synchronous communication to be conducted between the host apparatus 2 and the semiconductor device 3 .
  • FIG. 5 is a block diagram of the host apparatus 2 and any one of the electronic devices 4 , particularly illustrates a configuration relating to data link.
  • the host apparatus 2 includes transmission I/Os 20 - 1 and 20 - 2 that transmit the signals D 0 + and D 0 ⁇ , reception I/Os 21 - 1 and 21 - 2 that receive the differential signals D 1 + and D 1 ⁇ , and a voltage level detection circuit 22 .
  • the voltage level detection circuit 22 detects a level change of the differential signal D 1 + and D 1 ⁇ . A determination that the interface with the electronic device 4 can be used is made when the voltage level detection circuit 22 detects the change in signal level.
  • the electronic device 4 includes transmission I/Os 23 - 1 and 23 - 2 that transmit the differential signals D 1 + and D 1 ⁇ , reception I/O 24 - 1 and 24 - 2 that receive the differential signals D 0 + and D 0 ⁇ , and a voltage level detection circuit 25 .
  • the voltage level detection circuit 25 detects a level change of the differential signal D 0 + and D 0 ⁇ . For example, when the host apparatus 2 is started up from the electronic device 4 , the voltage level detection circuit 25 detects the change in signal level, which allows the host apparatus 2 to be started up.
  • any one of the electronic devices 4 is a memory device that retains the boot code.
  • the electronic device 4 -N is the memory device that retains the boot code.
  • the boot code means a program code that is necessary to start up the system in the host apparatus 2 .
  • the boot code is transferred to a system memory of the host apparatus 2 , and the boot code is executed by the host apparatus 2 .
  • a device driver and an OS are loaded on the system memory by a boot loader included in the boot code.
  • the electronic device 4 -N receives the symbol STB from the host apparatus 2 and returns the symbol STB to the host apparatus 2 . Then, the electronic device 4 -N voluntarily reads the boot code without receiving the command from the host apparatus 2 , and the electronic device 4 -N transmits the boot code to the host apparatus 2 .
  • FIG. 6 is a block diagram of the electronic device 4 -N, and FIG. 6 illustrates the detailed configuration of the electronic device 4 -N rather than that of FIG. 1 .
  • the electronic device 4 -N includes a memory controller 30 and a NAND type flash memory 31 .
  • the memory controller 30 includes a packet decoder 7 -N, a processing unit 8 -N, register 9 -N, and a packet update circuit 10 -N.
  • the NAND type flash memory 31 retains a boot code 32 .
  • the processing unit 8 -N After transmitting the level STB to the host apparatus 2 , the processing unit 8 -N reads the boot code 32 from the NAND type flash memory 31 .
  • the processing unit 8 -N assembles the boot code 32 as the packet and transmits the packet from the output signal pin 6 to the host apparatus 2 .
  • FIG. 7 is a schematic diagram illustrating a configuration of the packet.
  • the packet 33 includes a packet header 34 and a payload 35 .
  • the payload 35 includes the boot code 32 that is read from the NAND type flash memory 31 .
  • a size of the boot code may be set as a preset value to the host and the boot device, or a region indicating the size of the boot code may be secured in the packet header or a specific portion of the boot code.
  • the electronic device except the electronic device 4 -N may be used as the electronic device including the boot code.
  • the electronic device 4 -(N ⁇ 1) may be used as the electronic device including the boot code.
  • the electronic device 4 -(N ⁇ 1) transmits the packet 33 to the electronic device 4 -N. Because the destination of the packet 33 is the host apparatus 2 , the electronic device 4 -N transmits the packet 33 to the host apparatus 2 without change.
  • Step S 13 of FIG. 2 will be described below.
  • the host apparatus 2 provides the device IDs to the electronic devices 4 - 0 to 4 -N included in the semiconductor device 3 .
  • a method disclosed in Japanese Patent Application No. 2009-221468 can be adopted in Step S 13 .
  • FIG. 8 is a schematic diagram of the packet issued by the host apparatus 2 in performing Step S 13 .
  • a packet header of a packet 40 includes at least fields 41 - 1 and 41 - 2 .
  • the device ID that indicates the destination of the packet 40 is stored in the field 41 - 1 .
  • a command identifier corresponding to a command to provide the device ID is stored in the field 41 - 2 .
  • a payload includes at least fields 42 - 1 and 42 - 2 .
  • the field 42 - 1 indicates a start device ID (start device number), and a value of the field 42 - 1 is determined by the electronic device 4 - 1 that initially receives the packet 40 from the host apparatus 2 .
  • the number of electronic devices 4 to which the setting of the device ID is completed is stored in the field 42 - 2 .
  • the value of the field 42 - 1 is incremented in a process of transferring the packet among the electronic devices 4 , which allows the host apparatus 2 to recognize the total number of electronic devices 4 .
  • the host apparatus 2 can specify the device ID of each electronic device 4 from the values of the fields 42 - 1 and 42 - 2 .
  • a final device ID (final device number) may be indicated in the field 42 - 2 instead of the number of electronic devices 4 to which the setting of the device ID is completed, because the number of devices can be computed by subtraction when the final device number and the initial device number are found.
  • FIG. 9 is a flowchart illustrating the operation of the host apparatus 2 in providing the device ID.
  • the host apparatus 2 assembles the packet in order to specify the device ID (Step S 20 ). That is, the command identifier (field 41 - 2 ) corresponding to the command (hereinafter referred to as ID providing command) to specify the device ID is set to the packet header, and initial values (in the first embodiment, zero) are set to the values of the start device ID (field 42 - 1 ) and the number of devices (field 42 - 2 ) of the payload.
  • the host apparatus 2 transmits the packet assembled in Step S 20 to the semiconductor device 3 (Step S 21 ). Whether the packet is transmitted in the form of the broadcast (multicast) or unicast is previously made in each command.
  • the ID providing command is a broadcast command. Accordingly, the destination in the field 41 - 1 of the packet header is ignored, and the packet is transmitted to the initial electronic device 4 - 1 of the ring connection in the case of the connection relationship in FIG. 1 .
  • the host apparatus 2 receives the packet from the final electronic device 4 -N of the ring connection (Step S 22 ). Therefore, the host apparatus 2 reads the initial device ID (field 42 - 1 ) and the number of devices (field 42 - 2 ) in the received packet (Step S 23 ).
  • the value of the field 42 - 1 is the device ID of the initial electronic device 4 - 1 of the ring connection
  • the value of the field 42 - 2 is the number N of ring-connected electronic devices 4 - 1 to 4 -N.
  • the host apparatus 2 performs predetermined calculation using the values of the fields 42 - 1 and 42 - 2 to recognize the device ID and the total number of devices of the electronic devices 4 - 2 to 4 -N (Step S 24 ).
  • the number of identifiable devices is determined by the number of bits of the device ID field.
  • the predetermined calculation means a rule in which the electronic devices 4 - 2 to 4 -N compute the IDs thereof with respect to the start device ID. For example, predetermined calculation means that the increment is performed by the number of devices.
  • the start device ID has a value “n (n is a natural number)” in the packet received from the electronic device 4 -N, it is found that the electronic device 4 - 1 has the device ID “n”, the electronic device 4 - 2 has the device ID “n+1”, and the electronic device 4 -N has the device ID “n+N”.
  • the host apparatus 2 manages the electronic devices 4 - 1 to 4 - 3 using the device IDs obtained in Step S 24 .
  • the electronic device 4 receives the packet at the input signal pin 5 (Step S 30 ).
  • the packet decoder 7 commands the processing unit 8 to compute the device ID thereof.
  • the processing unit 8 confirms whether the value (start device ID) of the field 42 - 1 of the received packet is a predetermined value (in the first embodiment, zero) set by the host apparatus 2 (Step S 31 ).
  • the processing unit 8 determines any number except zero as the device ID thereof, and the processing unit 8 commands the packet update circuit 10 to update the value (start device ID) of the field 42 - 1 to the determined device ID. Therefore, the packet update circuit 10 updates the field 42 - 1 .
  • the reason for using the number other than zero is that zero has been already allocated to the device ID of the host apparatus 2 .
  • Step S 34 when the value of the field 42 - 1 is not the predetermined value set by the host apparatus 2 (NO in Step S 32 ), the value of the field 42 - 1 is maintained (Step S 34 ). That is, the processing unit 8 does not command the packet update circuit 10 to update the value of the field 42 - 1 .
  • the processing unit 8 performs the predetermined calculation using the field 42 - 1 to compute the device ID thereof (Step S 35 ).
  • the calculation in Step S 35 is identical to the calculation in Step S 24 of FIG. 9 .
  • the calculation in Step S 35 means that the field 42 - 1 (start device ID) is incremented by the number of times corresponding to the field 42 - 2 (the number of devices).
  • the processing unit 8 stores the device ID thereof determined in Step S 33 or S 35 in the register 9 (Step S 36 ).
  • the packet update circuit 10 updates (increments) the value of the field 42 - 2 of the received packet.
  • the packet update circuit 10 outputs the packet in which the field 42 - 2 or both the fields 42 - 1 and 42 - 2 are updated.
  • FIG. 11 is a block diagram of the semiconductor system 1
  • square marks added to a side of an arrow between the devices indicate payload contents of the packet, the left side of the square marks indicates the field 42 - 1 (start device ID), and the right side indicates the field 42 - 2 (the number of devices).
  • the packet including the ID providing command is broadcasted from the host apparatus 2 .
  • the values of the fields 42 - 1 and 42 - 2 of the packet are the predetermined value (zero) set by the host apparatus 2 (Steps S 20 and S 21 of FIG. 9 ).
  • the packet is initially received by the electronic device 4 - 1 .
  • any number is determined as the device ID of the device 4 - 1 .
  • the device ID is the number “1”.
  • the field 42 - 1 is updated from “0” to “1” (Step S 33 of FIG. 10 ), the value of the field 42 - 2 is incremented and updated from “0” to “1” (Step S 37 of FIG. 10 ), and the updated value of the field 42 - 2 is output by the device 4 - 1 .
  • the packet output from the electronic device 4 - 1 is received by the electronic device 4 - 2 .
  • the device ID is allocated to the electronic device 4 . That is, the device IDs “3” to “15” are allocated to the electronic devices 4 - 3 to 4 - 15 .
  • the packet output from the electronic device 4 - 15 is received by the host apparatus 2 .
  • the field 42 - 1 has the value “1” and the field 42 - 2 has the value “15”. Accordingly, the host apparatus can recognize that the electronic device 4 - 1 has the device ID “1” and the total number of electronic devices 4 is “15” (Step S 23 of FIG. 9 ). Therefore, the host apparatus 2 understands that the electronic devices 4 - 1 to 4 - 15 have the device IDs “1” to “15”, respectively.
  • a command identifier indicating an initialization command is included in a packet header 51 of a packet 50 , and the maximum number of electronic devices M that can be initialized once by the host apparatus 2 is included in a payload 52 .
  • FIG. 13 is a flowchart illustrating an operation of the electronic device 4 in receiving the packet including the initialization command, and the flowchart of FIG. 13 is common to the electronic devices 4 - 1 to 4 -N.
  • the electronic device 4 receives the packet at the input signal pin 5 (Step S 40 ).
  • the packet decoder 7 notifies the processing unit 8 of the initialization command included in the packet and the number of electronic devices M of the payload 52 .
  • the processing unit 8 determines whether the electronic device 4 is currently initializing. When the electronic device 4 is currently executing the initialization (YES in Step S 41 ), the processing unit 8 waits for the initialization completion (Step S 42 ).
  • the processing unit 8 After the initialization completion, the processing unit 8 does not perform the initialization again (Step S 43 ), the processing unit 8 causes the packet update circuit 10 to transmit the received packet to the next electronic device 4 (in the case of the electronic device 4 -N, to the host apparatus 2 ) with no change (Step S 44 ).
  • the processing unit 8 determines whether the electronic device 4 has been already initialized. When the electronic device 4 has been already initialized (YES in Step S 45 ), the processing unit 8 does not perform the initialization again (Step S 43 ). The processing unit 8 causes the packet update circuit 10 to transmit the received packet to the next electronic device 4 (in the case of the electronic device 4 -N, to the host apparatus 2 ) with no change (Step S 44 ).
  • Step S 45 the processing unit 8 confirms whether the number of electronic devices M of the payload 52 is “0” (Step S 46 ).
  • Step S 46 the processing unit 8 goes to Step S 43 , and the processing unit 8 goes to Step S 44 without performing the initialization.
  • Step S 47 When the number of electronic devices M is not “0” (NO in Step S 46 ), the processing unit 8 performs the initialization (Step S 47 ).
  • the processing unit 8 commands the packet update circuit 10 to decrement the number of electronic devices of the payload 52 (Step S 48 ). That is, the number of electronic devices M is updated to M ⁇ 1.
  • the packet update circuit 10 outputs the packet in which the number of electronic devices M of the payload 52 is updated (Step S 44 ).
  • the packet update circuit 10 executes the processing in Step S 44 without waiting for the initialization completion of the electronic device 4 .
  • the host apparatus 2 repeatedly issues the initialization packet 50 until the host apparatus 2 receives the initialization packet 50 in which the number of electronic devices M is not “0”.
  • the number of devices that can be initialized is reset at the same time as the initialization packet 50 is issued. In other words, the host apparatus 2 can confirm that the initialization is completed for all the electronic devices 4 - 1 to 4 -N by receiving the packet 50 of M ⁇ “0”.
  • FIG. 14 is a flowchart illustrating the operation of the electronic device 4 in receiving the packet including the initialization completion confirming command, and the flowchart of FIG. 14 is common to the electronic devices 4 - 1 to 4 -N.
  • the electronic device 4 receives the packet at the input signal pin 5 (Step S 50 ).
  • the packet decoder 7 notifies the processing unit 8 that the packet includes the initialization completion confirming command.
  • the processing unit 8 determines whether the electronic device 4 is currently being initialized. When the electronic device 4 is currently being initialized (YES in Step S 51 ), the processing unit 8 waits for the initialization completion (Step S 52 ). After the initialization completion, the processing unit 8 causes the packet update circuit 10 to transmit the received packet to the next electronic device 4 (in the case of the electronic device 4 -N, to the host apparatus 2 ) without change (Step S 54 ).
  • the processing unit 8 determines whether the electronic device 4 has been already initialized. When the electronic device 4 has been already initialized (YES in Step S 53 ), the processing unit 8 commands the packet update circuit 10 to transmit the received packet to the next electronic device 4 (in the case of the electronic device 4 -N, to the host apparatus 2 ) without change (Step S 54 ). Therefore, the packet is transferred to the next electronic device 4 . On the other hand, when the electronic device 4 is not initialized yet (NO in Step S 53 ), the processing unit 8 does not transmit the packet to the next electronic device 4 . That is, the packet stays in the electronic device 4 .
  • the initialization is executed in each M of the electronic devices.
  • FIG. 15 to FIG. 18 are block diagrams of the semiconductor system 1
  • square marks added to the side of the arrow between the devices indicate the payload of the packet 50 , that is, the number of electronic devices M.
  • the device ID is provided to each electronic device 4 .
  • FIG. 15 illustrates the state in which the initialization is not performed yet to any electronic devices 4 while the initialization command is issued. As illustrated in FIG. 15 , it is assumed that the host apparatus 2 issues the packet while the number of electronic devices M is set to “4”. That is, the host apparatus 2 can initialize once up to four electronic devices.
  • “ ⁇ 1” added to the electronic device 4 means that the number of electronic devices M is decremented.
  • the electronic devices 4 - 3 and 4 - 4 perform the similar operation.
  • the electronic devices 4 - 5 to 4 - 15 transfer the packet to the subsequent electronic devices 4 - 6 to 4 - 16 without performing the initialization.
  • FIG. 16 illustrates the state in which the initialization completion confirming command is issued after the state in FIG. 15 .
  • the packet including the initialization completion confirming command is received by the electronic device 4 - 1 (Step S 50 ). Because the electronic device 4 - 1 has been already initialized (YES in Step S 53 ), the electronic device 4 - 1 transfers the packet to the next electronic device 4 - 2 (Step S 54 ). At this point, because the electronic devices 4 - 1 to 4 - 4 are initialized, the packet reaches the electronic device 4 - 5 . However, the electronic device 4 - 5 is not initialized yet, the packet stays in the electronic device 4 - 5 but the packet is not returned to the host apparatus 2 . Therefore, the host apparatus 2 can recognize the existence of the electronic device 4 whose initialization is not completed.
  • FIG. 17 illustrates this state.
  • the packet reaches the electronic device 4 - 5 without change.
  • the electronic devices 4 - 5 to 4 - 8 are initialized in the manner similar to that of FIG. 15 .
  • the packet including the initialization completion confirming command reaches the electronic device 4 - 9 .
  • FIG. 18 illustrates this state.
  • the above initialization technique initializes the electronic devices by grouping the electronic devices to shorten the initialization for the plural electronic device, and to enable the initialization within a power supply current supported by the host.
  • the method may be implemented by defining an upper limit of an initialization current necessary for each electronic device.
  • the current necessary for the initialization depends on the electronic device.
  • the initialization can be performed in a halftime when the current necessary for the initialization becomes double.
  • the initialization time can further be shortened by previously designating the optimum initialization group in each electronic device.
  • the further shortened initialization time can be realized by setting a group number to each electronic device.
  • the group number indicates that the initialization is performed to the electronic device in which times of initialization command.
  • each electronic device When the group number is set, the number of devices that can be initialized in the initialization command is ignored, each electronic device counts the number of received initialization commands, and each electronic device starts the initialization when the number of received initialization commands is matched with the group number.
  • the electronic device waits for the initialization completion to output the initialization command.
  • the host system can select the optimum initialization procedure according to the feature of the electronic device. This point is described in detail in a second embodiment.
  • Step S 15 of FIG. 2 will be described below.
  • the host apparatus 2 issues a command to read the setting value by broadcast. Parameters such as a maximum clock frequency range, time-out value, and various symbol lengths are indicated as an argument of the command, each electronic device does not update the argument that can be dealt therewith, and the electronic device updates the argument that cannot be dealt therewith to the parameter that can be dealt therewith.
  • the parameter received by the host apparatus 2 includes the condition that all the electronic devices can be operated.
  • Step S 16 of FIG. 2 will be described below. Because the host apparatus 2 determines the operating condition common to the electronic devices 4 in Step S 15 , the same value is set to all the electronic devices 4 by a command to write the setting value by broadcast (the value is set to the register 9 of each electronic device 4 ).
  • FIG. 19 is a table illustrating the information read in Step S 15 , and FIG. 19 illustrates a maximum operating frequency and operation timing in the case of the 15 electronic devices by way of example.
  • the electronic devices 4 - 1 to 4 - 15 have the maximum operating frequencies f 0 to f 15 , respectively, while the host apparatus has the maximum operating frequency f 0 . It is assumed that the lowest frequency is the maximum operating frequency f 3 of the electronic device 4 - 3 . From the information of FIG. 19 , the host apparatus 2 can recognize that all the electronic devices 4 - 1 to 4 - 15 and the host apparatus 2 can be operated at the frequency f 3 .
  • the electronic devices 4 - 1 to 4 - 15 have operation timings T 1 to T 15 , respectively, while the host apparatus 2 has operation timing T 0 . It is assumed that the worst timing is the operation timing T 1 of the electronic device 4 - 1 . From the information of FIG. 19 the host apparatus 2 can recognize that all the electronic devices 4 - 1 to 4 - 15 and the host apparatus 2 can be operated in operation timing T 1 .
  • the host apparatus 2 determines the operating frequencies of the electronic devices 4 - 1 to 4 - 15 as the operating frequency f 3 and determines the operation timings of the electronic devices 4 - 1 to 4 - 15 as the operation timing T 1 .
  • the host apparatus 2 writes the operating frequency f 3 and operation timing T 1 as the operating conditions in the register 9 of each electronic device 4 .
  • FIG. 20 illustrates a packet 60 that is issued by the host apparatus 2 at this point.
  • a command identifier corresponding to the register write command is stored in a packet header 61
  • the operating frequency f 3 and the operation timing T 1 are stored in a payload 62 .
  • the operating frequency f 3 and the operation timing T 1 are sequentially written in the register of each electronic device 4 by transmitting the packet 60 (Steps S 16 - 1 to S 16 -N).
  • the packet 60 may be transmitted by the broadcast, unicast, or multicast.
  • the configuration set in Step S 16 may include a length of a specific symbol, a kind of the packet supported, power control mode, and the number of retry times in addition to the maximum operating frequency and the operation timing.
  • Step S 17 of FIG. 2 will be described below.
  • the operating conditions common to all the electronic devices 4 are determined in the sequences in Steps S 15 and S 16 .
  • a transfer block size and the like depend on an individual I/O device. Accordingly, the host apparatus 2 reads the capability of the electronic devices 4 using the unicast command when the electronic device 4 has the parameter that should individually be set (Steps S 17 A- 1 , S 17 A- 1 , . . . , and S 17 A-N of FIG.
  • the host apparatus 2 determines the optimum value satisfying both the capability of the host apparatus 2 and the capability of the electronic device 4 , and the host apparatus 2 sets the optimum value to the electronic device 4 using the unicast command (Steps S 17 B- 1 , S 17 B- 1 , . . . , and S 17 B-N of FIG. 2 ).
  • Examples of the parameter include a size of a buffer used in the data transfer and data transfer timing.
  • the speed enhancement of the initialization operation can be achieved in the semiconductor device of the first embodiment.
  • the host apparatus 2 determines the bus interface that can be connected to the electronic device 4 can be used by detecting the voltage level (Step S 10 of FIG. 2 ). That is, the host apparatus 2 transmits the level STB to the electronic device 4 , and the host apparatus 2 determines that the bus interface can be used when the level STB is returned from the electronic device 4 . In other words, host apparatus 2 determines that the bus interface can be used by detecting that the signal D 1 changes from the in-phase level to the differential level after the signal D 0 changes from the in-phase level to the differential level.
  • the electronic device 4 When the host apparatus 2 transmits the level STB to the electronic device 4 , the electronic device 4 detects that the signal D 0 changes from the in-phase level to the differential level, and the electronic device 4 determines that the bus interface can be used.
  • the availability of the bus interface can be determined at high speed by detecting the voltage levels of the signals D 0 and D 1 .
  • the host apparatus 2 transmits the symbol SYN, whereby each electronic device 4 synchronizes the internal clock using the input symbol SYN.
  • the electronic device 4 continuously output the level STB during the clock synchronization by the internal PLL, and the electronic device 4 outputs the symbol SYN in synchronization with the clock when the clock synchronization is completed.
  • the host apparatus 2 recognizes that the synchronization is completed for all the electronic devices 4 .
  • the host apparatus 2 transmits a symbol IDLE after receiving the symbol SYN (time t 4 of FIG. 3 ).
  • the symbol IDLE is a symbol indicating that the host apparatus 2 is in an idle state.
  • the electronic device 4 that retains the boot code voluntarily transmits the boot code to the host apparatus 2 without waiting for the command from the host apparatus 2 (Step S 12 of FIG. 2 ).
  • the host controller directly loads the boot code from the boot device onto the system memory, it is not necessary that the host apparatus 2 generate the command, and the boot ROM is omitted, which allows the achievement of cost reduction. Accordingly, in the host apparatus 2 , the system is quickly started up, and the speed enhancement of the initialization can be achieved in the electronic device 4 .
  • the host apparatus 2 broadcasts the packet in order to make the request of the device ID of each electronic device 4 (Step S 13 of FIG. 2 ).
  • the packet is transferred among the electronic devices 4 in the order of connection while the device ID is issued in each electronic device 4 .
  • the device ID in the packet is updated every time the packet passes through the electronic device 4 , and the updated value becomes the device ID of each electronic device 4 . Accordingly, the device IDs do not overlap each other. Therefore, it is not necessary that the host apparatus 2 confirm the presence or absence of the overlap between the device IDs, so that the initialization operation can be simplified.
  • the initialization is performed using the broadcast command similarly to the allocation of the device ID (Step S 14 ). Accordingly, the speed enhancement of the initialization can be achieved.
  • the number of commands issued by the host apparatus 2 can be decreased to simplify the initialization sequence.
  • the plural electronic devices are simultaneously initialized by one command, which allows the shortening of the initialization time.
  • the host apparatus 2 determines the number of electronic devices 4 that are simultaneously initialized. Usually the current of 100 mA is maximally required to initialize one electronic device 4 . However, there is a restriction to current supply ability of the host apparatus. Therefore, the host apparatus 2 stores the number of electronic devices that can be initialized in the packet including the initialization command, and the host apparatus 2 simultaneously initializes the electronic devices as many as the number of electronic devices stored in the packet. The electronic devices 4 are sequentially initialized in the numerical unit, which allows the initialization to be performed in a short time within the current supply ability of the host apparatus 2 .
  • the method in which the group number is used can be adopted to further improve the initialization speed.
  • the initialization current is restricted up to 100 mA, sometimes the initialization time can be shortened when the larger current is passed.
  • the electronic devices to be initialized are divided into groups to which the current can be supplied by the host system, the group number is previously written in the electronic device, the number of issued initialization command is counted, and the electronic device starts the initialization when the count value is matched with the group number. Therefore, the host system can more efficiently customize the initialization.
  • the common operating conditions satisfying both the host apparatus 2 and the electronic device 4 are determined based on the capabilities of the host apparatus 2 and electronic device 4 (Steps S 15 and S 16 of FIG. 2 ).
  • the maximum operating frequency is determined by specifications of the bus.
  • the bus frequency is extremely increased, the bus frequency is hardly supported on the electronic device side or the host apparatus side.
  • Only the speed enhancement of the bus means very little for the memory device, and the data transfer rate should be determined according to write or read ability of the memory device. For example, because the ability of the memory device is restricted by memory ability, disadvantageously power consumption is increased even if the bus operating frequency is increased to enhance the bus interface speed.
  • the common operating conditions satisfying both the host apparatus 2 and the electronic device 4 are determined by referring to the capabilities of the host apparatus 2 and electronic device 4 . Therefore, the optimum operating condition can be set to at least part of the operating ability, and the operating ability of the semiconductor system 1 can be improved.
  • the operating condition is transmitted to the plural electronic devices 4 using the broadcast command, so that the speed enhancement of the initialization can be archived compared with the case in which the operating condition is determined in each electronic device 4 .
  • the operating condition of the electronic device 4 is individually determined (Step S 17 of FIG. 2 ). Accordingly, the electronic device 4 can sufficiently exert the operating ability. That is, while the operating conditions that should be communalized are determined in Step S 15 and S 16 , the point that is not necessary to be communalized is determined in Step S 17 . The operating conditions are individually determined, which allows each electronic device 4 to exert the excellent operating ability independently of the abilities of other electronic devices 4 .
  • Step S 14 of the first embodiment is performed by another method. Because other configurations of the second embodiment are similar to those of the first embodiment, the description is omitted.
  • a first example will be described as another method for performing the processing in Step S 14 .
  • electronic devices 4 - 1 to 4 -N are previously classified into groups.
  • the group number is provided to each group, and the group number is written in a register 9 of the electronic device 4 .
  • the operation may be performed in Step S 14 or Step S 13 , or the operation may previously be performed during production.
  • the number of power units M that can be used to initialize the electronic device 4 by the host apparatus 2 is used instead of the maximum number of electronic devices M that can be initialized at one time.
  • the number of power units M is a value that expresses power (electric power) that can be used for the initialization in a certain unit, and the host apparatus 2 consumes the predetermined number of power units when each electronic device 4 is initialized.
  • An initialization completion flag CF (Completion Flag) is also used in addition to the group and the number of power units M.
  • the initialization completion flag CF is set to “1” when the initialization is completed for all the electronic devices 4 , and, otherwise, the initialization completion flag CF is set to a value except “1” (for example, “0”).
  • Step S 14 the host apparatus 2 produces a packet 70 illustrated in FIG. 21 to transmit the packet 70 to a semiconductor device 3 .
  • the command identifier indicating the initialization command is included in a packet header 71 of the packet 70 , and a group number CC, the number of power units M, and the initialization completion flag CF are included as an argument in a payload.
  • the packet 70 is issued as the broadcast command.
  • FIG. 22 is a flowchart illustrating an operation of the electronic device 4 in receiving the packet 70 , and the flowchart of FIG. 22 is common to the electronic devices 4 - 1 to 4 -N.
  • the electronic device 4 receives the packet 70 at an input signal pin 5 (Step S 50 ).
  • a packet decoder 7 When recognizing that the packet includes the initialization command from the command identifier of the packet header 71 of the received packet 70 , a packet decoder 7 notifies a processing unit 8 that the packet includes the initialization completion confirming command, and the packet decoder 7 also notifies the processing unit 8 of the group number CC, the number of power units M, and the initialization completion flag CF in the payload.
  • the processing unit 8 determines whether the electronic device 4 is currently being initialized (Step S 51 ). When the electronic device 4 is currently being initialized (YES in Step S 51 ), the processing unit 8 waits for the initialization completion (Step S 52 ). The processing unit 8 does not perform the initialization (Step S 53 ), and the processing unit 8 transmits the packet 70 to the next electronic device 4 (in the case of the electronic device 4 -N, host apparatus 2 ) (Step S 60 ). At this point, a packet update circuit 10 does not update the number of power units M and initialization completion flag CF in the packet 70 .
  • Step S 51 When the electronic device 4 is not currently being initialized (NO in Step S 51 ), and when the electronic device 4 has been already initialized (YES in Step S 54 ), the flow goes to Steps S 53 and S 60 . At this point, the number of power units M and initialization completion flag CF are not updated in the packet 70 .
  • the processing unit 8 commands the packet update circuit 10 to clear the initialization completion flag CF in the payload to “0” (Step S 55 ).
  • the initialization completion flag CF is cleared to “0”
  • the host apparatus 2 recognizes that the issuance of the initialization command is continuously required (this point described later).
  • the processing unit 8 also confirms the group number CC in the payload (Step S 56 ).
  • the processing unit 8 determines whether the group number CC is matched with its group number GN stored in a register 9 .
  • the processing unit 8 compares the number of power units M in the payload and the number of power units P consumed in initializing the electronic device 4 (Step S 57 ).
  • the number of power units P for each electronic device 4 may be written in the register 9 of each electronic device 4 .
  • the processing unit 8 compares the number of power units P in the register 9 and the number of power units M in the payload of the received packet.
  • the number of power units P may be written in the register 9 in Step S 14 or Step S 13 , or the processing may previously be performed during production.
  • the processing unit 8 determines whether (M ⁇ P) is not lower than zero, that is, whether the number of power units M is not lower than the number of power units P.
  • (M ⁇ P) is not lower than zero, that is, when the number of power units M is not lower than the number of power units P (YES in Step S 57 )
  • the processing unit 8 commands the packet update circuit 10 to update the number of power units M in the payload to (M ⁇ P) (Step S 58 ).
  • the value of (M ⁇ P) indicates a difference in which the power consumed by the electronic device 4 is subtracted from the power that can be supplied by the host apparatus 2 , and the value of (M ⁇ P) also indicates the number of power units, which is necessary for other electronic devices to perform simultaneously the initialization.
  • the processing unit 8 starts the initialization (Step S 59 ). After the initialization is started, the processing unit 8 causes the packet update circuit 10 to transmit the packet 70 whose the number of power units M and completion flag are updated to the next electronic device 4 (in the case of the electronic device 4 -N, to the host apparatus 2 ) without waiting for the initialization completion (Step S 60 ).
  • Step S 60 When the group numbers CC and GN are not matched with each other (NO in Step S 56 ), the processing unit 8 goes to Step S 60 without performing the initialization (Step S 53 ). That is, the packet 70 is transmitted without updating the number of power units M.
  • the processing unit 8 also goes to Step S 60 without performing the initialization (Step S 53 ), when (M ⁇ P) is lower than zero, that is, when the number of power units M is lower than the number of power units P (NO in Step S 57 ).
  • the plural numbers of power units P can be implemented in the electronic device 4 .
  • the plural numbers of implementable power units P are previously written in the register 9 , and the pieces of processing in Steps S 57 to S 58 and the initialization can be performed using the numbers of power units P.
  • the electronic device 4 can select the optimum number of power units P with respect to a power unit M indicated in the initialization command
  • FIG. 23 is a flowchart illustrating the operation of the host apparatus 2 .
  • the host apparatus 2 sets the group number initial value CC to zero while setting the initialization completion flag CF to 1 (Step S 70 ).
  • the host apparatus 2 sets the group number CC, the initialization completion flag CF, and the number of power units M to the argument to assemble the packet 70 , and the host apparatus 2 transmits the packet 70 by the broadcast command (Step S 71 ).
  • the host apparatus 2 receives the packet 70 that passes through all the electronic devices 4 (Step S 72 ).
  • the host apparatus 2 confirms whether the initialization completion flag CF is 1 in the received packet 70 (Step S 73 ).
  • the host apparatus 2 determines that the initialization is completed for all the electronic devices 4 , and the initialization is ended.
  • Step S 74 the host apparatus 2 determines whether the number of power units M included in the received packet 70 differs from the value of the transmission of the packet 70 .
  • Step S 74 the host apparatus 2 determines that all the electronic devices 4 belonging to the group number CC have already started the initialization or that the initialization is completed for all the electronic devices 4 , the host apparatus 2 increments the group number CC (Step S 75 ), the host apparatus 2 sets the initialization completion flag CF to 1, and the host apparatus 2 goes to Step S 71 to issue the initialization command again.
  • Step S 74 the host apparatus 2 determines that possibly the electronic device 4 belonging to the group number does not start the initialization yet, the host apparatus 2 sets the initialization completion flag CF to 1 while leaving the group number CC as it is (Step S 76 ), and the host apparatus 2 goes to Step S 71 to issue the initialization command again.
  • the host apparatus 2 can confirm whether the initialization is completed for all the electronic devices 4 by checking the initialization completion flag CF of the received packet 70 .
  • the initialization command to initialize the electronic device 4 and the initialization completion confirming command to confirm whether the initialization is completed for all the electronic devices 4 are unified in the first example.
  • a command to confirm the initialization completion of the electronic device 4 may separately be issued.
  • the packet illustrated in FIG. 21 is used as the initialization completion confirming command by setting the group number CC to a predetermined value.
  • the electronic device that is not currently being initialized instantaneously outputs the command, while the electronic device that is currently being initialized outputs the command after waiting for the initialization completion.
  • the host apparatus 2 recognizes that the initialization is completed for one group. The host apparatus 2 repeatedly transmits the packet 70 including the initialization command while changing the group number CC until all the electronic devices 4 are initialized.
  • the initialization command can also be issued before the device ID is allocated to the electronic device 4 .
  • FIG. 24 and FIG. 25 are block diagrams of the semiconductor system 1
  • square marks added to the side of the arrow between the electronic devices indicate the payload 72 of the packet 70 , that is, group number CC, the number of power units M, and the initialization completion flag CF in the order from the left.
  • the host apparatus 2 transmits the packet 70 while the initialization is not performed yet to any electronic devices 4 .
  • the host apparatus 2 sets the group number CC to zero while setting the initialization completion flag CF to 1, and the host apparatus 2 issues the packet 70 . It is assumed that 4 is the number of power units M.
  • the packet 70 is received by the electronic device 4 - 1 .
  • the processing unit 8 of the electronic device 4 - 1 performs the initialization (Step S 59 ).
  • the processing unit 8 transmits packet 70 to the next electronic device 4 - 2 .
  • the electronic devices 4 - 3 and 4 - 4 perform the similar processing.
  • the electronic device 4 - 5 receives the packet 70 from the electronic device 4 - 4 .
  • the packet 70 is returned from the electronic device 4 - 15 to the host apparatus 2 .
  • the electronic device 4 - 1 transmits the packet 70 to the next electronic device 4 - 2 without changing the argument.
  • the electronic devices 4 - 2 to 4 - 4 perform the similar processing.
  • the electronic device 4 - 5 that receives the packet 70 from the electronic device 4 - 4 updates the initialization completion flag CF to 0 (Step S 55 ), because of CCGN (NO in Step S 56 ), the electronic device 4 - 5 does not perform the initialization (Step S 53 ), and the electronic device 4 - 5 transmits the packet 70 to the next electronic device 4 - 6 without updating the number of power units M.
  • the electronic devices 4 - 6 to 4 - 15 perform the similar processing.
  • the packet 70 is returned from the electronic device 4 - 15 to the host apparatus 2 .
  • FIG. 25 illustrates this state.
  • the host apparatus 2 receives the packet 70 having the value of M identical to that in the transmission. Therefore, the host apparatus 2 transmits the packet 70 whose group number CC is updated. Then the electronic devices 4 - 9 to 4 - 12 and the electronic devices 4 - 13 to 4 - 15 are similarly initialized.
  • FIG. 26 to FIG. 30 are block diagrams of the semiconductor system 1
  • square marks added to the arrow between the electronic devices indicate the payload of the packet 70 , that is, group number CC, the number of power units M, and the initialization completion flag CF in the order from the left.
  • the number of power units P and the group number GN of each electronic device are illustrated in FIG. 26 .
  • the host apparatus 2 transmits the packet 70 while the initialization is not performed yet to any electronic devices 4 .
  • the host apparatus 2 sets the group number CC to zero while setting the initialization completion flag CF to 1, and the host apparatus 2 issues the packet 70 . It is assumed that 3 is the number of power units M.
  • the electronic device 4 - 1 that first receives the packet 70 updates the initialization completion flag CF of the packet 70 from 1 to 0 (Step S 55 ). Because of CC ⁇ GN (NO in Step S 56 ), the electronic device 4 - 1 transmits the packet 70 to the electronic device 4 - 2 without updating the value of M. The electronic device 4 - 2 performs the similar processing. After the initialization is ended (Step S 52 ), the electronic device 4 - 3 transmits the packet 70 without updating the value of M. Because of CC ⁇ GN in the electronic device 4 - 4 (NO in Step S 56 ), the electronic device 4 - 4 returns the packet 70 to the host apparatus 2 without performing the initialization.
  • the electronic device 4 - 1 that first receives the packet 70 directly transfers the packet 70 to the electronic device 4 - 2 (YES in Step S 54 ).
  • the electronic device 4 - 2 directly transfers the packet 70 to the electronic device 4 - 3 .
  • the electronic device 4 - 3 also directly transfers the packet 70 to the electronic device 4 - 4 (YES in Step S 54 ).
  • the electronic device 4 - 4 directly transfers the packet 70 to the host apparatus 2 .
  • the group number CC of the first example is removed from the packet 70 . That is, similarly to the first embodiment, the initialization may be performed in the order from the electronic device 4 located closer to the host apparatus 2 . In this case, the processing in Step S 56 in FIG. 22 is removed in the operation of the electronic device 4 , and the operation associated with the group number CC in FIG. 23 is removed in the operation of the host apparatus 2 .
  • the electronic device 4 - 4 starts the initialization.
  • the host apparatus 2 can recognize whether the initialization is completed by the packet 70 .
  • the initialization completion confirming command may be used irrespective of the initialization command.
  • a third example will be described below.
  • a packet 90 illustrated in FIG. 31 is used in the first example.
  • the host apparatus 2 uses the packet 90 illustrated in FIG. 31 both in performing the initialization and in confirming the initialization completion.
  • the packet 90 includes a command identifier 91 , an S/C identifier 92 , and a group number 93 .
  • the command identifier 91 is shared by the initialization command and the initialization completion confirming command.
  • the S/C identifier 92 has a value of “0” or “1”.
  • the S/C identifier 92 indicates the initialization when having the value of “0”, and the S/C identifier 92 indicates the initialization completion confirmation when having the value of “1”. That is, the electronic device 4 that receives the packet 90 can determine the packet 90 is the initialization command or the initialization completion confirming command by the value of the S/C identifier 92 .
  • the packet 90 can also be applied to the second example. In such cases, the group number CC can be removed.
  • a fourth example will be described below.
  • the electronic devices 4 instead of allocating the group number GN to each electronic device 4 , the electronic devices 4 are classified into groups by the number of times in which the packet including the initialization command is received.
  • the electronic devices 4 - 1 to 4 - 4 are configured to perform the initialization in receiving the packet including the initialization command at the first time
  • the electronic devices 4 - 5 to 4 - 8 are configured to perform the initialization in receiving the packet at the second time
  • the electronic devices 4 - 9 to 4 - 12 are configured to perform the initialization in receiving the packet at the third time
  • the electronic devices 4 - 13 to 4 - 16 are configured to perform the initialization in receiving the packet at the fourth time.
  • this information is stored in the register 9 .
  • the timing at which the information is stored in the register 9 may be Step S 14 or Step S 13 , or the timing may exist during production.
  • the electronic device 4 that receives the packet including the initialization command increments the number of receiving times and retains the number of receiving times in the register 9 .
  • the processing unit 8 determines whether the incremented number of receiving times is matched with the number of receiving times stored in the register 9 . When the incremented number of receiving times is matched with the number of receiving times stored in the register 9 , the processing unit 8 performs the initialization and transmit the packet to the next electronic device 4 . When the incremented number of receiving times is not matched with the number of receiving times stored in the register 9 , the processing unit 8 transmits the packet to the next electronic device 4 without performing the initialization.
  • the operation associated with the group number CC in FIG. 23 is removed in the operation of the host apparatus 2 .
  • the electronic devices 4 - 1 to 4 - 4 are initialized when the host apparatus 2 initially transmits the packet including the initialization command.
  • the electronic devices 4 - 5 to 4 - 8 are initialized when the host apparatus 2 transmits the packet at the second time.
  • the electronic devices 4 - 9 to 4 - 12 are initialized when the host apparatus 2 transmits the packet at the third time.
  • the electronic devices 4 - 13 to 4 - 15 are initialized when the host apparatus 2 transmits the packet at the fourth time.
  • the initialization completion confirming command is not required. However, the initialization completion confirming command may be used. In this case, the operation of the electronic device 4 is similar to that in FIG. 14 .
  • the electronic device 4 - 3 is initialized when the host apparatus 2 initially transmits the packet including the initialization command.
  • the electronic device 4 - 1 is initialized when the host apparatus 2 transmits the packet at the second time.
  • the electronic devices 4 - 2 and 4 - 4 are initialized when the host apparatus 2 transmits the packet at the third time (electronic devices 4 - 2 and 4 - 4 are allocated to the group having the number of receiving times (in other words, GN) of 2).
  • the number of receiving times in each electronic device 4 is incremented every time the electronic device 4 receives the initialization command. Accordingly, it is necessary that the host system allocate the group to the electronic device 4 such that all the electronic devices 4 belonging to the groups can start the initialization in response to one initialization command. That is, it is necessary to perform the grouping in consideration of the number of power units P necessary to initialize the electronic devices 4 . More specifically, the number of electronic devices 4 belonging to one group (the number of receiving times) is selected such that the total number of power units ⁇ P necessary to initialize all electronic devices 4 belonging to the group does not exceed the number of power units M that can be used by the host apparatus 2 .
  • Step S 14 of the first embodiment can be performed by the above-described method.
  • the effect similar to that of the first embodiment is obtained in the second embodiment.
  • the third embodiment relates to an operation in performing re-initialization in the first and second embodiments. Because other configurations and operations are similar to those of the first and second embodiments, the description is omitted.
  • FIG. 32 is a block diagram illustrating a host apparatus 2 and one of electronic devices 4 , and particularly illustrating a configuration relating to a power supply line.
  • the host apparatus 2 includes voltage generation circuits 26 - 1 and 26 - 2 .
  • the voltage generation circuit 26 - 1 generates a voltage VDD 1
  • the voltage generation circuit 26 - 2 generates a voltage VDD 2 .
  • the voltages VDD 1 and VDD 2 are supplied as a power supply voltage to the electronic device 4 .
  • the electronic device 4 is operated based on the voltages VDD 1 and VDD 2 .
  • the electronic device 4 roughly includes a controller 27 , a device unit 28 , and a regulator 29 .
  • the device unit 28 performs main functions (such as a memory function and a wireless LAN function) of the electronic device 4 .
  • the controller 27 has a function of performing interface processing with the host apparatus 2 and a function of controlling the device unit 28 .
  • the controller 27 corresponds to the controller 30 illustrated in FIG. 6 of the first embodiment
  • the device unit 28 corresponds to the NAND type flash memory 31 illustrated in FIG. 6 .
  • the regulator 29 regulates the voltages VDD 1 and/or VDD 2 to produce a voltage VDD 3 (for example, 1.2 V) lower than the voltages VDD 1 and VDD 2 .
  • the device unit 4 is operated with the voltage VDD 1 as the power supply voltage.
  • the controller 27 is operated with the voltage VDD 3 , produced by the regulator 29 , as the power supply voltage.
  • a circuit block that performs the interface processing with the host apparatus 2 is operated with the voltage VDD 3 as the power supply voltage, and the voltage VDD 3 is also provided as the power supply voltage to a register 9 .
  • the register 9 includes an initialization flag.
  • the initialization flag includes a flag VDD 2 ON and a flag DIDA.
  • the initialization flag will be described in detail with reference to FIG. 33 .
  • FIG. 33 illustrates the initialization flag and an operation of the host apparatus 2 according to the initialization flag.
  • the flag VDD 2 ON indicates the state of the voltage VDD 2 .
  • the flag VDD 2 ON is information indicating whether supply stop of the voltage VDD 2 is occurred after the last initialization with respect to the electronic device 4 .
  • the flag DIDA indicates whether the allocation of the device ID is required.
  • the power supply voltage of the register 9 is the voltage VDD 3 that is obtained by regulating the voltage VDD 2 . Accordingly, the information in the register 9 is not deleted as long as the voltage VDD 2 is supplied even if the supply of the voltage VDD 1 is stopped. Specifically, the device ID in each electronic device 4 , capability information, the operating condition set in Steps S 16 and S 17 of FIG. 2 , and the initialization flag are maintained as long as the supply of the voltage VDD 2 is stopped.
  • first re-initialization is recovery from a power-down mode
  • second re-initialization is initialization performed to only one electronic device. The first initialization and the second initialization will be described in detail with reference to FIG. 2 .
  • the procedure of re-initializing only one electronic device is supported in the semiconductor system 1 of the third embodiment. In this case, not the broadcast command but the unicast command is used.
  • a specific electronic device is reset by a reset command, the electronic device returns to the state in which the allocation of the device ID is completed in Step S 13 (Step S 18 of FIG. 2 ).
  • Only the specific electronic device 4 is initialized by a unicast initialization command
  • the host apparatus 2 supplies the two kinds of the power supply voltages VDD 1 and VDD 2 to the electronic device 4 .
  • the reason for supplying the low-voltage power supply VDD 2 is that the semiconductor system meets the speed enhancement of the operation.
  • the high-voltage power supply VDD 1 is used in the device unit 28 in the electronic device 4
  • the low-voltage power supply VDD 2 (the power supply VDD 3 produced by regulating the power supply VDD 2 ) is used in the communication between the controller 27 and the host apparatus 2 .
  • the information in the register 9 is not deleted as long as the low-voltage power supply VDD 2 is supplied. Accordingly, in a period in which the electronic device 4 is not used, the supply of the high-voltage power supply VDD 1 can be stopped to reduce the power consumption.
  • the information in the register 9 can be used. Accordingly, the pieces of processing in Step S 12 to S 17 of FIG. 2 can be omitted. That is, it is not necessary to perform the re-initialization sequence, but the electronic device 4 can be returned to the usable state. Accordingly, the electronic device 4 can quickly recover from the power-down state.
  • the host apparatus 2 refers to the flag DIDA and the flag VDD 2 ON by way of example. However, it is not always necessary to provide the flag DIDA and the flag VDD 2 ON.
  • the host apparatus 2 performs the initialization sequence of FIG. 2 again in case where the host apparatus 2 shut down the second power supply voltage VDD 2 after the initialization, and the host apparatus 2 omits the initialization sequence of FIG. 2 when the host apparatus 2 did not shut down the second power supply voltage VDD 2 .
  • the host apparatus 2 may issue an initial command after recovering the first power supply voltage VDD 1 and may detect response time-out.
  • the time-out of the response means the state in which the electronic device 4 cannot be used yet, that is, the host apparatus 2 can determine that the second power supply voltage VDD 2 is shut down in past time. At this point, the host apparatus 2 performs a power cycle to perform the re-initialization.
  • the reset command is roughly classified into two kinds.
  • the command (CMD 0 ) resets only an upper layer that processes the SD command.
  • the layer is roughly divided into a physical layer, a link layer, and a transaction layer.
  • the physical layer is an I/O cell unit based on the LVDS technology.
  • the physical layer performs serial-parallel conversion of an LVDS signal to obtain a frequency that can be operated in the LSI.
  • 8B10B coding is used.
  • the link layer performs processing in units of symbol (for example, 1 symbol is 2 bytes). That is, for example, the link layer is involved in encode and decode of the symbol, and symbol synchronization.
  • the transaction layer performs packet-based transmission, and the transaction layer is involved in communication by a command-response described in the packet, transfer of the packetized data, and protocol-based management.
  • An interval between SOP (Start of Packet) and EOP (End of Packet) is the packet.
  • Another command is Full_Reset. According to the command Full_Reset, all the layers are initialized to put the electronic device 4 in the state immediately after the power-on. In this case, therefore, the initialization sequence is required.
  • the command CMD 0 is also issued during the initialization.
  • the fourth embodiment relates to various connection methods of an electronic device 4 in the first to third embodiments.
  • the description of the same point as the first to third embodiments is omitted.
  • FIG. 34 is a block diagram illustrating an example of a semiconductor system 1 according to the first connection example of the fourth embodiment.
  • the semiconductor system 1 includes a host apparatus 2 , electronic devices 4 - 1 to 4 - 3 , and a hub 100 .
  • the hub 100 includes four ports P 1 to P 4 , and a packet is transferred in the order from ports P 1 to P 4 .
  • the host apparatus 2 is connected to the port P 1 of the hub 100 , and electronic devices 4 - 1 to 4 - 3 are connected to the ports P 2 to P 4 , respectively.
  • the configurations and operations of the host apparatus 2 and electronic devices 4 are described in the first to fourth embodiments. Similarly to the first embodiment of FIG. 11 , square marks of FIG.
  • Step S 14 indicate a field 42 - 1 (start device ID) and a field 42 - 2 (the number of devices) of a payload for the purpose of a flow of the packet.
  • the packet-flow illustrated in FIG. 34 is similarly applied to the processing of Step S 14 .
  • the flow of the packet transmitted by the host apparatus 2 will be described below.
  • the packet is transmitted to the hub 100 , and the hub 100 transfers the packet to the electronic device 4 - 1 .
  • the electronic device 4 - 1 returns the packet to the hub 100 after performing necessary processing.
  • the hub 100 transfers the packet received from the electronic device 4 - 1 to the electronic device 4 - 2 .
  • the electronic device 4 - 2 returns the packet to the hub 100 after performing necessary processing.
  • the hub 100 transfers the packet received from the electronic device 4 - 2 to the electronic device 4 - 3 .
  • the electronic device 4 - 3 returns the packet to the hub 100 after performing necessary processing.
  • the hub 100 returns the packet received from the electronic device 4 - 3 to the host apparatus 2 .
  • FIG. 35 is a block diagram of a semiconductor system 1 according to the second connection example of the fourth embodiment.
  • the second connection example relates to a two-stage hub connection.
  • the semiconductor system 1 includes a host apparatus 2 , electronic devices 4 - 1 to 4 - 5 , and hubs 100 - 1 and 100 - 2 .
  • each of the hubs 100 - 1 and 100 - 2 includes four ports P 1 to P 4 , and the packet is transferred in the order from ports P 1 to P 4 .
  • the host apparatus 2 is connected to the port P 1 of the hub 100 - 1
  • electronic devices 4 - 1 and 4 - 5 are connected to the ports P 2 and P 4 , respectively
  • the port P 1 of the hub 100 - 2 is connected to the port P 3 .
  • the electronic devices 4 - 2 to 4 - 4 are connected to the ports P 2 to P 4 of the hub 100 - 2 , respectively.
  • FIG. 35 The configurations and operations of the host apparatus 2 and electronic device 4 are described in the first to third embodiments. Similarly to the first embodiment of FIG. 11 , square marks of FIG. 35 indicate a field 42 - 1 (initial value of a device ID) and a field 42 - 2 (the number of devices) of a payload for the purpose of a flow of the packet.
  • the packet-flow illustrated in FIG. 35 is similarly applied to the processing of Step S 14 .
  • the hub 100 - 1 receives the packet from the host apparatus 2 , and the hub 100 - 1 transfers the packet to the electronic device 4 - 1 .
  • the electronic device 4 - 1 returns the packet to the hub 100 - 1 .
  • the hub 100 - 1 transmits the packet received from the electronic device 4 - 1 to the hub 100 - 2 .
  • the hub 100 - 2 transmits the packet received from the hub 100 - 1 to the electronic device 4 - 2 .
  • the electronic device 4 - 2 returns the packet to the hub 100 - 2 .
  • the hub 100 - 2 transmits the packet received from the electronic device 4 - 2 to the electronic device 4 - 3 .
  • the electronic device 4 - 3 returns the packet to the hub 100 - 2 .
  • the hub 100 - 2 transmits the packet received from the electronic device 4 - 3 to the electronic device 4 - 4 .
  • the electronic device 4 - 4 returns the packet to the hub 100 - 2 .
  • the hub 100 - 2 returns the packet received from the electronic device 4 - 4 to the hub 100 - 1 .
  • the hub 100 - 1 transmits the packet received from the hub 100 - 2 to the electronic device 4 - 5
  • the electronic device 4 - 5 returns the packet to the hub 100 - 1 .
  • the hub 100 - 1 returns the packet received from the electronic device 4 - 5 to the host apparatus 2 .
  • the configurations of the first to third embodiments can be applied to not only the ring connection but also the hub connection, and the effect similar to that of the first to third embodiments is obtained in the fourth embodiment.
  • the hub 100 originally has the function of transferring the packet to the electronic device 4 when the packet is broadcasted from the host apparatus 2 . Accordingly, it is not necessary for the host apparatus 2 to understand the connection relationship among the plural electronic devices 4 .
  • a semiconductor system and an electronic device initializing method according to a fifth embodiment will be described below.
  • the fifth embodiment relates to specific examples of the first to fourth embodiments. Hereinafter, the description of the same point as the first to third embodiments is omitted.
  • FIG. 36 is a block diagram illustrating an example of a memory system according to the fifth embodiment.
  • a memory system 110 includes a host controller 111 , a card slot 112 , a CPU (central processing unit) 113 , a system memory 114 , electronic devices 4 - 1 to 4 - 4 , and a hub 100 .
  • the CPU 113 controls the whole operation of the memory system 110 , and the CPU 113 is operated according to a program stored in a ROM (Read Only Memory, not illustrated).
  • the system memory 114 is used in order that the CPU 113 temporarily stored various pieces of data in the system memory 114 , and the system memory 114 is used to execute the executable program.
  • the host controller 111 corresponds to the host apparatus 2 of the first to fourth embodiments.
  • the host controller 111 includes various pieces of hardware and software, various protocols, and the like, which are necessary to conduct communication with a device (element) possibly connected to the host controller 111 .
  • the host controller 111 is configured to be able to communicate with the electronic devices 4 through a plurality of signal lines. Examples of the signal line include a signal line through which a packet is transferred, a signal line through which a clock is transferred, and a power supply line (VDD 1 and VDD 2 , described previously). Part of the function of the host controller 111 outputs and captures the signals on the signal lines according to previously-set rules.
  • the host controller 111 analyzes the signal supplied through the signal line to recognize a previously-set bit pattern from the signal, and the host controller 111 captures a command from the signal. Similarly the host controller 111 recognizes a predetermined bit pattern to capture data from the signal. There are prepared various commands defined in the host controller 111 .
  • the host controller 111 can be implemented by part of the function of the CPU, which is executed under the control of the software, or a semiconductor chip such the functions can be realized.
  • the host controller 111 supports the signal lines D 0 and D 1 through which the packet is transferred and the signal line through which the clock RCLK are transferred. That is, the host controller 111 is configured to transfer the data using these signal lines. More specifically, the host controller 111 is configured to be able to control, for example, the SD interface.
  • the electronic devices 4 - 1 to 4 - 4 are incorporated in the memory system 110 . Any type of device configured to be able to communicate with the CPU 113 through the host controller 111 can be used as the electronic devices 4 - 1 to 4 - 4 .
  • a memory device and a wireless LAN (Local Area Network) device can be cited as an example of the device.
  • a main part of the device that can be used as the electronic devices 4 - 1 to 4 - 4 can be implemented by a well-known technology according to the function of each of the electronic devices 4 - 1 to 4 - 4 .
  • the electronic devices 4 - 1 to 4 - 4 can be implemented using the semiconductor chip sealed in a portable device such as the SD card.
  • the electronic devices 4 - 1 to 4 - 4 include device units 28 - 1 to 28 - 4 in order to perform main functions (such as a memory function and a wireless LAN function) of the electronic devices 4 - 1 to 4 - 4 , respectively.
  • the electronic devices 4 - 1 to 4 - 4 also include controllers (device controller) 27 - 1 to 27 - 4 , respectively.
  • controllers 27 - 1 to 27 - 4 is configured to be able to communicate with the CPU 113 through the host controller 111 using an interface. That is, each of the controllers 27 - 1 to 27 - 4 includes hardware and software configurations in order to support the interface.
  • the controllers 27 - 1 to 27 - 4 are configured to support the SD interface as well.
  • the controllers 27 - 1 to 27 - 4 may be implemented as the CPU and/or the semiconductor chip, which is independent of the device units 28 - 1 to 28 - 4 .
  • a semiconductor chip in which the controller 27 - 1 to 27 - 4 and the device units 28 - 1 to 28 - 4 are integrated may be implemented.
  • each of the controllers 27 - 1 to 27 - 4 includes an input signal pin 5 , an output signal pin 6 , a packet decoder 7 , a processing unit 8 , a register 9 , and a packet update circuit 10 .
  • the electronic devices 4 - 1 and 4 - 2 are memory devices.
  • the electronic devices 4 - 1 and 4 - 2 include the NAND type flash memories as device units 28 - 1 and 28 - 2 .
  • the NAND type flash memory includes a plurality of pages as a storage region. Each page includes a plurality of memory cell transistors connected in series. Each memory cell transistor is formed by a so-called stacked gate structure type MOS transistor.
  • the stacked gate structure type MOS transistor includes a gate electrode and a source/drain diffusion layer. A tunnel insulator, a charge accumulation layer (such as floating gate electrode), an inter-electrode insulator, and a control gate electrode are sequentially stacked in the gate electrode.
  • a control circuit includes a memory sense amplifier and a potential generating circuit.
  • the control circuit has a configuration in which multi-bit data can be written in and read from the memory cell transistor.
  • the data write and read are performed units of pages.
  • Data deletion is performed in units of blocks each of which includes a plurality of pages.
  • the electronic devices 4 - 3 and 4 - 4 are SD IO devices, and the electronic devices 4 - 3 and 4 - 4 have the wireless LAN functions as the device units 28 - 3 and 28 - 4 .
  • a removable card type electronic device 4 - 5 (hereinafter referred to as a card device 4 - 5 ) can be inserted in and pulled out from the card slot 112 .
  • the card device 4 - 5 includes a memory system and other devices that are supported by the card slot 112 .
  • the card slot 112 includes terminals to be connected to the card device 4 - 5 , and lines in the interface are connected to the corresponding terminals.
  • terminals necessary for the SD interface are provided in the card slot 112 .
  • the card device 4 - 5 includes all the card devices, which can communicates with the host controller 111 through the SD interface, such as the SD memory card and the SDIO card.
  • the card device 4 - 5 is the SD memory card.
  • the card device 4 - 5 includes a controller 27 - 5 and a device unit 28 - 5 .
  • the controller 27 - 5 includes the input signal pin 5 , the output signal pin 6 , the packet decoder 7 , the processing unit 8 , the register 9 , and the packet update circuit 10 .
  • the device unit 28 - 5 includes the NAND type flash memory. The configuration of the device unit 28 - 5 is similar to that of the device units 28 - 1 and 28 - 2 .
  • the electronic device 4 - 1 receives the packet transmitted from the host controller 111 , the electronic device 4 - 1 transfers the packet to the electronic device 4 - 2 , the electronic device 4 - 2 transfers the packet to the electronic device 4 - 3 , the electronic device 4 - 3 transfers the packet to the electronic device 4 - 4 , and the electronic device 4 - 4 transfers the packet to the hub 100 .
  • the hub 100 transfers the packet transferred from the electronic device 4 - 4 to the card slot 112 if needed, thereby providing the packet to the card device 4 - 5 inserted in the card slot 112 .
  • the packet output from the output signal pin 6 of the card device 4 - 5 and/or the packet output from the output signal pin 6 of the electronic device 4 - 4 are returned to the host controller 111 through the hub 100 .
  • the first to fourth embodiments can be applied to the configuration of the fifth embodiment.
  • a semiconductor system and an electronic device initializing method according to a sixth embodiment will be described below.
  • the first to fifth embodiments are applied to a semiconductor system including single electronic device.
  • FIG. 37 is a block diagram of a semiconductor system 1 according to the sixth embodiment. As illustrated in FIG. 37 , the semiconductor system 1 includes one electronic device 4 .
  • the electronic device 4 is the SD memory card.
  • the memory card 4 includes a NAND flash memory chip (sometimes simply referred to as a NAND flash memory or a flash memory) 28 , a memory controller 27 that controls the NAND flash memory chip 28 , and a plurality of signal pins (first pin to seventeenth pin) 29 .
  • a NAND flash memory chip sometimes simply referred to as a NAND flash memory or a flash memory
  • a memory controller 27 that controls the NAND flash memory chip 28
  • a plurality of signal pins first pin to seventeenth pin
  • FIG. 38 illustrates an example of allocation of signals to the first pin to seventeenth pin in the plurality of signal pins 29 .
  • FIG. 38 is a table illustrating the first pin to seventeenth pin and the signals allocated to the first pin to the seventeenth pin.
  • the seventh pin, eighth pin, ninth pin, and first pin are allocated to data 0 to data 3 , respectively.
  • the first pin is also allocated to a card detection signal.
  • the second pin is allocated to a command CMD, the third pin and the sixth pin are allocated to a ground potential GND, the fourth pin is allocated to the power supply voltage VDD 1 described above, and the fifth pin is allocated to the clock signal RCLK.
  • the tenth pin, thirteenth pin, fourteenth pin, and seventeenth pin are allocated to the power supply voltage VDD 2 described above or ground potential GND.
  • the eleventh pin, twelfth pin, fifteenth pin, and sixteenth pin are allocated to the data (D 1 +), data (D 1 ⁇ ), the data (D 0 ⁇ ), and data (D 0 +).
  • the data (D 1 +) and data (D 1 ⁇ ), and the data (D 0 ⁇ ) and data (D 0 +) are pairs of the differential signals described above, respectively.
  • the signal pair D 0 + and D 0 ⁇ is used for the signal transmission from the host apparatus 2 to the electronic device 4 .
  • the signal pair D 1 + and D 1 ⁇ is used for the signal transmission from the electronic device 4 to the host apparatus 2 .
  • the memory card 4 is formed so as to be able to be inserted in and pulled out from the slot provided in the host apparatus 2 .
  • a host controller (not illustrated) which is provided in the host apparatus 2 transmits and receives various signals and data to and from the memory controller 27 in the electronic device 4 through the first pin to seventeenth pin. For example, when the data is written in the memory card 4 , the host controller transmits a write command as a serial signal to the memory controller 27 through the eleventh and twelfth pins. At this point, the memory controller 27 captures the write command provided to the eleventh and twelfth pins in response to the clock RCLK supplied to the seventh and eighth pins.
  • the write command is serially input to the memory controller 27 using only the eleventh and twelfth pins.
  • the eleventh and twelfth pins allocated to the command input are disposed as illustrated in FIG. 38 .
  • the plurality of signal pins 29 and the bus interface 120 associated with the pins 29 are used in order that the host controller in the host apparatus 2 and the memory card 4 communicate with each other.
  • the communication between the NAND type flash memory 28 and the memory controller 27 is conducted by a NAND flash memory interface. Accordingly, although not illustrated here, the NAND flash memory 28 and the memory controller 27 are connected by, for example, an 8-bit input and output (I/O) line.
  • I/O input and output
  • the memory controller 27 corresponds to the controllers 27 and 30 of the first to fifth embodiments
  • the NAND flash memory 28 corresponds to the device units 28 and 31 of the first to fifth embodiments.
  • the operations of the first to third embodiments can be performed by the configuration of the sixth embodiment.
  • the plurality of electronic devices 4 and the host apparatus 2 which simultaneously initializes the electronic devices 4 in units of group are included. Therefore, the initialization speed of the electronic device 4 can be enhanced.
  • the word “simultaneously” mean “simultaneously” in terms of time, but the word “simultaneously” means that, for example, the plurality of electronic devices 4 are initialized by one packet issued by the host apparatus.
  • the electronic devices 4 - 1 to 4 - 4 are collectively initialized by the one-time issuance of the packet 52 .
  • the temporally simultaneous initialization may be included.
  • the electronic device 4 starts the initialization with the reception of the packet as a trigger. At this point, the electronic device 4 that receives the packet to start the initialization transmits the packet to the next electronic device 4 without waiting for the initialization completion.
  • the period during which the plurality of electronic devices 4 simultaneously perform the initialization exists when the time necessary for the initialization is longer than the packet transmission time.
  • the electronic device 4 when receiving the packet during the initialization, the electronic device 4 waits for the initialization completion, and the electronic device 4 transmits the packet to the next electronic device after the completion. Accordingly, it is necessary that the host apparatus wait for the packet for a finite period of time until the packet returns to the host apparatus.
  • the initialization has been already started by the last packet, plurality of electronic devices 4 simultaneously perform the initialization, and there is a restriction (maximum time) to the time necessary for the initialization of each electronic device 4 . Therefore, even if the number of electronic devices 4 is increased, the host apparatus does not wait for the packet for a long time.
  • the initialization is completed for all the electronic devices 4 .
  • the semiconductor system 1 includes the plurality of electronic devices 4 and the host apparatus 2 .
  • the host apparatus 2 supplies the first power supply voltage VDD 1 and the second power supply voltage VDD 2 lower than the first power supply voltage VDD 1 to the electronic devices 4 , and the host apparatus 2 can initialize the electronic devices 4 .
  • Each of the electronic devices 4 includes the device unit 28 and the controller unit 27 .
  • the device unit 28 operates using the first power supply voltage VDD 1 .
  • the controller unit 27 operates using the second power supply voltage VDD 2 , and the controller unit 27 performs the interface processing with the host apparatus 2 .
  • the controller unit 27 includes the register 9 which retains the operating condition information between the host apparatus 2 and the electronic devices 4 .
  • the operating condition information in the register 9 is retained in the period in which the second power supply voltage VDD 2 is supplied, even if the first power supply voltage VDD 1 is shut down.
  • both the signals D 0 + and D 0 ⁇ have the “L” level when the semiconductor system 1 is in the dormant state.
  • the signals D 0 + and D 0 ⁇ may have the “H” level.
  • the signal D 0 + or D 0 ⁇ may change to the “L” level by the transmission of the symbol STB, thereby detecting that the signal D 0 changes to the differential level. The same holds true for the signal D 1 .
  • the embodiments can be applied to devices such as a UHS (Ultra High Speed)-II card which transfer the data at high speed.
  • UHS Ultra High Speed
  • the memory structure of the electronic device 4 is not limited to the NAND flash memory, but memory structures of a NOR flash memory and a semiconductor memory except the flash memory may be used as the memory structure of the electronic device 4 .
  • the transfer of the boot code (Step S 12 ) and the allocation of the device ID (Step S 13 ) can be interchanged.
  • the processing in Step S 12 can be performed before the processing in Step S 13 as illustrated in FIG. 2 .
  • the electronic device 4 may make a request to issue the read command to the host apparatus 2 . That is, the electronic device 4 that retains the boot code makes a request to read the boot code to the host apparatus 2 immediately after the power-on.
  • the host apparatus 2 reads the boot code from the electronic device 4 in response to the request.
  • the processing in Step S 13 is performed before the processing in Step S 12 when the read command is issued from the side of the electronic device 4 .
  • the flowchart can be performed by hardware, software, or a combination thereof.
  • a program corresponding to the flowchart is stored in the ROM, and the processor such as the CPU executes the program to perform the operation described in the flowchart.

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TWI567561B (zh) * 2015-11-26 2017-01-21 新唐科技股份有限公司 匯流排系統
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JP2022049599A (ja) * 2020-09-16 2022-03-29 キオクシア株式会社 通信システム、デバイス及び通信方法
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