WO2019165804A1 - 驱动控制方法、组件及显示装置 - Google Patents

驱动控制方法、组件及显示装置 Download PDF

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Publication number
WO2019165804A1
WO2019165804A1 PCT/CN2018/116430 CN2018116430W WO2019165804A1 WO 2019165804 A1 WO2019165804 A1 WO 2019165804A1 CN 2018116430 W CN2018116430 W CN 2018116430W WO 2019165804 A1 WO2019165804 A1 WO 2019165804A1
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WO
WIPO (PCT)
Prior art keywords
configuration
point
data
configuration data
indicator
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PCT/CN2018/116430
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English (en)
French (fr)
Inventor
于淑环
段欣
罗信忠
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/339,419 priority Critical patent/US11455926B2/en
Priority to EP18863789.6A priority patent/EP3761296A4/en
Publication of WO2019165804A1 publication Critical patent/WO2019165804A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/06—Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell
    • H03M5/12—Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/04—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller
    • G09G2370/045—Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller using multiple communication channels, e.g. parallel and serial
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/10—Use of a protocol of communication by packets in interfaces along the display data pipeline
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/14—Use of low voltage differential signaling [LVDS] for display data communication

Definitions

  • the present disclosure relates to the field of panel manufacturing, and more particularly to a drive control method, assembly, and display device.
  • the display device may generally include a display panel and a panel driving circuit for driving the display panel.
  • the driving circuit may include a timing controller (TCON) and a source driving circuit, and the source driving circuit includes a plurality of source driver chips.
  • the two signal lines include: a first signal line and a second signal line.
  • the signal transmission rate of the first signal line is smaller than the second signal line.
  • the first signal line can be referred to as a low speed signal line and is typically used to transmit configuration instructions.
  • the second signal line can be referred to as a high speed signal line and is typically used to transmit high speed differential signals.
  • a point-to-point high-speed signal transmission technology is generally used for signal transmission, which is characterized in that a one-to-one second signal line is established between the timing controller and the source driver chip to transmit a high-speed differential signal.
  • the timing controller is also provided with an additional first signal line.
  • a plurality of source driver chips are connected in parallel and are connected to the first signal line.
  • the first signal line is configured to transmit a configuration command to perform transmission of the high speed differential signal in conjunction with the second signal line.
  • the transmission efficiency of the first signal line described above is low, and the utilization rate of the first signal line is low.
  • the present disclosure provides a drive control method, assembly, and display device.
  • a drive control method for use in a timing controller.
  • the timing controller communicates with a plurality of source driver chips connected in parallel through a first signal line.
  • the method includes: generating a point-to-point configuration instruction, the point-to-point configuration instruction comprising: n configuration data, n ⁇ 2; transmitting, by the first signal line, the point-to-point configuration instruction to a first source driving chip, where a source driving chip is any one of the plurality of source driving chips; receiving, by the first signal line, a configuration response instruction sent by the first source driving chip according to the point-to-point configuration instruction, the configuration
  • the response instruction includes configuration response data for each of the n configuration data.
  • the peer-to-peer configuration instruction includes: an address for the n configuration data, a first indicator, and a data portion.
  • the first indicator is configured to indicate whether the addresses for the n configuration data are continuous.
  • the data portion carries the n configuration data.
  • the address for the n configuration data includes the first address and the last address in the consecutive addresses.
  • the point-to-point configuration command further includes a second indicator.
  • the second indicator is used to indicate the number of configuration data in the point-to-point configuration command.
  • the point-to-point configuration instruction includes at least five bytes.
  • the first indicator includes a fifth one of the third of the at least five bytes.
  • the second indicator includes a sixth to eighth bit of the third byte.
  • the timing controller is respectively connected to the plurality of source driving chips in a one-to-one correspondence by using a plurality of second signal lines, and the timing controller and the first source driving chip pass the plurality of Of the second signal lines, the target second signal lines are assigned to the first source driver chip shown.
  • the method further includes: transmitting, by the allocated second signal line, a start instruction to the first source driving chip, the start instruction being used to indicate the point-to-point configuration instruction The maximum number of configuration data carried.
  • the start instruction includes at least seven bytes. Four of the seventh of the at least seven bytes are used to indicate the maximum number.
  • each of the point-to-point configuration instruction and the configuration response instruction includes: a preamble, a start identifier, a data body, and an end identifier that are sequentially arranged.
  • the preamble includes: a first signal of at least eight consecutive bit periods, each of the bit periods being two microseconds.
  • the initial identifier includes: a continuous second signal of at least two of the bit periods.
  • the data body includes: the n configuration data or the n configuration response data.
  • the end identifier includes: a continuous third signal of at least two of the bit periods.
  • the first signal, the second signal, the n configuration data, and configuration response data thereof are all obtained by Manchester coding.
  • a drive control method for use in a first source driver chip.
  • the first source driving chip is any one of a plurality of source driving chips.
  • the plurality of source driving chips are connected in parallel and communicate with the timing controller through a first signal line.
  • the method includes: receiving a point-to-point configuration instruction sent by the timing controller by using the first signal line, where the point-to-point configuration instruction comprises: n configuration data for a first source driving chip, n ⁇ 2;
  • the point-to-point configuration instruction sends a configuration response instruction to the timing controller through the first signal line, the configuration response instruction comprising: configuration response data of each configuration data of the n configuration data.
  • the peer-to-peer configuration instruction includes: the address, the first indicator, and the data part for the n configuration data.
  • the method further includes: acquiring a value of the first indicator, where the first indicator is used And indicating whether the address for the n configuration data is continuous, the data portion carries the n configuration data; and acquiring a target address from the address for the n configuration data according to the value of the first indicator
  • the address for n configuration data includes: a first address and a last address in consecutive addresses
  • the acquired target address includes: a continuous address defined by the first address and the last address; when the first indicator indicates that the address for the n configuration data is discontinuous, the acquired target address includes An address of each of the n configuration data; acquiring the n configuration data carried by the data part according to the reference information, where the reference information includes the target Site.
  • the point-to-point configuration command further includes a second indicator.
  • the method further includes: acquiring a value of the second indicator, where the second indicator is used to indicate the point-to-point configuration instruction Configuring the number of data; determining the number according to the value of the second indicator, the reference information further including the number.
  • the point-to-point configuration instruction includes at least five bytes.
  • the first indicator includes a fifth one of the third of the at least five bytes.
  • the second indicator includes a sixth to eighth bit of the third of the at least five bytes.
  • the timing controller is respectively connected to the plurality of source driving chips in a one-to-one correspondence by using a plurality of second signal lines, and the timing controller and the first source driving chip pass the plurality of The second signal line of the second signal line is connected to the target second signal line of the first source driving chip.
  • the method further includes: receiving the timing controller to pass the allocated second signal line And a start instruction sent to indicate a maximum number of configuration data carried by the point-to-point configuration command.
  • the start instruction includes at least seven bytes. Four of the seventh of the at least seven bytes are used to indicate the maximum number.
  • each of the point-to-point configuration instruction and the configuration response instruction includes: a preamble, a start identifier, a data body, and an end identifier that are sequentially arranged.
  • the preamble includes: a first signal of at least eight consecutive bit periods, each of the bit periods being two microseconds.
  • the initial identifier includes: a continuous second signal of at least two of the bit periods.
  • the data body includes: the n configuration data or the n configuration response data.
  • the end identifiers each include: a continuous third signal of at least two of the bit periods.
  • the first signal, the second signal, the n configuration data, and configuration response data thereof are all obtained by Manchester coding.
  • a drive control assembly for use in a timing controller.
  • the timing controller communicates with a plurality of source driver chips connected in parallel through a first signal line.
  • the driving control component includes: a generating module, configured to generate a point-to-point configuration command, where the point-to-point configuration command includes: n configuration data, n ⁇ 2; and a first sending module, configured to go to the first through the first signal line.
  • the source driving chip transmits the point-to-point configuration command, the first source driving chip is any one of the plurality of source driving chips, and the receiving module is configured to receive the first through the first signal line And a configuration response instruction sent by the source driver chip according to the point-to-point configuration instruction, the configuration response instruction comprising: configuration response data for each of the n configuration data.
  • the peer-to-peer configuration instruction includes: the address, the first indicator, and the data part for the n configuration data.
  • the first indicator is configured to indicate whether the address for the n configuration data is continuous, and the data part carries the n configuration data.
  • the address for n configuration data includes a first address and a last address in consecutive addresses.
  • the point-to-point configuration instruction further includes a second indicator, the second indicator is used to indicate the number of configuration data in the point-to-point configuration instruction.
  • the point-to-point configuration instruction includes at least five bytes.
  • the first indicator includes a fifth one of the third of the at least five bytes.
  • the second indicator includes a sixth to eighth bit of the third byte.
  • the timing controller is respectively connected to the plurality of source driving chips in a one-to-one correspondence by using a plurality of second signal lines, and the timing controller and the first source driving chip pass the plurality of Of the second signal lines, the target second signal lines are assigned to the first source driver chip shown.
  • the driving control component further includes: a second transmitting module, configured to send a start instruction to the first source driving chip by using the allocated second signal line, where the starting instruction is used to indicate the point-to-point configuration instruction The maximum number of configuration data carried.
  • the start instruction includes at least seven bytes. Four of the seventh of the at least seven bytes are used to indicate the maximum number.
  • each of the point-to-point configuration instruction and the configuration response instruction includes: a preamble, a start identifier, a data body, and an end identifier that are sequentially arranged.
  • the preamble includes: a first signal of at least eight consecutive bit periods, each of the bit periods being two microseconds.
  • the initial identifier includes: a continuous second signal of at least two of the bit periods.
  • the data body includes: the n configuration data or the n configuration response data.
  • the end identifier includes: a continuous third signal of at least two of the bit periods.
  • the first signal, the second signal, the n configuration data, and configuration response data thereof are all obtained by Manchester coding.
  • a drive control assembly for use in a first source drive chip.
  • the first source driving chip is any one of a plurality of source driving chips.
  • the plurality of source driving chips are connected in parallel and communicate with the timing controller through a first signal line.
  • the driving control component includes: a first receiving module, configured to receive a point-to-point configuration instruction sent by the timing controller by using the first signal line, where the point-to-point configuration instruction includes: n for the first source driving chip a configuration module, n ⁇ 2; a sending module, configured to send, by using the first signal line, a configuration response instruction according to the point-to-point configuration instruction, where the configuration response instruction includes: the n configuration data Configuration response data for each configuration data.
  • the peer-to-peer configuration instruction includes: the address, the first indicator, and the data part for the n configuration data.
  • the driving control component further includes: a first obtaining module, configured to acquire a value of the first indicator, the first indicator is used to indicate whether the address for the n configuration data is continuous, the data part Carrying the n configuration data; the second obtaining module is configured to acquire a target address from the address for the n configuration data according to the value of the first indicator, where the first indicator is used to indicate
  • the addresses for the n configuration data are consecutive
  • the address for the n configuration data includes: a first address and a last address in the consecutive addresses
  • the acquired target address includes: by the first a consecutive address defined by the address and the last address;
  • the acquired target address includes: each of the n configuration data An address of the configuration data, where the third obtaining module is configured to acquire the n configuration data carried by the data part according to the reference information, where the reference
  • the point-to-point configuration command further includes a second indicator.
  • the driving control component further includes: a fourth acquiring module, configured to acquire the second indicator, the second indicator is used to indicate the number of configuration data in the point-to-point configuration command; and a determining module is configured to The value of the second indicator determines the number, and the reference information further includes the number.
  • the point-to-point configuration instruction includes at least five bytes.
  • the first indicator includes a fifth one of the third of the at least five bytes.
  • the second indicator includes: a sixth to eighth bit of the third byte of the at least five bytes.
  • the timing controller is respectively connected to the plurality of source driving chips in a one-to-one correspondence by using a plurality of second signal lines, and the timing controller and the first source driving chip pass the plurality of The second signal line of the second signal line is connected to the target second signal line of the first source driving chip.
  • the driving control component further includes: a second receiving module, configured to receive a start instruction sent by the timing controller by the allocated second signal line, where the start instruction is used to indicate that the point-to-point configuration command is carried The maximum number of configuration data.
  • the start instruction includes at least seven bytes. Four of the seventh of the at least seven bytes are used to indicate the maximum number.
  • each of the point-to-point configuration instruction and the configuration response instruction includes: a preamble, a start identifier, a data body, and an end identifier that are sequentially arranged.
  • the preamble includes: a first signal of at least eight consecutive bit periods, each of the bit periods being two microseconds.
  • the initial identifier includes: a continuous second signal of at least two of the bit periods.
  • the data body includes: the n configuration data or the n configuration response data.
  • the end identifiers each include: a continuous third signal of at least two of the bit periods.
  • the first signal, the second signal, the n configuration data, and configuration response data thereof are all obtained by Manchester coding.
  • a drive control component comprising a memory, a processor, and a computer program stored on the memory and operable on the processor, the processor executing the computer program to implement the first aspect The steps of the method.
  • a drive control component comprising a memory, a processor, and a computer program stored on the memory and operable on the processor, the processor executing the computer program to implement the second aspect The steps of the method.
  • a computer readable storage medium having stored thereon a computer program, the program being executed by a processor to implement the steps of the method of the first aspect and the second aspect.
  • a display device in an eighth aspect, includes: a timing controller and a source driving chip; the timing controller includes the driving control component according to the third aspect or the fifth aspect, wherein the source driving chip includes the fourth aspect or the sixth aspect The drive control component described.
  • a chip comprising programmable logic circuitry and/or program instructions for implementing the method of the first aspect when the chip is in operation.
  • a chip comprising programmable logic circuitry and/or program instructions for implementing the method of the second aspect when the chip is in operation.
  • FIG. 1 is a schematic diagram of an application environment of a driving control method according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of an instruction transmitted on a first signal line according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic flowchart diagram of a driving control method according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic flow chart of another driving control method provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic flowchart diagram of still another driving control method according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a driving control component according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of another driving control component according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of still another driving control component according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of still another driving control component according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a driving control component according to another embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of another driving control component according to another embodiment of the present disclosure.
  • the panel driving circuit includes a first signal line and a second signal line.
  • the timing controller can transmit a configuration command through the first signal line to perform transmission of the high speed differential signal in conjunction with the second signal line.
  • the configuration command includes: a preamble, a start identifier, data, and an end identifier. Since each instruction transmitted by the first signal line carries less data, multiple data needs to be transmitted through multiple instructions, and the preamble, the start identifier, and the end identifier that need to be transmitted during the transmission of multiple instructions are more Therefore, the transmission efficiency and utilization rate of the first signal line are low.
  • Embodiments of the present disclosure provide a driving control method that can improve transmission efficiency and utilization of a first signal line.
  • FIG. 1 is a schematic diagram of an application environment of a driving control method according to an embodiment of the present disclosure.
  • the drive control method is applied to a display device.
  • the display device includes a timing controller 01 and a plurality of source driving chips 02.
  • the timing controller 01 is connected to the plurality of source driving chips 02 via a plurality of second signal lines H, respectively.
  • the timing controller 01 is connected to the plurality of source driving chips 02 in one-to-one correspondence through a plurality of second signal lines H, wherein the signals in the second signal lines are unidirectionally transmitted.
  • the timing controller is also connected to a first signal line L.
  • a plurality of source driving chips 02 are connected in parallel and connected to the first signal line L to communicate with the timing controller.
  • the signals in the first signal line are transmitted bidirectionally.
  • the first signal line L can perform transmission of different instructions to implement different data transmission functions.
  • Each data transmission function corresponds to at least one transmission mode.
  • the timing controller can implement a function of transmitting a broadcast configuration command to the source driver chip through the first signal line, that is, setting an initialization program in all the source driver chips.
  • This function corresponds to the broadcast communication (BC) mode, that is, the broadcast communication mode instructs the timing controller to perform data broadcasting.
  • the timing controller can also send an identity configuration instruction to the source driver chip through the first signal line to implement a function of transmitting an identity (ID) for the source driver chip.
  • the function corresponds to an identity assignment (IA) mode, that is, the identity assignment mode indicates that the timing controller assigns an identity to the source driver chip.
  • IA identity assignment
  • the timing controller can also send a point-to-point (also called end-to-end) configuration instruction to the source driving chip through the first signal line to implement a point-to-point control function on the source driving chip, and the function corresponds to downlink communication;
  • the DC) mode that is, the downlink AC mode, instructs the timing controller to perform point-to-point data transmission to the source driver chip.
  • the source driving chip may send a control response instruction for the point-to-point configuration instruction to the timing controller through the first signal line, or send an identity configuration response instruction for the identity configuration instruction to the timing controller through the first signal line.
  • the function corresponds to a reply transaction (RT) mode, that is, the reply transfer mode indicates that the source driver chip responds to the command of the timing controller.
  • RT reply transaction
  • the timing controller can sequentially perform operations such as identity assignment of the source driver chip, read/write operation of the data, and data feedback of the source driver chip. It should be noted that the driving control method provided by the embodiment of the present disclosure may be used in a DC mode.
  • FIG. 2 is a schematic diagram of an instruction transmitted on a first signal line according to an embodiment of the present disclosure. As shown in FIG. 2, each instruction transmitted on the first signal line includes a preamble, a start identifier, a data body (also referred to as a transmission body), and an end (stop). ) Identification.
  • the preamble is used to indicate the clock and phase calibration at the receiving end.
  • the receiving end timing controller or source driving chip
  • the clock and phase adjustment are performed according to the content of the preamble.
  • Clock and phase adjustment means that the clock at the receiving end is kept the same as the clock at the transmitting end, and the phase is the same as the transmitting end.
  • the receiving end adjusts the clock and phase during the reception of the preamble. After the preamble transmission is completed, the clock and phase are adjusted.
  • the start identifier is used to indicate the start of data transmission
  • the data body is used to carry configuration data
  • the end identifier is used to indicate the end of data transmission.
  • the preamble may be composed of signals comprising regularly changing transition edges.
  • the preamble can include consecutive first signals of at least eight bit periods, and each bit period is two microseconds.
  • the start identifier may include: a second signal of at least two consecutive bit periods.
  • the end identification may include: a third signal of at least two consecutive bit periods.
  • the first signal, the second signal, the configuration data carried by the data body, and the configuration response data thereof can all be obtained by Manchester coding (such as the second version of Manchester code MII).
  • the level transition of the first signal is from low to high
  • the level transition of the second signal is from low to high
  • the level transition of the third signal is high to low. It can be understood that in addition to the Manchester encoding, the start identifier and the end marker can also adopt other forms of signals agreed by the transmitting end and the receiving end, including signals that maintain a low level or a high level for a specified time.
  • the first bit of the configuration data in the data body may generate a hop edge with the start identifier (ie, the configuration data in the data body).
  • the first bit is different from the last digit of the start identifier. For example, the first bit of the configuration data in the data body is 1, and the last digit of the start identifier is 0).
  • the last bit of the configuration data in the data body may generate a hop edge with the end identifier (ie, the first bit value of the last bit and the end tag of the configuration data in the data body is different. For example, the last bit of the configuration data in the data body is 0, the last digit of the end marker is 1).
  • the above transition edge can facilitate the effective identification of data at the receiving end.
  • Manchester coding can be used to realize data transmission, thereby enriching the function of the first signal line and improving the utilization of the first signal line.
  • the configuration data carried by the data body of the point-to-point configuration command may include: an identifier of the first source driving chip, and the first source driving chip needs The address of the configured register, the type of operation, and the data corresponding to the operation indicated by the operation type.
  • the register can be used to store configuration data received by the first source driver chip.
  • the first source driver chip retrieves configuration data from different register addresses for different operations.
  • FIG. 3 is a schematic flowchart diagram of a driving control method according to an embodiment of the present disclosure. This drive control method can be applied to the timing controller in FIG.
  • the timing controller communicates with a plurality of source driver chips connected in parallel through a first signal line. As shown in FIG. 3, the method includes:
  • Step 301 Generate a point-to-point configuration instruction, and the point-to-point configuration instruction includes: n configuration data, n ⁇ 2.
  • Step 302 Send a point-to-point configuration command to the first source driving chip through the first signal line, where the first source driving chip is any one of the plurality of source driving chips.
  • Step 303 Receive, by using the first signal line, a configuration response instruction sent by the first source driving chip according to the point-to-point configuration instruction, where the configuration response instruction includes: configuration response data for each configuration data of the n configuration data.
  • the point-to-point configuration command includes: n configuration data, and n ⁇ 2, that is, one command can carry multiple data.
  • the point-to-point configuration command transmitted to the first source driver chip through the first signal line may include a plurality of configuration data. This reduces the number of instructions when transmitting multiple configuration data, thereby reducing the number of preambles, start identifiers, and end identifiers that need to be transmitted during command transmission, thereby improving data transmission of the first signal line. Efficiency and utilization.
  • FIG. 4 is a schematic flow chart of another driving control method provided by an embodiment of the present disclosure.
  • the driving control method can be applied to the first source driving chip in FIG. 1, and the first source driving chip is any one of a plurality of source driving chips.
  • the plurality of source driving chips are connected in parallel and communicate with the timing controller through a first signal line.
  • the method includes:
  • Step 401 Receive a point-to-point configuration command sent by the timing controller through the first signal line, where the point-to-point configuration command includes: n configuration data for the first source driving chip, where n ⁇ 2.
  • Step 402 Send a configuration response instruction to the timing controller through the first signal line according to the point-to-point configuration instruction, where the configuration response instruction includes: configuration response data of each configuration data in the n configuration data.
  • the point-to-point configuration command includes: n configuration data, and n ⁇ 2, that is, one command can carry multiple data.
  • the point-to-point configuration command received through the first signal line may include a plurality of configuration data, reducing the number of instructions for transmitting when receiving a plurality of configuration data, thereby reducing the number of preambles, start identifiers, and end identifiers that need to be transmitted. Therefore, the data transmission efficiency and utilization rate of the first signal line are improved.
  • FIG. 5 is a schematic flowchart diagram of still another driving control method according to an embodiment of the present disclosure.
  • the drive control method can be applied to the application environment in FIG. It is assumed that the first source driving chip is any one of a plurality of source driving chips.
  • the timing controller may be respectively connected to the plurality of source driving chips in a one-to-one correspondence through the plurality of second signal lines.
  • the timing controller communicates with the first source driving chip through a second signal line allocated to the first source driving chip among the plurality of second signal lines.
  • the method can include:
  • Step 501 The timing controller sends a start instruction to the first source driving chip through the allocated second signal line.
  • the start command can be used to indicate the maximum number of configuration data in the point-to-point configuration command that the timing controller is about to send.
  • the start instruction may include at least seven bytes, and four of the seventh bytes of the at least seven bytes are used to indicate the maximum number, for example, by fifteen state indication configurations.
  • the fifteen largest number of data may be used.
  • the four bits have sixteen states, one of the sixteen states being inactive, and the remaining fifteen states indicating fifteen largest. For example, when the binary digits stored on the four bits are both 0, the state represented by the four bits may be in an invalid state; or, when the binary digits stored on the four bits are all 1, The state represented by the four bits can be an invalid state.
  • the four bits may also be four bits in other bytes (such as the sixth byte), and the number of the bits may also be other values (such as three bits). The example is not limited to this.
  • Step 502 The timing controller generates a point-to-point configuration instruction.
  • the peer-to-peer configuration command may be, for example, the instruction shown in FIG. 2.
  • the point-to-point pairing instruction may include: an address for configuring data, a first indicator, and a data part.
  • the data portion carries n configuration data, n ⁇ 2.
  • the address for n configuration data may be a register address in the first source driver chip for storing configuration data.
  • the first indicator is for indicating whether the address for the n configuration data is continuous.
  • the data body may further include a second indicator, the second indicator may be used to indicate the number n of configuration data in the point-to-point configuration command.
  • the second indicator can be used to directly determine or check whether the number of configuration data during transmission is accurate, thereby further avoiding omission of configuration data due to errors.
  • the data body can include at least five bytes.
  • the address for n configuration data may be stored in a bit preceding the fifth bit of the third byte of the data body (eg, stored in the second byte).
  • the first indicator can include a fifth one of the third of the at least five bytes.
  • the second indicator can include: a sixth to eighth bit of the third byte.
  • the data portion can be stored in a byte following the third byte of the at least five bytes.
  • the binary number stored in the first indicator is 0, which can be used to indicate that the addresses for the n configuration data are continuous, and the binary number stored in the first indicator is 1 can be used to indicate the n configuration data.
  • the address is not continuous. If the binary digits stored in the sixth to eighth bits of the third byte of the data body are all 1, the number of configuration data indicated by the second indicator is the largest, and the number may be 8. If the binary digits stored in the sixth to eighth bits of the third byte are all 0, the number of configuration data indicated by the second indicator is the smallest, and the number may be 1; The binary digits stored in the sixth to eighth bits of the third byte are 0, 0, and 1, respectively, and the number of configuration data indicated by the second indicator may be 2; and so on. In this way, the number of configuration data indicated by the respective states of the second indicator can be obtained.
  • Step 503 The timing controller sends a point-to-point configuration instruction to the first source driving chip through the first signal line.
  • Step 504 The first source driving chip acquires a value of the first indicator in the received point-to-point configuration command.
  • the first source driver chip can acquire a binary number stored on the fifth bit, the binary The number is the value of the first indicator.
  • Step 505 The first source driver chip acquires a value of the second indicator in the point-to-point configuration command.
  • the first source driver chip can acquire the sixth to eighth bits.
  • the binary digits stored on the sixth to eighth bits are both 0, and the binary digits of the three binary digits are 000, which is the value of the second indicator.
  • Step 506 The first source driving chip determines the number of configuration data in the point-to-point configuration command according to the value of the second indicator.
  • the value of the second indicator acquired by the first source driving chip in step 505 may be the same as the number of configuration data in the point-to-point configuration instruction, but embodiments of the present disclosure are not limited thereto.
  • the value of the second indicator and the number of configuration data in the point-to-point configuration command may also be different as long as there is a predetermined correspondence between the two.
  • the number of configuration data in the point-to-point configuration command indicated by the value of the second indicator 011 may not be 3, but 4.
  • Step 507 The first source driver chip acquires the target address from the address for the n configuration data according to the value of the first indicator.
  • the target address may indicate a register address for storing n configuration data in the configuration instruction.
  • the address for the n configuration data may be: the number in the consecutive addresses. One address and the last address.
  • the address for n pieces of configuration data may be the address of the first configuration data and the address of the last configuration data.
  • the target address can be a contiguous address defined by the first address and the last address.
  • the target address may include: an address of each of the n configuration data . Since the target address acquired by the first source driving chip is different when the addresses for the n configuration data are continuous and discontinuous, and the address for the n configuration data is continuous, the first source driving chip needs to acquire The address is small, so the data transfer rate is faster.
  • the addresses for the three configuration data in the configuration command are 1 and 3.
  • the first source driver chip will obtain addresses 1 and 3 from the configuration command as the head address and the tail address of the target address.
  • the addresses used for the three configuration data are all n addresses corresponding to n data.
  • the first source driver chip will acquire each of the addresses for the n data.
  • Step 508 The first source driver chip acquires n configuration data according to the reference information.
  • the reference information may include: a target address and, optionally, a number of configuration data (ie, a value of n) in the point-to-point configuration instruction. If the addresses for the n configuration data are not continuous, the first source driver chip needs to acquire configuration data corresponding to the address of each configuration data. If the addresses for the n configuration data are consecutive, the first source driver chip only needs to directly acquire the configuration data between the address of the first configuration data of the n configuration data and the address of the last configuration data. At this time, the first source driving chip can quickly acquire all the configuration data, so the efficiency of acquiring the configuration data is high. The number of configuration data can be used to further verify the correctness of the configuration data transmission in the configuration instructions.
  • Step 509 The first source driving chip executes n configuration operations indicated by n configuration data.
  • the configuration data may include: an address of a register to be configured on the first source driver chip, an operation type, and data corresponding to an operation indicated by the operation type.
  • the configuration operation corresponding to the configuration data can be a read operation or a write operation.
  • Step 510 The first source driving chip sends a configuration response instruction to the timing controller through the first signal line according to the point-to-point configuration command.
  • the specific structure of the configuration response instruction may be, for example, the structure of the instruction shown in FIG. 2.
  • the configuration response command may include: configuration response data for each of the n configuration data.
  • the configuration response data of each configuration data may be used to indicate whether the configuration operation indicated by each configuration data is performed. For example, when the configuration operation indicated by a certain configuration data has been completed, the configuration response data corresponding to the configuration data may be 1. When the configuration operation indicated by the configuration data is not completed, the configuration response data corresponding to the configuration data may be 0, and at this time, the timing controller may resend the point-to-point configuration instruction to the first source driver chip.
  • the first source driving chip may send a configuration response instruction to the timing controller through the first signal line after receiving the preset response waiting time after receiving the point-to-point configuration command.
  • the interval length at which the timing controller sends two adjacent instructions may be referred to as a suspend duration or a standby duration.
  • the response waiting time of the first source driving chip may be longer than the suspending time period to prevent the first source driving chip from transmitting the next instruction when an instruction sent by the timing controller is not transmitted, which may cause a line conflict. Therefore, the response wait time can be greater than the suspend duration.
  • the suspend duration can be 10 microseconds (us), and accordingly, the reply wait time is greater than 10 microseconds.
  • the first signal line may be referred to as a bidirectional command channel (BCC) signal line.
  • BCC bidirectional command channel
  • the above point-to-point configuration command and configuration response command may be referred to as a BCC command.
  • the point-to-point configuration command includes: n configuration data, and n ⁇ 2, that is, one command can carry multiple data.
  • the point-to-point configuration command transmitted to the first source driver chip through the first signal line may include a plurality of configuration data. In this way, the number of instructions when transmitting multiple configuration data is reduced, thereby reducing the number of preambles, start identifiers, and end identifiers that need to be transmitted, thereby improving data transmission efficiency and utilization of the first signal line. .
  • FIG. 6 is a schematic structural diagram of a driving control component according to an embodiment of the present disclosure.
  • the drive control component is applied to a timing controller.
  • the timing controller communicates with a plurality of source driver chips connected in parallel through a first signal line.
  • the drive control assembly 60 can include:
  • the generating module 601 is configured to generate a point-to-point configuration command, where the point-to-point configuration command comprises: n configuration data, n ⁇ 2.
  • the first sending module 602 is configured to send a point-to-point configuration command to the first source driving chip by using the first signal line, where the first source driving chip is any one of the plurality of source driving chips.
  • the receiving module 603 is configured to receive, by using the first signal line, a configuration response instruction sent by the first source driving chip according to the point-to-point configuration instruction.
  • the configuration response instruction includes: configuration response data of each configuration data in the n configuration data.
  • the point-to-point configuration command includes: n configuration data, and n ⁇ 2, that is, one command can carry multiple configuration data.
  • the point-to-point configuration command sent by the first transmitting module to the first source driving chip through the first signal line may include a plurality of configuration data. This reduces the number of instructions transmitted when transmitting multiple configuration data, thereby reducing the number of preambles, start identifiers, and end markers that need to be transmitted. Therefore, the data transmission efficiency and utilization of the first signal line are improved. rate.
  • the peer-to-peer configuration instructions include: an address for the n configuration data, a first indicator, and a data portion.
  • the first indicator is used to indicate whether the address for the n configuration data is continuous, and the data portion carries n configuration data.
  • the peer-to-peer configuration command further includes a second indicator.
  • the second indicator is used to indicate the number of configuration data in the point-to-point configuration command.
  • the peer-to-peer configuration instruction includes at least five bytes.
  • the first indicator comprises: a fifth of the third of the at least five bytes.
  • the second indicator includes a sixth to eighth bit of the third byte.
  • FIG. 7 is a schematic structural diagram of another driving control component according to an embodiment of the present disclosure. As shown in FIG. 7, in addition to the modules already shown in FIG. 6, the drive control assembly 60 further includes:
  • the second sending module 604 is configured to send a start command to the first source driving chip by using the target second signal line, where the start command is used to indicate the maximum number of configuration data carried by the point-to-point configuration command.
  • the start instruction includes at least seven bytes, and four of the seventh of the at least seven bytes are used to indicate fifteen maximum numbers by, for example, fifteen states.
  • each of the peer-to-peer configuration command and the configuration response command includes: a preamble, a start identifier, a data body, and an end identifier, which are sequentially arranged,
  • the preamble includes: a first signal of at least eight consecutive bit periods, each bit period being two microseconds.
  • the start identifier includes: a second signal of at least two consecutive bit periods.
  • the end identifier includes: a third signal of at least two consecutive bit periods.
  • the first signal, the second signal, the n configuration data, and the configuration response data thereof are all obtained by Manchester coding, and the level transition of the first signal is from low to high, and the level transition of the second signal is from low to high.
  • the level transition of the third signal is high to low.
  • the point-to-point configuration command includes: n configuration data, and n ⁇ 2, that is, one command can carry multiple configuration data.
  • the point-to-point configuration command sent by the first sending module to the first source driving chip through the first signal line may include a plurality of configuration data, thereby reducing the number of instructions transmitted when transmitting the plurality of configuration data, thereby reducing the need for transmission.
  • the number of preambles, start identifiers, and end markers thus improving the data transmission efficiency and utilization of the first signal line.
  • FIG. 8 is a schematic structural diagram of still another driving control component according to an embodiment of the present disclosure.
  • the drive control assembly is applied to the first source drive chip.
  • the first source driver chip is any one of a plurality of source driver chips.
  • the plurality of source driving chips are connected in parallel, and communicate with the timing controller through a first signal line.
  • the driving control component 80 can include:
  • the first receiving module 801 is configured to receive a point-to-point configuration command sent by the timing controller through the first signal line, where the point-to-point configuration command comprises: n configuration data of the first source driving chip, n ⁇ 2;
  • the sending module 802 is configured to send, by using the first signal line, a configuration response instruction to the timing controller according to the point-to-point configuration instruction, where the configuration response instruction includes: configuration response data of each configuration data in the n configuration data.
  • the point-to-point configuration command includes: n configuration data, and n ⁇ 2, that is, an instruction may carry multiple configuration data.
  • the point-to-point configuration command received by the first receiving module through the first signal line may include a plurality of configuration data, thereby reducing the number of instructions transmitted when receiving the plurality of configuration data, thereby reducing the preamble, the starting identifier, and the transmission required to be transmitted. The number of the identification ends, and therefore, the data transmission efficiency and utilization rate of the first signal line are improved.
  • the peer-to-peer configuration instructions include: an address for the n configuration data, a first indicator, and a data portion.
  • FIG. 9 is a schematic structural diagram of still another driving control component according to an embodiment of the present disclosure.
  • the driving control component 80 further includes:
  • the first obtaining module 803 is configured to obtain a value of the first indicator, where the first indicator is used to indicate whether the address for the n configuration data is continuous, and the data part carries n configuration data;
  • the second obtaining module 804 is configured to acquire a target address in the address for the n configuration data according to the value of the first indicator.
  • the target address includes: an address of the first configuration data among the n configuration data and an address of the last configuration data.
  • the target address includes: an address of each of the n configuration data;
  • the third obtaining module 805 is configured to obtain n configuration data carried in the data part according to the reference information, where the reference information includes a target address.
  • the peer-to-peer configuration command further includes a second indicator.
  • FIG. 10 is a schematic structural diagram of a driving control component according to another embodiment of the present disclosure.
  • the driving control component 80 further includes:
  • a fourth obtaining module 806, configured to acquire a second indicator, where the second indicator is used to indicate the number of configuration data in the point-to-point configuration command;
  • the determining module 807 is configured to determine, according to the value of the second indicator, the number of configuration data in the point-to-point configuration command, where the reference information further includes the number.
  • the peer-to-peer configuration instruction includes at least five bytes.
  • the first indicator comprises: a fifth of the third of the at least five bytes.
  • the second indicator comprises: a sixth to eighth of the third of the at least five bytes.
  • FIG. 11 is a schematic structural diagram of another driving control component according to another embodiment of the present disclosure.
  • the driving control component 80 further includes:
  • the second receiving module 808 is configured to receive a start instruction sent by the timing controller through the target second signal line, where the start instruction is used to indicate the maximum number of configuration data carried by the point-to-point configuration command.
  • the start instruction includes at least seven bytes, and four of the seventh of the at least seven bytes are used to indicate fifteen maximum numbers by fifteen states.
  • each of the peer-to-peer configuration command and the configuration response command includes: a preamble, a start identifier, a data body, and an end identifier, which are sequentially arranged,
  • the preamble includes: a first signal of at least eight consecutive bit periods, each bit period being two microseconds.
  • the start identifier includes: a second signal of at least two consecutive bit periods.
  • the end identifiers each include: a third signal of at least two consecutive bit periods;
  • the first signal, the second signal, the n configuration data, and the configuration response data thereof are all obtained by Manchester coding, and the level transition of the first signal is from low to high, and the level transition of the second signal is from low to high.
  • the level transition of the third signal is high to low.
  • the point-to-point configuration command includes: n configuration data, and n ⁇ 2, that is, one command can carry multiple configuration data.
  • the point-to-point configuration command received by the first receiving module through the first signal line may include a plurality of configuration data. In this way, the number of instructions transmitted when receiving multiple configuration data is reduced, thereby reducing the number of preambles, start identifiers, and end identifiers that need to be transmitted, thereby improving data transmission efficiency and utilization of the first signal line. rate.
  • Another embodiment of the present disclosure provides a further drive control component, including a memory, a processor, and a computer program stored on the memory and operable on the processor, the processor executing the program to implement timing in the above drive control method The steps performed by the controller or source driver chip.
  • the embodiment of the present disclosure further provides a computer readable storage medium having stored thereon a computer program that, when executed by the processor, implements the steps performed by the timing controller or the source driver chip in the above-described drive control method.
  • the computer readable storage medium can be a non-transitory computer readable storage medium.
  • Embodiments of the present disclosure also provide a chip including programmable logic circuits and/or program instructions for implementing the steps of the timing controller or the source driver chip in the above-described drive control method when the chip is in operation.
  • the embodiment of the present disclosure provides a display device, including: a timing controller and a source driver chip, and the connection manner of the two may refer to FIG. 1 described above. Both the timing controller and the source driver chip can include corresponding drive control components.
  • the drive control component in the timing controller is as shown in FIG. 6 or FIG. 7, and the drive control component in the source drive chip is as shown in any of FIGS. 8 to 11.
  • the drive control component in the timing controller includes: a memory, a processor, and a computer program stored on the memory and operable on the processor, and when the processor executes the program, implementing the timing controller execution in the driving control method A step of.
  • the drive control component in the source driver chip includes: a memory, a processor, and a computer program stored on the memory and operable on the processor, the processor executing the program to implement the first source driver in the driving control method The steps performed by the chip.
  • the display device can be any liquid crystal panel, electronic paper, organic light-emitting diode (OLED) panel, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. Or parts.
  • OLED organic light-emitting diode
  • association relationship describing an association object, indicating that there may be three relationships, for example, A and/or B, which may indicate that A exists separately. There are three cases of A and B, and B alone.
  • character "/" in this article generally indicates that the contextual object is an "or" relationship.
  • Modules in various embodiments may be implemented using hardware units, software units, or combinations thereof.
  • hardware units may include devices, components, processors, microprocessors, circuits, circuit components (eg, transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic Devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, and more.
  • ASICs application specific integrated circuits
  • PLDs programmable logic Devices
  • DSPs digital signal processors
  • FPGAs field programmable gate arrays
  • memory cells logic gates, registers, semiconductor devices, chips, microchips, chipsets, and more.
  • Examples of software units may include software components, programs, applications, computer programs, applications, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, Software interface, application programming interface (API), instruction set, calculation code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an embodiment is implemented by using hardware units and/or software units may vary depending on any number of factors desired for a given implementation, such as desired calculation rate, power level, heat resistance, Processing cycle budgets, input data rates, output data rates, memory resources, data bus speeds, and other design or performance constraints.

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Abstract

一种驱动控制方法、组件及显示装置。驱动控制方法应用于时序控制器（01），包括：生成点对点配置指令，点对点配置指令包括：n个配置数据，n≥2（S301）；通过第一信号线向第一源极驱动芯片发送点对点配置指令，第一源极驱动芯片为多个源极驱动芯片（02）中的任意一个（S302）；通过第一信号线（L）接收第一源极驱动芯片根据点对点配置指令发送的配置响应指令，配置响应指令包括：对于n个配置数据中每个配置数据的配置响应数据（S303）。驱动控制方法用于显示面板的信号驱动控制，提高了第一信号线（L）的传输效率与利用率。

Description

驱动控制方法、组件及显示装置
相关申请
本申请要求于2018年3月1日递交的中国专利申请No.201810172362.7的优先权，在此全文引用上述中国专利申请公开的内容作为本申请的一部分。
技术领域
本公开涉及面板制造领域，特别涉及驱动控制方法、组件及显示装置。
背景技术
显示装置一般可以包括显示面板以及用于驱动该显示面板的面板驱动电路。该驱动电路可以包括时序控制器(timer controller；TCON)和源极驱动电路，源极驱动电路包括多个源极驱动(source driver)芯片。
在面板驱动电路中，通常包括两种信号线。该两种信号线包括：第一信号线和第二信号线。第一信号线的信号传输速率小于第二信号线。该第一信号线可称为低速信号线，通常用于传输配置指令。第二信号线可称为高速信号线，通常用于传输高速差分信号。在面板驱动过程中，一般采用点对点的高速信号传输技术来进行信号传输，其特点是在时序控制器和源极驱动芯片之间建立一对一的第二信号线，以传输高速差分信号。另外，时序控制器还设置有额外的一根第一信号线。多个源极驱动芯片并行连接，且都连接到第一信号线上。该第一信号线用于传输配置指令，以配合第二信号线进行高速差分信号的传输。
但是，上述第一信号线的传输效率较低，而且第一信号线的利用率较低。
发明内容
本公开提供了一种驱动控制方法、组件及显示装置。
在第一方面，提供了一种驱动控制方法，应用于时序控制器。所 述时序控制器通过一第一信号线与并行连接的多个源极驱动芯片通信。所述方法包括：生成点对点配置指令，所述点对点配置指令包括：n个配置数据，n≥2；通过所述第一信号线向第一源极驱动芯片发送所述点对点配置指令，所述第一源极驱动芯片为所述多个源极驱动芯片中的任意一个；通过所述第一信号线接收所述第一源极驱动芯片根据所述点对点配置指令发送的配置响应指令，所述配置响应指令包括：对于所述n个配置数据中每个配置数据的配置响应数据。
可选的，所述点对点配置指令包括：用于n个配置数据的地址、第一指示器和数据部分。所述第一指示器用于指示所述用于n个配置数据的地址是否连续。所述数据部分携带所述n个配置数据。
可选的，在所述第一指示器指示所述用于n个配置数据的地址连续时，所述用于n个配置数据的地址包括连续地址中的第一地址和最后一个地址。
可选的，所述点对点配置指令还包括第二指示器。所述第二指示器用于指示所述点对点配置指令中配置数据的个数。
可选的，所述点对点配置指令包括至少五个字节。所述第一指示器包括：所述至少五个字节中第三个字节中的第五个比特位。所述第二指示器包括：所述第三个字节中的第六个至第八个比特位。
可选的，所述时序控制器通过多个第二信号线分别与所述多个源极驱动芯片一一对应连接，且所述时序控制器与所述第一源极驱动芯片通过所述多个第二信号线中的被分配给所示第一源极驱动芯片的目标第二信号线连接。在所述生成点对点配置指令之前，所述方法还包括：通过所述被分配的第二信号线向所述第一源极驱动芯片发送开始指令，所述开始指令用于指示所述点对点配置指令所携带的配置数据的最大个数。
可选的，所述开始指令包括至少七个字节。所述至少七个字节中的第七个字节中的四个比特位用于指示所述最大个数。
可选的，所述点对点配置指令和所述配置响应指令中的每个指令均包括：依次排列的前导码、起始标识、数据主体和结束标识。所述前导码包括：连续的至少八个比特周期的第一信号，每个所述比特周期为两微秒。所述起始标识包括：连续的至少两个所述比特周期的第二信号。所述数据主体包括：所述n个配置数据或所述n个配置响应 数据。所述结束标识包括：连续的至少两个所述比特周期的第三信号。所述第一信号、所述第二信号、所述n个配置数据及其配置响应数据均采用曼彻斯特编码得到。
在第二方面，提供了一种驱动控制方法，应用于第一源极驱动芯片。所述第一源极驱动芯片是多个源极驱动芯片中的任意一个。所述多个源极驱动芯片并行连接，且通过一第一信号线与时序控制器通信。所述方法包括：接收所述时序控制器通过所述第一信号线发送的点对点配置指令，所述点对点配置指令包括：用于第一源极驱动芯片的n个配置数据，n≥2；根据所述点对点配置指令通过所述第一信号线向所述时序控制器发送配置响应指令，所述配置响应指令包括：所述n个配置数据中每个配置数据的配置响应数据。
可选的，所述点对点配置指令包括：所述用于n个配置数据的地址、第一指示器和数据部分。在所述根据所述点对点配置指令通过所述第一信号线向所述时序控制器发送配置响应指令之前，所述方法还包括：获取所述第一指示器的值，所述第一指示器用于指示所述用于n个配置数据的地址是否连续，所述数据部分携带所述n个配置数据；根据所述第一指示器的值从所述用于n个配置数据的地址获取目标地址，其中，当所述第一指示器指示所述用于n个配置数据的地址连续时，所述用于n个配置数据的地址包括：连续地址中的第一个地址和最后一个地址，以及获取的目标地址包括：由所述第一个地址和最后一个地址界定的一段连续地址；当所述第一指示器指示所述用于n个配置数据的地址不连续时，获取的目标地址包括：所述n个配置数据中的每个配置数据的地址；根据参考信息获取所述数据部分携带的所述n个配置数据，所述参考信息包括所述目标地址。
可选的，所述点对点配置指令还包括第二指示器。在所述根据参考信息获取所述数据部分携带的所述n个配置数据之前，所述方法还包括：获取所述第二指示器的值，所述第二指示器用于指示所述点对点配置指令中配置数据的个数；根据所述第二指示器的值确定所述个数，所述参考信息还包括所述个数。
可选的，所述点对点配置指令包括至少五个字节。所述第一指示器包括：所述至少五个字节中第三个字节中的第五个比特位。所述第二指示器包括：所述至少五个字节中第三个字节中的第六个至第八个 比特位。
可选的，所述时序控制器通过多个第二信号线分别与所述多个源极驱动芯片一一对应连接，且所述时序控制器与所述第一源极驱动芯片通过所述多个第二信号线中的分配给所述第一源极驱动芯片的目标第二信号线连接。在所述根据所述点对点配置指令通过所述第一信号线向所述时序控制器发送配置响应指令之前，所述方法还包括：接收所述时序控制器通过所述被分配的第二信号线发送的开始指令，所述开始指令用于指示所述点对点配置指令所携带的配置数据的最大个数。
可选的，所述开始指令包括至少七个字节。所述至少七个字节中的第七个字节中的四个比特位用于指示所述最大个数。
可选的，所述点对点配置指令和所述配置响应指令中的每个指令均包括：依次排列的前导码、起始标识、数据主体和结束标识。所述前导码包括：连续的至少八个比特周期的第一信号，每个所述比特周期为两微秒。所述起始标识包括：连续的至少两个所述比特周期的第二信号。所述数据主体包括：所述n个配置数据或所述n个配置响应数据。所述结束标识均包括：连续的至少两个所述比特周期的第三信号。所述第一信号、所述第二信号、所述n个配置数据及其配置响应数据均采用曼彻斯特编码得到。
在第三方面，提供了一种驱动控制组件，应用于时序控制器。所述时序控制器通过一第一信号线与并行连接的多个源极驱动芯片通信。所述驱动控制组件包括：生成模块，用于生成点对点配置指令，所述点对点配置指令包括：n个配置数据，n≥2；第一发送模块，用于通过所述第一信号线向第一源极驱动芯片发送所述点对点配置指令，所述第一源极驱动芯片为所述多个源极驱动芯片中的任意一个；接收模块，用于通过所述第一信号线接收所述第一源极驱动芯片根据所述点对点配置指令发送的配置响应指令，所述配置响应指令包括：对于所述n个配置数据中每个配置数据的配置响应数据。
可选的，所述点对点配置指令包括：所述用于n个配置数据的地址、第一指示器和数据部分。所述第一指示器用于指示所述用于n个配置数据的地址是否连续，所述数据部分携带所述n个配置数据。
可选的，在所述第一指示器指示所述用于n个配置数据的地址连 续时，所述用于n个配置数据的地址包括连续地址中的第一地址和最后一个地址。
可选的，所述点对点配置指令还包括第二指示器，所述第二指示器用于指示所述点对点配置指令中配置数据的个数。
可选的，所述点对点配置指令包括至少五个字节。所述第一指示器包括：所述至少五个字节中第三个字节中的第五个比特位。所述第二指示器包括：所述第三个字节中的第六个至第八个比特位。
可选的，所述时序控制器通过多个第二信号线分别与所述多个源极驱动芯片一一对应连接，且所述时序控制器与所述第一源极驱动芯片通过所述多个第二信号线中的被分配给所示第一源极驱动芯片的目标第二信号线连接。所述驱动控制组件还包括：第二发送模块，用于通过所述被分配的第二信号线向所述第一源极驱动芯片发送开始指令，所述开始指令用于指示所述点对点配置指令所携带的配置数据的最大个数。
可选的，所述开始指令包括至少七个字节。所述至少七个字节中的第七个字节中的四个比特位用于指示所述最大个数。
可选的，所述点对点配置指令和所述配置响应指令中的每个指令均包括：依次排列的前导码、起始标识、数据主体和结束标识。所述前导码包括：连续的至少八个比特周期的第一信号，每个所述比特周期为两微秒。所述起始标识包括：连续的至少两个所述比特周期的第二信号。所述数据主体包括：所述n个配置数据或所述n个配置响应数据。所述结束标识包括：连续的至少两个所述比特周期的第三信号。所述第一信号、所述第二信号、所述n个配置数据及其配置响应数据均采用曼彻斯特编码得到。
在第四方面，提供了一种驱动控制组件，应用于第一源极驱动芯片。所述第一源极驱动芯片是多个源极驱动芯片中的任意一个。所述多个源极驱动芯片并行连接，且通过一第一信号线与时序控制器通信。所述驱动控制组件包括：第一接收模块，用于接收所述时序控制器通过所述第一信号线发送的点对点配置指令，所述点对点配置指令包括：用于第一源极驱动芯片的n个配置数据，n≥2；发送模块，用于根据所述点对点配置指令通过所述第一信号线向所述时序控制器发送配置响应指令，所述配置响应指令包括：所述n个配置数据中每个配置数 据的配置响应数据。
可选的，所述点对点配置指令包括：所述用于n个配置数据的地址、第一指示器和数据部分。所述驱动控制组件还包括：第一获取模块，用于获取所述第一指示器的值，所述第一指示器用于指示所述用于n个配置数据的地址是否连续，所述数据部分携带所述n个配置数据；第二获取模块，用于根据所述第一指示器的值从所述用于n个配置数据的地址获取目标地址，其中，当所述第一指示器用于指示所述用于n个配置数据的地址连续时，所述用于n个配置数据的地址包括：连续地址中的第一个地址和最后一个地址，以及获取的目标地址包括：由所述第一个地址和最后一个地址界定的一段连续地址；当所述第一指示器用于指示所述用于n个配置数据的地址不连续时，获取的目标地址包括：所述n个配置数据中的每个配置数据的地址；第三获取模块，用于根据参考信息获取所述数据部分携带的所述n个配置数据，所述参考信息包括所述目标地址。
可选的，所述点对点配置指令还包括第二指示器。所述驱动控制组件还包括：第四获取模块，用于获取所述第二指示器，所述第二指示器用于指示所述点对点配置指令中配置数据的个数；确定模块，用于根据所述第二指示器的值确定所述个数，所述参考信息还包括所述个数。
可选的，所述点对点配置指令包括至少五个字节。所述第一指示器包括：所述至少五个字节中第三个字节中的第五个比特位。所述第二指示器包括：所述至少五个字节中第三个字节中的第六个至第八个比特位。
可选的，所述时序控制器通过多个第二信号线分别与所述多个源极驱动芯片一一对应连接，且所述时序控制器与所述第一源极驱动芯片通过所述多个第二信号线中的分配给所述第一源极驱动芯片的目标第二信号线连接。所述驱动控制组件还包括：第二接收模块，用于接收所述时序控制器通过所述被分配的第二信号线发送的开始指令，所述开始指令用于指示所述点对点配置指令所携带的配置数据的最大个数。
可选的，所述开始指令包括至少七个字节。所述至少七个字节中的第七个字节中的四个比特位用于指示所述最大个数。
可选的，所述点对点配置指令和所述配置响应指令中的每个指令均包括：依次排列的前导码、起始标识、数据主体和结束标识。所述前导码包括：连续的至少八个比特周期的第一信号，每个所述比特周期为两微秒。所述起始标识包括：连续的至少两个所述比特周期的第二信号。所述数据主体包括：所述n个配置数据或所述n个配置响应数据。所述结束标识均包括：连续的至少两个所述比特周期的第三信号。所述第一信号、所述第二信号、所述n个配置数据及其配置响应数据均采用曼彻斯特编码得到。
在第五方面，提供了一种驱动控制组件，包括存储器，处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现第一方面所述方法的步骤。
在第六方面，提供了一种驱动控制组件，包括存储器，处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现第二方面所述方法的步骤。
在第七方面，提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现第一方面和第二方面所述的方法的步骤。
在第八方面，提供了一种显示装置。所述显示装置包括：时序控制器和源极驱动芯片；所述时序控制器包括第三方面或第五方面所述的驱动控制组件，所述源极驱动芯片包括第四方面或第六方面所述的驱动控制组件。
在第九方面，提供了一种芯片，所述芯片包括可编程逻辑电路和/或程序指令，当所述芯片运行时用于实现第一方面所述的方法。
在第十方面，提供了一种芯片，所述芯片包括可编程逻辑电路和/或程序指令，当所述芯片运行时用于实现第二方面所述的方法。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本公开。
附图说明
现在将参考示出本公开的实施例的附图来更详细地描述本公开的上述以及其它方面。
图1是本公开实施例提供的一种驱动控制方法的应用环境示意图。
图2是本公开实施例提供的一种第一信号线上传输的指令的示意图。
图3是本公开实施例提供的一种驱动控制方法的流程示意图。
图4是本公开实施例提供的另一种驱动控制方法的流程示意图。
图5是本公开实施例提供的又一种驱动控制方法的流程示意图。
图6是本公开实施例提供的一种驱动控制组件的结构示意图。
图7是本公开实施例提供的另一种驱动控制组件的结构示意图。
图8是本公开实施例提供的又一种驱动控制组件的结构示意图。
图9是本公开实施例提供的再一种驱动控制组件的结构示意图。
图10是本公开另一实施例提供的一种驱动控制组件的结构示意图。
图11是本公开另一实施例提供的另一种驱动控制组件的结构示意图。
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。
具体实施方式
在以下的说明中，为了解释而不是限制，阐述了所公开的实施例的某些特定细节，以便清楚和彻底地理解本公开。然而本领域技术人员应当容易明白，在不严重偏离本公开的精神和范围的情况下，本公开可以按并非精确地符合本文中所述细节的其它实施例来实施。此外，在这个上下文中，为了简单明了，省略了对熟悉的设备、电路和方法的详细描述，以避免多余的细节和可能的混淆。
面板驱动电路包括第一信号线与第二信号线。时序控制器可以通过第一信号线传输配置指令，以配合第二信号线进行高速差分信号的传输。该配置指令包括：前导码、起始标识、数据以及结束标识。由于第一信号线传输的每个指令携带的数据较少，导致需要通过多个指令来传输多个数据，且传输多个指令过程中需要传输的前导码、起始标识以及结束标识均较多，使得第一信号线的传输效率与利用率较低。本公开实施例提供了一种驱动控制方法，可以提高第一信号线的传输效率与利用率。
图1是本公开实施例提供的一种驱动控制方法的应用环境示意图。 如图1所示，该驱动控制方法应用于显示装置中。该显示装置包括时序控制器01和多个源极驱动芯片02。该时序控制器01通过多个第二信号线H分别与多个源极驱动芯片02连接。通常的，该时序控制器01通过多个第二信号线H与多个源极驱动芯片02一一对应连接，其中，第二信号线中的信号是单向传输的。该时序控制器还连接有一第一信号线L。多个源极驱动芯片02并行连接，且与第一信号线L连接，以便与时序控制器通信。第一信号线中的信号是双向传输的。
在显示装置的面板驱动电路中，第一信号线L可以进行不同指令的传输以实现不同的数据传输功能。每种数据传输功能对应至少一种传输模式(mode)。例如，时序控制器可以通过该第一信号线实现向源极驱动芯片发送广播配置指令的功能，也即在所有源极驱动芯片中设置初始化程序。该功能对应广播交流(broadcast communication；BC)模式，也即广播交流模式指示时序控制器进行数据广播。时序控制器还可以通过该第一信号线向源极驱动芯片发送身份配置指令以实现为源极驱动芯片发送身份标识(identification，ID)的功能。该功能对应身份标识分配(ID assignment；IA)模式，也即身份标识分配模式指示时序控制器对源极驱动芯片进行身份标识的分配。时序控制器还可以通过该第一信号线向源极驱动芯片发送点对点(也称端对端)配置指令，以实现对源极驱动芯片的点对点控制的功能，该功能对应下行交流(downstream communication；DC)模式，也即下行交流模式指示时序控制器对源极驱动芯片进行点对点数据传输。源极驱动芯片可以通过该第一信号线向时序控制器发送针对点对点配置指令的控制响应指令，或者通过该第一信号线向时序控制器发送针对身份配置指令的身份配置响应指令。该功能对应回复传输(reply transaction；RT)模式，也即回复传输模式指示源极驱动芯片对时序控制器进行指令的回复。通过上述各个模式的配合，时序控制器可以依次完成对源极驱动芯片的身份标识分配、数据的读/写操作、接收源极驱动芯片的数据反馈等操作。需要说明的是，本公开实施例提供的驱动控制方法可以用于DC模式。
可选的，在本公开实施例中，时序控制器和源极驱动芯片之间在第一信号线L上传输的指令的格式相同。图2是本公开实施例提供的一种第一信号线上传输的指令的示意图。如图2所示，第一信号线上 传输的每个指令均包括依次排列的前导码(preamble)、起始(start)标识、数据主体(也称：传输主体，transaction body)和结束(stop)标识。
前导码用于指示接收端进行时钟和相位校准。接收端(时序控制器或源极驱动芯片)在检测到第一信号线上有前导码传输时，便根据前导码的内容进行时钟和相位调整。时钟和相位调整是指保持接收端的时钟与发送端的时钟一致，相位与发送端相同。接收端在接收前导码的过程中调整时钟和相位。在前导码传输结束后，时钟和相位调整完毕。起始标识用于指示数据传输开始，数据主体用于携带配置数据，结束标识用于指示数据传输结束。
在实施例中，前导码可以由包含规律变化的跳变沿的信号构成。示例的，继续参考图2，前导码可以包括连续的至少八个比特周期的第一信号，且每个比特周期为两微秒。起始标识可以包括：连续的至少两个比特周期的第二信号。结束标识可以包括：连续的至少两个比特周期的第三信号。该第一信号、第二信号、数据主体携带的配置数据及其配置响应数据均可以采用曼彻斯特(Manchester)编码(如第二版的曼彻斯特编码MII)得到。在一个示例中，第一信号的电平跳变由低到高，第二信号的电平跳变由低到高，第三信号的电平跳变由高到低。可以理解，除了曼彻斯特编码外，起始标识和结束标识还可以采用发送端和接收端约定的其他形式的信号，包括在指定时间内维持低电平或者高电平的信号。
需要说明的是，由于采用曼彻斯特编码可以使数据产生明显的跳变沿，便于数据的检测，因此，本公开实施例中需要编码的数据均可以采用曼彻斯特编码。但是实际应用中，也可以采用其他编码方式或者不进行编码。进一步的，为了保证数据主体携带的配置数据在解码端能够有效识别，参考图2，在数据主体中的配置数据的首位可以与起始标识产生一跳变沿(即数据主体中的配置数据的首位与起始标识的末位数值不同。例如，数据主体中的配置数据的首位为1，起始标识的末位为0)。在数据主体中的配置数据的末位可以与结束标识产生一跳变沿(即数据主体中的配置数据的末位与结束标识的首位数值不同。例如，数据主体中的配置数据的末位为0，结束标识的末位为1)。上述跳变沿可以便于接收端进行数据的有效识别。在仅有一根第一信号线的情况下，可以采用曼彻斯特编码实现数据的传输，从而可以丰富 第一信号线的功能，提高第一信号线的利用率。
进一步的，假设点对点配置指令的接收端为第一源极驱动芯片，则点对点配置指令的数据主体携带的配置数据可以包括：第一源极驱动芯片的身份标识，第一源极驱动芯片上需要配置的寄存器的地址、操作类型和与操作类型所指示的操作对应的数据。寄存器可用以存储第一源极驱动芯片所接收的配置数据。第一源极驱动芯片从不同的寄存器地址取回配置数据来用于不同的操作。
图3是本公开实施例提供的一种驱动控制方法的流程示意图。该驱动控制方法可以应用于图1中的时序控制器。该时序控制器通过一第一信号线与并行连接的多个源极驱动芯片通信。如图3所示，该方法包括：
步骤301、生成点对点配置指令，且点对点配置指令包括：n个配置数据，n≥2。
步骤302、通过第一信号线向第一源极驱动芯片发送点对点配置指令，第一源极驱动芯片为多个源极驱动芯片中的任意一个。
步骤303、通过第一信号线接收第一源极驱动芯片根据点对点配置指令发送的配置响应指令，配置响应指令包括：对于n个配置数据中每个配置数据的配置响应数据。
综上所述，在本公开实施例提供的驱动控制方法中，点对点配置指令包括：n个配置数据，且n≥2，也即一个指令中可以携带多个数据。通过第一信号线向第一源极驱动芯片发送的点对点配置指令可以包括多个配置数据。这减少了传输多个配置数据时的指令的个数，进而减少了在指令传输过程中需要传输的前导码、起始标识和结束标识的个数，因此，提高了第一信号线的数据传输效率和利用率。
图4是本公开实施例提供的另一种驱动控制方法的流程示意图。该驱动控制方法可以应用于图1中的第一源极驱动芯片，该第一源极驱动芯片为多个源极驱动芯片中的任意一个。该多个源极驱动芯片并行连接，且通过一第一信号线与时序控制器通信。如图4所示，该方法包括：
步骤401、接收时序控制器通过第一信号线发送的点对点配置指令，点对点配置指令包括：用于第一源极驱动芯片的n个配置数据，n≥2。
步骤402、根据点对点配置指令通过第一信号线向时序控制器发送配置响应指令，配置响应指令包括：n个配置数据中每个配置数据的配置响应数据。
综上所述，在本公开实施例提供的驱动控制方法中，点对点配置指令包括：n个配置数据，且n≥2，也即一个指令中可以携带多个数据。通过第一信号线接收的点对点配置指令可以包括多个配置数据，减少了接收多个配置数据时的传输的指令的个数，进而减少了需要传输的前导码、起始标识和结束标识的个数，因此，提高了第一信号线的数据传输效率和利用率。
图5是本公开实施例提供的又一种驱动控制方法的流程示意图。该驱动控制方法可以应用于图1中的应用环境。假设第一源极驱动芯片为多个源极驱动芯片中的任意一个。时序控制器可以通过多个第二信号线分别与多个源极驱动芯片一一对应连接。时序控制器通过所述多个第二信号线中分配给所述第一源极驱动芯片的第二信号线与第一源极驱动芯片通信。该方法可以包括：
步骤501、时序控制器通过该被分配的第二信号线向第一源极驱动芯片发送开始指令。
该开始指令可以用于指示时序控制器即将发送的点对点配置指令中配置数据的最大个数。示例的，该开始指令可以包括至少七个字节，该至少七个字节中的第七个字节中的四个比特位用于指示所述最大个数，例如通过十五种状态指示配置数据的十五种最大个数。示例性地，该四个比特位具有十六种状态，这十六种状态中有一种状态为无效状态，剩余十五种状态指示十五种最大个数。例如，当该四个比特位上存储的二进制数字均为0时，该四个比特位所表示的状态可以为无效状态；或者，当该四个比特位上存储的二进制数字均为1时，该四个比特位所表示的状态可以为无效状态。另外，该四个比特位也可以为其他字节(如第六个字节)中的四个比特位，该比特位的个数也可以为其他数值(如三个比特位)，本公开实施例不限于此。
步骤502、时序控制器生成点对点配置指令。
点对点配置指令可以是例如参考图2所示的指令。可选的，该点对点配对指令可以包括：用于配置数据的地址、第一指示器和数据部分。该数据部分携带n个配置数据，n≥2。用于n个配置数据的地址 可以是第一源极驱动芯片中用于存储配置数据的寄存器地址。该第一指示器用于指示该用于n个配置数据的地址是否连续。可选的，该数据主体还可以包括第二指示器，该第二指示器可以用于指示点对点配置指令中配置数据的个数n。第二指示器可以用于直接确定或者检查传输过程中的配置数据个数是否准确，从而进一步避免因差错而造成的配置数据的遗漏。
示例的，该数据主体可以包括至少五个字节。该用于n个配置数据的地址可以存储于数据主体的第三个字节中的第五个比特位之前的比特位中(如存储在第二个字节中)。该第一指示器可以包括：该至少五个字节中第三个字节中的第五个比特位。第二指示器可以包括：该第三个字节中的第六个至第八个比特位。数据部分可以存储在该至少五个字节中第三个字节之后的字节中。
另外，第一指示器中存储的二进制数字为0可以用于指示用于n个配置数据的地址是连续的，第一指示器中存储的二进制数字为1可以用于指示用于n个配置数据的地址是不连续的。若数据主体的第三个字节中的第六个至第八个比特位中存储的二进制数字均为1，则第二指示器指示的配置数据的个数最大，该个数可以为8。若该第三个字节中的第六个至第八个比特位中存储的二进制数字均为0，则第二指示器指示的配置数据的个数最小，该个数可以为1；若该第三个字节中的第六个至第八个比特位中存储的二进制数字依次为0、0和1，则第二指示器指示的配置数据的个数可以为2；以此类推。这样便可以得出第二指示器的各个状态所指示的配置数据的个数。
步骤503、时序控制器通过第一信号线向第一源极驱动芯片发送点对点配置指令。
步骤504、第一源极驱动芯片获取接收到的点对点配置指令中的第一指示器的值。
示例的，若第一指示器包括：点对点配置指令中第三个字节中的第五个比特位，则第一源极驱动芯片可以获取该第五个比特位上存储的二进制数字，该二进制数字即为第一指示器的值。
步骤505、第一源极驱动芯片获取点对点配置指令中的第二指示器的值。
示例的，若第二指示器包括：点对点配置指令中第三个字节中的 第六个至第八个比特位，则第一源极驱动芯片可以获取该第六个至第八个比特位上存储的三个二进制数字，该三个二进制数字组成的二进制数即为该第二指示器的值。例如，第六个至第八个比特位上存储的二进制数字均为0，该三个二进制数字组成的二进制数为000，该二进制数即为第二指示器的值。
步骤506、第一源极驱动芯片根据第二指示器的值确定点对点配置指令中配置数据的个数。
示例的，步骤505中第一源极驱动芯片获取的第二指示器的值与点对点配置指令中配置数据的个数可以相同，但是本公开的实施例不限于此。在其他实施例中，第二指示器的值与点对点配置指令中配置数据的个数也可以不同，只要两者之间存在预定的对应关系即可。例如，第二指示器的值为011所指示的点对点配置指令中配置数据的个数可以不是3，而是4。
步骤507、第一源极驱动芯片根据第一指示器的值从用于n个配置数据的地址来获取目标地址。目标地址可以指示用于存储配置指令中的n个配置数据的寄存器地址。
若在步骤504中，在第一源极驱动芯片获取的第一指示器指示用于n个配置数据的地址连续时，则所述用于n个配置数据的地址可以是：连续地址中的第一个地址和最后一个地址。当n个配置数据被顺序存储时，所述用于n个配置数据的地址可以是第一个配置数据的地址和最后一个配置数据的地址。相应地，目标地址可以是由该第一个地址和最后一个地址所界定的一段连续地址。若第一指示器指示用于n个配置数据的地址不连续，则所述用于n个配置数据的地址，以及相应地，目标地址可以包括：n个配置数据中的每个配置数据的地址。由于在用于n个配置数据的地址连续和间断时，第一源极驱动芯片获取的目标地址不同，且在该用于n个配置数据的地址连续时，第一源极驱动芯片需要获取的地址较少，因此数据传输的速率较快。
示例的，若第一指示器指示用于n个配置数据的地址连续，且配置数据的个数n＝3，则当用于存储该n个数据的寄存器地址分别为1、2和3时，配置指令中用于该3个配置数据的地址为1和3。这样，第一源极驱动芯片将从配置指令中获取地址1和3，作为目标地址的头地址和尾地址。若第一指示器指示用于n个配置数据的地址不连续，且 配置数据的个数n＝3，则当用于存储该n个数据的寄存器地址分别为1、3和4时，配置指令中用于该3个配置数据的地址即为全部的对应该n个数据的n个地址。这样，第一源极驱动芯片将获取用于该n个数据的地址中的每一个地址。
步骤508、第一源极驱动芯片根据参考信息获取n个配置数据。
该参考信息可以包括：目标地址和可选地，点对点配置指令中配置数据的个数(也即n的值)。若用于n个配置数据的地址不连续，则第一源极驱动芯片需要分别获取每个配置数据的地址对应的配置数据。若用于n个配置数据的地址连续，则第一源极驱动芯片仅需直接获取n个配置数据中的第一个配置数据的地址和最后一个配置数据的地址之间的配置数据。此时，第一源极驱动芯片可以快速的获取到所有的配置数据，因此获取配置数据的效率较高。配置数据的个数可以用于进一步校验配置指令中配置数据传输的正确性。
步骤509、第一源极驱动芯片执行n个配置数据所指示的n个配置操作。
示例的，配置数据可以包括：第一源极驱动芯片上需要配置的寄存器的地址、操作类型和与操作类型所指示的操作对应的数据。配置数据对应的配置操作可以为读操作或写操作。
步骤510、第一源极驱动芯片根据点对点配置指令通过第一信号线向时序控制器发送配置响应指令。
配置响应指令的具体结构可以是例如参照图2所示的指令的结构。另外，该配置响应指令可以包括：n个配置数据中每个配置数据的配置响应数据。每个配置数据的配置响应数据可以用于指示每个配置数据所指示的配置操作是否执行完成。例如，当某个配置数据所指示的配置操作已经执行完成时，该配置数据对应的配置响应数据可以为1。当某个配置数据所指示的配置操作未执行完成时，该配置数据对应的配置响应数据可以为0，且此时，时序控制器可以重新向该第一源极驱动芯片发送点对点配置指令。
可选的，第一源极驱动芯片可以在接收到点对点配置指令后预设的回复等待时长后，通过第一信号线向时序控制器发送配置响应指令。另外，时序控制器发送两个相邻的指令的间隔时长可称为挂起时长或待命时长。第一源极驱动芯片的回复等待时长可以大于挂起时长，以 避免第一源极驱动芯片在时序控制器发送的一个指令未传输完时发送下一个指令，那样会导致线路冲突。因此，该回复等待时长可以大于挂起时长。挂起时长可以为10微秒(us)，相应地，回复等待时长大于10微秒。
需要说明的是，上述第一信号线可以称为双向指令通道(Bidirectional command channel；BCC)信号线。上述点对点配置指令以及配置响应指令均可以称为BCC指令。
综上所述，在本公开实施例提供的驱动控制方法中，点对点配置指令包括：n个配置数据，且n≥2，也即一个指令中可以携带多个数据。通过第一信号线向第一源极驱动芯片发送的点对点配置指令可以包括多个配置数据。这样便减少了传输多个配置数据时的指令的个数，进而减少了需要传输的前导码、起始标识和结束标识的个数，因此，提高了第一信号线的数据传输效率与利用率。
图6是本公开实施例提供的一种驱动控制组件的结构示意图。该驱动控制组件应用于时序控制器。时序控制器通过一第一信号线与并行连接的多个源极驱动芯片通信。该驱动控制组件60可以包括：
生成模块601，用于生成点对点配置指令，点对点配置指令包括：n个配置数据，n≥2。
第一发送模块602，用于通过第一信号线向第一源极驱动芯片发送点对点配置指令，第一源极驱动芯片为多个源极驱动芯片中的任意一个。
接收模块603，用于通过第一信号线接收第一源极驱动芯片根据点对点配置指令发送的配置响应指令。配置响应指令包括：n个配置数据中每个配置数据的配置响应数据。
综上所述，在本公开实施例提供的驱动控制组件中，点对点配置指令包括：n个配置数据，且n≥2，也即一个指令中可以携带多个配置数据。第一发送模块通过第一信号线向第一源极驱动芯片发送的点对点配置指令中可以包括多个配置数据。这样便减少了传输多个配置数据时传输的指令的个数，进而减少了需要传输的前导码、起始标识和结束标识的个数，因此，提高了第一信号线的数据传输效率与利用率。
可选的，点对点配置指令包括：用于n个配置数据的地址、第一 指示器和数据部分。第一指示器用于指示用于n个配置数据的地址是否连续，数据部分携带n个配置数据。
可选的，点对点配置指令还包括第二指示器。第二指示器用于指示点对点配置指令中配置数据的个数。
可选的，点对点配置指令包括至少五个字节。第一指示器包括：至少五个字节中第三个字节中的第五个比特位。第二指示器包括：第三个字节中的第六个至第八个比特位。
可选的，时序控制器通过多个第二信号线分别与多个源极驱动芯片一一对应连接，且时序控制器与第一源极驱动芯片通过多个第二信号线中的目标第二信号线连接。图7是本公开实施例提供的另一种驱动控制组件的结构示意图。如图7所示，除了图6中已示出的模块外，驱动控制组件60还包括：
第二发送模块604，用于通过目标第二信号线向第一源极驱动芯片发送开始指令，开始指令用于指示点对点配置指令所携带的配置数据的最大个数。
可选的，开始指令包括至少七个字节，至少七个字节中的第七个字节中的四个比特位用于通过例如十五种状态指示十五种最大个数。
可选的，点对点配置指令和配置响应指令中的每个指令均包括：依次排列的前导码、起始标识、数据主体和结束标识，
前导码包括：连续的至少八个比特周期的第一信号，每个比特周期为两微秒。起始标识包括：连续的至少两个比特周期的第二信号。结束标识包括：连续的至少两个比特周期的第三信号。
第一信号、第二信号、n个配置数据及其配置响应数据均采用曼彻斯特编码得到，且第一信号的电平跳变由低到高，第二信号的电平跳变由低到高，第三信号的电平跳变由高到低。
综上所述，在本公开实施例提供的驱动控制组件中，点对点配置指令包括：n个配置数据，且n≥2，也即一个指令中可以携带多个配置数据。第一发送模块通过第一信号线向第一源极驱动芯片发送的点对点配置指令中可以包括多个配置数据这样便减少了传输多个配置数据时传输的指令的个数，进而减少了需要传输的前导码、起始标识和结束标识的个数，因此，提高了第一信号线的数据传输效率与利用率。
图8是本公开实施例提供的又一种驱动控制组件的结构示意图。 该驱动控制组件应用于第一源极驱动芯片。该第一源极驱动芯片是多个源极驱动芯片中的任意一个。该多个源极驱动芯片并行连接，且通过一第一信号线与时序控制器通信，该驱动控制组件80可以包括：
第一接收模块801，用于接收时序控制器通过第一信号线发送的点对点配置指令，点对点配置指令包括：第一源极驱动芯片的n个配置数据，n≥2；
发送模块802，用于根据点对点配置指令通过第一信号线向时序控制器发送配置响应指令，配置响应指令包括：n个配置数据中每个配置数据的配置响应数据。
综上所述，本公开实施例提供的驱动控制组件中，点对点配置指令包括：n个配置数据，且n≥2，也即一个指令中可以携带多个配置数据。第一接收模块通过第一信号线接收的点对点配置指令可以包括多个配置数据这样便减少了接收多个配置数据时传输的指令的个数，进而减少了需要传输的前导码、起始标识和结束标识的个数，因此，提高了第一信号线的数据传输效率与利用率。
可选的，点对点配置指令包括：用于n个配置数据的地址、第一指示器和数据部分。图9是本公开实施例提供的再一种驱动控制组件的结构示意图，除了图8中所示的模块外，该驱动控制组件80还包括：
第一获取模块803，用于获取第一指示器的值，第一指示器用于指示用于n个配置数据的地址是否连续，数据部分携带n个配置数据；
第二获取模块804，用于根据第一指示器的值获取用于n个配置数据的地址中的目标地址。当第一指示器指示用于n个配置数据的地址连续时，目标地址包括：n个配置数据中的第一个配置数据的地址和最后一个配置数据的地址。当第一指示器用于指示用于n个配置数据的地址不连续时，目标地址包括：n个配置数据中的每个配置数据的地址；
第三获取模块805，用于根据参考信息获取数据部分携带的n个配置数据，参考信息包括目标地址。
可选的，点对点配置指令还包括第二指示器。图10是本公开另一实施例提供的一种驱动控制组件的结构示意图，除了图8所示的模块外，该驱动控制组件80还包括：
第四获取模块806，用于获取第二指示器，第二指示器用于指示点对点配置指令中配置数据的个数；
确定模块807，用于根据第二指示器的值确定点对点配置指令中配置数据的个数，参考信息还包括该个数。
可选的，点对点配置指令包括至少五个字节。第一指示器包括：至少五个字节中第三个字节中的第五个比特位。第二指示器包括：至少五个字节中第三个字节中的第六个至第八个比特位。
可选的，时序控制器通过多个第二信号线分别与多个源极驱动芯片一一对应连接，且时序控制器与第一源极驱动芯片通过多个第二信号线中的目标第二信号线连接。图11是本公开另一实施例提供的另一种驱动控制组件的结构示意图，除了图8所示的模块外，该驱动控制组件80还包括：
第二接收模块808，用于接收时序控制器通过目标第二信号线发送的开始指令，开始指令用于指示点对点配置指令所携带的配置数据的最大个数。
可选的，开始指令包括至少七个字节，至少七个字节中的第七个字节中的四个比特位用于通过十五种状态指示十五种最大个数。
可选的，点对点配置指令和配置响应指令中的每个指令均包括：依次排列的前导码、起始标识、数据主体和结束标识，
前导码包括：连续的至少八个比特周期的第一信号，每个比特周期为两微秒。起始标识包括：连续的至少两个比特周期的第二信号。结束标识均包括：连续的至少两个比特周期的第三信号；
第一信号、第二信号、n个配置数据及其配置响应数据均采用曼彻斯特编码得到，且第一信号的电平跳变由低到高，第二信号的电平跳变由低到高，第三信号的电平跳变由高到低。
综上所述，在本公开实施例提供的驱动控制组件中，点对点配置指令包括：n个配置数据，且n≥2，也即一个指令中可以携带多个配置数据。第一接收模块通过第一信号线接收的点对点配置指令可以包括多个配置数据。这样便减少了接收多个配置数据时传输的指令的个数，进而减少了需要传输的前导码、起始标识和结束标识的个数，因此，提高了第一信号线的数据传输效率与利用率。
本公开另一实施例提供了又一种驱动控制组件，包括存储器，处理器及存储在存储器上并可在处理器上运行的计算机程序，该处理器执行该程序时实现上述驱动控制方法中时序控制器或源极驱动芯片执 行的步骤。
本公开实施例还提供了一种计算机可读存储介质，其上存储有计算机程序，该程序被处理器执行时实现上述驱动控制方法中时序控制器或源极驱动芯片执行的步骤。计算机可读存储介质可以为非瞬态的计算机可读存储介质。
本公开实施例还提供了一种芯片，该芯片包括可编程逻辑电路和/或程序指令，当该芯片运行时用于实现上述驱动控制方法中时序控制器或源极驱动芯片执行的步骤。
本公开实施例提供了一种显示装置，包括：时序控制器和源极驱动芯片，两者连接方式可以参考在前文描述的图1。该时序控制器和源极驱动芯片均可以包括相应的驱动控制组件。
该时序控制器中的驱动控制组件如图6或图7所示，该源极驱动芯片中的驱动控制组件如图8至图11任一所示。
或者，该时序控制器中的驱动控制组件包括：存储器，处理器及存储在存储器上并可在处理器上运行的计算机程序，该处理器执行该程序时实现上述驱动控制方法中时序控制器执行的步骤。该源极驱动芯片中的驱动控制组件包括：存储器，处理器及存储在存储器上并可在处理器上运行的计算机程序，该处理器执行该程序时实现上述驱动控制方法中第一源极驱动芯片执行的步骤。
该显示装置可以为液晶面板、电子纸、有机发光二极管(Organic Light-Emitting Diode；OLED)面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
需要说明的是，本公开实施例中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
本公开实施例提供的驱动控制方法步骤的先后顺序可以进行适当调整，步骤也可以根据情况进行相应增减，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本公开的保护范围之内。所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的装置、组件和模块的具体工作过程， 可以参考前述方法实施例中的对应过程。
各种实施例中的模块可以通过使用硬件单元、软件单元或它们的组合而被实施。硬件单元的例子可包括设备、构件、处理器、微处理器、电路、电路元件(例如，晶体管、电阻器、电容器、电感器等等)、集成电路、专用集成电路(ASIC)、可编程逻辑器件(PLD)、数字信号处理器(DSP)、现场可编程门阵列(FPGA)、存储器单元、逻辑门、寄存器、半导体器件、芯片、微芯片、芯片组等等。软件单元的例子可包括软件构件、程序、应用、计算机程序、应用程序、系统程序、机器程序、操作系统软件、中间件、固件、软件模块、例行程序、子程序、函数、方法、过程、软件接口、应用程序接口(API)、指令集、计算代码、计算机代码、代码段、计算机代码段、单词、值、符号、或它们的任何组合。确定实施例是否通过使用硬件单元和/或软件单元来实施可以根据对于给定实现所想要的任意数量的因素而变化，因素可以是诸如想要的计算速率、功率电平、耐热性、处理周期预算、输入数据速率、输出数据速率、存储器资源、数据总线速度、和其它设计或性能约束等。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。

Claims (34)

  1. 一种驱动控制方法，应用于时序控制器，所述时序控制器通过一第一信号线与并行连接的多个源极驱动芯片通信，所述方法包括：
    生成点对点配置指令，所述点对点配置指令包括：n个配置数据，n≥2；
    通过所述第一信号线向第一源极驱动芯片发送所述点对点配置指令，所述第一源极驱动芯片为所述多个源极驱动芯片中的任意一个；
    通过所述第一信号线接收所述第一源极驱动芯片根据所述点对点配置指令发送的配置响应指令，所述配置响应指令包括：对于所述n个配置数据中每个配置数据的配置响应数据。
  2. 根据权利要求1所述的方法，其中，所述点对点配置指令包括：用于n个配置数据的地址、第一指示器和数据部分，
    所述第一指示器用于指示所述用于n个配置数据的地址是否连续，所述数据部分携带所述n个配置数据。
  3. 根据权利要求2所述的方法，其中，在所述第一指示器指示所述用于n个配置数据的地址连续时，所述用于n个配置数据的地址包括连续地址中的第一地址和最后一个地址。
  4. 根据权利要求2所述的方法，其中，所述点对点配置指令还包括第二指示器，所述第二指示器用于指示所述点对点配置指令中配置数据的个数。
  5. 根据权利要求4所述的方法，其中，所述点对点配置指令包括至少五个字节，所述第一指示器包括：所述至少五个字节中第三个字节中的第五个比特位，所述第二指示器包括：所述第三个字节中的第六个至第八个比特位。
  6. 根据权利要求1所述的方法，其中，所述时序控制器通过多个第二信号线分别与所述多个源极驱动芯片一一对应连接，且所述时序控制器与所述第一源极驱动芯片通过所述多个第二信号线中的被分配给所示第一源极驱动芯片的第二信号线连接，在所述生成点对点配置指令之前，所述方法还包括：
    通过所述被分配的第二信号线向所述第一源极驱动芯片发送开始指令，所述开始指令用于指示所述点对点配置指令所携带的配置数据 的最大个数。
  7. 根据权利要求6所述的方法，其中，所述开始指令包括至少七个字节，所述至少七个字节中的第七个字节中的四个比特位用于指示所述最大个数。
  8. 根据权利要求1所述的方法，其中，所述点对点配置指令和所述配置响应指令中的每个指令均包括：依次排列的前导码、起始标识、数据主体和结束标识，
    所述前导码包括：连续的至少八个比特周期的第一信号，每个所述比特周期为两微秒；所述起始标识包括：连续的至少两个所述比特周期的第二信号；所述数据主体包括：所述n个配置数据或所述n个配置响应数据；所述结束标识包括：连续的至少两个所述比特周期的第三信号；
    所述第一信号、所述第二信号、所述n个配置数据及其配置响应数据均采用曼彻斯特编码得到。
  9. 一种驱动控制方法，应用于第一源极驱动芯片，所述第一源极驱动芯片是多个源极驱动芯片中的任意一个，所述多个源极驱动芯片并行连接，且通过一第一信号线与时序控制器通信，所述方法包括：
    接收所述时序控制器通过所述第一信号线发送的点对点配置指令，所述点对点配置指令包括：用于第一源极驱动芯片的n个配置数据，n≥2；
    根据所述点对点配置指令通过所述第一信号线向所述时序控制器发送配置响应指令，所述配置响应指令包括：所述n个配置数据中每个配置数据的配置响应数据。
  10. 根据权利要求9所述的方法，其中，所述点对点配置指令包括：所述用于n个配置数据的地址、第一指示器和数据部分，在根据所述点对点配置指令通过所述第一信号线向所述时序控制器发送配置响应指令之前，所述方法还包括：
    获取所述第一指示器的值，所述第一指示器指示所述用于n个配置数据的地址是否连续，所述数据部分携带所述n个配置数据；
    根据所述第一指示器的值从所述用于n个配置数据的地址获取目标地址，其中，当所述第一指示器指示所述用于n个配置数据的地址连续时，所述用于n个配置数据的地址包括：连续地址中的第一个地 址和最后一个地址，以及获取的目标地址包括：由所述第一个地址和最后一个地址界定的一段连续地址；当所述第一指示器指示所述用于n个配置数据的地址不连续时，获取的目标地址包括：所述n个配置数据中的每个配置数据的地址；
    根据参考信息获取所述数据部分携带的所述n个配置数据，所述参考信息包括所述目标地址。
  11. 根据权利要求10所述的方法，其中，所述点对点配置指令还包括第二指示器，在根据参考信息获取所述数据部分携带的所述n个配置数据之前，所述方法还包括：
    获取所述第二指示器的值，所述第二指示器用于指示所述点对点配置指令中配置数据的个数；
    根据所述第二指示器的值确定所述个数，所述参考信息还包括所述个数。
  12. 根据权利要求11所述的方法，其中，所述点对点配置指令包括至少五个字节，
    所述第一指示器包括：所述至少五个字节中第三个字节中的第五个比特位，所述第二指示器包括：所述至少五个字节中第三个字节中的第六个至第八个比特位。
  13. 根据权利要求9所述的方法，其中，所述时序控制器通过多个第二信号线分别与所述多个源极驱动芯片一一对应连接，且所述时序控制器与所述第一源极驱动芯片通过所述多个第二信号线中的分配给所述第一源极驱动芯片的第二信号线连接，
    在所述根据所述点对点配置指令通过所述第一信号线向所述时序控制器发送配置响应指令之前，所述方法还包括：
    接收所述时序控制器通过所述被分配的第二信号线发送的开始指令，所述开始指令用于指示所述点对点配置指令所携带的配置数据的最大个数。
  14. 根据权利要求13所述的方法，其中，所述开始指令包括至少七个字节，所述至少七个字节中的第七个字节中的四个比特位用于指示所述最大个数。
  15. 根据权利要求9所述的方法，其中，所述点对点配置指令和所述配置响应指令中的每个指令均包括：依次排列的前导码、起始标 识、数据主体和结束标识，
    所述前导码包括：连续的至少八个比特周期的第一信号，每个所述比特周期为两微秒；所述起始标识包括：连续的至少两个所述比特周期的第二信号；所述数据主体包括：所述n个配置数据或所述n个配置响应数据；所述结束标识均包括：连续的至少两个所述比特周期的第三信号；
    所述第一信号、所述第二信号、所述n个配置数据及其配置响应数据均采用曼彻斯特编码得到，且所述第一信号的电平跳变由低到高，所述第二信号的电平跳变由低到高，所述第三信号的电平跳变由高到低。
  16. 一种驱动控制组件，应用于时序控制器，所述时序控制器通过一第一信号线与并行连接的多个源极驱动芯片通信，所述驱动控制组件包括：
    生成模块，用于生成点对点配置指令，所述点对点配置指令包括：n个配置数据，n≥2；
    第一发送模块，用于通过所述第一信号线向第一源极驱动芯片发送所述点对点配置指令，所述第一源极驱动芯片为所述多个源极驱动芯片中的任意一个；
    接收模块，用于通过所述第一信号线接收所述第一源极驱动芯片根据所述点对点配置指令发送的配置响应指令，所述配置响应指令包括：对于所述n个配置数据中每个配置数据的配置响应数据。
  17. 根据权利要求16所述的驱动控制组件，其中，所述点对点配置指令包括：所述用于n个配置数据的地址、第一指示器和数据部分，
    所述第一指示器用于指示所述用于n个配置数据的地址是否连续，所述数据部分携带所述n个配置数据。
  18. 根据权利要求17所述的驱动控制组件，其中，在所述第一指示器指示所述用于n个配置数据的地址连续时，所述用于n个配置数据的地址包括连续地址中的第一地址和最后一个地址。
  19. 根据权利要求17所述的驱动控制组件，其中，
    所述点对点配置指令还包括第二指示器，所述第二指示器用于指示所述点对点配置指令中配置数据的个数。
  20. 根据权利要求19所述的驱动控制组件，其中，
    所述点对点配置指令包括至少五个字节，所述第一指示器包括：所述至少五个字节中第三个字节中的第五个比特位，所述第二指示器包括：所述第三个字节中的第六个至第八个比特位。
  21. 根据权利要求16所述的驱动控制组件，其中，所述时序控制器通过多个第二信号线分别与所述多个源极驱动芯片一一对应连接，且所述时序控制器与所述第一源极驱动芯片通过所述多个第二信号线中的被分配给所示第一源极驱动芯片的第二信号线连接，所述驱动控制组件还包括：
    第二发送模块，用于通过所述被分配的第二信号线向所述第一源极驱动芯片发送开始指令，所述开始指令用于指示所述点对点配置指令所携带的配置数据的最大个数。
  22. 根据权利要求21所述的驱动控制组件，其中，所述开始指令包括至少七个字节，所述至少七个字节中的第七个字节中的四个比特位用于指示所述最大个数。
  23. 根据权利要求16所述的驱动控制组件，其中，所述点对点配置指令和所述配置响应指令中的每个指令均包括：依次排列的前导码、起始标识、数据主体和结束标识，
    所述前导码包括：连续的至少八个比特周期的第一信号，每个所述比特周期为两微秒；所述起始标识包括：连续的至少两个所述比特周期的第二信号；所述数据主体包括：所述n个配置数据或所述n个配置响应数据；所述结束标识包括：连续的至少两个所述比特周期的第三信号；
    所述第一信号、所述第二信号、所述n个配置数据及其配置响应数据均采用曼彻斯特编码得到，且所述第一信号的电平跳变由低到高，所述第二信号的电平跳变由低到高，所述第三信号的电平跳变由高到低。
  24. 一种驱动控制组件，应用于第一源极驱动芯片，所述第一源极驱动芯片是多个源极驱动芯片中的任意一个，所述多个源极驱动芯片并行连接，且通过一第一信号线与时序控制器通信，所述驱动控制组件包括：
    第一接收模块，用于接收所述时序控制器通过所述第一信号线发送的点对点配置指令，所述点对点配置指令包括：用于第一源极驱动 芯片的n个配置数据，n≥2；
    发送模块，用于根据所述点对点配置指令通过所述第一信号线向所述时序控制器发送配置响应指令，所述配置响应指令包括：所述n个配置数据中每个配置数据的配置响应数据。
  25. 根据权利要求24所述的驱动控制组件，其中，所述点对点配置指令包括：所述用于n个配置数据的地址、第一指示器和数据部分，所述驱动控制组件还包括：
    第一获取模块，用于获取所述第一指示器的值，所述第一指示器指示所述用于n个配置数据的地址是否连续，所述数据部分携带所述n个配置数据；
    第二获取模块，用于根据所述第一指示器的值从所述用于n个配置数据的地址获取目标地址，其中，当所述第一指示器用于指示所述用于n个配置数据的地址连续时，所述用于n个配置数据的地址包括：连续地址中的第一个地址和最后一个地址，以及获取的目标地址包括：由所述第一个地址和最后一个地址界定的一段连续地址；当所述第一指示器用于指示所述用于n个配置数据的地址不连续时，获取的目标地址包括：所述n个配置数据中的每个配置数据的地址；
    第三获取模块，用于根据参考信息获取所述数据部分携带的所述n个配置数据，所述参考信息包括所述目标地址。
  26. 根据权利要求25所述的驱动控制组件，其中，所述点对点配置指令还包括第二指示器，所述驱动控制组件还包括：
    第四获取模块，用于获取所述第二指示器，所述第二指示器用于指示所述点对点配置指令中配置数据的个数；
    确定模块，用于根据所述第二指示器的值确定所述个数，所述参考信息还包括所述个数。
  27. 根据权利要求26所述的驱动控制组件，其中，所述点对点配置指令包括至少五个字节，
    所述第一指示器包括：所述至少五个字节中第三个字节中的第五个比特位，所述第二指示器包括：所述至少五个字节中第三个字节中的第六个至第八个比特位。
  28. 根据权利要求24所述的驱动控制组件，其中，所述时序控制器通过多个第二信号线分别与所述多个源极驱动芯片一一对应连接， 且所述时序控制器与所述第一源极驱动芯片通过所述多个第二信号线中的分配给所述第一源极驱动芯片的第二信号线连接，所述驱动控制组件还包括：
    第二接收模块，用于接收所述时序控制器通过所述被分配的第二信号线发送的开始指令，所述开始指令用于指示所述点对点配置指令所携带的配置数据的最大个数。
  29. 根据权利要求28所述的驱动控制组件，其中，所述开始指令包括至少七个字节，所述至少七个字节中的第七个字节中的四个比特位用于指示所述最大个数。
  30. 根据权利要求24所述的驱动控制组件，其中，所述点对点配置指令和所述配置响应指令中的每个指令均包括：依次排列的前导码、起始标识、数据主体和结束标识，
    所述前导码包括：连续的至少八个比特周期的第一信号，每个所述比特周期为两微秒；所述起始标识包括：连续的至少两个所述比特周期的第二信号；所述数据主体包括：所述n个配置数据或所述n个配置响应数据；所述结束标识均包括：连续的至少两个所述比特周期的第三信号；
    所述第一信号、所述第二信号、所述n个配置数据及其配置响应数据均采用曼彻斯特编码得到。
  31. 一种驱动控制组件，包括存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其中，所述处理器执行所述计算机程序时实现权利要求1至8中任一项所述方法的步骤。
  32. 一种驱动控制组件，包括存储器，处理器及存储在存储器上并可在处理器上运行的计算机程序，其中，所述处理器执行所述计算机程序时实现权利要求9至15中任一项所述方法的步骤。
  33. 一种计算机可读存储介质，其上存储有计算机程序，其中，该计算机程序在被处理器执行时使得处理器实现权利要求1至15中任一项所述方法的步骤。
  34. 一种显示装置，包括：时序控制器和源极驱动芯片；
    所述时序控制器包括权利要求16至23和31中任一项所述的驱动控制组件，所述源极驱动芯片包括权利要求24至30和32中任一项所述的驱动控制组件。
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