USRE37124E1 - Ring oscillator using current mirror inverter stages - Google Patents

Ring oscillator using current mirror inverter stages Download PDF

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Publication number
USRE37124E1
USRE37124E1 US09/096,693 US9669398A USRE37124E US RE37124 E1 USRE37124 E1 US RE37124E1 US 9669398 A US9669398 A US 9669398A US RE37124 E USRE37124 E US RE37124E
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US
United States
Prior art keywords
transistor
coupled
stage
oscillator
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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US09/096,693
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English (en)
Inventor
Trevor K. Monk
Andrew M. Hall
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STMicroelectronics lnc USA
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STMicroelectronics Ltd Great Britain
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Priority to US09/096,693 priority Critical patent/USRE37124E1/en
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Publication of USRE37124E1 publication Critical patent/USRE37124E1/en
Assigned to STMICROELECTRONICS, INC. reassignment STMICROELECTRONICS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STMICROELECTRONICS LIMITED
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03—Astable circuits
    • H03K3/0315—Ring oscillators
    • H03K3/0322—Ring oscillators with differential cells
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/354—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's
    • H03K2005/00202—Layout of the delay element using FET's using current mirrors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/03—Logic gate active element oscillator

Definitions

  • This invention relates to an oscillator and more particularly to a ring oscillator.
  • Advanced Phase-Locked Loops require stable oscillators which may be varied in frequency by a control signal.
  • oscillators integrated into a noisy VLSI environment often use a regulator to generate a quiet power supply. This usually has to be at an even lower voltage than the normal power supply.
  • CMOS Ring Oscillator with controlled frequency which describes a ring oscillator using CMOS transistors and is designed to give an almost sinusoidal output. This design suffers from stability problems outside a narrow range of frequencies. In particular, as the frequency increases, the amplitude decreases and it becomes difficult to convert the signal to CMOS levels.
  • a ring oscillator comprising a plurality of oscillator stages, each stage comprising a first and second transistors.
  • the first transistor has a controllable path connected between an output node and a reference voltage and a control node acting as an input node to the stage.
  • the second transistor has a controllable path connected between the output node and the reference voltage and a control node connected to the output node.
  • the gain of each stage is selectively determined by the ratio of the widths of the first and second transistors to produce an output signal having a sawtooth or trapezoidal waveform.
  • Each stage further comprise a respective current source which controls the speed of the stage and which is connected to the output node.
  • the input node of one stage is connected to the output node of a preceding stage to form a ring and the number of stages is selected so that there is a total phase shift of 360° around the ring at the frequency of operation.
  • the width of the first transistor can be set to m times the width of the second transistor where m>1 to determine the d.c. gain of the stage.
  • This ratio m determines the shape of the waveform output by the oscillator. The higher the value of m, the more the waveform moves away from a sinusoid. For a three stage oscillator, a ratio of m close to 2 produces a substantially sinusoidal output.
  • the present invention uses a ratio higher than 2 and preferably with a minimum value of 2.5. In practice the smallest value that can be selected to provide an appropriately shaped waveform will be selected.
  • the maximum value of m is limited by practical considerations and particularly layout considerations. A practical maximum value for m is likely to be about 10.
  • the first and second transistors can be n-channel field effect devices having a gate as the control node and the source-drain path as the controllable path. As the transistors are of the same type, process variations affect the transistors in the same manner. The maximum frequency of operation is limited only by the ratio of gain to gate capacitance.
  • the current source can comprise a p-channel transistor gated by a control voltage.
  • the first transistor is preferably operated in its saturation region.
  • the current sources of each stage can either be controlled by a common control signal or by respective different control signals.
  • the present oscillator can operate at voltages down to a level just above the threshold voltages of the transistors.
  • FIG. 1 is a circuit diagram of a low-voltage inverting gain stage in MOS technology
  • FIG. 1a is a circuit diagram of an implementation of a current source
  • FIG. 2 is a circuit diagram of a low-voltage inverting gain stage in bipolar technology
  • FIG. 3 is a diagram showing the transistor structure of a ring oscillator
  • FIG. 4 is an equivalent logical schematic for FIG. 3.
  • FIG. 5 shows typical waveforms for the 3-stage ring oscillator of FIGS. 3 and 4 .
  • FIG. 1 shows a low-voltage inverting gain stage in MOS technology.
  • the stage comprises first and second transistors T 1 , T 2 which have their drains connected together and their sources connected to ground.
  • the gate of the first transistor T 1 acts as the input S in for the stage and the gate of the second transistor T 2 acts as the output S out .
  • the gate of the second transistor T 2 is connected to its drain.
  • Each stage is controlled by a control current I which is generated by a current source 2 .
  • the current source 2 is connected between a supply voltage Vcc and the drains of the first and second transistors T 1 ,T 2 .
  • the common node between the current source 2 and the drains of the transistors T 1 and T 2 is denoted 4 . As shown in FIG.
  • the current source 2 can comprise a p-channel MOS field effect transistor T 3 with its source/drain path connected between the supply voltage Vcc and the node 4 and its gate connected to receive a control signal V which is taken with respect to the supply voltage Vcc.
  • V the supply voltage
  • the control current I this can be taken in practice as being derived from the control voltage V.
  • the stage also has capacitance C, the largest component of which is the gate capacitance of the transistors connected to the output S out .
  • the ratio of gains of the transistors T 1 ,T 2 is indicated as “m”.
  • the value of m controls the relative charge and discharge rates of the output mode S out , and thus determines the gain of the stage.
  • the speed of the stage (and thus the phaseshift at the frequency of operation) is readily controlled by varying the current I supplied by the current source 2 .
  • FIG. 2 shows the low-voltage inverting gain stage in bipolar technology. This also has excellent low-voltage operation characteristics and the speed can be controlled using a current source 2 in precisely the same way.
  • MOS circuits it should be understood that the same idea can easily be applied to bipolar technology.
  • the first and second transistors are denoted Ti′ and T 2 ′ and are connected in the same way as for FIG. 1, where gates correspond to bases, drains correspond to collectors and sources correspond to emitters.
  • FIG. 3 illustrates a 3-stage ring oscillator, the three stages being denoted S 1 ,S 2 ,S 3 .
  • Each stage S 1 ,S 2 ,S 3 is as illustrated in FIG. 1 .
  • FIG. 4 shows the ring oscillator in an equivalent logical schematic.
  • Each stage is a so-called single-ended stage, that is with a single input and a single output and is inverting.
  • For oscillation to occur it can be shown that there must be:
  • n number of stages
  • the gain m W(T 1 )/W(T 2 ), where W is the width of a transistor.
  • the parameter m can be made substantially independent of manufacturing process variables which would tend to affect the width of both transistors by corresponding amounts.
  • the required value for m, and hence the transistor sizes, is selected to satisfy small signal and large signal design requirements to provide a sawtooth or trapezoidal waveform.
  • a system designed to produce these waveforms produces a more stable output amplitude from the oscillator across all operating frequencies.
  • a more stable amplitude over a wide range of operating frequencies provides a signal which can be more reliably and easily converted to CMOS levels over a wide range of frequencies.
  • Node 1 , node 2 and node 3 are denoted N 1 , N 2 and N 3 in FIG. 4 .
  • the frequency of oscillation of the ring can be controlled by the control current I.
  • each stage has the same phase shift at the frequency of operation (equal to 180°/n for inverting stages) and receives a common control signal so that the control currents I are the same.
  • the phase shift can differ for each stage provided that the complete phase shift in the loop is 360° at the frequency of oscillation.
  • the control currents I for the individual stages can be independently varied.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Logic Circuits (AREA)
  • Amplitude Modulation (AREA)
  • Superheterodyne Receivers (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
US09/096,693 1993-04-30 1994-04-27 Ring oscillator using current mirror inverter stages Expired - Lifetime USRE37124E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/096,693 USRE37124E1 (en) 1993-04-30 1994-04-27 Ring oscillator using current mirror inverter stages

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
GB939308944A GB9308944D0 (en) 1993-04-30 1993-04-30 Ring oscillator
GB9308944 1993-04-30
US08/360,699 US5525938A (en) 1993-04-30 1994-04-27 Ring oscillator using current mirror inverter stages
PCT/GB1994/000890 WO1994026025A1 (en) 1993-04-30 1994-04-27 Ring oscillator
US09/096,693 USRE37124E1 (en) 1993-04-30 1994-04-27 Ring oscillator using current mirror inverter stages

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/360,699 Reissue US5525938A (en) 1993-04-30 1994-04-27 Ring oscillator using current mirror inverter stages

Publications (1)

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USRE37124E1 true USRE37124E1 (en) 2001-04-03

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Family Applications (5)

Application Number Title Priority Date Filing Date
US08/360,696 Expired - Lifetime US5635866A (en) 1993-04-30 1994-04-27 Frequency Doubler
US08/360,698 Expired - Lifetime US5635877A (en) 1993-04-30 1994-04-27 Low voltage high frequency ring oscillator for controling phase-shifted outputs
US09/096,693 Expired - Lifetime USRE37124E1 (en) 1993-04-30 1994-04-27 Ring oscillator using current mirror inverter stages
US08/360,699 Ceased US5525938A (en) 1993-04-30 1994-04-27 Ring oscillator using current mirror inverter stages
US08/636,851 Expired - Lifetime US5602514A (en) 1993-04-30 1996-04-23 Quadrature oscillator having a variable frequency

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US08/360,696 Expired - Lifetime US5635866A (en) 1993-04-30 1994-04-27 Frequency Doubler
US08/360,698 Expired - Lifetime US5635877A (en) 1993-04-30 1994-04-27 Low voltage high frequency ring oscillator for controling phase-shifted outputs

Family Applications After (2)

Application Number Title Priority Date Filing Date
US08/360,699 Ceased US5525938A (en) 1993-04-30 1994-04-27 Ring oscillator using current mirror inverter stages
US08/636,851 Expired - Lifetime US5602514A (en) 1993-04-30 1996-04-23 Quadrature oscillator having a variable frequency

Country Status (6)

Country Link
US (5) US5635866A (de)
EP (5) EP0648389B1 (de)
JP (4) JPH07507435A (de)
DE (4) DE69421035T2 (de)
GB (1) GB9308944D0 (de)
WO (4) WO1994026025A1 (de)

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US8686787B2 (en) 2011-05-11 2014-04-01 Peregrine Semiconductor Corporation High voltage ring pump with inverter stages and voltage boosting stages
US8742502B2 (en) 2005-07-11 2014-06-03 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
US8994452B2 (en) 2008-07-18 2015-03-31 Peregrine Semiconductor Corporation Low-noise high efficiency bias generation circuits and method
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US9264053B2 (en) 2011-01-18 2016-02-16 Peregrine Semiconductor Corporation Variable frequency charge pump
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US10236872B1 (en) 2018-03-28 2019-03-19 Psemi Corporation AC coupling modules for bias ladders
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US5635877A (en) 1997-06-03
EP0749207A2 (de) 1996-12-18
WO1994026028A1 (en) 1994-11-10
WO1994026026A1 (en) 1994-11-10
GB9308944D0 (en) 1993-06-16
JPH07507914A (ja) 1995-08-31
EP0648386B1 (de) 1999-10-06
DE69426498T2 (de) 2001-05-03
EP0749207B1 (de) 2000-12-27
EP0648387A1 (de) 1995-04-19
EP0648389A1 (de) 1995-04-19
US5525938A (en) 1996-06-11
DE69421035D1 (de) 1999-11-11
DE69404935D1 (de) 1997-09-18
DE69404255T2 (de) 1997-12-18
DE69404935T2 (de) 1998-01-22
JPH07507434A (ja) 1995-08-10
JP2980685B2 (ja) 1999-11-22
EP0648388B1 (de) 1997-07-16
EP0648386A1 (de) 1995-04-19
EP0648388A1 (de) 1995-04-19
DE69426498D1 (de) 2001-02-01
DE69421035T2 (de) 2000-01-27
EP0749207A3 (de) 1997-01-15
JPH07507435A (ja) 1995-08-10
JPH07507436A (ja) 1995-08-10
US5602514A (en) 1997-02-11
WO1994026027A1 (en) 1994-11-10
US5635866A (en) 1997-06-03
EP0648389B1 (de) 1997-08-13
DE69404255D1 (de) 1997-08-21
WO1994026025A1 (en) 1994-11-10

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