US9960153B2 - Semiconductor device and electronic apparatus of a cascode-coupled system - Google Patents

Semiconductor device and electronic apparatus of a cascode-coupled system Download PDF

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US9960153B2
US9960153B2 US14/733,776 US201514733776A US9960153B2 US 9960153 B2 US9960153 B2 US 9960153B2 US 201514733776 A US201514733776 A US 201514733776A US 9960153 B2 US9960153 B2 US 9960153B2
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semiconductor chip
source
gate
semiconductor device
mosfet
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US20160211246A1 (en
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Satoru Akiyama
Hiroyoshi Kobayashi
Hisao Inomata
Sei SAITOU
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Renesas Electronics Corp
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Renesas Electronics Corp
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Definitions

  • the present invention relates to a semiconductor device and an electronic apparatus, and to a technology effective when applied to a power semiconductor device used in, for example, an inverter for an air conditioner, a DC/DC converter for a computer power supply, an AC/AC inverter, inverter modules for a hybrid vehicle and an electric vehicle, etc., and an electronic apparatus including the power semiconductor device.
  • a power semiconductor device used in, for example, an inverter for an air conditioner, a DC/DC converter for a computer power supply, an AC/AC inverter, inverter modules for a hybrid vehicle and an electric vehicle, etc.
  • Patent Document 1 a mounting technique for a semiconductor device in which one junction FET (Junction Field Effect Transistor) with silicon carbide (SiC) as a material, and one MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with silicon (Si) as a material are cascode-coupled.
  • junction FET Joint Field Effect Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • Patent Document 2 A circuit diagram for cascode-coupling a plurality of junction FETs and one MOSFET has been described in U.S. Pat. No. 6,535,050 Specification (Patent Document 2).
  • a switching element power semiconductor device which makes an improvement in breakdown voltage and a reduction in on resistance compatible
  • a switching element using a cascode coupling system has a configuration in which, for example, a normally-on junction FET using a material larger in bandgap than silicon, and a normally-off MOSFET using silicon are coupled in series.
  • the switching element of the cascode coupling system there can be obtained a switching element which is capable of ensuring a breakdown voltage by a junction FET large in insulation breakdown voltage and makes an improvement in breakdown voltage and a reduction in on resistance compatible by a reduction in on resistance by a normally-on junction FET and a reduction in on resistance by a low breakdown voltage MOSFET.
  • an inverter module (electronic apparatus) for a hybrid vehicle is required to have a large current capacity.
  • a power semiconductor device using a cascode coupling system is adopted as a power semiconductor device that configures an inverter module, there is a need to increase the size of a semiconductor chip in order to increase the current capacity.
  • the power semiconductor device using the cascode coupling system has a junction FET semiconductor chip formed with a junction FET with silicon carbide as a material, and a MOSFET semiconductor chip formed with a MOSFET with silicon as a material.
  • the power semiconductor device using the cascode coupling system has a junction FET semiconductor chip formed with a junction FET with silicon carbide as a material, and a MOSFET semiconductor chip formed with a MOSFET with silicon as a material.
  • the junction FET semiconductor chip uses, for example, silicon carbide as the material and is larger in crystal defects than the MOSFET semiconductor chip with silicon as the material. Therefore, it has been found that particularly when the size (active size) of the junction FET semiconductor chip is designed large to increase the current capacity, a proper product yield for the junction FET semiconductor chip is degraded. That is, according to the examinations of the present inventors, there exists in the semiconductor device using the cascode coupling system, room for its improvement when increasing the current capacity in terms of improving the manufacturing yield of the semiconductor device.
  • a semiconductor device of a cascode coupling system has a plurality of junction FET semiconductor chips formed with a plurality of junction FETs in a divided fashion, and a MOSFET semiconductor chip formed with a MOSFET.
  • an electronic apparatus includes a semiconductor device of a cascode coupling system as a semiconductor device which is electrically coupled to a load and drives the load.
  • the semiconductor device of the cascode coupling system has a plurality of junction FET semiconductor chips formed with a plurality of junction FETs in a divided fashion, and a MOSFET semiconductor chip formed with a MOSFET.
  • FIG. 1 is a diagram showing a circuit configuration of a power semiconductor device adopting a cascode coupling system according to an embodiment 1;
  • FIG. 2 is a diagram showing a circuit configuration of a power semiconductor device adopting a general cascode coupling system
  • FIG. 3A is a circuit diagram showing an inverter using cascode-coupled junction FETs and MOSFETs both shown in FIG. 2 as switching elements
  • FIG. 3B is a diagram showing waveforms when the switching element configuring an upper arm is turned on
  • FIG. 3C is a diagram showing waveforms when the switching element configuring the upper arm is turned off;
  • FIG. 4 is a diagram showing a mounting structure of a power semiconductor device according to an embodiment 2;
  • FIG. 5 is a diagram showing a mounting structure of a power semiconductor device according to a modification 1;
  • FIG. 6 is a diagram showing a mounting structure of a power semiconductor device according to a modification 2;
  • FIG. 7 is a typical diagram showing a cross-section of the power semiconductor device according to the modification 2 and a sectional diagram cut along line A-A of FIG. 6 ;
  • FIG. 8 is a diagram of the power semiconductor device according to the modification 2 as viewed from the lower surface side of a sealing body MR;
  • FIG. 9 is a diagram showing a mounting structure of a power semiconductor device according to a modification 3.
  • FIG. 10 is a diagram showing a mounting structure of a power semiconductor device according to a modification 4.
  • FIG. 11 is a sectional diagram cut along line A-A of FIG. 10 ;
  • FIG. 12 is a diagram showing a mounting structure of a power semiconductor device according to a modification 5.
  • FIG. 13 is a sectional diagram showing an example of a device structure of a MOSFET according to an embodiment 3;
  • FIG. 14 is a sectional diagram typically showing a partial area of a junction FET semiconductor chip
  • FIG. 15 is an enlarged diagram of the partial area of FIG. 14 and a sectional diagram showing a device structure of a unit junction FET;
  • FIG. 16 is a block diagram showing the configuration of a control system according to an embodiment 4.
  • FIG. 17 is a circuit block diagram of an inverter which drives a motor in accordance with an input signal from a control unit.
  • the number of elements or the like is not limited to a specific number and may be greater than or less than or equal to the specific number unless otherwise specified in particular and definitely limited to the specific number in principle.
  • a power semiconductor device has been used in inverters for a railway vehicle, a hybrid car and an electric vehicle, an inverter for an air conditioner, and a power supply for a consumer appliance such as a personal computer.
  • An improvement in the performance of the power semiconductor device contributes greatly to an improvement in power efficiency of an infrastructure system or a consumer appliance. Improving the power efficiency enables an energy resource necessary for the operation of a system to be reduced. In other words, a reduction in the emission amount of carbon dioxide, i.e., an environmental load can be reduced. Therefore, the research and development toward improving the performance of the power semiconductor device have been actively carried out by respective companies.
  • a power semiconductor device uses silicon as a material in a manner similar to large scale integration (LSI).
  • LSI large scale integration
  • SiC silicon carbide
  • GaN gallium nitride
  • a power semiconductor device with silicon carbide as a material can be made thinner in thickness than the power semiconductor device with silicon as the material, so that a resistance value (on resistance value) Ron during conduction can remarkably be reduced.
  • the power semiconductor device with silicon carbide as the material is capable of greatly reducing a conduction loss (Ron ⁇ i 2 ) represented by the product of the resistance value Ron and a conduction current i and contributes greatly to an improvement in the power efficiency.
  • Ron ⁇ i 2 conduction loss
  • MOSFET, a schottky diode and a junction FET using silicon carbide as the material has been advanced at home and abroad by paying attention to the properties of such silicon carbide.
  • junction FET junction FET
  • the junction FET requires no gate insulating film comprised of, for example, a silicon oxide film when compared with the MOSFET with silicon carbide as the material, it is possible to avoid a defect at the interface between the silicon oxide film and silicon carbide, and a problem typified by degradation of element characteristics with the defect.
  • the junction FET is capable of controlling the extension of a depletion layer due to a pn junction to control on/off of a channel, a normally-off junction FET and a normally-on junction FET can easily and separately be formed.
  • the junction FET with silicon carbide as the material is excellent even in long-term reliability and also has a feature to facilitate the manufacture of the power semiconductor device.
  • the channel is normally turned on to allow current to flow therein.
  • a negative voltage is applied to a gate electrode to extend the depletion layer from the pn junction and thereby turn off the channel.
  • the “normally-on field effect transistor” is a field effect transistor in which even when no gate voltage is applied, a channel exists and a drain current flows.
  • the normally-on junction FET is destroyed due to some cause, the current continues to flow with the channel on. It is normally desirable in terms of a fail-safe that the current does not flow when the junction FET is destroyed.
  • the normally-on junction FET is however subject to the limitation of use because the current continues to flow even when the junction FET is destroyed.
  • the normally-off junction FET is desired in terms of the fail-safe.
  • the “normally-off field effect transistor” is a field effect transistor in which when the gate voltage is not applied, a channel does not exist and a drain current does not flow.
  • the normally-off junction FET has the following problems. That is, the gate electrode and the source region of the junction FET respectively have a pn junction diode structure comprised of a p-type semiconductor region (gate electrode) and an n-type semiconductor region (source region). Therefore, when the voltage between the gate electrode and the source region reaches 3V or so, the parasitic diode between the gate electrode and the source region is turned on. As a result, a large current may flow between the gate electrode and the source region. Thus, heat is excessively generated in the junction FET to cause a possibility of destroying the junction FET.
  • the gate voltage is limited to a low voltage of 2.5V or so, and the junction FET is used in a state in which the parasitic diode is not turned on or a state in which the diode current between the gate electrode and the source region is sufficiently small.
  • a gate voltage of 0 to 15V or 20V or so is applied in the normal MOSFET with silicon as the material. Therefore, in order to use the normally-off junction FET, there is a need to add a step-down circuit (DC/DC converter) for generating a voltage of 2.5V or so, a level conversion circuit, etc. in addition to the gate drive circuit for the existing MOSFET.
  • DC/DC converter step-down circuit
  • This design change, i.e., the addition of parts results in an increase in the cost of the entire system.
  • the junction FET is provided which is excellent in long-term reliability and has the property of being easy to make, but is much different from the general MOSFET in terms of the gate voltage for its driving. Therefore, when the junction FET is newly used, a large design change including a drive circuit and the like is required, thereby resulting in the presence of a problem that the cost of the entire system rises.
  • This cascode coupling system is a system in which a normally-on junction FET with silicon carbide as a material, and a low breakdown voltage MOSFET with silicon as a material are coupled in series. Since a gate drive circuit drives the low breakdown voltage MOSFET when such a coupling system is adopted, it is not necessary to change the gate drive circuit. On the other hand, the breakdown voltage between the drain and source can be determined by the property of the junction FET high in insulation breakdown voltage.
  • the cascode coupling system has a possibility of being capable of solving the problem of the normally-off junction FET. That is, the power semiconductor device that adopts the cascode coupling system has utility in terms of improving the performance of the power semiconductor device while suppressing a rise in the cost.
  • the general current capacity of the power semiconductor device ranges from about 10 A to 20 A, but the power semiconductor device used in the hybrid vehicle or the like has been required to have a large current capacity in recent years. Specifically, a current capacity of 50 A or higher may be required.
  • a current capacity of 50 A or higher may be required.
  • the size of each semiconductor chip included in the power semiconductor device This applies even to the power semiconductor device using the cascode coupling system in like manner. That is, in order to increase the current capacity in the power semiconductor device of the cascode coupling system, there is a need to increase the size of a junction FET semiconductor chip and increase the size of a MOSFET semiconductor chip.
  • the junction FET semiconductor chip uses, for example, silicon carbide as the material and is larger in crystal defect (killer defect) than the MOSFET semiconductor chip with silicon as the material. From this, particularly when the size of the junction FET semiconductor chip is increased to make the current capacity large, the probability that the killer defects being fatal defects are formed in the junction FET semiconductor chip becomes high. This means that the proper product yield of the junction FET semiconductor chip is degraded. Thus, in the power semiconductor device using the cascode coupling system, when the manufacturing yield of the power semiconductor device is taken into consideration where the current capacity is made large, it is difficult to simply increase the size of the junction FET semiconductor chip.
  • FIG. 1 is a diagram showing a circuit configuration of a power semiconductor device adopting a cascode coupling system, according to the present embodiment 1.
  • the power semiconductor device having adopted the cascode coupling system, according to the present embodiment 1 has a plurality of normally-on junction FETs Q 1 A and Q 1 B each provided between a source S and a drain D, and one normally-off MOSFET Q 2 . That is, as shown in FIG. 1 , in the power semiconductor device according to the present embodiment 1, the junction FETs Q 1 A and Q 1 B are coupled in parallel with each other. Further, the parallel-coupled junction FETs Q 1 A and Q 1 B are coupled in series with one MOSFET Q 2 .
  • the junction FETs Q 1 A and Q 1 B are arranged on the drain D side, whereas one MOSFET Q 2 is arranged on the source S side. That is, a source Sj of the junction FET Q 1 A is coupled to a drain Dm of the MOSFET Q 2 , and a source Sm of the MOSFET Q 2 is coupled to a source S of the power semiconductor device. Further, a gate electrode Gj 0 of the junction FET Q 1 A is coupled to the source S of the power semiconductor device. A gate electrode Gm of the MOSFET Q 2 is coupled to a gate drive circuit (not shown).
  • a source Sj of the junction FET Q 1 B is coupled to the drain Dm of the MOSFET Q 2
  • a gate electrode Gj 1 of the junction FET Q 1 B is coupled to the source S of the power semiconductor device.
  • Such a coupling system as shown in FIG. 1 corresponds to the cascode coupling system in the present embodiment 1.
  • the power semiconductor device that has adopted the cascode coupling system According to the power semiconductor device that has adopted the cascode coupling system, according to the present embodiment 1, there can be obtained an advantage of making it unnecessary to make a change in the gate drive circuit from when a single MOSFET is used as the power semiconductor device, because the gate drive circuit (not shown) drives the gate electrode Gm of the MOSFET Q 2 . From this, according to the present embodiment 1, it is possible to suppress an increase in production cost because there is no need to provide a new gate drive circuit.
  • the junction FETs Q 1 A and Q 1 B respectively use a substance larger in bandgap than silicon as a material as typified by silicon carbide or gallium nitride, the insulation breakdown voltage of each of the junction FETs Q 1 A and Q 1 B becomes large. Therefore, the breakdown voltage of the cascode-coupled power semiconductor device is mainly determined by the characteristics of the junction FETs Q 1 A and Q 1 B. Thus, the insulation breakdown voltage required of the MOSFET Q 2 coupled in series with the junction FETs Q 1 A and Q 1 B can be made lower than that for the power semiconductor device using the single MOSFET.
  • a MOSFET of a low breakdown voltage e.g., a few 10 volts or so
  • the MOSFET Q 2 even if the insulation breakdown voltage is required as for the power semiconductor device, it is possible to reduce the on resistance of the MOSFET Q 2 .
  • the FETs Q 1 A and Q 1 B are respectively comprised of a normally-on junction FET, the on resistances of the junction FETs Q 1 A and Q 1 B can also be reduced.
  • the cascode-coupled power semiconductor device it has an advantage that a design change in the gate drive circuit is made unnecessary. Further, securing the insulation resistance and a reduction in the on resistance can be made compatible. Consequently, it is possible to improve the electrical characteristics of the power semiconductor device.
  • the cascode-coupled junction FETs Q 1 A and Q 1 B are of the normally-on junction FETs.
  • the gate electrode Gj 0 of the junction FET Q 1 A and the gate electrode Gj 1 of the junction FET Q 1 B are both electrically coupled to the source S of the power semiconductor device.
  • the voltage between the gate electrode Gj 0 of the junction FET Q 1 A and the source S, and the voltage between the gate electrode Gj 1 of the junction FET Q 1 B and the source S are not forward-biased at switching (turning-on).
  • the application of the positive voltage to the gate electrodes Gj 0 and Gj 1 with respect to the source S means that a forward voltage (forward bias) is applied between the source region and the gate electrode Gj 0 and between the source region and the gate electrode Gj 1 . Therefore, in the normally-off junction FET, when the forward voltage is excessively increased, the parasitic diode comprised of the source region and the gate electrode Gj 0 , and the parasitic diode comprised of the source region and the gate electrode Gj 1 are turned on. As a result, a large current may flow between the gate electrode Gj 0 and the source region and between the gate electrode Gj 1 and the source region, and the junction FET may result in breakdown with excessive heat generation.
  • the normally-on junction FETs Q 1 A and Q 1 B are used, and the gate electrode Gj 0 and the gate electrode Gj 1 are electrically coupled to the source S of the power semiconductor device. From this, the voltage between the gate electrode Gj 0 of the junction FET Q 1 A and the source S, and the voltage between the gate electrode Gj 1 of the junction FET Q 1 B and the source S are not forward-biased even at the switching (turning-on). Thus, since a large current due to the parasitic diode of each of the junction FETs Q 1 A and Q 1 B does not flow in the cascode connection in the present embodiment 1, it is possible to suppress breakdown of the power semiconductor device due to excessive heat generation.
  • the feature point in the present embodiment 1 resides in that with, as an assumption, the circuit configuration in which the junction FETs Q 1 A and Q 1 B and one MOSFET Q 2 are cascode-coupled as shown in FIG. 1 , the junction FET Q 1 A is formed in a semiconductor chip CHP 0 , and the junction FET Q 1 B is formed in a semiconductor chip CHP 1 .
  • the feature point in the present embodiment 1 resides in that the junction FET Q 1 A and the junction FET Q 1 B both coupled in parallel with each other are formed in the separate semiconductor chips.
  • the junction FET Q 1 A is formed in the semiconductor chip CHP 0 having a substrate comprised of a semiconductor larger in bandgap than silicon. Further, the junction FET Q 1 B is formed in the semiconductor chip CHP 1 having a different substrate comprised of a semiconductor larger in bandgap than silicon. On the other hand, the MOSFET Q 2 is formed in a semiconductor chip CHP 2 having a substrate comprised of silicon.
  • the power semiconductor device of the cascode coupling system can be realized which deals with an increase in current while improving the manufacturing yield.
  • the junction FETs Q 1 A and Q 1 B are coupled in parallel in the cascode coupling in the present embodiment 1. Therefore, the current flowing through the cascode-coupled power semiconductor device becomes the sum of the current flowing through the junction FET Q 1 A, and the current flowing through the junction FET Q 1 B, thereby making it possible to cope with the large current flow in the power semiconductor device. That is, since the current capacity can be made large in the cascode-coupled power semiconductor device according to the present embodiment 1, so that the power semiconductor device according to the present embodiment 1 can be applied even to, for example, applications for a hybrid vehicle and the like, which are large in current capacity.
  • the junction FET Q 1 A is formed in the semiconductor chip CHP 0
  • the junction FET Q 1 B is formed in the semiconductor chip CHP 1 . This means that the size of the semiconductor chip CHP 0 and the size of the semiconductor chip CHP 1 can be reduced.
  • junction FET Q 1 A is comprised of 10,000 pieces of unit junction FETs
  • junction FET Q 1 B is also comprised of 10,000 pieces of unit junction FETs.
  • the junction FETs Q 1 A and Q 1 B are formed in the single same semiconductor chip, the 20,000 pieces of unit junction FETs are formed in the same semiconductor chip.
  • the junction FET Q 1 A and the junction FET Q 1 B are formed in the separate semiconductor chips as in the case where the junction FET Q 1 A is formed in the semiconductor chip CHP 0 and the junction FET Q 1 B is formed in the semiconductor chip CHP 1 , the number of unit junction FETs formed in each of the semiconductor chip CHP 0 and the semiconductor chip CHP 1 becomes 10,000 pieces.
  • junction FET Q 1 A and the junction FET Q 1 B are formed in the single same semiconductor chip, it is necessary to form 20,000 pieces of unit junction FETs in the semiconductor chip.
  • the junction FET Q 1 A and the junction FET Q 1 B are formed in the separate semiconductor chips, 10,000 pieces of unit junction FETs equal to half of 20,000 pieces are formed in each of the separate semiconductor chips CHP 0 and CHP 1 .
  • the size of the semiconductor chip in which the junction FETs Q 1 A and Q 1 B are formed becomes larger than the size of the semiconductor chip CHP 0 and the size of the semiconductor chip CHP 1 , both chips having formed the junction FETs Q 1 A and Q 1 B separately.
  • the size of the semiconductor chip CHP 0 and the size of the semiconductor chip CHP 1 both chips having formed the junction FETs Q 1 A and Q 1 B separately, become smaller than the size of the semiconductor chip in which the junction FET Q 1 A and the junction FET Q 1 B are formed.
  • junction FET Q 1 A and the junction FET Q 1 B are formed in the separate semiconductor chips as in the present embodiment 1, an increase in the size of each individual semiconductor chip can be suppressed even while increasing the current capacity. Further, if the size of each individual semiconductor chip is made small, the manufacturing yield of the semiconductor chip is improved.
  • the junction FET semiconductor chip which forms each junction FET uses, as a material, a substance larger in bandgap than silicon. Specifically, as the substance larger in bandgap than silicon, there is known silicon carbide.
  • the junction FET semiconductor chip can be formed of silicon carbide.
  • a semiconductor wafer comprised of silicon carbide has more crystal defects than a semiconductor wafer comprised of silicon and hence has also many killer defects that influence the manufacturing yield. That is, since the technology using the silicon carbide is a technology which has begun to appear in recent years, the manufacturing technology is not so developed as the already-established technology using silicon. There is room for improvement in terms of manufacturing a semiconductor wafer having less crystal defects and high quality.
  • the probability that many fatal killer defects that influence the manufacturing yield are contained in the semiconductor chip becomes high. That is, as in the present embodiment 1, when the size of the junction FET semiconductor chip formed of silicon carbide is increased to enlarge the current capacity, corresponding to an increase in current, the probability that the killer defects are formed within the junction FET semiconductor chip becomes high. This means that the manufacturing yield of the junction FET semiconductor chip is degraded. Thus, increasing the size of the junction FET semiconductor chip formed of silicon carbide to make the current capacity large in correspondence with the increase in current is not reasonable in terms of improving the manufacturing yield.
  • the junction FETs Q 1 A and Q 1 B coupled in parallel with each other are formed in the separate semiconductor chips as shown in FIG. 1 .
  • the reduction in the size of each of the individual semiconductor chips CHP 0 and CHP 1 means that the probability that the killer effects are contained in the semiconductor chips CHP 0 and CHP 1 becomes low as described above. This means that the manufacturing yields of the semiconductor chip CHP 0 formed with the junction FET Q 1 A and the semiconductor chip CHP 1 formed with the junction FET Q 1 B are improved.
  • the power semiconductor device of the cascode coupling system can be realized which deals with the increase in current while improving the manufacturing yield of each individual junction FET semiconductor chip.
  • the junction FET semiconductor chips may be different in size from each other, but are desirably identical in size to each other. This is because when the sizes of the junction FET semiconductor chips are made identical to each other, mass productivity of the junction FET semiconductor chips can be improved. That is, when the sizes of the junction FET semiconductor chips are made different from each other, there is a need to provide manufacturing equipment corresponding to the respective sizes, thus leading to the complication of the manufacturing equipment. On the other hand, when the sizes of the junction FET semiconductor chips are made identical to each other, the manufacturing equipment is simplified and can thus be improved in mass productivity.
  • the manufacturing yield of the entire power semiconductor device including the junction FET semiconductor chip of the first size and the junction FET semiconductor chip of the second size is however taken into consideration, the manufacturing yield of the entire power semiconductor device depends on the probability that the killer defects are contained in the junction FET semiconductor chip of the first size being of the relatively large size. That is, when the sizes of the junction FET semiconductor chips are made different from each other, the manufacturing yield of the entire power semiconductor device is determined depending on the manufacturing yield of the junction FET semiconductor chip having the relatively large size (first size).
  • the size (third size) of the junction FET semiconductor chip becomes larger than the above-described second size, but smaller than the above-described first size.
  • the manufacturing yield of the entire power semiconductor device depends on the probability that killer defects are contained in the junction FET semiconductor chip of the third size. That is, when the sizes of the junction FET semiconductor chips are made identical to each other, the manufacturing yield of the entire power semiconductor device is determined depending on the manufacturing yield of the junction FET semiconductor chip of the third size.
  • the probability that the killer defects are contained in the junction FET semiconductor chip of the third size becomes smaller than the probability that the killer defects are contained in the junction FET semiconductor chip of the first size.
  • the configuration that the sizes of the junction FET semiconductor chips are made identical to each other provides that the manufacturing yield of the entire power semiconductor device can be improved, as compared with the configuration that the sizes of the junction FET semiconductor chips are made different from each other. From the above, considering the improvement in mass productivity and the improvement in the manufacturing yield of the entire power semiconductor device, it is understood that the sizes of the junction FET semiconductor chips are preferably made identical to each other rather than the sizes of the junction FET semiconductor chips being made different from each other.
  • the present embodiment 2 will next describe a mounting structure of a power semiconductor device in which the technical idea in the embodiment 1 has been embodied.
  • an improvement in the performance of the power semiconductor device is attained considering even room for improvement peculiar to the cascode coupling system upon embodying the technical idea in the embodiment 1. That is, the present embodiment 2 will describe the mounting structure in which the technical idea in the embodiment 1 is embodied, while improving the performance of the power semiconductor device of the cascode coupling system.
  • the first room for improvement widely exists not only in the configuration example in which the junction FETs and one MOSFET are cascode-coupled as in the embodiment 1, but also in a general configuration example in which one junction FET and one MOSFET are cascode-coupled. Therefore, the first room for improvement will be described below by, for the safe of simplicity, taking for example the general configuration in which one junction FET and one MOSFET are cascode-coupled.
  • FIG. 2 is a diagram showing a circuit configuration of a power semiconductor device having adopted a general cascode coupling system.
  • the power semiconductor device having adopted the general cascode coupling system has a configuration in which a normally-on junction FET Q 1 and a normally-off MOSFET Q 2 are coupled in series between a source S and a drain D.
  • the junction FET Q 1 is arranged on the drain D side
  • the MOSFET Q 2 is arranged on the source S side. That is, a source Sj of the junction FET Q 1 is coupled to a drain Dm of the MOSFET Q 2 , and a source Sm of the MOSFET Q 2 is coupled to the source S of the power semiconductor device.
  • a gate electrode Gj of the junction FET Q 1 is coupled to the source S of the power semiconductor device, and a gate electrode Gm of the MOSFET Q 2 is coupled to a gate drive circuit (not shown).
  • a free wheel diode is coupled in antiparallel with the MOSFET Q 2 .
  • the free wheel diode has the function of circulating a backward current to release energy stored in an inductance. That is, when the power semiconductor device is turned off where the power semiconductor device shown in FIG. 2 is coupled to a load including an inductance, a backward current in the direction opposite to the direction in which the current of the MOSFET Q 2 flows is generated by the inductance included in the load. From this, the backward current is circulated by providing the free wheel diode in antiparallel with the MOSFET Q 2 to release the energy stored in the inductance.
  • the drain Dm of the low breakdown voltage MOSFET Q 2 and the source Sj of the junction FET Q 1 are coupled via the bonding wire.
  • a parasitic inductance based on the bonding wire is added to the source Sj of the junction FET Q 1 .
  • a large surge voltage is generated at the switching.
  • a voltage more than the breakdown voltage is applied to the low breakdown voltage MOSFET Q 2 .
  • FIG. 3A is a circuit diagram showing an inverter which uses the cascode-coupled junction FET and MOSFET shown in FIG. 2 as each switching element (power semiconductor device).
  • the inverter shown in FIG. 3A has an upper arm UA and a lower arm BA coupled in series with a power supply VCC.
  • the upper arm UA is comprised of a switching element coupled between a drain D 1 and a source S 1 .
  • the switching element which configures the upper arm UA is comprised of a junction FET Q 1 a and a MOSFET Q 2 a cascode-coupled.
  • a drain Dj 1 of the junction FET Q 1 a is coupled to the drain D 1 of the switching element, and a source Sj 1 of the junction FET Q 1 a is coupled to a drain Dm 1 of the MOSFET Q 2 a .
  • a source Sm 1 of the MOSFET Q 2 a is coupled to the source S 1 of the switching element.
  • a gate electrode Gj 1 of the junction FET Q 1 a is coupled to the source S 1 of the switching element, and a gate drive circuit (G/D) is coupled between a gate electrode Gm 1 of the MOSFET Q 2 a and the source S 1 of the switching element.
  • a parasitic inductance Lse 1 based on a bonding wire exists between the source Sj 1 of the junction FET Q 1 a and the drain Dm 1 of the MOSFET Q 2 a
  • a parasitic inductance Lgi 1 based on a bonding wire exists between the gate electrode Gj 1 of the junction FET Q 1 a and the source S 1 of the switching element.
  • the voltage between the source S 1 of the switching element and the drain D 1 of the switching element is defined as a voltage Vdsu
  • the voltage between the source S 1 of the switching element and the drain Dm 1 of the MOSFET Q 2 a is defined as a voltage Vdsmu.
  • the lower arm BA is comprised of a switching element coupled between a drain D 2 and a source S 2 .
  • the switching element which configures the lower arm BA is comprised of a junction FET Q 1 b and a MOSFET Q 2 b cascode-coupled. Specifically, a drain Dj 2 of the junction FET Q 1 b is coupled to the drain D 2 of the switching element, and a source Sj 2 of the junction FET Q 1 b is coupled to a drain Dm 2 of the MOSFET Q 2 b . Also, a source Sm 2 of the MOSFET Q 2 b is coupled to the source S 2 of the switching element.
  • a gate electrode Gj 2 of the junction FET Q 1 b is coupled to the source S 2 of the switching element, and a gate drive circuit (G/D) is coupled between a gate electrode Gm 2 of the MOSFET Q 2 b and the source S 2 of the switching element. Furthermore, a load inductance LL is coupled between the source S 2 of the switching element and the drain D 2 of the switching element.
  • a parasitic inductance Lse 2 based on a bonding wire exists between the source Sj 2 of the junction FET Q 1 b and the drain Dm 2 of the MOSFET Q 2 b
  • a parasitic inductance Lgi 2 based on a bonding wire exists between the gate electrode Gj 2 of the junction FET Q 1 b and the source S 2 of the switching element.
  • the voltage between the source S 2 of the switching element and the drain D 2 of the switching element is defined as a voltage Vak
  • the voltage between the source S 2 of the switching element and the drain Dm 2 of the MOSFET Q 2 b is defined as a voltage Vdsmd.
  • the inverter using the cascode-coupled switching elements shown in FIG. 3 is configured as described above.
  • the mechanism for causing the first room for improvement will be described below while describing the operation of the inverter.
  • a description will first be made about the case where the switching element configuring the upper arm UA is turned on. That is, a description will be made about the case where the power supply voltage is applied to the load (including load inductance) by turning on the switching element configuring the upper arm UA and turning off the switching element configuring the lower arm BA.
  • FIG. 3B shows waveforms where the switching element configuring the upper arm UA is turned on. Specifically, since the junction FET Q 1 a and the MOSFET Q 2 a configuring the upper arm UA are turned on when the switching element configuring the upper arm UA is tuned on, a reflux current flows through a path from the drain Dj 1 of the junction FET Q 1 a to the power supply VCC to which it returns through the load inductance LL by way of the drain Dm 1 and source Sm 1 of the MOSFET Q 2 a . At this time, as shown in FIG.
  • the voltage Vdsmu is changed to 0V or so from a predetermined voltage, whereas the voltage Vak rises from 0V to the voltage of the power supply voltage or so when the switching element of the upper arm UA is being turned off.
  • the voltage Vdsmd corresponding to the drain voltage of the MOSFET Q 2 b of the lower arm BA rises up to a voltage at which the junction FET Q 1 b of the lower arm BA is cut off. After the junction FET Q 1 b of the lower arm BA is turned off, a certain constant voltage is maintained.
  • a change in the voltage Vdsmd is a change in ideal state that the parasitic inductance is negligible and is indicated by a broken line in FIG. 3B .
  • FIG. 3C shows waveforms where the switching element configuring the upper arm UA is turned off.
  • the voltage Vdsmd changes from a predetermined voltage to 0V or so as shown in FIG. 3C .
  • the voltage Vdsu rises from 0V to the voltage of the power supply voltage or so when the switching element of the upper arm UA is being turned on.
  • the voltage Vdsmu corresponding to the drain voltage of the MOSFET Q 2 a of the upper arm UA rises up to a voltage at which the junction FET Q 1 a of the upper arm UA is cut off.
  • a change in the voltage Vdsmu is a change in an ideal state that the parasitic inductance is negligible and is indicated by a broken line in FIG. 3C .
  • the parasitic inductance Lse 1 and the parasitic inductance Lgi 1 are increased, the voltage Vdsmu suddenly rises greatly as indicated by a solid line in FIG. 3C when the switching element of the upper arm UA is turned off.
  • the first mechanism results from the parasitic inductance Lse 2 which exists between the source Sj 2 of the junction FET Q 1 b configuring the lower arm BA and the drain Dm 2 of the MOSFET Q 2 b configuring the lower arm BA. Specifically, when the switching element of the upper arm UA is turned on, the MOSFET Q 2 b of the lower arm BA is turned off. At this time, the voltage Vak begins to increase from 0V or so, and the voltage Vdsmd corresponding to the drain voltage of the MOSFET Q 2 b of the lower arm BA also begins to increase with the increase in the voltage Vak.
  • the voltage Vdsmd is not made larger than the gate voltage applied to the gate electrode Gj 2 of the junction FET Q 1 b beyond a predetermined value. Therefore, the junction FET Q 1 b is not cut off so that the current flows from the drain Dj 2 of the junction FET Q 1 b to the source Sj 2 thereof. As a result, the current flows into the drain Dm 2 of the MOSFET Q 2 b where an electric charge is accumulated. From this, the voltage Vdsmd corresponding to the drain voltage of the MOSFET Q 2 b rises.
  • the junction FET Q 1 b is cut off so that the current does not flow any more. That is, since in the initial stage of increasing the voltage Vdsmd, the current flows between the drain Dj 2 of the junction FET Q 1 b and the source Sj 2 thereof, and the electric charge is accumulated in the drain Dm 2 of the MOSFET Q 2 b , the voltage Vdsmd increases.
  • the junction FET Q 1 b is cut off by making the voltage Vdsmd larger beyond the predetermined value than the gate voltage of the junction FET Q 1 b .
  • the electric charge flowing into the drain Dm 2 of the MOSFET Q 2 b does not appear and hence the voltage Vdsmd becomes substantially constant.
  • the switching element of the upper arm UA is turned on, the MOSFET Q 2 b of the lower arm BA is turned off, but in this stage, the junction FET Q 1 b of the lower arm BA is not cut off immediately and hence the current flows from the drain Dj 2 of the junction FET Q 1 b to the source Sj 2 thereof. Then, the current having flowed into the source Sj 2 of the junction FET Q 1 b flows into the drain Dm 2 of the MOSFET Q 2 b through the parasitic inductance Lse 2 . At this time, the point to be noted resides in that the current flowing from the drain Dj 2 of the junction FET Q 1 b of the lower arm BA to the source Sj 2 thereof decreases.
  • the current flowing through the parasitic inductance Lse 2 also decreases with time.
  • such an electromotive force as to cancel the decrease in current occurs in the parasitic inductance Lse 2 .
  • the parasitic inductance Lse 2 functions so as to increase the current flowing from the drain Dj 2 of the junction FET Q 1 b to the source Sj 2 thereof. Therefore, when the parasitic inductance Lse 2 becomes large, a large current flows transiently from the drain Dj 2 of the junction FET Q 1 b to the source Sj 2 thereof. As a result, the electric charge flowing into the drain Dm 2 of the MOSFET Q 2 b increases suddenly, whereby that the voltage Vdsmd increases suddenly. This corresponds to the first mechanism.
  • the second mechanism results from the parasitic inductance Lgi 2 which exists between the gate electrode Gj 2 of the junction FET Q 1 b configuring the lower arm BA and the source S 2 of the lower arm BA.
  • the switching element of the upper arm UA is turned on
  • the MOSFET Q 2 b of the lower arm BA is turned off.
  • the voltage Vak begins to increase from 0V or so, but vibrates to a range exceeding the power supply voltage in the initial stage at which the switching element of the upper arm UA is turned on, as shown in FIG. 3B , for example. This is based on a counter electromotive force caused by the load inductance LL included in the load coupled to the inverter.
  • the voltage Vak fluctuates in the initial stage at which the upper arm UA is turned on. If attention is paid to the junction FET Q 1 b here, a parasitic capacitance is formed between the drain Dj 2 of the junction FET Q 1 b and the gate electrode Gj 2 thereof, and the voltage applied to the parasitic capacitance also varies when the voltage Vak fluctuates. Further, since the electrostatic capacitance value of the parasitic capacitance becomes a relatively large value, a charging/discharging current generated with the fluctuation in the voltage applied to the parasitic capacitance also becomes large. The charging/discharging current flows between the gate electrode Gj 2 of the junction FET Q 1 b and the source S 2 of the lower arm BA.
  • the charging/discharging current is a current which temporally changes. Therefore, since the charging/discharging current which temporally changes flows through the parasitic inductance Lgi 2 when the parasitic inductance Lgi 2 exists between the gate electrode Gj 2 of the junction FET Q 1 b and the source S 2 of the lower arm BA, a resistive component proportional to the product of the magnitude of the parasitic inductance Lgi 2 and a time differential of the charging/discharging current is generated between the gate electrode Gj 2 of the junction FET Q 1 b and the source S 2 of the lower arm BA.
  • the gate electrode Gj 2 of the junction FET Q 1 b and the source S 2 of the lower arm BA are not brought to the same potential, so that there occurs a mode for setting the gate electrode Gj 2 of the junction FET Q 1 b in the direction to rise to a positive voltage with respect to the source S 2 of the lower arm BA.
  • the gate electrode Gj 2 of the junction FET Q 1 b becomes the positive voltage, a depletion layer that extends from the gate electrode Gj 2 of the junction FET Q 1 b is suppressed so that the width of a channel region is made large. Therefore, the current flowing from the drain Dj 2 of the junction FET Q 1 b to the source Sj 2 thereof becomes large transiently.
  • the third mechanism results from the parasitic resistance which exists between the gate electrode Gj 2 of the junction FET Q 1 b configuring the lower arm BA and the source S 2 of the lower arm BA.
  • the charging/discharging current flows between the gate electrode Gj 2 of the junction FET Q 1 b and the source S 2 of the lower arm BA. From this, when the parasitic resistance exists between the gate electrode Gj 2 of the junction FET Q 1 b and the source S 2 of the lower arm BA, the charging/discharging current flows through the parasitic resistance so that a voltage drop is developed thereacross.
  • the gate electrode Gj 2 of the junction FET Q 1 b and the source S 2 of the lower arm BA are not brought to the same potential, so that there occurs a mode for setting the gate electrode Gj 2 of the junction FET Q 1 b in the direction to rise to a positive voltage with respect to the source S 2 of the lower arm BA.
  • the gate electrode Gj 2 of the junction FET Q 1 b becomes the positive voltage. Therefore, a depletion layer that extends from the gate electrode Gj 2 of the junction FET Q 1 b is suppressed so that the width of a channel region is made large.
  • the voltage Vdsmd suddenly increases by the first to third mechanisms related to the parasitic inductance Lse 2 , the parasitic inductance Lgi 2 and the parasitic resistance.
  • the voltage Vdsmd corresponding to the drain voltage of the MOSFET Q 2 b of the lower arm BA rises up to a voltage greater than the breakdown voltage of the MOSFET Q 2 b , whereby the MOSFET Q 2 b of the lower arm BA is avalanche-operated, finally resulting in a possibility that the MOSFET Q 2 b of the lower arm BA will be broken down.
  • the gate-to-source voltage of each of the junction FETs Q 1 A and Q 1 B is around ⁇ 5V and in an off state.
  • a displacement current from the drain D to the gate electrode Gj 0 flows into the junction FET Q 1 A through its gate-to-drain capacitance.
  • the displacement current flows from the gate electrode Gj 0 of the junction FET Q 1 A to the source S via a gate wiring resistance rgj 0 and a parasitic resistance Rgj 0 existing inside the junction FET Q 1 A.
  • a displacement current from the drain D to the gate electrode Gj 1 flows into the junction FET Q 1 B via its gate-to-drain capacitance.
  • the displacement current flows from the gate electrode Gj 1 of the junction FET Q 1 B to the source S via a gate wiring resistance rgj 1 and a parasitic resistance Rgj 1 existing inside the junction FET Q 1 B.
  • the gate potential of the gate electrode Gj 0 of the junction FET Q 1 A rises by an integrated value of the displacement current and the gate resistance (gate wiring resistance rgj 0 +parasitic resistance Rgj 0 ).
  • the gate potential of the junction FET Q 1 A rises by 50V with respect to the source potential of the MOSFET Q 2 .
  • the gate potential of the gate electrode Gj 0 of the junction FET Q 1 B also rises by an integrated value of the displacement current and the gate resistance (gate wiring resistance rgj 1 +parasitic resistance Rgj 1 ).
  • the gate potential of the junction FET Q 1 B rises by 50V with respect to the source potential of the MOSFET Q 2 .
  • the gate-to-source voltages of the junction FETs Q 1 A and Q 1 B are respectively brought to the on state at +45V, the electric charge is charged from the high-potential drain D to the drain Dm of the MOSFET Q 2 , i.e., the source Sj of each of the junction FETs Q 1 A and Q 1 B. With this charging operation, the drain potential of the MOSFET Q 2 begins to rise from +5V.
  • the rise in the drain potential of the MOSFET Q 2 is continued until the junction FETs Q 1 A and Q 1 B are respectively brought to the off state. That is, the rise in the drain potential of the MOSFET Q 2 is continued until the gate-to-source voltages of the junction FETs Q 1 A and Q 1 B reach around ⁇ 5V. Accordingly, when the drain potential of the MOSFET Q 2 becomes +55V and the gate potentials of the junction FETs Q 1 A and Q 1 B are respectively brought to a state of 50V, the rise in the drain potential of the MOSFET Q 2 is stopped. Since, at this time, the source potential of the MOSFET Q 2 is 0V, the drain-to-source voltage of the MOSFET Q 2 becomes around 55V.
  • the MOSFET Q 2 when a MOSFET having a breakdown voltage of 30V or so is selected for the MOSFET Q 2 used in the power semiconductor device of the cascode coupling system shown in FIG. 1 , the MOSFET Q 2 is operated in the avalanche mode to cause a possibility that the MOSFET Q 2 will be broken down.
  • a parasitic npn bipolar transistor formed by a source region (n-type semiconductor region), a channel forming region (p-type semiconductor region), and a drift region (n-type semiconductor region) is turned on by the electron-positive hole pairs generated in large quantities.
  • the parasitic npn bipolar transistor is turned on, a large current uncontrollable by the gate electrode Gm of the MOSFET Q 2 flows to generate heat.
  • the MOSFET Q 2 is avalanche-operated by the influence of the gate resistance (gate wiring resistance rgj 0 +parasitic resistance Rgj 0 ) and the gate resistance (gate wiring resistance rgj 1 +parasitic resistance Rgj 1 ) each being of the parasitic resistance, finally resulting in a possibility that the MOSFET Q 2 will be broken down. Further, even in the power semiconductor device of the cascode coupling system shown in FIG. 1 in a manner similar to the general cascode coupling system shown in FIG.
  • the MOSFET Q 2 is avalanche-operated depending on the influence of the parasitic inductance (LS 0 , LS 1 ) due to the above-described first mechanism, and the parasitic inductance (Lgj 1 , Lgj 2 ) due to the above-described second mechanism, finally resulting in a possibility that the MOSFET Q 2 will be broken down.
  • These points correspond to the first room for improvement.
  • the second room for improvement is a problem peculiar to the cascode coupling system shown in FIG. 1 . That is, the second room for improvement is a problem peculiar to a power semiconductor device in which a plurality of junction FETs and one MOSFET are cascode-coupled as in the case of the embodiment 1. That is, when a power semiconductor device of a cascode coupling system is configured using a plurality of FETs, there is a need to pay attention to such second room for improvement as shown below.
  • the source potential becomes a common potential. Therefore, the surge voltage caused by the latter junction FET Q 1 B is applied to the drain potential of the MOSFET Q 2 .
  • the power semiconductor device of the cascode coupling system is configured using the junction FETs, it is very important to equalize the magnitudes of the gate and/or source impedances of the junction FETs in addition to the gate and/or source impedances of the junction FETs being reduced, from the viewpoint of an improvement in the reliability of the power semiconductor device. This point corresponds to the second room for improvement.
  • the first room for improvement and the second room for improvement both described above are respectively given device while embodying the technical idea in the embodiment 1. That is, in the present embodiment 2, in order to suppress the application of the voltage greater than the insulation breakdown voltage to the MOSFET, which causes the avalanche breakdown, a contrivance for reducing the gate and source impedances of the junction FETs and setting them to a uniform value is applied. A technical idea in the present embodiment 2 to which this contrivance has been applied will be described below.
  • the present embodiment 2 is characterized in that the mounting structure of the power semiconductor device of the cascode coupling system shown in FIG. 1 is given the contrivance. The mounting structure of the power semiconductor device including this feature point will be described below.
  • FIG. 4 is a diagram showing a mounting structure (package configuration) of a power semiconductor device PKG 1 according to the present embodiment 2.
  • the power semiconductor device PKG 1 according to the present embodiment 2 has two chip mounting sections PLT 1 and PLT 2 separated from each other.
  • the chip mounting section PLT 1 and the chip mounting section PLT 2 are respectively comprised of a metal plate, for example.
  • the chip mounting section PLT 1 is formed integrally with a drain lead DL so to be coupled thereto.
  • the chip mounting section PLT 1 and the drain lead DL are electrically coupled to each other.
  • a source lead SL and a gate lead GL are arranged separately in such a manner that the drain lead DL is spacedly held therebetween.
  • the source lead SL is separately arranged on the right side of the drain lead DL
  • the gate lead GL is separately arranged on the left side of the drain lead DL.
  • These drain lead DL, source lead SL and gate lead GL are electrically insulated from each other in the off state of the power semiconductor device.
  • a source lead post section SPST comprised of a wide area is formed at the tip portion of the source lead SL
  • a gate lead post section GPST comprised of a wide area is formed at the tip portion of the gate lead GL.
  • a semiconductor chip CHP 0 and a semiconductor chip CHP 1 are mounted over the chip mounting section PLT 1 via, for example, a conductive adhesive comprised of silver paste or solder.
  • the semiconductor chip CHP 0 and the semiconductor chip CHP 1 are respectively formed with, for example, junction FETs with silicon carbide as a material. Further, the back surfaces of the semiconductor chips CHP 0 and CHP 1 serve as drain electrodes respectively.
  • a source pad SPj 0 and a gate pad GPj 0 are formed in the surface (main surface) of the semiconductor chip CHP 0 .
  • a source pad SPj 1 and a gate pad GPj 1 are formed in the surface (main surface) of the semiconductor chip CHP 1 .
  • the semiconductor chip CHP 0 and the semiconductor chip CHP 1 are respectively formed with, in a divided fashion, a plurality of junction FETs that configure a part of the power semiconductor device of the cascode coupling system shown in FIG. 1 .
  • the drain electrodes electrically coupled to the drains of the junction FETs are respectively formed in the back surfaces of the semiconductor chip CHP 0 and the semiconductor chip CHP 1 .
  • the source pad SPj 0 electrically coupled to the source of each junction FET, and the gate pad GPj 0 electrically coupled to the gate electrode of each junction FET are formed in the surface of the semiconductor chip CHP 0 .
  • the source pad SPj 1 electrically coupled to the source of each junction FET, and the gate pad GPj 1 electrically coupled to the gate electrode of each junction FET are formed in the surface of the semiconductor chip CHP 1 .
  • a semiconductor chip CHP 2 is mounted over the chip mounting section PLT 2 through, for example, a conductive adhesive comprised of silver paste or solder.
  • the semiconductor chip CHP 2 is formed with a MOSFET with silicon as a material, for example.
  • the back surface of the semiconductor chip CHP 2 serves as a drain electrode, and a source pad SPm and a gate pad GPm are formed in the surface (main surface) of the semiconductor chip CHP 2 . That is, the semiconductor chip CHP 2 is formed with the MOSFET that configures a part of the power semiconductor device of the cascode coupling system shown in FIG. 1 .
  • the drain electrode electrically coupled to the drain of the MOSFET is formed in the back surface of the semiconductor chip CHP 2 .
  • the source pad SPm electrically coupled to a source of the MOSFET, and the gate pad GPm electrically coupled to a gate electrode of the MOSFET are formed in the surface of the semiconductor chip CHP 2 .
  • the semiconductor chip CHP 0 and the semiconductor chip CHP 1 mounted over the chip mounting section PLT 1 , and the semiconductor chip CHP 2 mounted over the chip mounting section PLT 2 are coupled by bonding wires to thereby make it possible to configure the cascode-coupled power semiconductor device shown in FIG. 1 .
  • the gate pad GPj 0 formed in the surface of the semiconductor chip CHP 0 , and the source lead post section SPST formed at the tip portion of the source lead SL are electrically coupled by a wire Wgj 0 .
  • the gate pad GPj 1 formed in the surface of the semiconductor chip CHP 1 , and the source lead post section SPST formed at the tip portion of the source lead SL are electrically coupled by a wire Wgj 1 .
  • the source pad SPj 0 formed in the surface of the semiconductor chip CHP 0 , and the chip mounting section PLT 2 are electrically coupled by a wire Wds 0 .
  • the source pad SPj 1 formed in the surface of the semiconductor chip CHP 1 , and the chip mounting section PLT 2 are electrically coupled by a wire Wds 1 .
  • the source pad SPm formed in the surface of the semiconductor chip CHP 2 , and the source lead post section SPST formed at the tip portion of the source lead SL are electrically coupled by a wire Wsm.
  • the gate pad GPm formed in the surface of the semiconductor chip CHP 2 , and the gate lead post section GPST formed at the tip portion of the gate lead GL are electrically coupled by a wire Wgm.
  • an area to which the wires Wgj 0 , Wgj 1 and Wsm of the source lead post section SPST are coupled, and an area to which the wire Wgm of the gate lead post section GPST is coupled are respectively configured so as to be positioned at higher positions than the upper surface of the chip mounting section PLT 1 and the upper surface of the chip mounting section PLT 2 , for example.
  • the drain electrodes formed in the back surfaces of the semiconductor chips CHP 0 and CHP 1 are electrically coupled to the chip mounting section PLT 1 .
  • the semiconductor chip CHP 2 is mounted over the chip mounting section PLT 2 through the conductive adhesive, the drain electrode formed in the back surface of the semiconductor chip CHP 2 is electrically coupled to the chip mounting section PLT 2 .
  • a part of the sealing body MR is arranged between the chip mounting section PLT 1 and the chip mounting section PLT 2 , whereby the chip mounting section PLT 1 and the chip mounting section PLT 2 are electrically insulated by the sealing body MR.
  • the sealing body MR is formed in, for example, a rectangular parallelepiped shape and has a first side surface and a second side surface opposite to the first side surface.
  • a part of the drain lead DL, a part of the source lead SL, and a part of the gate lead GL are protruded from the first side surface of the sealing body.
  • These protruded parts of the drain lead DL, source lead SL and gate lead GL function as external coupling terminals.
  • the existing general-purpose package having only one chip mounting section within the power semiconductor device PKG 1 cannot be diverted as it is.
  • a so-called vertical structure having drain electrodes at the back surfaces of semiconductor chips has been adopted for the junction FETs formed in the semiconductor chips CHP 0 and CHP 1 in the divided form and the MOSFET formed in the semiconductor chip CHP 2 , considering even the use thereof at a large rated current of a few A or more.
  • the drain electrodes formed in the back surfaces of the semiconductor chips CHP 0 and CHP 1 , and the drain electrode formed in the back surface of the semiconductor chip CHP 2 cannot be electrically coupled. From this, in the existing general-purpose package having only one chip mounting section within the power semiconductor device (package), when the semiconductor chip CHP 0 , the semiconductor chip CHP 1 , and the semiconductor chip CHP 2 are arranged in this one chip mounting section, the drain electrodes formed in the back surfaces of the semiconductor chip CHP 0 and the semiconductor chip CHP 1 , and the drain electrode formed in the back surface of the semiconductor chip CHP 2 are electrically coupled, so that the power semiconductor device PKG 1 of the cascode coupling system cannot be realized.
  • the power semiconductor device PKG 1 is configured such that the two chip mounting sections PLT 1 and PLT 2 electrically insulated from each other are provided inside the sealing body MR with, as an assumption, its outer shape being equal to that of the general-purpose package. Further, the power semiconductor device PKG 1 is configured in such a manner that the semiconductor chip CHP 0 and the semiconductor chip CHP 1 are mounted over the chip mounting section PLT 1 , and the semiconductor chip CHP 2 is mounted over the chip mounting section PLT 2 .
  • the power semiconductor device PKG 1 of the cascode coupling system is realized by providing the electrically-insulated two chip mounting sections PLT 1 and PLT 2 within the power semiconductor device PKG 1 , flatly arranging the semiconductor chip CHP 0 , the semiconductor chip CHP 1 , and the semiconductor chip CHP 2 , and coupling the flatly-arranged semiconductor chip CHP 0 , semiconductor chip CHP 1 and semiconductor chip CHP 2 by the wires.
  • an existing general-purpose package mounted with switching elements used in a power supply circuit or the like can be replaced with the power semiconductor device PKG 1 according to the present embodiment 2, which is equivalent in outer shape to the existing general-purpose package.
  • the power semiconductor device PKG 1 of the present embodiment 2 since the drain lead DL, the source lead SL, and the gate lead GL are similar in arrangement to the general-purpose package, the general-purpose package can be replaced with the package PKG 1 according to the present embodiment 2, and there is no need to design and change other drive circuits, wirings of a printed board, etc.
  • the first feature point in the present embodiment 2 resides in that the semiconductor chip CHP 0 and the semiconductor chip CHP 1 are mounted over the chip mounting section PLT 1 .
  • the junction FET Q 1 A and the junction FET Q 1 B both shown in FIG. 1 which are coupled in parallel with each other, are formed in the separate junction FET semiconductor chips. That is, the junction FET Q 1 A shown in FIG. 1 is formed in the semiconductor chip CHP 0 shown in FIG. 4 , and the junction FET Q 1 B shown in FIG. 1 is formed in the semiconductor chip CHP 1 shown in FIG.
  • the power semiconductor device PKG 1 according to the present embodiment 2, it is possible to reduce the sizes of the separate semiconductor chips CHP 0 and CHP 1 . Therefore, the power semiconductor device PKG 1 of the cascode coupling system can be provided which copes with an increase in current while improving the manufacturing yields of the semiconductor chip CHP 0 and the semiconductor chip CHP 1 .
  • the surface of the semiconductor chip CHP 0 and the surface of the semiconductor chip CHP 1 are identical to each other in layout configuration. Described in detail, as shown in FIG. 4 , the arrangement position of the gate pad GPj 0 of the semiconductor chip CHP 0 is equal to the arrangement position of the gate pad GPj 1 of the semiconductor chip CHP 1 , and the arrangement position of the source pad SPj 0 of the semiconductor chip CHP 0 is equal to the arrangement position of the source pad SPj 1 of the semiconductor chip CHP 1 .
  • the semiconductor chip CHP 0 and the semiconductor chip CHP 1 are made identical.
  • the terms “identical to each other” described herein means identicalness on the design idea, but does not mean physical identicalness in a strict sense.
  • design ideas made identical in design drawings exist even if the strict physical identicalness is not satisfied due to manufacturing variations or the like, they are included in the concept of “identical to each other” described in the present specification. That is, the “identical to each other” described in the present specification may exist to include the design idea of being positively made identical, and is used with the intention of allowing inevitable manufacturing variations.
  • a second feature point of the present embodiment 2 resides in that a layout configuration is adopted which reduces the gate impedances of the junction FETs.
  • the semiconductor chip CHP 0 and the semiconductor chip CHP 1 are respectively arranged at a position closest to the source lead SL of the drain lead DL, the source lead SL, and the gate lead GL.
  • the semiconductor chip CHP 0 is arranged in such a manner that the gate pad GPj 0 becomes closer to source lead SL than the source pad SPj 0
  • the semiconductor chip CHP 1 is arranged in such a manner that the gate pad Gpj 1 becomes closer to the source lead SL than the source pad SPj 1 .
  • the length of the wire Wgj 0 for coupling the gate pad GPj 0 and the source lead SL can be made short, and the length of the wire Wgj 1 for coupling the gate pad GPj 1 and the source lead SL can be shortened.
  • the gate impedances of the junction FETs can be reduced. That is, the parasitic resistance Rgj 0 and the parasitic inductance Lgj 0 both shown in FIG. 1 are reduced by shortening the length of the wire Wgj 0 , and the parasitic resistance Rgj 1 and the parasitic inductance Lgj 1 both shown in FIG. 1 are reduced by shortening the wire Wgj 1 .
  • the gate impedances of the junction FETs can be reduced, the application of the voltage greater than the insulation breakdown voltage to the MOSFET due to an increase in the gate impedance of each of the junction FETs can be suppressed, thereby making it possible to effectively suppress avalanche breakdown of the cascode-coupled MOSFET.
  • a third feature point in the present embodiment 2 resides in that the source impedance of each of the junction FETs is reduced.
  • the source pad SPj 0 of the semiconductor chip CHP 0 and the chip mounting section PLT 2 are electrically coupled by a plurality of wires Wds 0
  • the source pad SPj 1 of the semiconductor chip CHP 1 and the chip mounting section PLT 2 are electrically coupled by a plurality of wires Wds 1 .
  • the wires Wds 0 enable the parasitic inductance LS 0 shown in FIG. 1 to be reduced
  • the wires Wds 1 enable the parasitic inductance LS 1 shown in FIG. 1 to be reduced.
  • the source impedances of the junction FETs can be reduced by using the wirers. From this, according to the power semiconductor device PKG 1 according to the present embodiment 2, since the source impedances of the junction FETs can be reduced, the application of the voltage greater than the insulation breakdown voltage to the MOSFET due to an increase in the source impedance of each of the junction FETs can be suppressed, thereby making it possible to effectively suppress avalanche breakdown of the cascode-coupled MOSFET.
  • a fourth feature point in the present embodiment 2 resides in that the magnitudes of the gate impedances of the junction FETs and the source impedances thereof are equalized.
  • the length of the wire Wgj 0 for coupling the gate pad GPj 0 and the source lead SL, and the length of the wire Wgj 1 for coupling the gate pad GPj 1 and the source lead SL are made identical to each other. Further, as shown in FIG.
  • the length of the wire Wds 0 for coupling the source pad SPj 0 and the chip mounting section PLT 2 , and the length of the wire Wds 1 for coupling the source pad SPj 1 and the chip mounting section PLT 2 are made identical to each other.
  • the gate and source impedances of the junction FETs can be suppressed from extremely increasing in some junction FETs of the junction FETs.
  • the term “identical to each other” also means identicalness on the design idea.
  • the gate pad GPj 0 provided in the surface of the semiconductor chip CHP 0 formed with the junction FETs in the divided fashion, and the source lead SL are uniformly arranged so as to be as close to each other as possible.
  • the gate pad GPj 1 provided in the surface of the semiconductor chip CHP 1 , and the source lead SL are uniformly arranged so as to be as close to each other as possible.
  • the chip mounting section PLT 1 mounted with the semiconductor chip CHP 0 and the semiconductor chip CHP 1 is arranged on the same side as the side at which the source lead SL is arranged with respect to the drain lead DL.
  • the chip mounting section PLT 1 can be made close to the source lead SL. This means that the semiconductor chip CHP 0 and the semiconductor chip CHP 1 mounted over the chip mounting section PLT 1 can be arranged so as to approach the source lead SL.
  • the semiconductor chip CHP 0 and the semiconductor chip CHP 1 mounted over the chip mounting section PLT 1 are uniformly arranged at the center of the chip mounting section PLT 1 .
  • the semiconductor chip CHP 0 and the semiconductor chip CHP 1 can be arranged so as to be closest to the source lead SL and at equal distances.
  • the semiconductor chip CHP 0 and the semiconductor chip CHP 1 are arranged so as to be as uniformly close to the source lead SL as possible. Further, the gate pad GPj 0 formed in the surface of the semiconductor chip CHP 0 and the gate pad GPj 1 formed in the surface of the semiconductor chip CHP 1 are arranged so as to uniformly approach the source lead SL.
  • the chip mounting section PLT 1 mounted with the semiconductor chips CHP 0 and CHP 1 formed with the junction FETs is arranged at the position close to the source lead SL. Further, the semiconductor chip CHP 0 and the semiconductor chip CHP 1 are uniformly mounted in the area close to the source lead SL, of the internal area in the chip mounting section PLT 1 . Besides, in the present embodiment 2, the gate pad GPj 0 formed in the surface of the semiconductor chip CHP 0 , and the gate pad GPj 1 formed in the surface of the semiconductor chip CHP 1 are arranged so as to uniformly approach the source lead SL.
  • both the gate pad GPj 0 formed in the surface of the semiconductor chip CHP 0 and the gate pad GPj 1 formed in the surface of the semiconductor chip CHP 1 uniformly become close to the source lead SL.
  • the gate pad GPj 0 formed in the surface of the semiconductor chip CHP 0 , and the gate pad GPj 1 formed in the surface of the semiconductor chip CHP 1 are arranged so as to be closer to the source lead SL than other leads (drain lead DL and gate lead GL).
  • both the length of the wire Wgj 0 for coupling the gate pad GPj 0 and the source lead SL, and the length of the wire Wgj 1 for coupling the gate pad GPj 1 and the source lead SL can uniformly be shortened.
  • the lengths of the wires Wgj 0 and Wgj 1 can further be shortened.
  • the ability to shorten the length of the wire Wgj 0 and the length of the wire Wgj 1 enables reductions in the parasitic capacitances (parasitic resistance Rgj 0 and parasitic resistance Rgj 1 described in FIG. 1 ) that exist in the wires Wgj 0 and Wgj 1 . That is, according to the present embodiment 2, the parasitic resistances respectively existing in the wires Wgj 0 and Wgj 1 can be reduced uniformly and sufficiently. From this, according to the power semiconductor device PKG 1 according to the present embodiment 2, the application of the voltage greater than the insulation breakdown voltage to the cascode-coupled MOSFET can be suppressed, thereby making it possible to effectively suppress avalanche breakdown of the MOSFET. As a result, according to the present embodiment 2, the reliability of the power semiconductor device PKG 1 can be improved.
  • the fifth feature point in the present embodiment 2 resides in that the gate pad GPm provided in the surface of the semiconductor chip CHP 2 formed with the MOSFET, and the gate lead GL are arranged so as to be as close as possible.
  • the chip mounting section PLT 2 mounted with the semiconductor chip CHP 2 is arranged on the same side as the side at which the gate lead GL is arranged with respect to the drain lead DL.
  • the chip mounting section PLT 2 can be made close to the gate lead GL.
  • the semiconductor chip CHP 2 mounted over the chip mounting section PLT 2 can be arranged so as to approach the gate lead GL.
  • the semiconductor chip CHP 2 mounted over the chip mounting section PLT 2 is arranged so as to approach the side closest to the gate lead GL of the chip mounting section PLT 2 without arranging the semiconductor chip CHP 2 at the center of the chip mounting section PLT 2 .
  • the semiconductor chip CHP 2 can be made arranged so as to come closest to the gate lead GL.
  • the semiconductor chip CHP 2 is arranged so as to be as close to the gate lead GL as possible, and the gate pad GPm formed in the surface of the semiconductor chip CHP 2 is arranged so as to approach the gate lead GL.
  • the chip mounting section PLT 2 mounted with the semiconductor chip CHP 2 formed with the MOSFET is arranged at the position close to the gate lead GL. Further, the semiconductor chip CHP 2 is mounted to the area close to the gate lead GL, of the internal area in the chip mounting section PLT 2 .
  • the gate pad GPm formed in the surface of the semiconductor chip CHP 2 is arranged such that the gate pad GPm approaches the gate lead GL. Thus, the gate pad GPm formed in the surface of the semiconductor chip CHP 2 , and the gate lead GL become close to each other.
  • the gate pad GPm formed in the surface of the semiconductor chip CHP 2 is arranged so as to be closer to the gate lead GL than other leads (drain lead DL and source lead SL).
  • the distance between the gate pad GPm and the gate lead GL can be shortened, the length of the wire Wgm for coupling the gate pad GPm and the gate lead GL can be shortened.
  • the length of the wire Wgm can further be shortened.
  • the parasitic inductance of the wire Wgm can be reduced.
  • the ability to reduce the parasitic inductance of the wire Wgm contributes to an improvement in the electrical characteristics of the cascode-coupled power semiconductor device PKG 1 , but is not related directly to the suppression of the application of the voltage greater than the insulation breakdown voltage to the MOSFET.
  • the application of the voltage greater than the insulation breakdown voltage to the MOSFET can be suppressed indirectly without being suppressed directly.
  • the fifth feature point in the present embodiment 2 resides in that the semiconductor chip CHP 2 formed with the MOSFET is arranged so as to be as close to the gate lead GL as possible.
  • the semiconductor chip CHP 2 is arranged biasedly on the front side of the chip mounting section PLT 2 .
  • this feature as shown in FIG.
  • the chip mounting section PLT 2 is electrically coupled to the drain electrode formed in the back surface of the mounted semiconductor chip CHP 2 . Therefore, according to the present embodiment 2, the drain of the MOSFET and the sources of the junction FETs are coupled by the wires Wds 0 and the wires Wds 1 . This means that the parasitic inductances (parasitic inductance Ls 0 and parasitic inductance Ls 1 shown in FIG. 1 ) of the wires Wds 0 and Wds 1 for coupling the drain of the MOSFET and the sources of the junction FETs can be reduced.
  • the parasitic inductances between the drain of the MOSFET and the sources of the junction FETs can sufficiently be reduced by using the wires Wds 0 and Wds 1 .
  • the parasitic inductances can be reduced, it is possible to suppress a surge voltage generated due to the amount of change in switching current to be small.
  • a MOSFET low (low in breakdown voltage) in on resistance it is possible to suppress avalanche breakdown of the MOSFET because the surge voltage applied to the drain of the MOSFET is small,
  • the formation position of the source pad SPj 0 formed in the surface of the semiconductor chip CHP 0 , and the formation position of the source pad SPj 1 formed in the surface of the semiconductor chip CHP 1 are preferably arranged to be as close to the chip mounting section PLT 2 as possible. This is because the length of the wire Wds 0 for coupling the source pad SPj 0 and the chip mounting section PLT 2 , and the length of the wire Wds 1 for coupling the source pad SPj 1 and the chip mounting section PLT 2 can be made as short as possible by arranging the source pad SPj 0 and the source pad Spj 1 in this way.
  • parasitic inductances parasitic inductance Ls 0 and parasitic inductance Ls 1 shown in FIG. 1 .
  • the fifth feature point in the present embodiment 2 it is possible to suppress the application of the voltage greater than the insulation breakdown voltage to the MOSFET.
  • the avalanche breakdown of the cascode-coupled MOSFET can effectively be suppressed.
  • the present embodiment 2 it is possible to improve the reliability of the semiconductor device.
  • the gate pad GPj 0 is electrically coupled to the source lead SL by the wire Wgj 0
  • the gate pad GPj 1 is electrically coupled to the source lead SL by the wire Wgj 1
  • the gate pad GPm is electrically coupled to the gate lead GL by the wire Wgm.
  • the thickness (width) of the wire Wgj 0 and the thickness (width) of the wire Wgj 1 are desirably made thicker than the thickness (width) of the wire Wgm. This is because when the parasitic resistances existing in the wire Wgj 0 and wire Wgj 1 become large, the voltage greater than the insulation breakdown voltage is applied to the drain of the MOSFET as described above. Therefore, from the viewpoint of reducing the parasitic resistances existing in the wires Wgj 0 and Wgj 1 , the thickness of the wire Wgj 0 and the thickness of the wire Wgj 1 are desirably made thicker than the thicknesses of other wires.
  • the parasitic resistance between the gate electrode of each of the junction FETs and the source (which can also be defined as the source of the MOSFET) of the power semiconductor device PKG 1 can be reduced.
  • the application of the voltage greater than the insulation breakdown voltage to the MOSFET can be suppressed, thereby making possible to effectively suppress the avalanche breakdown of the cascode-coupled MOSFET.
  • the reliability of the semiconductor device can be improved.
  • the sixth feature point in the present embodiment 2 resides in that as shown in FIG. 4 , the source pad SPm provided in the surface of the semiconductor chip CHP 2 formed with the MOSFET, and the source lead SL (source lead post section SPST) are coupled by a plurality of wires Wsm.
  • the parasitic capacitance and parasitic inductance between the source of the MOSFET and the source lead SL can be reduced.
  • the potential of the source of the MOSFET can be suppressed from varying from a GND potential (reference potential) supplied from the source lead SL, so that the source of the MOSFET can securely be fixed to the GND potential.
  • the parasitic resistance between the source of the MOSFET and the source lead SL is reduced, the on resistance of the cascode-coupled power semiconductor device PKG 1 can also be reduced.
  • the electrical characteristics of the power semiconductor device PKG 1 can be improved.
  • the application of the voltage greater than the insulation breakdown voltage to the MOSFET can be suppressed by providing the above-described first to six feature points, thereby making it possible to effectively suppress the avalanche breakdown of the cascode-coupled MOSFET.
  • the reliability of the power semiconductor device PKG 1 according to the present embodiment 2 it is possible to improve the reliability of the power semiconductor device PKG 1 according to the present embodiment 2.
  • the power semiconductor device PKG 1 according to the present embodiment 2 is capable of reducing the parasitic resistance and the parasitic inductance, the electrical characteristics of the power semiconductor device PKG 1 can be improved.
  • the power semiconductor device PKG 1 according to the present embodiment 2 adopts the configuration in which the semiconductor chips CHP 0 and CHP 1 formed by dividing the junction FETs, and the semiconductor chip CHP 2 formed with the MOSFET are planarly arranged, the areas of the semiconductor chip CHP 0 , semiconductor chip CHP 1 and semiconductor chip CHP 2 can be freely designed. From this, the design of a low on resistance, and the design of an on-state current density also become easy, and a power semiconductor device PKG 1 with various specifications can be realized.
  • the present modification 1 will describe a power semiconductor device PKG 2 having separate semiconductor chips CHP 0 , CHP 1 , and CHP 3 formed with a plurality of junction FETs in a divided fashion.
  • FIG. 5 is a diagram showing a mounting structure of the power semiconductor device PKG 2 according to the present modification 1.
  • the semiconductor chip CHP 0 , the semiconductor chip CHP 1 , and the semiconductor chip CHP 3 are mounted over a chip mounting section PLT 1 .
  • the junction FETs are formed in these semiconductor chips CHP 0 , CHP 1 , and CHP 3 in the divided fashion.
  • a source pad SPj 0 and a gate pad GPj 0 are formed in the surface of the semiconductor chip CHP 0 .
  • a source pad SPj 1 and a gate pad GP are formed in the surface of the semiconductor chip CHP 1 .
  • a source pad SPj 3 and a gate pad GPj 3 are formed in the surface of the semiconductor chip CHP 3 .
  • the gate pad GPj 0 and a source lead SL are coupled by a wire Wgj 0
  • the gate pad GPj 1 and the source lead SL are coupled by a wire Wgj 1
  • the gate pad GPj 3 and the source lead SL are coupled by a wire Wgj 3 .
  • the source pad SPj 0 and a chip mounting section PLT 2 are coupled by wires Wds 0
  • the source pad SPj 1 and the chip mounting section PLT 2 are coupled by wires Wds 1
  • the source pad SPj 3 and the chip mounting section PLT 2 are coupled by wires Wds 3 .
  • the power semiconductor device PKG 2 according to the present modification 1 configured in this way, since the junction FETs are formed in the three semiconductor chips (semiconductor chip CHP 0 , semiconductor chip CHP 1 , and semiconductor chip CHP 3 ) in the divided fashion, the sizes of the respective semiconductor chips can further be reduced. Therefore, according to the power semiconductor device PKG 2 according to the present modification 1, the probability that killer defects are contained in each semiconductor chip can be reduced, thereby making it possible to improve the manufacturing yield of each semiconductor chip.
  • the present modification 2 will describe an example in which one of two semiconductor chips formed with a plurality of junction FETs in a divided fashion, and a semiconductor chip formed with a MOSFET are laminated over each other.
  • FIG. 6 is a diagram showing a mounting structure of the power semiconductor device PKG 3 according to the present modification 2.
  • the power semiconductor device PKG 3 according to the present modification 2 has a chip mounting section PLT 1 comprised of, for example, a rectangular-shaped metal plate.
  • the chip mounting section PLT 1 is formed integrally with a drain lead DL so as to be coupled thereto.
  • the chip mounting section PLT 1 and the drain lead DL are electrically coupled to each other.
  • a source lead SL and a gate lead GL are arranged in such a manner that the drain lead DL is spacedly held therebetween.
  • a semiconductor chip CHP 0 and a semiconductor chip CHP 1 are mounted over the chip mounting section PLT 1 via, for example, a conductive adhesive comprised of silver paste or solder.
  • the semiconductor chip CHP 0 and the semiconductor chip CHP 1 are respectively formed with, for example, junction FETs with silicon carbide as a material. Further, the back surfaces of the semiconductor chips CHP 0 and CHP 1 serve as drain electrodes respectively.
  • a source pad SPj 0 and a gate pad GPj 0 are formed in the surface (main surface) of the semiconductor chip CHP 0 .
  • a source pad SPj 1 and a gate pad GPj 1 are formed in the surface of the semiconductor chip CHP 1 .
  • the gate pad GPj 0 and the source lead SL are coupled by a wire Wgj 0
  • the gate pad GPj 1 and the source lead SL are coupled by a wire Wgj 1
  • the source pad SPj 0 and the source pad SPj 1 are coupled by wires Wjj.
  • a semiconductor chip CHP 2 is mounted over the semiconductor chip CHP 0 via a conductive adhesive comprised of, for example, silver paste or solder.
  • the semiconductor chip CHP 2 is formed with a MOSFET with silicon as a material.
  • the back surface of the semiconductor chip CHP 2 serves as a drain electrode, and a source pad SPm and a gate pad GPm are formed in the surface of the semiconductor chip CHP 2 .
  • the semiconductor chip CHP 2 is mounted over the semiconductor chip CHP 0 .
  • the semiconductor chip CHP 2 is mounted over the source pad SPj 0 formed in the surface of the semiconductor chip CHP 0 .
  • the drain electrode formed in the back surface of the semiconductor chip CHP 2 , and the source pad SPj 0 formed in the surface of the semiconductor chip CHP 0 are electrically coupled to each other.
  • the source of each junction FET formed in the semiconductor chip CHP 0 and the drain of the MOSFET formed in the semiconductor chip CHP 2 are electrically coupled.
  • the semiconductor chip CHP 2 needs to be formed so as to be included in the source pad SPj 0 formed in the surface of the semiconductor chip CHP 0 in plan view. That is, in the present modification 2, the size of the semiconductor chip CHP 2 needs to be smaller than the size of the semiconductor chip CHP 0 . To say more, the size of the semiconductor chip CHP 2 needs to be smaller than the size of the source pad SPj 0 . Further, the gate pad GPm and the gate lead GL are coupled by a wire Wgm, and the source pad SPm and the source lead SL are coupled by a wire Wsm.
  • FIG. 7 is a typical diagram showing a cross-section of the power semiconductor device PKG 3 according to the modification 2 and a sectional diagram cut along line A-A of FIG. 6 .
  • the semiconductor chip CHP 0 is mounted over the chip mounting section PLT 1 through a conductive adhesive PST interposed therebetween.
  • the semiconductor chip CHP 2 is mounted over the semiconductor chip CHP 0 through a conductive adhesive (not shown). Further, the semiconductor chip CHP 2 (source pad) and the source lead SL are electrically coupled by the wire Wsm.
  • a broken line part shown in FIG. 7 indicates a part covered with a sealing body MR.
  • the feature point peculiar to the present modification 2 resides in that as shown in FIG. 6 , the semiconductor chip CHP 2 formed with the MOSFET is mounted over the semiconductor chip CHP 0 formed with a part of the junction FETs.
  • the source pad SPj 0 formed in the surface of the semiconductor chip CHP 0 and the drain electrode formed in the back surface of the semiconductor chip CHP 2 can directly be coupled. That is, according to the present modification 2, it is possible to directly couple the source of the junction FET formed in the semiconductor chip CHP 0 and the drain of the MOSFET formed in the semiconductor chip CHP 2 without using the wire.
  • the parasitic inductance interposed between the source of the junction FET and the drain of the MOSFET can be almost completely eliminated. That is, the feature point peculiar to the present modification 2 resides in that the semiconductor chip CHP 2 is mounted directly on the semiconductor chip CHP 0 . Since the source of the junction FET formed in the semiconductor chip CHP 0 and the drain of the MOSFET formed in the semiconductor chip CHP 2 are coupled by this configuration, no wire is required. When the wire is used, the parasitic inductance existing in the wire comes to the problem.
  • the parasitic inductance (parasitic inductance Ls 0 in FIG. 1 ) between the drain of the MOSFET formed in the semiconductor chip CHP 2 and the source of the junction FET formed in the semiconductor chip CHP 0 can be almost completely eliminated.
  • the semiconductor chip CHP 0 and the semiconductor chip CHP 1 are arranged closely, and the source pad SPj 0 and the source pad SPj 1 are electrically coupled by the wires Wjj.
  • the parasitic inductance (parasitic inductance Ls 1 in FIG. 1 ) of each wire Wjj can be suppressed to minimum.
  • the power semiconductor device PKG 3 according to the present modification 2 it is possible to suppress a surge voltage generated with an increase/decrease in switching current.
  • the application of the voltage greater than the insulation breakdown voltage to the MOSFET can be suppressed, thereby making it possible to effectively suppress avalanche breakdown of the cascode-coupled MOSFET.
  • the reliability of the power semiconductor device PKG 3 can be improved.
  • the semiconductor chip CHP 0 and the semiconductor chip CHP 2 are arranged in lamination over the chip mounting section PLT 1 . From this, in the power semiconductor device PKG 3 according to the present modification 2, the existing general-purpose package having only one chip mounting section within the package can be diverted as it is. That is, according to the power semiconductor device PKG 3 according to the present modification 2, since the so-called inexpensive general-purpose package can be diverted as it is, the cascode-coupled high-performance power semiconductor device PKG 3 can be provided at low cost. In other words, according to the present modification 2, it is possible to reduce the cost of the cascode-coupled high-performance power semiconductor device PKG 3 .
  • FIG. 8 is a diagram of the power semiconductor device PKG 3 according to the present modification 2 as viewed from the lower surface side of the sealing body MR. As shown in FIG.
  • FIG. 9 is a diagram showing a mounting structure of the power semiconductor device PKG 4 according to the present modification 3.
  • the mounting structure of the power semiconductor device PKG 4 according to the present modification 3 shown in FIG. 9 is substantially similar to that of the power semiconductor device PKG 3 according to the modification 2 shown in FIG. 6 .
  • the differences between the power semiconductor device PKG 4 according to the present modification 3 shown in FIG. 9 and the power semiconductor device PKG 3 according to the present modification 2 shown in FIG. 6 are as follows. That is, in the modification 2 shown in FIG. 6 , the layout configuration of the surface of the semiconductor chip CHP 0 and the layout configuration of the surface of the semiconductor chip CHP 1 are different from each other, whereas in the present modification 3 shown in FIG. 9 , the layout configuration of the surface of the semiconductor chip CHP 0 and the layout configuration of the surface of the semiconductor chip CHP 1 are identical to each other. Specifically, in the present modification 3, as shown in FIG.
  • the formation position of the gate pad GPj 0 formed in the semiconductor chip CHP 0 and the formation position of the gate pad GPj 1 formed in the semiconductor chip CHP 1 are identical to each other, and the formation position of the source pad SPj 0 and the formation position of the source pad SPj 1 are identical to each other.
  • the manufacturing cost can be suppressed low as compared with the case where the semiconductor chip CHP 0 and the semiconductor chip CHP 1 different in layout configuration are used.
  • FIG. 10 is a diagram showing the mounting structure of the power semiconductor device PKG 5 according to the present modification 4.
  • the configuration of the power semiconductor device PKG 5 according to the present modification 4 shown in FIG. 10 and the configuration of the power semiconductor device PKG 1 according to the embodiment 2 shown in FIG. 4 differ from each other in terms of the outer shape of each package.
  • the package form of the power semiconductor device PKG 5 according to the present modification 4 takes a SOP (Small Outline Package).
  • SOP Small Outline Package
  • various types of general-purpose packages are known as for the package form in which the switching elements are configured to be mounted.
  • the technical idea of the embodiment 2 can be realized by improving various general-purpose packages typified by, for example, the power semiconductor device PKG 1 having the package form shown in FIG. 4 and the power semiconductor device PKG 5 having the package form shown in FIG. 10 .
  • the application of the voltage greater than the insulation breakdown voltage to the MOSFET can be suppressed, thereby making it possible to effectively suppress the avalanche breakdown of the cascode-coupled MOSFET.
  • the reliability of the power semiconductor device PKG 5 can be improved.
  • the technical idea in the embodiment 1 that the junction FETs are divided and formed in the separate semiconductor chips has been embodied even in the power semiconductor device PKG 5 according to the present modification 4, the manufacturing yield of the power semiconductor device PKG 5 can be improved.
  • FIG. 11 is a sectional diagram cut along line A-A of FIG. 10 .
  • a semiconductor chip CHP 1 is mounted over a chip mounting section PLT 1 through a conductive adhesive (not shown). Then, for example, the semiconductor chip CHP 1 (gate pad) and a source lead SL (source lead post section SPST) are electrically coupled by a wire Wgj 1 .
  • the chip mounting section PLT 1 , the semiconductor chip CHP 1 , the wire Wgj 1 , some of leads, etc. are sealed by a sealing body MR comprised of a resin.
  • the sealing body MR is formed in an approximately rectangular parallelepiped shape and has a first side surface and a second side surface opposite to the first side surface. Further, a gate lead GL and the source lead SL are configured so as to protrude from the first side surface of the sealing body MR. A drain lead DL is configured so as to protrude from the second side surface of the sealing body MR.
  • FIG. 12 is a diagram showing the mounting structure of the power semiconductor device PKG 6 according to the present modification 5.
  • the power semiconductor device PKG 6 according to the present modification 5 is configured by combining the modification 2 and the modification 4. That is, as shown in FIG. 12 , the power semiconductor device PKG 6 according to the present modification 5 adopts the package form called SOP as with the modification 4.
  • SOP package form
  • one semiconductor chip CHP 0 of two semiconductor chips (CHP 0 and CHP 1 ) formed by dividing a plurality of junction FETs, and a semiconductor chip CHP 2 formed with a MOSFET are laminated over each other.
  • the power semiconductor device PKG 6 according to the present modification 5 is capable of obtaining the advantage by the modification 2 and the advantage (advantage in the embodiment 2) by the modification 4. That is, even in the present modification 5, the reliability of the power semiconductor device PKG 6 can be improved, and the manufacturing yield of the power semiconductor device PKG 6 can be improved.
  • the present embodiment 3 will describe points of device related to a device structure.
  • FIG. 13 is a sectional diagram showing one example of the device structure of the MOSFET according to the present embodiment 3.
  • a drain electrode DEm comprised of, for example, a gold film is formed over the back surface of a semiconductor substrate SUBm comprised of silicon doped with n-type impurities, for example, a drift layer DFTm comprised of an n-type semiconductor region is formed on the main surface side of the semiconductor substrate SUBm.
  • a body region PR comprised of a p-type semiconductor region is formed in the drift layer DFTm, and a source region SR comprised of an n-type semiconductor region is formed so as to be included in the body region PR.
  • a surface region of the body region PR interposed between the source region SR and the drift layer DFTm functions as a channel forming region.
  • a source electrode SE is formed so as to be electrically coupled to both the source region SR and the body region PR.
  • GOX comprised of, for example, a silicon oxide film is formed in the surface of the drift layer DFTm including over the channel forming region.
  • a gate electrode G is formed over the gate insulating film GOX.
  • the MOSFET configured in this way is configured in such a manner that, for example, electrons pass through the channel forming region formed in the surface of the body region PR from the source region SR and flow from the drift layer DFTm to the drain electrode DEm formed in the back surface of the semiconductor substrate SUBm.
  • the MOSFET has a structure referred to as a so-called vertical MOSFET.
  • the advantage of the vertical MOSFET can include the point that a MOSFET large in current density can be formed because it can be formed densely in the semiconductor chip CHP 2 . Accordingly, a power semiconductor device large in current density can be realized by using the vertical MOSFET in the power semiconductor device (switching element) in the embodiment 1.
  • the semiconductor chip CHP 2 formed with the MOSFET is laminated over the semiconductor chip CHP 0 formed with the junction FETs as shown in FIG. 9 , for example, the area of the semiconductor chip CHP 2 formed with the MOSFET arranged over the source pad SPj 0 also becomes relatively small. Even in this case, however, if the vertical MOSFET shown in FIG. 13 is used as the MOSFET formed in the semiconductor chip CHP 2 , a MOSFET relatively large in current density can be realized even in a small chip area. As a result, the current density of the whole power semiconductor device cascode-coupled can be made large. That is, there can be provided a high-performance power semiconductor device capable of securing a large current by using the vertical MOSFET even when the area of the semiconductor chip CHP 2 formed with the MOSFET becomes small.
  • FIG. 14 is a sectional diagram typically showing a partial area of the junction FET semiconductor chip, As shown in FIG. 14 , in the junction FET semiconductor chip, a drain electrode DEj is formed in the back surface of a semiconductor substrate SUBj, and a drift layer DFTj is formed in the main surface (surface) of the semiconductor substrate SUBj. An active region ACTj is formed in the drift layer DFTj, and a termination region TMj is formed in an outside region of the active region ACTj.
  • the active region ACTj is formed with a plurality of unit junction FETs which configure each junction FET. That is, gate electrodes GE and source regions SR of the unit junction FETs are formed in the active region ACTj. Then, the gate electrodes GE of the unit junction FETs are electrically coupled to a gate lead-out electrode GW. Further, an insulating film IL 1 is formed over the active region ACTj and the termination region TMj, and a source pad SPj is formed over the insulating film IL 1 . Specifically, a first metal wiring layer is formed over the insulating film IL 1 , and an insulating film IL 2 is formed over the first metal wiring layer.
  • an opening OP 1 is formed in the insulating film IL 2 , and an exposure region of the first metal wiring layer, which is exposed from the opening OP 1 , serves as the source pad SPj.
  • the source pad SPj is electrically coupled to the source regions SR of the unit junction FETs.
  • a second metal wiring layer formed in the same layer as the first metal wiring layer and electrically isolated therefrom is provided over the insulating film IL 1 .
  • An insulating film IL 2 is formed over the second metal wiring layer.
  • an opening OP 2 is formed in the insulating film IL 2 , and an exposure region of the second metal wiring layer, which is exposed from the opening OP 2 , serves as a gate pad GPj.
  • the gate pad GPj is electrically coupled to the gate lead-out electrode GW shown in the left figure in FIG. 14 . Accordingly, the gate pad GPj is electrically coupled to the gate electrodes GE of the unit junction FETs through the gate lead-out electrode GW.
  • the “junction FET” formed in the junction FET semiconductor chip is comprised of a plurality of unit junction FETs coupled in parallel with each other as shown in the left figure in FIG. 14 . That is, an assembly of the unit junction FETs coupled in parallel with each other configures one “junction FET”, and one “junction FET” is formed in one junction FET semiconductor chip. That is, in the present specification, one “junction FET” is formed in each of the junction FET semiconductor chips. For example, one “junction FET” is formed in the semiconductor chip CHP 0 , and one “junction FET” is formed even in the semiconductor chip CHP 1 .
  • junction FET is comprised of, for example, several thousands to several tens of thousands of unit junction FETs coupled in parallel with one another.
  • the gate electrodes GE of the unit junction FETs serve as the gate electrode of one “junction FET”.
  • the source regions SR of the unit junction FETs serve as the source region of one “junction FET”.
  • each of the junction FET semiconductor chips has the semiconductor substrate SUBj formed with one “junction FET”, the gate lead-out electrode GW electrically coupled to the gate electrodes GE, and the gate pad GPj electrically coupled to the gate lead-out electrode GW.
  • FIG. 15 is an enlarged diagram of the area AR in FIG. 14 and a sectional diagram showing the device structure of the unit junction FET.
  • a drain electrode DEj is formed in the back surface of a semiconductor substrate SUBj.
  • a drift layer DFTj is formed on the main surface side opposite to the back surface of the semiconductor substrate SUBj, and a plurality of trenches TR are formed in the drift layer DFTj.
  • gate electrodes GE also called gate regions
  • a channel forming region is formed so as to be interposed between the gate electrodes GE formed at the side and bottom surfaces of the adjacent trenches TR.
  • a source region SR is formed above the channel forming region, and a source electrode SE is formed over the source region SR. Further, an insulating film IL 1 is formed so as to embed each trench TR.
  • the extension of a depletion layer from each of the gate electrodes GE is controlled by controlling the voltage applied to the gate electrode GE.
  • the channel forming region disappears so that an off state is realized.
  • the depletion layers extending from the gate electrodes GE adjacent to each other are not linked, the channel forming region is formed so that the on state is realized.
  • the feature point in the present embodiment 3 resides in that the gate pad GPj is formed in an upper layer of the gate lead-out electrode GW as shown in FIG. 14 . That is, in the present embodiment 3, the gate pad GPj and the gate lead-out electrode GW are formed in a two-layer structure.
  • the gate resistance of the junction FET can be reduced.
  • the gate wiring resistance rgj 0 and the gate wiring resistance rgj 1 shown in FIG. 1 can be reduced in value.
  • the thickness of the gate pad GPj can be made thicker than the thickness of the gate lead-out electrode GW, so that the gate wiring resistance becomes small with its thickening.
  • the gate pad GPj and the gate lead-out electrode GW are formed in the same layer. That is, it is considered that the gate pad GPj and the gate lead-out electrode GW are formed as one layer structure. In this case, however, the thickness of the gate pad GPj becomes the same degree as the thickness of the gate lead-out electrode GW. On the other hand, when the gate pad GPj and the gate lead-out electrode GW are formed in the two-layer structure as in the present embodiment 3, the thickness of the gate pad GPj can be made thicker than the thickness of the gate lead-out electrode GW.
  • the gate pad GPj and the gate lead-out electrode GW are formed of a material comprised principally of aluminum low in resistivity. From this point also, the resistances of the gate pad GPj and the gate lead-out electrode GW can be reduced.
  • the “principal component” described in the present specification refers to a material component most contained in component materials that configure members (layers and films).
  • the “member comprised principally of aluminum” means that the member most contains aluminum (Al).
  • the intention to use the term of “principal component” in the present specification is used to express that, for example, the member is basically comprised of aluminum, but in addition, containing impurities therein is not excluded.
  • the conductor film (metal film) comprised principally of aluminum described in the present specification is used in abroad concept including not only where it is a pure aluminum film, but also an aluminum alloy film (AlSi film) containing aluminum added with silicon, and an aluminum alloy film (AlSiCu film) containing aluminum added with silicon and copper. Accordingly, the gate pad GPj containing these aluminum alloy films is also included in the “gate pad GPj comprised principally of aluminum”.
  • the feature point in the present embodiment 3 includes (1) the point that the gate pad GPj and the gate lead-out electrode GW are formed in the two-layer structure, (2) the point that the thickness of the gate pad GPj is thicker than that of the gate lead-out electrode GW, and (3) the point that the gate pad GPj and the gate lead-out electrode GW are respectively formed of the material comprised principally of aluminum low in resistivity. Therefore, according to the present embodiment 3, the gate wiring resistances (gate wiring resistance rgj 0 and gate wiring resistance rgj 1 shown in FIG. 1 ) of the junction FETs can be reduced by the synergistic effect of the feature points described in the above (1) through (3).
  • the reliability of the power semiconductor device can be improved.
  • the gate wiring resistance rgj 0 and the gate wiring resistance rgj 1 shown in FIG. 1 can be reduced, and the parasitic resistance Rgj 0 and the parasitic resistance Rgj 1 shown in FIG. 1 can be reduced.
  • the gate impedances of the junction FETs can be further reduced, a further improvement in the reliability of the power semiconductor device can be achieved, and advantageous effects shown below can also be obtained.
  • the reduction in the parasitic resistance of each junction FET means that the resistive component difficult to adjust becomes small.
  • the adjustment range of the gate resistance of each junction FET becomes large.
  • the degree of freedom in adjustment of the switching speed of the power semiconductor device can be improved. That is, as a result of facilitating the setting of the external resistor to the optimum value, the switching speed of the power semiconductor device can be controlled while preventing the cascode-coupled MOSFET from insulation breakdown. There can be obtained an advantageous effect that switching noise in a system apparatus.
  • the present embodiment 4 will describe an example in which the power semiconductor device described in each of the embodiments 1 through 3 is applied to a control system for controlling a motor mounted to, for example, a hybrid vehicle or an electric vehicle.
  • FIG. 16 is a block diagram showing the configuration of the control system according to the present embodiment 4.
  • the control system according to the present embodiment 4 has a power supply PS, a control unit ECU, an inverter INV and a motor MT.
  • the inverter INV which receives the supply of power from the power supply PS is controlled by control by the control unit ECU and configured to drive the motor MT corresponding to a load.
  • the control unit ECU and the inverter INV configure an electronic apparatus.
  • the electronic apparatus in the present embodiment 4 is equipped with the inverter INV which is electrically coupled to the motor MT corresponding to the load and drives the motor MT, and the control unit which controls the inverter INV.
  • the inverter INV includes as a component, the power semiconductor device described in each of the embodiments 1 through 3.
  • FIG. 17 is a circuit block diagram of the inverter INV which drives the motor MT as a three-phase motor, for example, in accordance with an input signal from the control unit (control unit ECU in FIG. 16 ).
  • the inverter INV has six cascode switches SWU, SWV, SWW, SWX, SWY, and SWZ. Each of these six cascode switches SWU, SWV, SWW, SWX, SWY, and SWZ is comprised of the power semiconductor device described in each of the embodiments 1 through 3.
  • the cascode switch SWU configures an upper arm UA (U) which controls a U phase of the motor MT.
  • the cascode switch SWX configures a lower arm BA (X) which controls the U phase of the motor MT.
  • the cascode switch SWU is comprised of a cascode coupling of a plurality of junction FETs (JU 1 , JU 2 ) and a MOSFET (MU).
  • the cascode switch SWX is comprised of a cascode coupling of a plurality of junction FETs (JX 1 , JX 2 ) and a MOSFET (MX).
  • the cascode switch SWV configures an upper arm UA (V) which controls a V phase of the motor MT.
  • the cascode switch SWY configures a lower arm BA (Y) which controls the V phase of the motor MT.
  • the cascode switch SWV is comprised of a cascode coupling of a plurality of junction FETs (JV 1 , JV 2 ) and a MOSFET (MV).
  • the cascode switch SWX is comprised of a cascode coupling of a plurality of junction FETs (JY 1 , JY 2 ) and a MOSFET (MY).
  • the cascode switch SWW configures an upper arm UA (W) which controls a W phase of the motor MT.
  • the cascode switch SWZ configures a lower arm BA (Z) which controls the W phase of the motor MT.
  • the cascode switch SWW is comprised of a cascode coupling of a plurality of junction FETs (JW 1 , JW 2 ) and a MOSFET (MW).
  • the cascode switch SWZ is comprised of a cascode coupling of a plurality of junction FETs (JZ 1 , JZ 2 ) and a MOSFET (MZ).
  • the six cascode switches SWU, SWV, SWW, SWX, SWY, and SWZ are respectively controlled by six drive circuits GDU, GDV, GDW, GDX, GDY, and GDZ which configure part of the control unit ECU shown in FIG. 16 . That is, the six drive circuits GDU, GDV, GDW, GDX, GDY, and GDZ are provided corresponding to the six cascode switches SWU, SWV, SWW, SWX, SWY, and SWZ.
  • the drive circuit GDU electrically couples a gate electrode of the MOSFET (MU) configuring the cascode switch SWU and gate electrodes of the junction FETs (JU 1 , JU 2 ).
  • the drive circuit GDV electrically couples a gate electrode of the MOSFET (MV) configuring the cascode switch SWV and gate electrodes of the junction FETs (JV 1 , JV 2 ).
  • the drive circuit GDW electrically couples a gate electrode of the MOSFET (MW) configuring the cascode switch SWW and gate electrodes of the junction FETs (JW 1 , JW 2 ).
  • the drive circuit GDX electrically couples a gate electrode of the MOSFET (MX) configuring the cascode switch SWX and gate electrodes of the junction FETs (JX 1 , JX 2 ).
  • the drive circuit GDY electrically couples a gate electrode of the MOSFET (MY) configuring the cascode switch SWY and gate electrodes of the junction FETs (JY 1 , JY 2 ).
  • the drive circuit GDZ electrically couples a gate electrode of the MOSFET (MZ) configuring the cascode switch SWZ and gate electrodes of the junction FETs (JZ 1 , JZ 2 ).
  • the gate electrodes of the junction FETs are controlled by the drive circuit (gate drive circuit).
  • the drive circuit since the source voltage of each junction FET can be controlled to a desired level by controlling the gate electrode of the junction FET by the drive circuit, it is possible to obtain an effect that a surge voltage at an intermediate node can be suppressed.
  • the drive circuit may of course be configured to drive only the gate electrode of the MOSFET. In this case, it is possible to obtain an advantage that a change in the drive circuit (gate drive circuit) where a single MOSFET is used as the power semiconductor device becomes unnecessary.
  • the two cascode switches (upper and lower arms) operated as corresponding to one phase of each switch circuit are coupled in series across a power supply voltage (e.g., 300V) supplied from the power supply PS.
  • the two cascode switches coupled in series perform switching operations complementarily to each other in accordance with input signals from the drive circuits. With the complementary switching operations, an output signal is outputted from a coupling point (U, V, W) of the two cascode switches to the motor MT as the load.
  • the cascode switch SWU and the cascode switch SWX are coupled in series, and a signal for driving the U phase of the motor MT as the load is outputted from the coupling point (U) thereof.
  • the cascode switch SWV and the cascode switch SWY are coupled in series, and a signal for driving the V phase of the motor MT is outputted from the coupling point (V) thereof.
  • the cascode switch SWW and the cascode switch SWZ are coupled in series, and a signal for driving the W phase of the motor MT is outputted from the coupling point (W) thereof.
  • a free wheel diode is a built-in diode of each MOSFET (MU, MV, MW, MX, MY, MZ). Further, in FIG. 17 , the positive potential side of the power supply PS is indicated by “P”, and the negative potential side of the power supply PS is indicated by “N”.
  • each of the cascode switches SWU, SWV, SWW, SWX, SWY, and SWZ described in the present embodiment 4 is comprised of the power semiconductor device described in each of the embodiments 1 through 3, it is low in on resistance and capable of preventing the breakdown of the MOSFET. Therefore, even when a motor drive current is large, a reduction in power loss of the control system (inverter system) and its high reliability can be made compatible.
  • each of the junction FET semiconductor chips uses silicon carbide as the material
  • the technical idea in the embodiment can be applied even to the example in which the junction FET semiconductor chips respectively use gallium nitride as the material.
  • junction FETs are coupled in parallel
  • the number of junction FETs is not however limited to the two, but may be three or more, for example.
  • the arrangement of the leads is not limited to these either. That is, the arrangement positions of the gate, drain and source leads can be changed in various ways. For example, when a package is mounted onto a mounting substrate, the lead arrangement of the package can be determined in such a manner that the existing lead arrangement can be diverted. In this case, a change in the mounting substrate becomes unnecessary, and an increase in the cost accompanying a design change can also be suppressed.
  • the layout configuration of the laminated semiconductor chips is particularly not limited only to the layout configuration described in the specification either.
  • the shape of each semiconductor chip, the shape of each pad, the shape of the termination region, etc. are not particularly limited either.
  • the structures of the junction FET and the MOSFET are not limited, and the various existing structures can be applied.
  • the profile of impurities in the device can be changed freely. For example, in the MOSFET, impurities may be injected such that the concentration thereof in its surface is made low to avoid punch-through, and the concentration thereof is made high gradually in a depth direction.
  • the above-described MOSFET is not limited to the case where the gate insulating film is formed of the oxide film, but is assumed as including even a MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which a gate insulating film is formed widely of an insulating film. That is, the term MOSFET is used for convenience in the present specification, but this MOSFET is used in the present specification as a term intended to include even the MISFET.
  • MISFET Metal Insulator Semiconductor Field Effect Transistor
  • the power semiconductor device described in the embodiment can be applied to an inverter for a hybrid vehicle or an electric vehicle, but is not limited to it.
  • the power semiconductor device is applicable to various devices such as an inverter for an air conditioner, a power conditioner for a solar power generation system, a switching power supply circuit, a power supply module for a PC, a white LED inverter, etc.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Inverter Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
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US10607978B2 (en) 2020-03-31
US20180166430A1 (en) 2018-06-14
EP2955844A1 (de) 2015-12-16
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CN105280625A (zh) 2016-01-27
JP2015228445A (ja) 2015-12-17
US20160211246A1 (en) 2016-07-21
JP6374225B2 (ja) 2018-08-15
TW201611189A (zh) 2016-03-16

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