US9330957B2 - Process for assembling two wafers and corresponding device - Google Patents

Process for assembling two wafers and corresponding device Download PDF

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Publication number
US9330957B2
US9330957B2 US13/330,146 US201113330146A US9330957B2 US 9330957 B2 US9330957 B2 US 9330957B2 US 201113330146 A US201113330146 A US 201113330146A US 9330957 B2 US9330957 B2 US 9330957B2
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wafer
bonding
wafers
silicon
forming
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US20120161292A1 (en
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Aomar Halimaoui
Marc Zussy
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STMicroelectronics Crolles 2 SAS
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STMicroelectronics Crolles 2 SAS
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS reassignment COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES CORRECTIVE ASSIGNMENT TO CORRECT THE ADDRESS OF SECOND ASSIGNEE PREVIOUSLY RECORDED ON REEL 027813 FRAME 0347. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNOR'S INTEREST. Assignors: HALIMAOUI, AOMAR, ZUSSY, MARC
Publication of US20120161292A1 publication Critical patent/US20120161292A1/en
Priority to US15/087,093 priority Critical patent/US20160218178A1/en
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Assigned to STMICROELECTRONICS (CROLLES 2) SAS reassignment STMICROELECTRONICS (CROLLES 2) SAS ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table

Definitions

  • the invention relates to integrated circuits, and more particularly, to the assembly of at least two wafers used in microelectronics, especially semiconductor wafers.
  • the wafers may be silicon wafers, for example.
  • the fabrication of integrated circuits in silicon substrates may require the assembly of two silicon wafers.
  • three-dimensional structures comprise components fabricated on at least two separate wafers that are then assembled.
  • backlit imaging devices in which the photodetection cells are placed near the back side of the substrates in which they are fabricated. These substrates are generally thinned in mechanical polishing or grinding steps to bring the back surface of the active regions of the photodetection cells closer. To enable this thinning, a second wafer of silicon is attached to the front side of the first substrate to form a handle.
  • TSVs through-silicon vias
  • FIG. 1 a A conventional assembly of two wafers, for example, silicon wafers, is illustrated in FIG. 1 a .
  • two silicon wafers P 1 and P 2 are schematically illustrated.
  • a bonding layer OX for example, a layer of silicon dioxide (SiO 2 )
  • SiO 2 silicon dioxide
  • the two wafers P 1 and P 2 are generally wafers that are 200 mm or 300 mm in diameter, and they conventionally comprise a bevelled peripheral part BIS.
  • the bevelled peripheral part BIS may extend over a portion of the wafers P 1 and P 2 , which is about 1 mm to 3 mm in width.
  • a cavity CV is formed between the bevelled peripheral parts BIS of the two wafers P 1 and P 2 .
  • the presence of the cavity CV has the particular drawback of not allowing the peripheral parts of the wafers to be rigidly connected to each other during bonding.
  • the edge of the wafer P 1 is too fragile and may delaminate and cause the bevelled peripheral part BIS to crack.
  • This cracking may produce splinters that can deeply scratch the surface of the wafer P 1 during the thinning step, and thus represents a source of particulates.
  • FIG. 2 a Before bonding, it is possible to cut off the bevelled parts of the silicon wafer to be thinned ( FIG. 2 a ) using a technique well know to those skilled in the art called edge grinding or edge trimming.
  • edge grinding or edge trimming a technique well know to those skilled in the art.
  • the bevelled peripheral part BIS of the wafer P 1 has been trimmed, for example, mechanically trimmed, before the wafer P 1 is thinned.
  • the wafer P 1 is shown after the thinning step.
  • the absence of the bevelled peripheral part BIS makes it possible to obtain a thickness of about a micron without cracks appearing. Nonetheless, apart from the fact that an additional step is performed in the assembly of two wafers, the cutting may also create particles that contaminate equipment.
  • an object of the present invention is to omit the step of trimming the bevelled edges of a wafer during assembly of two wafers, especially two semiconductor wafers.
  • a process for assembling a first wafer and a second wafer each bevelled on their peripheries.
  • the process may comprise excavating the bevelled peripheral part of at least one first side of the first wafer to create a deposit bordering the region excavated in the material of the first wafer.
  • the first side may then be bonded to a second side of the second wafer.
  • bevelled is to be understood in a very broad sense.
  • the term especially covers a cut at the ends of the wafers in a substantially oblique direction.
  • the cut surface may have a profile decreasing towards the end, whether this profile is straight or rounded, for example.
  • the deposit bordering the region excavated in the material that formerly made up this region on the bevelled peripheral part makes it possible to fill at least partially the space between the two bevelled parts.
  • the bonding step may comprise direct bonding of the first side and the second side.
  • direct bonding also sometimes called molecular bonding
  • bonding occurs when the two sides to be assembled are brought into contact.
  • the bonding may comprise, before the direct bonding, forming a bonding layer on the first side of the first wafer obtained after the excavation step, and/or on the second side of the second wafer.
  • the formation of the bonding layer (made of silicon oxide or silicon nitride, for example) also makes it possible to level the surfaces. This makes the subsequent direct bonding easier.
  • Formation of the bonding layer on a wafer may comprise oxidizing the wafer.
  • the bonding layer may be made of a layer of silicon dioxide (SiO 2 ). This may, for example, be an oxidation of the whole first wafer.
  • the excavation may lead to polycrystalline silicon being deposited so that it borders the excavated region. Since the polycrystalline silicon may be more porous than single-crystal silicon, oxygen atoms may diffuse more rapidly into the polycrystalline silicon than into the single-crystal substrate during formation of the silicon dioxide by oxidation.
  • the oxidation may be dry oxidation, for example. Consequently, the silicon dioxide may be thicker in the bevelled peripheral parts that comprise polycrystalline silicon.
  • the bonding layer (for example, made of silicon dioxide or silicon nitride) may be formed by deposition.
  • the cavity formed between the bevelled peripheral parts may be filled with the material of the excavated region and of the bonding layer.
  • the bonding region between the two wafers may thus be laterally added to in this bevelled region.
  • the bevelled peripheral part of the wafer to be thinned may be supported during the thinning step, thus preventing cracking in this peripheral part without an edge trimming step being required.
  • the bonding step may comprise, before the direct bonding, preparing the surfaces to be assembled to make the direct bonding easier, especially in terms of planarity, roughness and hydrophilicity.
  • the process may furthermore comprise excavating the bevelled peripheral part of the second side.
  • the excavation may be produced using a laser beam.
  • Application of this laser beam may cause the material forming the wafer to be expulsed and redeposited about the point of impact of the laser beam. If the wafer is made of silicon, the redeposited material may be polycrystalline silicon.
  • the process may further comprise thinning at least one of the two wafers.
  • a device comprising at least two wafers bevelled at their peripheries and rigidly connected to one another. At least one of the wafers may have on its assembled side, in its bevelled periphery, an excavation having a contour that comprises a surplus of material of the excavated wafer. The side joined to the other wafer may be covered with a bonding layer. One of the two wafers may be thinner than the other.
  • the wafers may be made of a semiconductor, especially silicon, germanium or an III-V or II-VI semiconductor, or glass.
  • the two wafers may comprise different materials.
  • the bonding layer may comprise silicon dioxide (SiO 2 ) or silicon nitride (Si 3 N 4 ).
  • FIGS. 1 a , 1 b , 2 a and 2 b schematically illustrate an assembly of two silicon wafers according to the prior art
  • FIGS. 3 to 7 illustrate a method of implementation and embodiments according to the present invention.
  • FIG. 3 a schematic top view of a wafer P 1 is shown.
  • the wafer P 1 is a silicon wafer, for example, comprising a bevelled peripheral part BIS.
  • the wafer P 1 may have a diameter of 200 or 300 millimeters, for example, and a thickness of 700 microns.
  • the bevelled peripheral part BIS may extend, by way of example, 1 to 3 millimeters.
  • a laser beam is applied to the bevelled peripheral part BIS, for example, along the path T.
  • the path T is a circular path (e.g., 2 or 3 mm from the edge of the wafer). However, it is also possible to follow other paths, for example, a sinusoidal path.
  • the path T is a continuous path but it is also possible to apply the laser beam to a discontinuous path T.
  • the path T may have a width of about 500 microns.
  • the laser used may be a laser typically used for marking reference codes in wafers, as readily known by those skilled in the art.
  • a cross-sectional view of the wafer P 1 after the laser has been applied along the path T is shown in FIG. 4 .
  • the bevelled peripheral part BIS now comprises an excavation or crater CR (typically a few microns in depth) formed when the applied laser beam melts the silicon. During this melting, silicon grains are extracted and redeposited on the bevelled peripheral part BIS to form a polysilicon mass POLY.
  • excavation or crater CR typically a few microns in depth
  • the power of the laser may be adjusted to control the depth of the crater, and therefore, the amount of material redeposited to fill to the bevelled region.
  • the amount of material redeposited my thus be greater or lesser based on the depth of the crater.
  • a bonding layer OX for example, a layer of silicon dioxide, is at least formed on the upper surface of the wafer P 1 by dry oxidation ( FIG. 5 ), for example.
  • the polysilicon layer POLY is a porous layer which is easier for the oxygen atoms introduced during the dry oxidation to diffuse into, thereby promoting growth of the silicon dioxide.
  • the silicon grains in the layer POLY are transformed at least partially into silicon dioxide OXB to form a layer that is thicker than the layer OX. This is because a silicon grain at least partially converted into silicon dioxide has a larger volume after conversion.
  • the silicon dioxide may be deposited, for example, by chemical vapour deposition (CVD).
  • CVD chemical vapour deposition
  • the polysilicon mass POLY covered with silicon dioxide makes it possible to at least partially fill the cavity between the bevelled peripheral parts BIS of the wafers P 1 and P 2 .
  • This may, for example, be a deposit of tetraethyl orthosilicate (TEOS) having a thickness between 500 and 1000 nanometers.
  • TEOS tetraethyl orthosilicate
  • This bonding layer may undergo conventional preparation steps to make the subsequent direct bonding easier, especially in terms of planarity, roughness and hydrophilicity.
  • This preparation may comprise a chemical-mechanical polishing (CMP) step or treatment with plasma, UV or ozone.
  • CMP chemical-mechanical polishing
  • FIG. 6 shows bonding of the wafer P 1 to a silicon wafer P 2 on which an optional bonding layer OX has also been formed, for example, a layer of silicon dioxide (SiO 2 ). It could also be a layer of silicon nitride (Si 3 N 4 ).
  • the layer of silicon dioxide OXB enables the cavity formed between the bevelled parts BIS of the wafers P 1 and P 2 to be at least partially filled.
  • the bonding layer OX of the second wafer P 2 may also have undergone the above mentioned preparation steps with a view to making the direct bonding easier.
  • the wafers P 1 and P 2 are bonded using conventional direct bonding by placing the two wafers in contact.
  • a heat treatment step e.g., at about 350° C. for two hours may be used to increase the bonding energy.
  • the presence of the crater CR does not affect the filling of the cavity. This is because the edges of the crater on the bevelled peripheral part, covered by the silicon oxide layer OXB, are sufficiently high to meet the wafer P 2 . Moreover, since the layer OXB is porous, the crater CR does not form a cavity in which the gas could be encapsulated causing a defect.
  • the thinning step may comprise a mechanical grinding step followed by a chemical-mechanical polishing.
  • a device comprising at least two wafers bevelled at their peripheries and rigidly connected to one another. At least one of which has on its assembled side, in its bevelled periphery, an excavation having a contour that comprises a surplus of material of the excavated wafer.
  • the wafer P 2 may furthermore be thinned, and the wafer P 1 is replaced in the thinning step.
  • wafers made of different materials whether or not a bonding layer is used. More particularly, it is possible to assemble wafers of silicon, germanium or of III-V or II-VI semiconductors, or of glass. Bonding layers made of silicon dioxide (SiO 2 ) or of silicon nitride (Si 3 N 4 ) may also be used.
  • steps may be implemented to make the direct bonding easier.
  • steps of preparing the surfaces to be assembled may be implemented. This is especially so in terms of planarity, roughness and hydrophilicity.
  • an assembly of silicon wafers may be obtained in which the bevelled peripheral parts of the wafers have not been trimmed, while equipment contamination during the assembly of the silicon wafers and their thinning is reduced.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
US13/330,146 2010-12-20 2011-12-19 Process for assembling two wafers and corresponding device Expired - Fee Related US9330957B2 (en)

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US15/087,093 US20160218178A1 (en) 2010-12-20 2016-03-31 Process for assembling two wafers and corresponding device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1060839A FR2969373B1 (fr) 2010-12-20 2010-12-20 Procede d'assemblage de deux plaques et dispositif correspondant
FR1060839 2010-12-20

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CN104733300B (zh) * 2013-12-23 2018-09-25 中芯国际集成电路制造(上海)有限公司 一种键合晶片的减薄方法
FR3036223B1 (fr) * 2015-05-11 2018-05-25 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de collage direct de substrats avec amincissement des bords d'au moins un des deux substrats
CN108242393B (zh) * 2016-12-23 2021-04-23 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
CN109712875B (zh) * 2018-12-29 2020-11-20 上海华力微电子有限公司 晶圆直接键合方法

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FR2860842A1 (fr) 2003-10-14 2005-04-15 Tracit Technologies Procede de preparation et d'assemblage de substrats
EP1887613A1 (fr) 2005-05-31 2008-02-13 Shin-Etsu Handotai Co., Ltd Procede de fabrication de tranche liee et appareil destine a rectifier la circonference exterieure de la tranche liee
EP1962325A1 (fr) 2005-12-16 2008-08-27 Shin-Etsu Handotai Co., Ltd. Procédé de fabrication d un substrat lié
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JP3580227B2 (ja) * 2000-06-21 2004-10-20 三菱住友シリコン株式会社 複合基板の分離方法及び分離装置
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US20030148595A1 (en) * 1998-01-13 2003-08-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor substrate processing method
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US20010055863A1 (en) * 1998-06-04 2001-12-27 Masatake Nakano Methods for manufacturing soi wafer and soi wafer
US6624047B1 (en) * 1999-02-02 2003-09-23 Canon Kabushiki Kaisha Substrate and method of manufacturing the same
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US20040206444A1 (en) 2003-03-14 2004-10-21 Fabrice Letertre Methods for forming an assembly for transfer of a useful layer
FR2860842A1 (fr) 2003-10-14 2005-04-15 Tracit Technologies Procede de preparation et d'assemblage de substrats
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US8628674B2 (en) * 2004-12-28 2014-01-14 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for trimming a structure obtained by the assembly of two plates
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US20120161292A1 (en) 2012-06-28
US20160218178A1 (en) 2016-07-28
FR2969373A1 (fr) 2012-06-22
FR2969373B1 (fr) 2013-07-19

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