US9111751B2 - Silicon carbide semiconductor device and method of fabricating same - Google Patents

Silicon carbide semiconductor device and method of fabricating same Download PDF

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US9111751B2
US9111751B2 US13/995,993 US201113995993A US9111751B2 US 9111751 B2 US9111751 B2 US 9111751B2 US 201113995993 A US201113995993 A US 201113995993A US 9111751 B2 US9111751 B2 US 9111751B2
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silicon carbide
cathode
contact
drift layer
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US20140001472A1 (en
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Akihiko Furukawa
Yasuhiro Kagawa
Naruhisa Miura
Masayuki Imaizumi
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Mitsubishi Electric Corp
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Definitions

  • the present invention relates to silicon carbide semiconductor devices that include diodes for measuring temperatures of silicon carbide semiconductor elements.
  • Silicon carbide (SiC) semiconductor elements are operable at a higher temperature as compared with semiconductor elements formed of silicon (Si). However, since the operable temperature has an upper limit, it is preferable to equip the semiconductor devices with temperature sensors for measuring temperatures of the semiconductor elements.
  • Patent Document 1 discloses that a pn junction diode, hetero junction diode, or Schottky diode (hereinafter called “SBD”) is formed on the same substrate as a static induction transistor formed of SiC, to use such a diode as the temperature sensor for measuring a temperature of the static induction transistor.
  • SBD Schottky diode
  • Patent Document 1 JP-A-2006-93382 (pages 2 through 8, and FIGS. 1 through 4)
  • Patent Document 1 has not described a specific configuration of, and a method of fabricating, an SiC semiconductor device equipped with the SBD for use as a temperature sensor that measures a temperature of an SiC semiconductor element.
  • the present invention is directed to overcome the above problem, and an object of the invention is to provide an SiC semiconductor device equipped with an SBD for measuring a temperature of an SiC semiconductor element.
  • An SiC semiconductor device comprises an SiC epitaxial substrate having an n-type SiC substrate, and an n-type SiC drift layer formed on a surface of the SiC substrate; an SiC semiconductor element formed on the SiC epitaxial substrate; and a Schottky diode formed on the SiC epitaxial substrate, for measuring a temperature of the SiC semiconductor element.
  • the Schottky diode includes an n-type cathode region in a surface portion of the SiC drift layer; a first titanium electrode formed on the cathode region, the first titanium electrode serving as a Schottky electrode; an n-type cathode contact region formed in the surface portion of the SiC drift layer so as to make contact with the cathode region, the cathode contact region having a higher concentration than the cathode region; a first ohmic electrode formed on the cathode contact region; and a first p-type well region formed so as to surround peripheries of the cathode region and the cathode contact region within the SiC drift layer.
  • a method of fabricating the SiC semiconductor device according to the present invention is that of fabricating an SiC semiconductor device that includes an SiC epitaxial substrate having an n-type SiC substrate, and an n-type SiC drift layer formed on a surface of the n-type SiC substrate; an SiC semiconductor element formed on the SiC epitaxial substrate; and a Schottky diode formed on the SiC epitaxial substrate, for measuring a temperature of the SiC semiconductor element.
  • the method of fabricating the SiC semiconductor device comprises, in order to form the Schottky diode, the steps of forming a first p-type well region formed so as to surround a periphery of an n-type cathode region in a surface portion of the SiC drift layer within the SiC drift layer; forming an n-type cathode contact region in the surface portion of the SiC drift layer and within a region surrounded by the first well so that the n-type cathode contact region makes contact with the cathode region, the cathode contact region having a higher concentration than the cathode region; forming a first ohmic electrode on the cathode contact region; and forming a first titanium electrode on the cathode region, the first titanium electrode serving as a Schottky electrode.
  • the present invention can provide an SiC semiconductor device that is equipped with an SBD for measuring a temperature of an SiC semiconductor element.
  • an SiC semiconductor device can be provided that is equipped with the SBD for measuring a temperature of an SiC semiconductor element.
  • FIG. 1 is a set of cross-sectional views illustrating an SiC semiconductor device 1 a according to Embodiment 1 of the present invention
  • FIG. 1A is a cross-sectional view showing an SBD section 2 and its neighborhood, and FIG. 1B , a cross-sectional view showing a MOSFET section 3 a;
  • FIG. 2 is a plan view illustrating an enlarged neighborhood of the SBD section of an SiC epitaxial substrate according to Embodiment 1 of the present invention
  • FIG. 3 is a set of cross-sectional views partially illustrating a method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention
  • FIG. 4 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention
  • FIG. 5 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 6 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 7 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 8 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 9 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 10 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 11 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 12 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 13 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 14 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 1 of the present invention.
  • FIG. 15 shows results calculated by device simulations of current-voltage characteristics of an SBD according to Embodiment 1 of the present invention
  • FIG. 16 is a graph showing a relationship between a temperature T of the SBD and an anode voltage V A for an anode current I A of 1 micro A;
  • FIG. 17 is a set of cross-sectional views illustrating an SiC semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 17A is a cross-sectional view showing a pn junction diode section and its neighborhood
  • FIG. 17B a cross-sectional view showing a MOSFET section
  • FIG. 18 is a set of cross-sectional views partially illustrating a method of fabricating a SiC semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 19 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 20 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 21 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 22 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 23 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 24 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 25 is a set of cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 2 of the present invention.
  • FIG. 1 is a set of cross-sectional views illustrating an SiC semiconductor device 1 a according to Embodiment 1 of the present invention
  • FIG. 1A is a cross-sectional view showing a neighborhood of an SBD section 2
  • FIG. 1B a cross-sectional view showing a MOSFET section 3 a
  • FIG. 2 is a plan view illustrating an enlarged neighborhood of the SBD section 2 of an SiC epitaxial substrate 11 according to Embodiment 1 of the present invention. Note that FIG. 1 shows the SiC semiconductor device 1 a taken along the same cross-section as A-A cross-section in FIG. 2 .
  • the SiC semiconductor device 1 a includes the MOSFET section 3 a —where a metal oxide semiconductor field effect transistor (MOSFET), which is an SiC semiconductor element, is formed on the SiC epitaxial substrate 11 where an n-type SiC drift layer 8 is formed on a surface 7 of the n-type SiC substrate 6 —and the SBD section 2 where an SBD for measuring a temperature of the MOSFET is formed.
  • MOSFET metal oxide semiconductor field effect transistor
  • the configurations of the SBD section 2 and its neighborhood will be described first.
  • the SBD section 2 has an n-type cathode region 12 formed in the surface portion of the SiC drift layer 8 , and has a first p-type well region 13 formed in a portion deeper than the cathode region 12 of the SiC drift layer 8 , as shown in FIG. 1A . Further, an n-type cathode contact region 16 having a higher concentration than the cathode region 12 is formed so that the cathode contact region 16 in the surface portion of the SiC drift layer 8 surrounds an outer circumference of the cathode region 12 , as shown in FIG. 1A and FIG. 2 .
  • a p-type guard region 17 having a higher concentration than the first well region 13 is formed so that the guard region 17 in the surface portion of the SiC drift layer 8 surrounds an outer circumference of the cathode contact region 16 .
  • the cathode region 12 adjoins the cathode contact region 16 , and peripheries of both regions are surrounded by a p-region formed by the first p-type well region 13 having a less concentration than the guard region 17 and the guard region 17 , within the SiC drift layer 8 .
  • a field oxide film 18 covers over a region of the SiC drift layer 8 other than those where elements are formed, and formed on the field oxide film 18 is a polysilicon electrode 21 that serves as a gate electrode.
  • An inter-layer dielectric film 22 is formed above the SiC drift layer 8 and the polysilicon electrode 21 , and an anode contact hole 23 a , a cathode contact hole 23 b , a guard contact hole 23 c , and a gate contact hole 23 d are formed on the cathode region 12 , the cathode contact region 16 , the guard region 17 , and the polysilicon electrode 21 , respectively.
  • a cathode ohmic electrode 26 b is formed, on the cathode contact region 16 , in a portion corresponding to a bottom of the cathode contact hole 23 b ; and a guard ohmic electrode 26 c , on the guard region 17 , in a portion corresponding to a bottom of the guard contact hole 23 c.
  • an anode titanium electrode 27 a is formed so as to make contact with the cathode region 12 and to cover an inner surface of the anode contact hole 23 a ;
  • a cathode titanium electrode 27 b is formed so as to make contact with the cathode ohmic electrode 26 b and to cover an inner surface of the cathode contact hole 23 b ;
  • a guard titanium electrode 27 c is formed so as to make contact with the guard ohmic electrode 26 c and to cover an inner surface of the guard contact hole 23 c ;
  • a gate titanium electrode 27 d is formed so as to make contact with the polysilicon electrode 21 and to cover an inner surface of the gate contact hole 23 d .
  • the anode titanium electrode 27 a is a Schottky electrode that forms a Schottky barrier between the anode titanium electrode 27 a and cathode region 12 .
  • an anode wiring 28 a is formed so as to make contact with the anode titanium electrode 27 a and to fill in the anode contact hole 23 a ;
  • a cathode wiring 28 b is formed so as to make contact with the cathode titanium electrode 27 b and to fill in the cathode contact hole 23 b ;
  • a guard wiring 28 c is formed so as to make contact with the guarde titanium electrode 27 c and to fill in the guarde contact hole 23 c ;
  • a gate wiring 28 d is formed so as to make contact with the gate titanium electrode 27 d and to fill in the gate contact hole 23 d.
  • a drain ohmic electrode 26 f is formed on the other surface 31 of the SiC substrate 6 , and a drain wiring 28 f is formed on the drain ohmic electrode 26 f.
  • an anode terminal 32 a is connected to the anode wiring 28 a ; a cathode terminal 32 b , to the cathode wiring 28 b ; a guard terminal 32 c , to the guard wiring 28 c ; and a drain terminal 32 f , to the drain wiring 28 f.
  • the configuration of the MOSFET section 3 a will be described next.
  • the MOSFET section 3 a has an n-type embedded channel region 33 formed in the surface portion of the SiC drift layer 8 , as shown in FIG. 1B .
  • a second p-type well region 36 having substantially the same concentration as that of the first well region 13 , is formed in contact with, and in a portion deeper than, the embedded channel region 33 of the SiC drift layer 8 .
  • an n-type source region 37 of substantially the same concentration as that of the cathode contact region 16 is formed in the surface portion of the SiC drift layer 8 so as to range from the embedded channel region 33 to the second well region 36 .
  • a p-type well contact region 38 of substantially the same concentration as that of the guard region 17 is formed in the surface portion of the SiC drift layer 8 so as to makes contact with the source region 37 and the second well region 36 .
  • a gate dielectric film 41 is formed above part of the SiC drift layer 8 of the MOSFET section 3 a , and the polysilicon electrode 21 serving as the gate electrode is formed on the gate dielectric film 41 .
  • the polysilicon electrode 21 is formed astride the source region 37 , the second well region 36 and the embedded channel region 33 , of the SiC drift layer 8 , with the gate dielectric film 41 intervening between the polysilicon electrode 21 and the source region 37 , the second well region 36 and the embedded channel region 33 .
  • the polysilicon electrode 21 on the gate dielectric film 41 described herein, and the polysilicon electrode 21 on the field oxide film 18 , described previously, are formed as a single continuous electrode, both of which are electrically connected together.
  • the inter-layer dielectric film 22 is formed on the SiC drift layer 8 and on the polysilicon electrode 21 , and the source contact hole 23 e is formed above the source region 37 and the well contact region 38 .
  • a source ohmic electrode 26 e is formed on a portion that is on the source region 37 and the well contact region 38 and corresponds to the bottom of a source contact hole 23 e .
  • a source titanium electrode 27 e is formed so as to make contact with the source ohmic electrode 26 e and to cover an inner surface of the source contact hole 23 e
  • a source wiring 28 e is formed so as to make contact with the source titanium electrode 27 e and to fill in the source contact hole 23 e .
  • a source terminal 32 e is connected to the source wiring 28 e.
  • drain ohmic electrode 26 f formed on the other surface 31 of the SiC substrate 6 is the drain ohmic electrode 26 f and the drain wiring 28 f in the same fashion as in the SBD section 2 .
  • the drain ohmic electrodes 26 f formed in the SBD section 2 and the MOSFET section 3 a are formed into a single continuous electrode, both of which are electrically connected together. This holds true for the drain wiring 28 f as well.
  • FIGS. 3 through 14 are cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device 1 a according to Embodiment 1 of the present invention. Note that, in each of the drawing numbers, the symbol A depicts the SBD section 2 and its neighborhood and the symbol B, the MOSFET section 3 a.
  • n-type silicon carbide substrate 6 with low resistance is first made ready and available whose plane orientation of the surface 7 is (0001) plane and the SiC substrate 6 has a 4H poly type.
  • the SiC epitaxial substrate 11 is formed by forming the n-type SiC drift layer 8 with a thickness of 4 ⁇ m through 200 ⁇ m by a chemical vapor deposition (CVD) technique on the surface 7 of the SiC substrate 6 .
  • n-type dopant concentration of the SiC drift layer 8 is determined to within a value range between, for example, 1 ⁇ 10 14 cm ⁇ 3 and 1 ⁇ 10 17 cm ⁇ 3 .
  • the plane orientation of the SiC substrate 6 may be of (000-1) plane, (11-20) plane or the like and may be slanted below 8 degrees from such a plane orientation.
  • the poly type may be of 6H, 3C or the like.
  • a process of implanting ions into the SiC drift layer 8 will be described below.
  • the ion-implantation is performed using a resist mask formed on the SiC drift layer 8 by photolithography.
  • the SiC epitaxial substrate 11 may be heated at 200° C. through 800° C., or alternatively, does not need to be heated actively.
  • a substance such as nitrogen, phosphorus or arsenic is used.
  • a p-type dopant therefor a substance such as aluminum, boron or gallium is employed.
  • the n-type dopant is next ion-implanted from a surface of the SiC drift layer 8 , to form the cathode region 12 and the embedded channel region 33 in the surface portion of the SiC drift layer 8 .
  • the cathode region 12 and the embedded channel region 33 are of substantially the same dopant concentration, and formed in one and the same ion-implantation process.
  • the n-type dopant concentration for ion-implantation is set to within a value range between, for example, 1 ⁇ 10 15 cm ⁇ 3 and 1 ⁇ 10 18 cm ⁇ 3 so as to exceed a value of the dopant concentration of the SiC drift layer 8 and not to exceed a value of the dopant concentration to be described later of the cathode contact region 16 .
  • the depth of ion-implantation is determined to within a value of, for example, 0.4 ⁇ m deep from the surface of the SiC drift layer 8 .
  • Forming the embedded channel region 33 in the MOSFET section 3 a can increase conductivity in the channel region of the MOSFET.
  • the cathode region 12 and the embedded channel region 33 may be formed as a single continuous ion-implantation layer, or alternatively may be formed as separate ion-implantation layers.
  • the p-type dopant is subsequently ion-implanted from the surface of the SiC drift layer 8 , to form the first well region 13 in a portion deeper than and in contact with the cathode region 12 , and the second well region 36 in a portion deeper than and in contact with the embedded channel region 33 of the SiC drift layer 8 .
  • the first well region 13 and the second well region 36 are of substantially the same dopant concentration, and formed in one and the same ion-implantation process.
  • the p-type dopant concentration for the ion-implantation exceeds a value of the dopant concentration of the SiC drift layer 8 , and is determined to within a value range between, for example, 1 ⁇ 10 15 cm ⁇ 3 and 1 ⁇ 10 19 cm ⁇ 3 .
  • the depth of ion-implantation is set so that the bottoms of the first well region 13 and the second well region 36 are at a higher position than that of the SiC drift layer 8 ; the depth thereof is determined to within a value range between, for example, 0.3 ⁇ m and 2 ⁇ m.
  • the n-type dopant is next ion-implanted from the surface of the SiC drift layer 8 , to form the cathode contact region 16 and the source region 37 in the surface portion of the SiC drift layer 8 .
  • the cathode contact region 16 is formed so as to surround an outer circumference of the cathode region 12 , resulting in the cathode contact region 16 making contact with the cathode region 12 .
  • the cathode contact region 16 and the source region 37 are of substantially the same dopant concentration, having a higher n-type concentration than the cathode region 12 and the embedded channel region 33 , and are formed in one and the same ion-implantation process.
  • the concentration of n-type dopant for ion-implantation which exceeds the values of dopant concentration of the first well region 13 and the second well region 36 , is determined to within a value range between, for example, 1 ⁇ 10 17 cm ⁇ 3 and 1 ⁇ 10 21 cm ⁇ 3 .
  • the depth of ion-implantation is set so that the bottoms of the cathode contact region 16 and the source region 37 are at a higher position than those of the first well region 13 and the second well region 36 , respectively.
  • a suitable ohmic contact can be made to electrodes to be formed in a later process on the cathode contact region 16 and the source region 37 .
  • the p-type dopant is ion-implanted from the surface of the SiC drift layer 8 , to form the guard region 17 and the well contact region 38 in the surface portion of the SiC drift layer 8 .
  • the guard region 17 is formed so as to surround the outer circumference of the cathode contact region 16 .
  • the well contact region 38 is formed so as to make contact with the source region 37 and the second well region 36 .
  • the guard region 17 and the well contact region 38 are of substantially the same dopant concentration, having a higher p-type concentration than the first well region 13 and the second well region 36 , and are formed in one and the same ion-implantation process.
  • the concentration of p-type dopant for ion-implantation which exceeds the values of dopant concentration of the first well region 13 and the second well region 36 , is determined to within a value between, for example, 1 ⁇ 10 17 cm ⁇ 3 and 1 ⁇ 10 21 cm ⁇ 3 .
  • the depth of ion-implantation is set so that the bottoms of the guard region 17 and the well contact region 36 are at a higher position than those of the first well region 13 and the second well region 36 , respectively.
  • the guard region 17 and the well contact region 38 By forming the guard region 17 and the well contact region 38 , a suitable ohmic contact can be made to electrodes that are to be formed, in a later process, on the guard region 17 and the well contact region 38 , thereby allowing low resistance electrical connection of the electrodes with the first well region 13 and the second well region 36 .
  • the ion-implantation is performed by heating the SiC epitaxial substrate 11 at 150° C. or more. With this, the guard region 17 and the well contact region 38 can be provided which have low sheet resistance.
  • heat treatment is performed at a temperature within the range between 1500° C. and 2200° C., within a time range between 0.5 min. and 60 min.
  • the ion-implanted dopants are electrically activated.
  • this heat treatment may be performed with the surface of the SiC epitaxial substrate 11 covered with a carbon film. Doing this way can prevent the SiC substrate 6 and SiC drift layer 8 from having roughed surfaces, during heat treatment, caused by etching of a substance, such as residual moisture and/or residual oxygen within the device.
  • the surface of the SiC drift layer 8 is thermally oxidized to form a sacrificial oxide film, and thereafter the sacrificial oxide film is removed by hydrofluoric acid. This allows removal of a degraded surface layer of the SiC drift layer 8 , thereby providing a clear surface.
  • the field oxide film 18 is formed on the SiC drift layer 8 , as shown in FIG. 8 .
  • the field oxide film 18 is formed by depositing a silicon oxide film by a technique such as CVD and by patterning the film; however, herein, the patterning is performed so that an open portion is provided above the region, of the SiC drift layer 8 , where a device is formed, and a region other than where the device is formed is covered with the field oxide film 18 . It will be adequate if the field oxide film 18 has a thickness between 0.5 ⁇ m and 2 ⁇ m.
  • the gate dielectric film 41 is next formed above the SiC drift layer 8 of the MOSFET section 3 a , as shown in FIG. 9 .
  • the gate dielectric film 41 is formed by forming the silicon oxide film by the thermal oxidation technique or CVD technique, and the film thickness is determined to be on the order of 50 nm.
  • the polysilicon electrode 21 serving as the gate electrode, is formed on the gate dielectric film 41 and the field oxide film 18 , as shown in FIG. 10 .
  • the polysilicon electrode 21 is formed astride the source region 37 , the second well region 36 and the embedded channel region 33 of the SiC drift layer 8 , with the gate dielectric film 41 intervening between the polysilicon electrode 21 and the source region 37 , the second well region 36 and the channel region 33 .
  • the polysilicon electrodes 21 are of high n-type concentration.
  • the inter-layer dielectric film 22 is next formed on the SiC drift layer 8 and the polysilicon electrodes 21 , and then, by a technique such as dry-etching, the cathode contact hole 23 b , the guard contact hole 23 c and the source contact hole 23 e are formed on the cathode contact region 16 , the guard region 17 and the source region 37 , respectively.
  • the silicon oxide film formed by a method such as the CVD technique is employed.
  • the cathode ohmic electrode 26 b , the guard ohmic electrode 26 c , and the source ohmic electrode 26 e are next formed at portions corresponding to the bottoms of the cathode contact hole 23 b on the cathode contact region 16 , the guard contact hole 23 c on the guard region 17 , and the source contact hole 23 e on the source region 37 and the well contact region 38 , respectively, and then the drain ohmic electrode 26 f is formed on the other surface 31 of the SiC substrate 6 .
  • nickel silicide is employed, for example.
  • a metal film having nickel as a chief component is formed over the entire surface of substrate from above the inter-layer dielectric film 22 , and likewise, the metal film having the nickel as the chief component is also formed over the other surface 31 of the SiC substrate 6 , and thereafter the heat treatment is performed at 600° C. through 1100° C. Through this treatment, the nickel silicide is formed between the SiC and the metal film.
  • the metal film that has remained on the inter-layer dielectric film 22 is eliminated by wet-etching using a liquid mixture or the like of sulfuric acid, nitric acid, or hydrochloric acid with hydrogen peroxide water.
  • the anode contact hole 23 a and the gate contact hole 23 d are next formed on the cathode region 12 and the polysilicon electrode 21 , respectively.
  • a method of forming the anode contact hole 23 a and the gate contact hole 23 d is as follows: First, a resist film is formed so as to cover the surface of the inter-layer dielectric film 22 except for the portions where the anode contact hole 23 a and the gate contact hole 23 d are to be formed, and to fill in the cathode contact hole 23 b , the guard contact hole 23 c and the source contact hole 23 e ; then, the respective anode contact hole 23 a and gate contact hole 23 d are formed by wet-etching or dry-etching; and thereafter, the resist film is removed, and degraded surface layers on the bottoms of the anode contact hole 23 a , the cathode contact hole 23 b , the guard contact hole 23 c , the gate contact hole 23 d and the source contact hole 23 .
  • the gate contact hole 23 d is formed on the field oxide film 18 that is thicker than the gate dielectric film 41 , and this formation can prevents electrodes to be formed in a later process from making contact with the SiC drift layer 8 , even in the event that the gate contact hole 23 d penetrates the polysilicon electrode 21 during the process of forming the gate contact hole 23 d .
  • the gate contact hole 23 d may be formed on the gate dielectric film 41 if the gate contact hole 23 d is not made to penetrate the polysilicon electrode 21 during the process of forming the gate contact hole 23 d.
  • a titanium film is formed from the surface of the inter-layer dielectric film 22 .
  • the titanium film is formed so as to make contact with the cathode region 12 , the cathode ohmic electrode 26 b , the guard ohmic electrode 26 c , the polysilicon electrode 21 and the source ohmic electrode 26 e , and to cover the inner surfaces of the anode contact hole 23 a , the cathode contact hole 23 b , the guard contact hole 23 c , the gate contact hole 23 d and the source contact hole 23 e.
  • an aluminum film is formed from the surface of the titanium film.
  • the aluminum film is formed so as to make contact with the titanium film and fill in the anode contact hole 23 a , the cathode contact hole 23 b , the guard contact hole 23 c , the gate contact hole 23 d and the source contact hole 23 e.
  • barrier metal such as a titanium nitride may be formed on the titanium film.
  • the patterning forms the anode titanium electrode 27 a and anode wiring 28 a , the cathode titanium electrode 27 b and cathode wiring 28 b , the guard titanium electrode 27 c and guard wiring 28 c , the gate titanium electrode 27 d and gate wiring 28 d , and the source titanium electrode 27 e and source wiring 28 e.
  • the Schottky barrier is formed between the cathode region 12 and the anode titanium electrode 27 a , while the ohmic contact can be made between the gate titanium electrode 27 d and the polysilicon electrode 21 serving as the gate electrode.
  • the heat treatment may be performed at about 500° C.
  • the heat treatment is preferably carried out for about 15 min. in an atmosphere of a gas such as argon. This allows a suitable Schottky barrier to be formed between the anode titanium electrode 27 a and the cathode region 12 , and can make an ohmic contact of lower resistance between the gate titanium electrode 27 d and the polysilicon electrode 21 .
  • the drain wiring 28 f is formed on the drain ohmic electrode 26 f using a metal such as nickel or gold, with the configuration being shown in FIG. 14 .
  • the anode terminal 32 a , the cathode terminal 32 b , the guard terminal 32 c , the gate terminal 32 d , the source terminal 32 e and the drain terminal 32 f are finally formed, resulting in completion of the SiC semiconductor device 1 a as shown in FIG. 1 .
  • the anode terminal 32 a and the cathode terminal 32 b are connected to a control integrated circuit (IC), not shown.
  • the control IC has a built-in current source and voltmeter.
  • This current source can supply a constant current in the forward direction of the SBD from the anode terminal 32 a to the cathode terminal 32 b , with a ground potential provided to the cathode terminal 32 b .
  • the voltmeter can measure voltage across the anode terminal 32 a and the cathode terminal 32 b.
  • a constant current of, for example, 1 ⁇ A is caused to flow from the anode terminal 32 a to the cathode terminal 32 b .
  • the voltmeter in the control IC measures the voltage across the anode terminal 32 a and the cathode terminal 32 b when the constant current flows.
  • the control IC determines that the MOSFET is in an over-temperature condition, and sends a stop signal to the MOSFET. Assuming that the set-point voltage is 0.4 V when the MOSFET is at, for example, 250° C., the control IC sends the stop signal to the MOSFET when the voltage measured becomes below 0.4 V for a certain amount of time.
  • FIG. 15 shows results calculated by a device simulation of current-voltage characteristic of the SBD according to Embodiment 1 of the present invention.
  • the horizontal axis represents voltage of the anode terminal 32 a (anode voltage V A ), while the vertical axis represents current that flows through the anode terminal 32 a (anode current I A ), that is, current that flows through the SBD.
  • the simulation was performed for temperatures T of the SBD, that is, the MOSFET temperatures T of 300K, 400K and 500K.
  • the ground potential is provided to the cathode terminal 32 b and a dopant concentration of the cathode region 12 is set to 1 ⁇ 10 17 cm ⁇ 3 .
  • a constant current (current for determination) of 1 ⁇ A is flowed from the anode terminal 32 a to the cathode terminal 32 b , i.e., that the anode current I A is 1 ⁇ A.
  • the broken lines indicate the current level where the anode current I A , i.e., the determination current is 1 ⁇ A.
  • FIG. 16 is a graph showing a relationship between the SBD temperature T and the anode voltage V A , for the anode current I A of 1 ⁇ A.
  • the horizontal axis represents the SBD temperature T
  • the vertical axis the anode voltage V A .
  • Points marked in FIG. 16 represent those where the anode current I A is 1 ⁇ A in FIG. 15 .
  • FIG. 16 shows that when the SBD temperature T, i.e., the MOSFET temperature T is 523K (250° C.), the anode voltage V A is 0.4 V. Therefore, as described previously, in order to prevent the MOSFET temperature T from exceeding 250° C., it will be adequate if the set-point temperature in the control IC, when the determination current is 1 ⁇ A, is set at a value corresponding to 0.4 V and the anode voltage V A is measured, and when this voltage measured is below 0.4 V for a certain amount of time, the control IC sends the stop signal to the MOSFET.
  • the SBD temperature T i.e., the MOSFET temperature T is 523K (250° C.
  • the anode voltage V A is 0.4 V. Therefore, as described previously, in order to prevent the MOSFET temperature T from exceeding 250° C., it will be adequate if the set-point temperature in the control IC, when the determination current is 1 ⁇ A, is set at a value corresponding to
  • anode voltage V A the voltage across the anode terminal 32 a and the cathode terminal 32 b
  • the SBD current voltage characteristic
  • the anode voltage V A (0.4 V in this case)
  • the set-point temperature here, set at 523K (250° C.)
  • the control IC is to stop the MOSFET operation.
  • the anode voltage V A derived is set as the set-point voltage, thereby enabling the MOSFET to be protected from becoming an over-temperature condition.
  • the results of simulations for the SBD temperatures of 300K, 400K and 500K were plotted in FIG. 16 , and the anode voltage V A was found to be 0.4 V from FIG. 16 and the set-point voltage was thereby determined to be 0.4 V.
  • the simulations may be initially performed for the temperature T of 523K (250° C.), to determine the set-point voltage from the results.
  • the SBD current—voltage characteristic was found by the simulations, and the results were used to determine the set-point voltage for which the control IC determines that the MOSFET is in the over-temperature condition; however, the set-point voltage may be determined based on the results obtained when the SBD current—voltage characteristic is actually measured instead of the simulations.
  • an advantageous effect is that the foregoing configuration can provide the SiC semiconductor device 1 a that is equipped with the SBD for measuring a MOSFET temperature.
  • the gate dielectric film 41 and the polysilicon electrode 21 are provided and the gate titanium electrode 27 d is provided on the polysilicon electrode 21 , thereby allowing for formation of the anode titanium electrode 27 a —the Schottky electrode—and the gate titanium electrode 27 d in the same process. Forming these in the same process allows reduction of a dedicated process for fabricating the SBD section 2 of the SiC semiconductor device 1 a , resulting in improved productivity.
  • the source region 37 , the source ohmic electrode 26 e and the second well region 36 allows formation of the source region 37 and the cathode contact region 16 in the same process, formation of the source ohmic electrode 26 e and the cathode ohmic electrode 26 b in the same process, and formation of the second well region 36 and the first well region 13 in the same process. Forming these in the same process allows further reduction of the dedicated process for fabricating the SBD section 2 of the SiC semiconductor device 1 a , resulting in improved productivity.
  • guard region 17 Providing the guard region 17 , the guard ohmic electrode 26 c and the well contact region 38 allows formation of the guard region 17 and the well contact region 38 in the same process and formation of the guard ohmic electrode 26 c , the cathode ohmic electrode 26 b and source ohmic electrode 26 e in the same process. Forming these in the same process allows further reduction of the dedicated process for fabricating the SBD section 2 of the SiC semiconductor device 1 a , resulting in improved productivity. In addition, providing the guard region 17 allows suppression of the switching noise from affecting the SBD.
  • the control IC which includes the current source and the voltmeter, across the anode terminal 32 a and the cathode terminal 32 b , the temperature of MOSFET can easily be measured and thereby the over-temperature of MOSFET can be detected.
  • the cathode region 12 and the embedded channel region 33 are formed in the surface portion of the SiC drift layer 8 .
  • the surface portion of the SiC drift layer 8 per se may be used as the cathode region 12 and the embedded channel region 33 .
  • the MOSFET serves as an SiC semiconductor element whose temperature is measured using the SBD; however, the element is not limited to the MOSFET, but an element such as an insulated gate bipolar transistor (IGBT), a junction FET (JFET), or a static induction transistor (SIT) may serve as the SiC semiconductor element.
  • IGBT insulated gate bipolar transistor
  • JFET junction FET
  • SIT static induction transistor
  • FIG. 17 is a set of cross-sectional views illustrating a SiC semiconductor device 1 b according to Embodiment 2 of the present invention
  • FIG. 17A is a cross-sectional view illustrating a neighborhood of a pn junction diode section 42
  • FIG. 17B is a cross-sectional view illustrating a MOSFET section 3 b .
  • those labeled with the same reference numerals as in FIG. 1 represent the same or corresponding configurations, and their descriptions will not be provided herein.
  • Embodiment 1 A difference between Embodiment 1 and the present embodiment according to the present invention is a configuration in which the SBD is not applied to a diode that serves as the temperature sensor for the MOSFET, but the pn junction diode is applied thereto. Another difference is a configuration in which there is not provided the embedded channel region 33 in the surface portion of the SiC drift layer 8 .
  • the SiC semiconductor device 1 b includes the MOSFET where a MOSFET, which is the SiC semiconductor element, is formed on the SiC epitaxial substrate 11 , and the pn junction diode section 42 where a pn junction diode is formed.
  • the pn junction diode section 42 has a shallow n-type well region 43 , serving as the cathode region, formed in the surface portion of the SiC drift layer 8 , and a deep p-type well region 46 formed in contact with and in a portion deeper than the shallow well 43 . Further, a third p-type well region 47 is formed in the surface portion of the SiC drift layer 8 so as to surround and partially overlap outer circumferences of the shallow well region 43 and the deep well region 46 .
  • a p-type anode region 48 of higher concentration than the third well region 47 is formed in the surface portion of the shallow well region 43 of the SiC drift layer 8 , and the n-type cathode contact region 16 of higher concentration than the shallow well region 43 is formed in the surface portion so as to surround an outer circumference of the anode region 48 .
  • the p-type guard region 17 of higher concentration than the third well region 47 is formed in the surface portion of the third well region 47 of the SiC drift layer 8 so as to surround an outer circumference of the cathode contact region 16 .
  • the inter-layer dielectric film 22 is formed on the SiC drift layer 8 and the polysilicon electrode 21 , and the anode contact hole 23 a , the cathode contact hole 23 b , the guard contact hole 23 c and the gate contact hole 23 d are formed on the anode region 48 , the cathode contact region 16 , the guard region 17 and the polysilicon electrode 21 , respectively.
  • the anode ohmic electrode 26 a , the cathode ohmic electrode 26 b and the guard ohmic electrode 26 c are formed in portions corresponding to the bottoms of the anode contact hole 23 a on the anode region 48 , of the cathode contact hole 23 b on the cathode contact region 16 , and of the guard contact hole 23 c on the guard region 17 , respectively.
  • the anode titanium electrode 27 a is formed so as to make contact with the anode ohmic electrode 26 a and cover the inner surface of the anode contact hole 23 a . Since other titanium electrodes, various wiring traces formed on the titanium electrodes, the drain ohmic electrode 26 f , the drain wiring 28 f and various terminals are the same as those in Embodiment 1, their descriptions will not be provided herein.
  • the configuration of the MOSFET section 3 b will be described next.
  • the second p-type well region 36 of substantially the same concentration as the third well region 47 is formed in the surface portion of the SiC drift layer 8 ;
  • the n-type source region 37 of substantially the same concentration as the cathode contact region 16 is formed in the surface portion of the second well region 36 of the SiC drift layer 8 ;
  • the p-type well contact region 38 of the same concentration as the anode region 48 and the guard region 17 is formed in the surface portion of the SiC drift layer 8 so as to make contact with the source region 37 and the second well region 36 .
  • the polysilicon electrode 21 is formed astride the source region 37 and the second well region 36 , of the SiC drift layer 8 , with the gate dielectric film 41 intervening between the polysilicon electrode and the source region 37 and the second well region 36 .
  • the inter-layer dielectric film 22 , the source contact hole 23 e , other electrodes and the like are the same as those in Embodiment 1 of the present invention and thus their descriptions will not be provided herein.
  • FIGS. 18 through 25 are cross-sectional views partially illustrating the method of fabricating the SiC semiconductor device according to Embodiment 2 of the present invention. Note that, in each of the drawing numbers, the symbol A depicts the pn junction diode section 42 and its neighborhood, and the symbol B, the MOSFET section 3 b.
  • the n-type SiC drift region 8 is first formed on the surface 7 of the n-type SiC substrate 6 and thereafter, by ion implantation, the deep p-type well region 46 and the shallow n-type well region 43 serving as the cathode region is formed at one and the same time.
  • the depth of the shallow well region 43 is set to within a value of 0.6 ⁇ m, for example.
  • the bottom of the deep well region 46 is determined to be deeper than that of the shallow well region 43 , and to be deeper than those of the second well region 36 and the third well region 47 , which are formed in a subsequent process.
  • the n-type dopant concentration of the SiC drift layer 8 is set to within a value between 1 ⁇ 10 14 cm ⁇ 3 and 1 ⁇ 10 17 cm ⁇ 3 , for example.
  • the dopant concentrations of the shallow well region 43 and the deep well region 46 are set to be values that exceed a value of the dopant concentration of the SiC drift layer 8 and that do not exceed those of the dopant concentrations of the second well region 36 and the third well region 47 , which are formed in a subsequent process.
  • a p-type dopant is ion-implanted, to form the third well region 47 and the second well region 36 in the surface portion of the SiC drift layer 8 .
  • the third well region 47 is formed so as to partially overlap with the shallow well region 43 and the deep well region 46 , and to surround outer circumferences of the shallow well region 43 and the deep well region 46 .
  • the bottom of the third region 47 is determined to be deeper than that of the shallow well region 43 , and to be shallower than that of the deep well region 46 .
  • the third well region 47 and the second well region 36 have substantially the same dopant concentration, and are formed by ion implantation at one and the same time.
  • the p-type dopant concentration for ion implantation which exceeds a value of dopant concentration of the SiC drift layer 8 , is determined to within a value range between 1 ⁇ 10 15 cm ⁇ 3 and 1 ⁇ 10 19 cm ⁇ 3 , for example.
  • an n-type dopant is next ion-implanted to form the cathode contact region 16 in the surface portion of the shallow well region 43 of the SiC drift layer 8 , and the source region 37 in the surface portion of the second well region 36 .
  • the cathode contact region 16 and the source region 37 which have substantially the same dopant concentration of a higher n-type concentration than the shallow well region 43 , are formed by ion implantation at one and the same time.
  • the n-type dopant concentration for ion-implantation which exceeds values of the dopant concentrations of the first well region 13 and the second well region 36 , is determined to within a value range between 1 ⁇ 10 17 cm ⁇ 3 and 1 ⁇ 10 21 cm ⁇ 3 , for example.
  • a p-type dopant is next ion-implanted to thereby form the anode region 48 in the surface portion of the shallow well region 43 of the SiC drift layer 8 , the guard region 17 in the surface portion of the third well region 47 , and the well contact region 38 in the surface portion of the second well region 36 .
  • the anode region 48 is disposed so that the cathode contact region 16 surrounds the outer circumference of the anode region.
  • the anode region 48 , the guard region 17 and the well contact region 38 which have substantially the same dopant concentrations of p-type having a higher concentration than the third well region 47 and the second well region 36 , are formed by ion implantation at one and the same time.
  • the bottoms of the anode region 48 , the guard region 17 and the well contact region 38 are set so as to be at a higher position than that of the shallow well region 43 ; their dopant concentrations are determined to within value ranges between 1 ⁇ 10 17 cm ⁇ 3 and 1 ⁇ 10 21 cm ⁇ 3 , for example.
  • the heat treatment is performed at a temperature within the range between 1500° C. and 2200° C., within a time range between 0.5 min. and 60 min. With this treatment, the ion-implanted dopants are electrically activated.
  • the field oxide film 18 is formed and the gate dielectric film 41 is formed, as shown in FIG. 22 .
  • the polysilicon electrode 21 is formed on the gate dielectric film 41 and the field oxide film 18 .
  • the polysilicon electrode 21 is formed astride the source region 37 and the second well region 36 of the SiC drift layer 8 , with the gate dielectric film 41 intervening between the polysilicon electrode 21 and the source region 37 and the second well region 36 .
  • the inter-layer dielectric film 22 is next formed on the SiC drift layer 8 and the polysilicon electrodes 21 , and by a technique such as dry-etching, the anode contact hole 23 a , cathode contact hole 23 b , the guard contact hole 23 c and the source contact hole 23 e are formed on the anode region 48 , the cathode contact region 16 , the guard region 17 and the source region 37 , respectively. Then, formed in portions corresponding to the bottoms of the respective contact holes are the anode ohmic electrode 26 a , the cathode ohmic electrode 26 b , the guard ohmic electrode 26 c and the source ohmic electrode 26 e . And the drain ohmic electrode 26 f is formed on the other surface 31 of the SiC substrate 6 .
  • the gate contact hole 23 d is next formed on the polysilicon electrode 21 , as shown in FIG. 24 .
  • a titanium film is formed from the surface of the inter-layer dielectric film 22 .
  • the titanium film is formed so as to cover the inner surfaces of the anode contact hole 23 a , the cathode contact hole 23 b , the guard contact hole 23 c , the gate contact hole 23 d and the source contact hole 23 e.
  • an aluminum film is formed from the surface of the titanium film.
  • the aluminum film is formed so as to fill in the anode contact hole 23 a , the cathode contact hole 23 b , the guard contact hole 23 c , the gate contact hole 23 d and the source contact hole 23 e.
  • anode titanium electrode 27 a and anode wiring 28 a the cathode titanium electrode 27 b and cathode wiring 28 b , the guard titanium electrode 27 c and guard wiring 28 c , the gate titanium electrode 27 d and gate wiring 28 d , and the source titanium electrode 27 e and source wiring 28 e.
  • the drain wiring 28 f is formed on the drain ohmic electrode 26 f using a metal such as nickel or gold, with the configuration being shown in FIG. 25 .
  • the anode terminal 32 a , the cathode terminal 32 b , the guard terminal 32 c , the gate terminal 32 d , the source terminal 32 e and the drain terminal 32 f are finally formed, resulting in completion of the SiC semiconductor device 1 b as shown in FIG. 17 .
  • Embodiment 2 of the present invention The operation of the pn junction diode serving as the temperature sensor, formed in the SiC semiconductor device 1 b according to Embodiment 2 of the present invention will not be provided herein because of being the same as that in Embodiment 1 thereof.
  • an advantageous effect of the configuration described above is that the SiC semiconductor device 1 b can be provided that is equipped with the pn junction diode for measuring the temperature of the MOSFET.
  • the shallow well region 43 serving as the cathode region, and the deep well region 46 can be formed in the one and same process. Forming these regions in the same process allows reduction of the fabrication process of the SiC semiconductor device 1 b , thereby improving the productivity.
  • the anode region 48 , the guard region 17 and the well contact region 38 can be formed in one and the same process. Forming these regions in the same process allows reduction of a dedicated process for fabricating the pn junction diode section 42 of the SiC semiconductor device 1 b , thereby improving the productivity.
  • anode ohmic electrode 26 a , the cathode ohmic electrode 26 b , the guard ohmic electrode 26 c and the source ohmic electrode 26 e are formed in one and the same process. Forming these in one and the same process allows further reduction of the dedicated process for fabricating the pn junction diode section 42 of the SiC semiconductor device 1 b , thereby improving the productivity.
  • the control IC which includes the current source and the voltmeter, across the anode terminal 32 a and the cathode terminal 32 b , the temperature of MOSFET can easily be measured, thus detecting the over-temperature of MOSFET.
  • Embodiment 2 of the present invention the difference from Embodiment 1 thereof has been described, and descriptions of the same or the corresponding portions have not been provided.

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JP6048126B2 (ja) * 2012-12-25 2016-12-21 日産自動車株式会社 半導体装置及び半導体装置の製造方法
JP6252585B2 (ja) 2013-06-04 2017-12-27 富士電機株式会社 半導体装置
CN105308754B (zh) * 2013-12-12 2018-02-13 富士电机株式会社 半导体装置及其制造方法
WO2016039073A1 (ja) 2014-09-08 2016-03-17 富士電機株式会社 半導体装置および半導体装置の製造方法
CN114530376A (zh) * 2020-11-23 2022-05-24 瑶芯微电子科技(上海)有限公司 一种集成肖特基结构温度传感器的mosfet器件及其制备方法
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