US9076742B2 - Oxidation annealing device and method for fabricating thin film transistor using oxidation annealing - Google Patents

Oxidation annealing device and method for fabricating thin film transistor using oxidation annealing Download PDF

Info

Publication number
US9076742B2
US9076742B2 US13/883,027 US201113883027A US9076742B2 US 9076742 B2 US9076742 B2 US 9076742B2 US 201113883027 A US201113883027 A US 201113883027A US 9076742 B2 US9076742 B2 US 9076742B2
Authority
US
United States
Prior art keywords
oxygen
substrate
device body
gas
oxidation annealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US13/883,027
Other languages
English (en)
Other versions
US20130280925A1 (en
Inventor
Yoshifumi Ota
Masato Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Assigned to SHARP KABUSHIKI KAISHA reassignment SHARP KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HASHIMOTO, MASATO, OTA, YOSHIFUMI
Publication of US20130280925A1 publication Critical patent/US20130280925A1/en
Application granted granted Critical
Publication of US9076742B2 publication Critical patent/US9076742B2/en
Expired - Fee Related legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67098—Apparatus for thermal treatment
    • H01L21/67115—Apparatus for thermal treatment mainly by radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67178—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers vertical arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/6719—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the processing chambers, e.g. modular processing chambers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present disclosure relates to oxidation annealing devices and methods for fabricating a thin film transistor using oxidation annealing.
  • An active matrix substrate includes, e.g., thin film transistors (hereinafter also referred to as “TFTs”) as switching elements, one for each pixel, which is the smallest unit of an image.
  • TFTs thin film transistors
  • a typical bottom-gate TFT includes, for example: a gate electrode provided on an insulating substrate; a gate insulating film provided to cover the gate electrode; an island-like semiconductor layer provided on the gate insulating film to lie above the gate electrode; and a source electrode and a drain electrode provided on the semiconductor layer to face each other.
  • a TFT including a semiconductor layer of an oxide semiconductor that is an In—Ga—Zn—O (IGZO) oxide semiconductor with high mobility (hereinafter also referred to as an “oxide semiconductor layer”) as a switching element for each pixel, which is the smallest unit of an image.
  • IGZO In—Ga—Zn—O
  • process steps of a thermal oxidation annealing process from the placement of a substrate in a diffusion furnace to a heat treatment process have been conventionally known to be performed in atmospheric gas (nitrogen, oxygen, and water vapor) in the diffusion furnace.
  • the multistage glass substrate calcining furnace has a furnace body made of a heat insulator, and includes infrared radiation plates that are vertically arranged with an air gap formed on the inner wall of the furnace body, and between which a plane heater is sandwiched.
  • One of the infrared radiation plates has a gas feed hole, and the other infrared radiation plate has an exhaust hole.
  • the multistage glass substrate calcining furnace of PATENT DOCUMENT 2 cannot ensure its hermeticity, and thus, water vapor is distributed only immediately above a substrate, thereby making it difficult to disperse water vapor in the furnace. Furthermore, when a mica heater that is a constituent member of an infrared heater is in contact with a large amount of moisture, this leads to a leakage current.
  • Portions of a substrate corresponding to seams between adjacent ones of targets are formed by AC sputter deposition, and the use of IGZO causes the performance of TFTs corresponding to the portions to vary; thus, not the performance of TFTs on the entire substrate, but the performance of some of the TFTs needs to be locally improved.
  • an oxygen addition gas containing water vapor and oxygen is fed only to an oxygen-deficient portion of a substrate.
  • a nitrogen gas is blown to a portion of the substrate except the oxygen-deficient portion, i.e., an oxygen-excessive portion thereof, to reduce oxidation.
  • an oxidation annealing device of a first aspect of the disclosure includes: a device body formed in a shape of a closed container; a far-infrared plane heater placed in the device body; an oxygen addition gas feed pipe through which an oxygen addition gas containing water vapor and oxygen is fed into the device body; a gas exhaust pipe through which gas in the device body is discharged; and jet nozzles that are brought into communication with the oxygen addition gas feed pipe and through which the oxygen addition gas containing water vapor and oxygen is ejected to an oxygen-deficient portion of a substrate.
  • the oxygen addition gas containing water vapor and oxygen is ejected through the jet nozzles only to the oxygen-deficient portion of the substrate, this prevents the interior of the device body from being filled with a larger amount of water vapor than necessary, thereby reducing the leakage current from the far-infrared plane heater (electrical breakdown).
  • the oxygen gas containing water vapor is blown to the substrate to heat the substrate, this improves the oxidation efficiency to eliminate the need for maintaining the interior of the device body at a high temperature of about 450° C., and thus, the device body can be made of metal.
  • the oxygen addition gas needs to be brought into contact with only the oxygen-deficient portion, the interior of the device body does not need to be entirely and uniformly filled with the oxygen addition gas, and thus, high hermeticity is not required. This allows vapor oxidation annealing of a large substrate.
  • the oxidation annealing device of the first aspect of the disclosure may further include: a nitrogen gas feed pipe configured to fill a space in the device body with a nitrogen gas, and the oxygen addition gas may be ejected through the jet nozzles with the device body filled with the nitrogen gas.
  • the oxygen addition gas containing water vapor and oxygen is ejected through the jet nozzles only to the oxygen-deficient portion of the substrate, thereby accelerating oxidation.
  • the interior of the device body is filled with nitrogen, this reduces oxidation of a portion of the substrate that does not require oxygen, and prevents the interior of the device body from being filled with a larger amount of water vapor than necessary, thereby reducing the leakage current from the far-infrared plane heater (electrical breakdown).
  • the substrate may correspond to a thin film transistor, and the oxygen-deficient portion may be a portion of the substrate corresponding to a seam between targets and formed by AC sputtering.
  • the oxygen addition gas containing water vapor and oxygen is ejected to the portion corresponding to the target seam to locally improve the performance.
  • the seam may include a plurality of seams, and the jet nozzles may be arranged depending on the number of the seams.
  • the jet nozzles may be arranged depending on portions of the substrate corresponding to the target seams and needing to be oxidized, thereby simplifying the device.
  • An oxidation annealing device of a fifth aspect of the disclosure includes: a device body formed in a shape of a closed container; a far-infrared plane heater placed in the device body; a nitrogen gas feed pipe through which a nitrogen gas is fed into the device body; a gas exhaust pipe through which gas in the device body is discharged; and jet nozzles that are brought into communication with the nitrogen gas feed pipe and through which the nitrogen gas is ejected to an oxygen-excessive portion of a substrate.
  • the nitrogen gas serving to reduce oxidation is ejected through the jet nozzles only to the oxygen-excessive portion of the substrate to provide uniform oxidation of the entire substrate.
  • the interior of the device body is not filled with water vapor, thereby reducing the leakage current from the far-infrared plane heater (electrical breakdown).
  • the nitrogen gas needs to be brought into contact with only the oxygen-excessive portion, the interior of the device body does not need to be entirely and uniformly filled with the nitrogen gas, and thus, high hermeticity is not required. This allows vapor oxidation annealing of a large substrate.
  • the substrate may correspond to a thin film transistor, and the oxygen-excessive portion may be a portion of the substrate except a portion of the substrate corresponding to a seam between targets and formed by AC sputtering.
  • the nitrogen gas is ejected to the portion of the substrate except the portion corresponding to the target seam to reduce oxidation, and thus, performance variations can be generally improved.
  • the far-infrared plane heater may include a mica heater and a flat infrared radiation plate.
  • the far-infrared plane heater when the far-infrared plane heater is made of mica, this facilitates shaping the heater of a size large enough to accommodate a large substrate, and allows the speed of response of the heater to be high.
  • a method for fabricating a thin film transistor using oxidation annealing includes: while heating a substrate in a device body using a far-infrared plane heater, locally ejecting an oxygen addition gas containing water vapor and oxygen to an oxygen-deficient portion of the substrate.
  • the oxygen addition gas containing water vapor and oxygen is ejected through the jet nozzles only to the oxygen-deficient portion of the substrate, this prevents the interior of the device body from being filled with a larger amount of water vapor than necessary, thereby reducing the leakage current from the far-infrared plane heater (electrical breakdown).
  • the oxygen gas containing water vapor is blown to the substrate to heat the substrate, this improves the oxidation efficiency to eliminate the need for maintaining the interior of the device body at a high temperature of about 450° C., and thus, the device body can be made of metal.
  • the oxygen addition gas needs to be brought into contact with only the oxygen-deficient portion, the interior of the device body does not need to be entirely and uniformly filled with the oxygen addition gas, and thus, high hermeticity is not required. This allows vapor oxidation annealing of a large substrate.
  • a method for fabricating a thin film transistor using oxidation annealing includes: while heating a substrate using a far-infrared plane heater with a device body filled with a nitrogen gas, locally ejecting an oxygen addition gas containing water vapor and oxygen to an oxygen-deficient portion of the substrate.
  • a large substrate is efficiently heated in the device body using the far-infrared plane heater.
  • the oxygen addition gas containing water vapor and oxygen is ejected through the jet nozzles only to the oxygen-deficient portion of the substrate, thereby accelerating oxidation.
  • the interior of the device body is filled with nitrogen, this reduces oxidation of a portion of the substrate that does not require oxygen, and prevents the interior of the device body from being filled with a larger amount of water vapor than necessary, thereby reducing the leakage current from the far-infrared plane heater (electrical breakdown).
  • the oxygen gas containing water vapor is blown to the substrate to heat the substrate, this improves the oxidation efficiency to eliminate the need for maintaining the interior of the device body at a high temperature of about 450° C., and thus, the device body can be made of metal.
  • the oxygen addition gas needs to be brought into contact with only the oxygen-deficient portion, the interior of the device body does not need to be entirely and uniformly filled with the oxygen addition gas, and thus, high hermeticity is not required. This allows vapor oxidation annealing of a large substrate.
  • the method of the eighth or ninth aspect of the disclosure may further include: an AC sputtering process of, before the annealing process, applying an alternating voltage having one of polarities to one of a plurality of pairs of targets arranged in parallel, and applying an alternating voltage having the other polarity to another one of the pairs adjacent to the pair, and the oxygen-deficient portion may be a portion of the substrate corresponding to a seam between targets and formed by the AC sputtering process.
  • the oxygen addition gas containing water vapor and oxygen is ejected to the portion corresponding to the target seam to locally improve the performance.
  • a method for fabricating a thin film transistor using oxidation annealing may include: while heating a substrate in a device body using a far-infrared plane heater, locally ejecting a nitrogen gas to an oxygen-excessive portion of the substrate.
  • the nitrogen gas serving to reduce oxidation is ejected through the jet nozzles only to the oxygen-excessive portion of the substrate to provide uniform oxidation of the entire substrate.
  • the interior of the device body is not filled with water vapor, thereby reducing the leakage current from the far-infrared plane heater (electrical breakdown).
  • the nitrogen gas needs to be brought into contact with only the oxygen-excessive portion, the interior of the device body does not need to be entirely and uniformly filled with the nitrogen gas, and thus, high hermeticity is not required. This allows vapor oxidation annealing of a large substrate.
  • the method of the eleventh aspect of the disclosure may further include: an AC sputtering process of, before the annealing process, applying an alternating voltage having one of polarities to one of a plurality of pairs of targets arranged in parallel, and applying an alternating voltage having the other polarity to another one of the pairs adjacent to the pair, and the oxygen-excessive portion may be a portion of the substrate except a portion of the substrate corresponding to a seam between targets and formed by the AC sputtering process.
  • the nitrogen gas is ejected to the portion of the substrate except the portion corresponding to the target seam to reduce oxidation, and thus, performance variations can be generally improved.
  • an oxygen addition gas containing water vapor and oxygen is locally ejected only to an oxygen-deficient portion of the substrate. This allows oxidation annealing of a large substrate at high throughput and low cost while preventing the leakage current.
  • a nitrogen gas is locally ejected only to an oxygen-excessive portion of the substrate. This allows oxidation annealing of a large substrate at high throughput and low cost while preventing the leakage current.
  • FIG. 1 is a cutaway front view of an oxidation annealing device according to an embodiment.
  • FIG. 2 is a cutaway top view of the oxidation annealing device according to the embodiment.
  • FIG. 3 is a front view schematically illustrating a bubbler system.
  • FIG. 4 is a flow chart illustrating a method for fabricating a thin film transistor using oxidation annealing.
  • FIGS. 5A and 5B schematically illustrate an AC sputtering device, in which FIG. 5A is a plan view of the AC sputtering device, and FIG. 5B is a cross-sectional view taken along the line Vb-Vb.
  • FIG. 6 is a graph illustrating the substrate characteristics after AC sputtering.
  • FIG. 7 is a plan view illustrating the layout of regions of a substrate.
  • FIG. 8 is a graph illustrating the distribution of the threshold voltages of the regions.
  • FIG. 9 is a table illustrating, for comparison, the average of the threshold voltages of portions of a substrate corresponding to seams between adjacent ones of targets and the average of the threshold voltages of portions of the substrate except the portions corresponding to the target seams in each of the regions, and the average of the threshold voltages of the regions.
  • FIG. 10 is a diagram that corresponds to a first variation of the embodiment and is equivalent to FIG. 2 .
  • FIG. 11 is a diagram that corresponds to a second variation of the embodiment and is equivalent to FIG. 2 .
  • FIGS. 1 and 2 illustrate an oxidation annealing device 1 of the embodiment of the present disclosure
  • the oxidation annealing device 1 includes a device body 3 covered with a heat insulator 2 formed in the shape of a closed container.
  • the device body 3 is, for example, in the shape of a rectangular parallelepiped, and is vertically partitioned into four chambers 5 , for example.
  • Five far-infrared plane heaters 6 are arranged one above another, and are placed on inside top and inside bottom walls of the device body 3 and at the locations at which the device body 3 is partitioned, and other far-infrared plane heaters 6 are also placed on front, back, left, and right side walls of the device body 3 .
  • the chambers 5 are each surrounded by corresponding ones of the far-infrared plane heaters 6 .
  • the number of the chambers 5 in the device body 3 is not specifically limited, and may be one through three, or five or more.
  • An oxygen addition gas feed pipe 8 through which an oxygen addition gas containing water vapor and oxygen is fed is connected to the device body 3 , and a front end portion of the oxygen addition gas feed pipe 8 is divided into branches, and the branches each reach a corresponding one of the chambers 5 .
  • Substrate support pins 10 are placed in each of the chambers 5 so as to be able to support a target substrate 50 for annealing at a distance apart from the far-infrared plane heaters 6 .
  • the far-infrared plane heaters 6 each include a mica heater, and flat infrared radiation plates between which the mica heater is sandwiched. When the heater is made of mica, this facilitates shaping the heater of a size large enough to accommodate a large substrate, and allows the speed of response of the heater to be high.
  • Gas exhaust pipes 11 are also connected to the device body 3 to discharge gas in the device body 3 , and each communicate with a corresponding one of the chambers 5 to discharge gas in the chamber 5 .
  • the oxygen addition gas feed pipe 8 reaching the chambers 5 is connected to a bubbler system 12 .
  • the bubbler system 12 includes a hot water tank 14 including a heater 13 configured to be heated to about 90° C., and an oxygen gas is fed through, e.g., an unshown oxygen tank into an oxygen gas feed pipe 15 extending into the hot water tank 14 .
  • an oxygen gas is fed through, e.g., an unshown oxygen tank into an oxygen gas feed pipe 15 extending into the hot water tank 14 .
  • upper part of the hot water tank 14 is filled with oxygen fed into heated hot water 14 a and water vapor, and a wet oxygen gas containing water vapor is fed into the oxygen addition gas feed pipe 8 .
  • the oxygen addition gas feed pipe 8 reaching the chambers 5 includes jet nozzles 16 .
  • the jet nozzles 16 are configured to locally eject the oxygen addition gas containing water vapor and oxygen therethrough only to oxygen-deficient portions of the substrate 50 supported by the substrate support pins 10 , i.e., portions 51 thereof corresponding to seams between adjacent ones of targets (see FIGS. 5A and 5B ).
  • the process includes a method for fabricating a thin film transistor using oxidation annealing according to this embodiment.
  • step S 01 scanning lines are formed on an active matrix substrate 50 .
  • a titanium layer, an aluminum layer, and a titanium layer are sequentially deposited on the active matrix substrate 50 , and then, the layers are patterned by photolithography, wet etching, and resist removal and cleaning to form the scanning lines made of the three layers.
  • step S 02 an insulating film is formed.
  • An SiO 2 layer and an In—Ga—Zn—O (IGZO) layer are respectively formed as an insulating film and a channel layer, for example, by CVD.
  • IGZO In—Ga—Zn—O
  • step S 03 an oxide semiconductor layer is formed.
  • the oxide semiconductor layer is patterned, for example, by photolithography, wet etching, and resist removal and cleaning.
  • step S 04 signal lines and drain electrodes are formed.
  • a titanium film that is a lower film and an aluminum film that is an upper film are deposited, for example, by AC sputtering, and then, the films are patterned by photolithography, dry etching, and resist removal and cleaning to form the signal lines and the drain electrodes made of the aluminum/titanium multilayer film.
  • an AC sputtering device 60 will be briefly described. As illustrated in FIGS. 5A and 5B , in AC sputtering, alternating voltages 62 having different polarities are applied to pairs of targets 61 arranged in parallel, and sputtered atoms from the targets 61 are deposited on the substrate 50 opposed to the targets 61 to form a metal film.
  • the substrate 50 has portions 51 corresponding to target seams between adjacent ones of targets.
  • the quality of a portion of the film located on the portions 51 of the substrate corresponding to the target seams is different from that of a portion of the film located on the other portions of the substrate immediately above the targets 61 , and a function of the drain current Id and gate voltage Vg of the portions 51 corresponding to the target seams is significantly different from that of the other portions as illustrated in FIG. 6 .
  • Such a difference in performance deteriorates the substrate quality.
  • step S 05 a protective film is formed.
  • a SiO 2 film is deposited on the substrate 50 , for example, by CVD.
  • step S 06 annealing according to the present disclosure is performed. Specifically, the interior of a device body 3 is kept at 350° C., and a given amount of wet oxygen gas, e.g., 250 liters of wet oxygen gas per minute, is fed from a bubbler system 12 through an oxygen addition gas feed pipe 8 into chambers 5 . The wet oxygen gas fed into the chambers 5 is ejected through jet nozzles 16 to the portions 51 of the substrate 50 corresponding to the target seams. The substrate 50 is heated, for example, for one hour.
  • wet oxygen gas e.g. 250 liters of wet oxygen gas per minute
  • the portions 51 of the substrate 50 corresponding to the target seams and formed by AC sputtering deposition vary in performance, and are oxygen deficient; however, while the wet oxygen gas is ejected to the portions 51 corresponding to the target seams, the substrate 50 is heated, and thus, oxidation of the portions 51 corresponding to the target seams is accelerated to eliminate variations in performance and provide uniform performance.
  • the gas in the chambers 5 is discharged through gas exhaust pipes 11 , and thus, the internal pressures of the chambers 5 are not much higher than atmospheric pressure. Since oxidation can be performed at about 350° C., this eliminates the need for using quartz that has high heat resistance and is difficult to be machined into a large member, and thus, the device body 3 can be made of metal.
  • the interiors of the chambers 5 are not filled with a larger amount of wet oxygen gas than necessary, and thus, no leakage current arises from far-infrared plane heaters 6 .
  • step S 07 an interlayer insulating film is formed.
  • a photosensitive interlayer insulating film material is patterned by photolithography, and then, the protective film and the insulating film are patterned by dry etching.
  • step S 08 pixel electrodes are formed.
  • An ITO film is deposited, for example, by sputtering, and then, the ITO film is patterned by photolithography, wet etching, and resist removal and cleaning to form the pixel electrodes made of the ITO film.
  • step S 09 the substrate 50 and a color filter substrate fabricated through another process are bonded together to form panels.
  • polyimide is formed, as an alignment film, on each of the active matrix substrate 50 fabricated through the process steps and the counter substrate by printing.
  • a sealant is formed on each of the substrates by printing, liquid crystal material is dropped onto the substrate, and the substrates are then bonded together.
  • the bonded substrates are partitioned by dicing.
  • step S 04 two substrates 50 on which in step S 04 , the signal lines and the drain electrodes have been formed were prepared, and the substrates 50 were annealed under the following conditions.
  • the wet oxygen gas was ejected through the jet nozzles 16 to the substrate 50 , and the substrate 50 was heated for one hour.
  • FIGS. 8 and 9 illustrate results obtained by comparing the degrees of difference in threshold voltage Vth between the portions 51 of each of the two annealed substrates 50 corresponding to the target seams and portions of each of the substrates except the portions 51 among regions A-C illustrated in FIG. 7 .
  • FIG. 8 illustrates the distribution of the threshold voltages of the regions of each of the example and the comparative example.
  • FIG. 9 illustrates the average of the threshold voltages of the portions 51 corresponding to the target seams and the average of the threshold voltages of the portions except the portions 51 on each of the regions, and also illustrates the average of the threshold voltages of the portions 51 on the regions and the average of the threshold voltages of the portions except the portions 51 on the regions.
  • the experimental data showed that in the example, the range of variation in threshold voltage is smaller than that in the comparative example, and the difference in threshold voltage between the portions 51 corresponding to the target seams and the portions except the target seams is also smaller than that in the comparative example, resulting in the performance difference reduced.
  • a large substrate 50 can be also treated by oxidation annealing at high throughput and low cost, and a leakage current can be simultaneously prevented.
  • FIG. 10 illustrates an oxidation annealing device 101 according to a first variation of the embodiment of the present disclosure, and unlike the embodiment, the interior of a device body 3 is filled with a nitrogen gas.
  • the same reference characters are used to represent the same elements as those in FIGS. 1-9 , and the detailed explanation thereof is omitted.
  • a nitrogen gas feed pipe 108 configured to fill a space in a device body 3 with a nitrogen gas is added to the device of the embodiment.
  • a nitrogen gas source such as a nitrogen gas tank, is connected to the nitrogen gas feed pipe 108 .
  • a gas serving to reduce oxidation can be used.
  • an oxygen addition gas containing water vapor and oxygen is locally ejected into chambers 5 with the interiors of the chambers 5 filled with a nitrogen gas.
  • the oxygen addition gas containing water vapor and oxygen is ejected through jet nozzles 16 only to oxygen-deficient portions of a substrate 50 (portions 51 of the substrate 50 corresponding to target seams), thereby accelerating oxidation.
  • the interior of the device body 3 is filled with nitrogen, this reduces oxidation of a portion of the substrate 50 that does not require oxygen, and prevents the interior of the device body 3 from being filled with a larger amount of water vapor than necessary, thereby reducing the leakage current from far-infrared plane heaters 6 (electrical breakdown).
  • a large substrate 50 can be also treated by oxidation annealing at high throughput and low cost, and a leakage current can be simultaneously prevented.
  • FIG. 11 illustrates an oxidation annealing device 201 according to a second variation of the embodiment of the present disclosure, and unlike the embodiment, nitrogen is ejected to portions 51 of a substrate corresponding to target seams.
  • the oxygen addition gas feed pipe 8 of the embodiment is replaced with a nitrogen gas feed pipe 208 through which a nitrogen gas is fed into a device body 3 .
  • a nitrogen gas source such as a nitrogen gas tank
  • a reducing gas such as a hydrogen gas or a carbon monoxide gas
  • a method in which the interior of the device body 3 is heated under vacuum to reduce oxidation cannot be utilized, because the device becomes complicated.
  • Jet nozzles 216 are connected to the nitrogen gas feed pipe 208 to eject a nitrogen gas to oxygen-excessive portions of the substrate 50 (portions thereof except the portions 51 corresponding to the target seams).
  • this variation is different from the embodiment in terms of the locations at which the jet nozzles 216 are disposed or the directions in which the nitrogen gas is ejected through the jet nozzles 216 .
  • the jet nozzles 216 are directed to the portions except the portions 51 corresponding to the target seams.
  • the annealing device is used to locally eject a nitrogen gas to the portions of the substrate 50 except the portions 51 corresponding to the target seams while heating the substrate 50 in the device body 3 using the far-infrared plane heaters 6 .
  • a nitrogen gas serving to reduce oxidation is ejected through the jet nozzles 216 only to the oxygen-excessive portions of the substrate 50 to provide uniform oxidation of the entire substrate 50 .
  • the interior of the device body 3 is not filled with water vapor, thereby reducing the leakage current from the far-infrared plane heaters 6 (electrical breakdown).
  • the nitrogen gas needs to be brought into contact with only the oxygen-excessive portions, the interior of the device body 3 does not need to be entirely and uniformly filled with the nitrogen gas, and thus, high hermeticity is not required. This allows vapor oxidation annealing of a large substrate 50 .
  • a large substrate 50 can be also treated by oxidation annealing at high throughput and low cost, and a leakage current can be simultaneously prevented.
  • the embodiment of the present disclosure may be configured as follows.
  • annealing is performed after the formation of a protective film in step S 05
  • annealing may be performed after the formation of an oxide semiconductor layer in step S 03 .
  • the present disclosure is useful for oxidation annealing devices configured to heat and oxidize a substrate, and methods for fabricating a thin film transistor using oxidation annealing.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
US13/883,027 2010-11-05 2011-10-28 Oxidation annealing device and method for fabricating thin film transistor using oxidation annealing Expired - Fee Related US9076742B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010-248647 2010-11-05
JP2010248647 2010-11-05
PCT/JP2011/006065 WO2012060079A1 (ja) 2010-11-05 2011-10-28 酸化アニール処理装置及び酸化アニール処理を用いた薄膜トランジスタの製造方法

Publications (2)

Publication Number Publication Date
US20130280925A1 US20130280925A1 (en) 2013-10-24
US9076742B2 true US9076742B2 (en) 2015-07-07

Family

ID=46024207

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/883,027 Expired - Fee Related US9076742B2 (en) 2010-11-05 2011-10-28 Oxidation annealing device and method for fabricating thin film transistor using oxidation annealing

Country Status (6)

Country Link
US (1) US9076742B2 (de)
EP (1) EP2637201A4 (de)
JP (1) JP5372264B2 (de)
KR (1) KR101609429B1 (de)
CN (1) CN103201828B (de)
WO (1) WO2012060079A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140363916A1 (en) * 2012-02-16 2014-12-11 Saint-Gobain Glass France Process box, arrangements and methods for processing coated substrates

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103855054B (zh) * 2012-11-30 2018-08-17 盛美半导体设备（上海）有限公司 工艺腔室
CN103632983B (zh) * 2013-11-22 2017-11-21 上海申和热磁电子有限公司 用于铜片预氧化的陶瓷支架
EP3153595B1 (de) * 2014-06-06 2020-04-29 Nippon Steel & Sumikin Texeng. Co., Ltd. Mehrstufiger ferninfrarotstrahlungsheizofen für stahlbleche zum heisspressen
TW201639063A (zh) * 2015-01-22 2016-11-01 應用材料股份有限公司 批量加熱和冷卻腔室或負載鎖定裝置
CN108022863B (zh) * 2017-11-30 2020-07-28 上海大学 一种水蒸气氧化退火系统
CN108611483A (zh) * 2018-04-24 2018-10-02 广州才是科技有限公司 一种远红外线能量源设备及制作抗菌抑菌不锈钢材料的方法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06267840A (ja) 1993-03-11 1994-09-22 Dainippon Screen Mfg Co Ltd 熱処理装置
JP3066387U (ja) 1999-08-05 2000-02-18 昭和鉄工株式会社 多段型ガラス基板焼成炉
US20060223328A1 (en) 2005-04-01 2006-10-05 Seiko Epson Corporation Apparatus and method for manufacturing semiconductor device, and electronic apparatus
US20070190744A1 (en) * 2002-10-31 2007-08-16 Atsushi Hiraiwa Method for fabricating semiconductor devices
JP2009128837A (ja) 2007-11-28 2009-06-11 Kyoshin Engineering:Kk 高圧アニール水蒸気処理装置
CN101681817A (zh) 2007-05-25 2010-03-24 国立大学法人东北大学 化合物系薄膜及其形成方法、以及使用该薄膜的电子装置
US20100107977A1 (en) * 2001-02-09 2010-05-06 Tokyo Electron Limited Film forming apparatus
US20110008930A1 (en) * 2009-06-30 2011-01-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20110068334A1 (en) * 2009-09-24 2011-03-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2701709B2 (ja) * 1993-02-16 1998-01-21 株式会社デンソー ２つの材料の直接接合方法及び材料直接接合装置
US5827918A (en) 1996-06-28 1998-10-27 Tektronix, Inc. Phase change ink formulation using urea and urethane isocyanate-derived resins
JP4286981B2 (ja) * 1999-07-22 2009-07-01 東京エレクトロン株式会社 枚葉式熱処理装置
JP4357786B2 (ja) * 2001-03-16 2009-11-04 株式会社半導体エネルギー研究所 熱処理装置及び熱処理方法
JP3929939B2 (ja) * 2003-06-25 2007-06-13 株式会社東芝 処理装置、製造装置、処理方法及び電子装置の製造方法
JP5053537B2 (ja) * 2004-11-10 2012-10-17 キヤノン株式会社 非晶質酸化物を利用した半導体デバイス
US20070065593A1 (en) * 2005-09-21 2007-03-22 Cory Wajda Multi-source method and system for forming an oxide layer
JP4362834B2 (ja) * 2006-10-11 2009-11-11 セイコーエプソン株式会社 半導体装置の製造方法、電子機器の製造方法および半導体製造装置
JP2008098375A (ja) * 2006-10-11 2008-04-24 Seiko Epson Corp 半導体装置の製造方法、電子機器の製造方法および半導体製造装置
JP5084236B2 (ja) * 2006-11-30 2012-11-28 東京エレクトロン株式会社 デバイス製造装置およびデバイス製造方法
JP2009038230A (ja) * 2007-08-02 2009-02-19 Ushio Inc 光照射式加熱処理装置
JP2010238770A (ja) * 2009-03-30 2010-10-21 Nippon Mining & Metals Co Ltd 酸化物薄膜及びその製造方法
JP5525380B2 (ja) * 2010-08-25 2014-06-18 富士フイルム株式会社 酸化物半導体薄膜の製造方法および薄膜トランジスタの製造方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06267840A (ja) 1993-03-11 1994-09-22 Dainippon Screen Mfg Co Ltd 熱処理装置
JP3066387U (ja) 1999-08-05 2000-02-18 昭和鉄工株式会社 多段型ガラス基板焼成炉
US20100107977A1 (en) * 2001-02-09 2010-05-06 Tokyo Electron Limited Film forming apparatus
US20070190744A1 (en) * 2002-10-31 2007-08-16 Atsushi Hiraiwa Method for fabricating semiconductor devices
US20060223328A1 (en) 2005-04-01 2006-10-05 Seiko Epson Corporation Apparatus and method for manufacturing semiconductor device, and electronic apparatus
CN1881545A (zh) 2005-04-01 2006-12-20 精工爱普生株式会社 半导体装置的制造方法、制造装置和电子设备
CN101681817A (zh) 2007-05-25 2010-03-24 国立大学法人东北大学 化合物系薄膜及其形成方法、以及使用该薄膜的电子装置
US20100139762A1 (en) 2007-05-25 2010-06-10 National University Corp Tohoku University Compound-type thin film, method of forming the same, and electronic device using the same
JP2009128837A (ja) 2007-11-28 2009-06-11 Kyoshin Engineering:Kk 高圧アニール水蒸気処理装置
US20110008930A1 (en) * 2009-06-30 2011-01-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20110068334A1 (en) * 2009-09-24 2011-03-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Official Communication issued in International Patent Application No. PCT/JP2011/006065, mailed on Dec. 6, 2011.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140363916A1 (en) * 2012-02-16 2014-12-11 Saint-Gobain Glass France Process box, arrangements and methods for processing coated substrates
US9799543B2 (en) * 2012-02-16 2017-10-24 Saint-Gobain Glass France Process box, arrangements and methods for processing coated substrates

Also Published As

Publication number Publication date
US20130280925A1 (en) 2013-10-24
EP2637201A4 (de) 2014-03-26
KR101609429B1 (ko) 2016-04-05
EP2637201A1 (de) 2013-09-11
CN103201828A (zh) 2013-07-10
CN103201828B (zh) 2016-06-29
JPWO2012060079A1 (ja) 2014-05-12
WO2012060079A1 (ja) 2012-05-10
KR20130100178A (ko) 2013-09-09
JP5372264B2 (ja) 2013-12-18

Similar Documents

Publication Publication Date Title
US9076742B2 (en) Oxidation annealing device and method for fabricating thin film transistor using oxidation annealing
JP5399274B2 (ja) 薄膜トランジスタ及びその製造方法、並びに薄膜トランジスタを備える平板表示装置
TWI437642B (zh) 半導體裝置的製造方法
TWI514478B (zh) 場效型電晶體之製造方法及製造裝置
US10381454B2 (en) Interface engineering for high capacitance capacitor for liquid crystal display
CN105070724A (zh) Tft基板的制作方法及制得的tft基板
JP6760439B2 (ja) 薄膜トランジスターの製造方法及び記憶媒体
CN104916568A (zh) 等离子体处理装置、基板处理系统和薄膜晶体管的制造方法
JP2005322845A (ja) 半導体デバイスと、その製造装置、および製造方法
US12080725B2 (en) Hybrid high-K dielectric material film stacks comprising zirconium oxide utilized in display devices
CN101263604B (zh) 薄膜晶体管
US20130026462A1 (en) Method for manufacturing thin film transistor and thin film transistor manufactured by the same, and active matrix substrate
US20100075506A1 (en) Apparatus and method for manufacturing semiconductor element and semiconductor element manufactured by the method
CN105940143A (zh) 用于消除遮蔽框架的气体限制器组件
CN106024828B (zh) 显示设备以及制造显示设备的设备和方法
US20140273342A1 (en) Vth control method of multiple active layer metal oxide semiconductor tft
CN101300681B (zh) 半导体装置及其制造方法
JP2007188953A (ja) 多結晶シリコン層の製造方法
JP3708940B2 (ja) Ｃｖｄ装置の反応室のコーティング方法
JP6703186B2 (ja) 薄膜トランジスタ及びその製造方法
KR20120084107A (ko) 산화물 반도체 박막 트랜지스터의 제조방법 및 반도체 설비 장치

Legal Events

Date Code Title Description
AS Assignment

Owner name: SHARP KABUSHIKI KAISHA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OTA, YOSHIFUMI;HASHIMOTO, MASATO;SIGNING DATES FROM 20130416 TO 20130703;REEL/FRAME:030764/0459

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20230707