US9064929B2 - Method for reducing the thickness of an SOI layer - Google Patents

Method for reducing the thickness of an SOI layer Download PDF

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US9064929B2
US9064929B2 US12/153,519 US15351908A US9064929B2 US 9064929 B2 US9064929 B2 US 9064929B2 US 15351908 A US15351908 A US 15351908A US 9064929 B2 US9064929 B2 US 9064929B2
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wafer
etching
soi
stage
soi layer
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US20080299742A1 (en
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Shoji Akiyama
Yoshihiro Kubota
Atsuo Ito
Koichi Tanaka
Makoto Kawai
Yuuji Tobisaka
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Shin Etsu Chemical Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Definitions

  • the present invention relates to a method for manufacturing an SOI wafer, and more particularly to a method for manufacturing an SOI wafer for bonding two wafers to form a thin-film SOI layer by delamination and then further reducing a film thickness of the SOI layer.
  • a silicon-on-insulator (SOI) wafer having a single-crystal silicon layer formed on an insulator has been widely utilized.
  • SOI silicon-on-insulator
  • a demand for a thin-film SOI having an SOI layer (a single-crystal silicon layer on an insulator) of 100 nm or below has been increased to fabricate a complete depletion layer type SOI device. That is because an increase in speed of the device by reducing a film thickness of the SOI layer can be expected.
  • a hydrogen ion is implanted into a single-crystal silicon wafer or a single-crystal silicon wafer having an oxide film formed on a surface thereof (a donor wafer), this wafer is bonded to a support wafer (a handle wafer) and then heated to a temperature close to 500° C., the donor wafer is delaminated along a hydrogen ion implanted interface, a single-crystal silicon thin film is transferred to the handle wafer, and a heat treatment is subsequently performed at a high temperature (approximately 1100 to 1200° C.) by a method for polishing the surface roughened due to a heat treatment to provide a mirror surface or by using an inert gas such as argon or an inert gas having hydrogen added thereto, thereby smoothening the surface (
  • CMP chemical mechanical polishing
  • the method called an SiGen method for bonding two wafers and then mechanically performing delamination at a room temperature also has the same problem as that of the Smartcut method and others, and an SOI layer after delamination must be polished for approximately 0.1 ⁇ m to be removed.
  • a method for fabricating a thin-film SOI layer there has been proposed, e.g., a PACE (Plasma Assisted Chemical Etching) method (see, e.g., Japanese Patent Application Laid-open No. H5-160074) for previously measuring a film thickness of an SOI layer after delamination and scraping the thin film while applying correction in accordance with a film thickness distribution thereof to fabricate a uniform thin-film silicon layer or a GCIB (Gas Cluster Ion Beam) method (see, e.g., Japanese Patent Application Laid-open No. H8-293483).
  • PACE Plasma Assisted Chemical Etching
  • GCIB Gas Cluster Ion Beam
  • both the methods can meet an object of obtaining an SOI layer having high film thickness uniformity since etching can be performed while correcting a film thickness fluctuation by scanning an entire wafer surface with a plasma or an ion beam having a diameter of several mm to several cm.
  • a method for manufacturing an SOI wafer comprising at least: a step of preparing a handle wafer and a donor wafer formed of a silicon substrate; an ion implantation step of implanting at least one of a hydrogen ion and a rare gas ion into the donor wafer to form an ion implanted layer; a bonding step of bonding an ion implanted surface of the donor wafer to a bonding surface of the handle wafer; a delamination step of delaminating the donor wafer at the ion implanted layer to reduce a film thickness of the donor wafer, thereby providing an SOI layer; and an etching step of etching the SOI layer to reduce a thickness of the SOI layer, wherein the etching step includes: a stage of performing rough etching as wet etching; a stage of measuring a film thickness distribution of the SOI layer after the rough etching; and a stage of performing precise etch
  • etching can be carried out at a relatively high etching rate on the rough etching stage, and film thickness uniformity of the SOI layer can be increased on the precise etching stage.
  • an etching removal on the precise etching stage can be set smaller than an etching removal on the rough etching stage.
  • the SOI wafer having the SOI layer with high film thickness uniformity can be further efficiently manufactured.
  • an etching technique on the precise etching stage can be a PACE method or a GCIB method.
  • the etching technique on the precise etching stage is the PACE method or the GCIB method in this manner, a highly flat surface of the SOI layer can be obtained.
  • a silicon substrate as the donor wafer can be a single-crystal silicon wafer or a single-crystal silicon wafer having a silicon oxide film formed on a surface thereof.
  • the silicon substrate that is the donor wafer a single-crystal silicon wafer or a single-crystal silicon wafer having a silicon oxide film formed on a surface thereof can be used.
  • the handle wafer is any one of a single-crystal silicon wafer, a single-crystal silicon wafer having a silicon oxide film formed on a surface thereof, a quartz wafer, a glass wafer, an alumina (sapphire) wafer, a SIC wafer, and an aluminum nitride wafer.
  • the handle wafer used in the present invention can be appropriately selected from these wafers in accordance with an object of a semiconductor device to be fabricated.
  • the wet etching can be performed by using an etchant containing at least one of KOH, NH 4 OH, a mixed solution of NH 4 OH+H 2 O 2 , NaOH, CsOH, EDP (ethylenediamine-pyrocatechol), TMAH (tetramethylammonium hydroxide), and hydrazine.
  • an etchant containing at least one of KOH, NH 4 OH, a mixed solution of NH 4 OH+H 2 O 2 , NaOH, CsOH, EDP (ethylenediamine-pyrocatechol), TMAH (tetramethylammonium hydroxide), and hydrazine.
  • the etchant used in the wet etching according to the present invention can be appropriately selected from these materials.
  • the dry etching can be performed by using a gas containing at least one of SF 6 , NF 3 , CF 4 , CHF 3 , HBr, Cl 2 , O 2 , and H 2 .
  • the etching gas used in the dry etching according to the present invention can be appropriately selected from these materials.
  • etching can be performed at a relatively high etching rate on the rough etching stage, and film thickness uniformity of the SOI layer can be increased on the precise etching stage.
  • a high polishing rate and high film thickness uniformity can be obtained at the entire etching step for the SOI layer, the SOI wafer having the SOI layer with a small film thickness of, e.g., 100 nm or below and high film thickness uniformity can be manufactured with excellent productivity.
  • FIG. 1 is a flow diagram showing an example of an etching step in a method for manufacturing an SOI wafer according to the present invention.
  • FIG. 2 is a flow diagram showing an example of a method for manufacturing an SOI wafer to which the method for manufacturing an SOI wafer according to the present invention is applied.
  • the PACE method or the GCIB method is suitable for an object of etching a silicon thin film having an uneven film thickness while correcting film thickness uniformity.
  • they have considered a method for immersing an SOI wafer obtained after delaminating a donor wafer in an etchant, etching an SOI layer to some extent based on wet etching, and then etching the SOI layer while correcting film thickness uniformity based on dry etching, e.g., the PACE method or the GCIB method.
  • the present inventors have conceived that adopting this method enables correcting film thickness uniformity based on subsequent dry etching even if film thickness uniformity is degraded due to wet etching that is hard to uniformly maintain a film thickness and a total time required for an etching step can be shortened because an etching time of dry etching can be reduced without problem, thereby bringing the present invention to completion.
  • FIG. 2 shows an example of a method for manufacturing an SOI wafer to which the present invention can be applied.
  • a donor wafer 10 formed of a silicon substrate and a handle wafer 20 are prepared (Step 1 ).
  • the donor wafer 10 is not restricted in particular as long as it is a silicon substrate that can eventually serve as an SOI layer (a single-crystal silicon layer), a single-crystal silicon wafer (a single-crystal silicon wafer formed of single-crystal silicon alone) or a single-crystal silicon wafer having an oxide film formed on a surface thereof can be used, for example.
  • a single-crystal silicon wafer having a silicon nitride or a silicon oxynitride formed on a surface thereof can be used, for example.
  • any one of a single-crystal silicon wafer, a single-crystal silicon wafer having a silicon oxide film formed on a surface thereof, a quartz wafer, a glass wafer, an alumina (sapphire) wafer, a SIC wafer, and an aluminum nitride wafer can be used, for example.
  • the handle wafer 20 can be appropriately selected from these wafers in accordance with an object of a semiconductor device to be fabricated. Of course, any other material can be also used.
  • a combination of the donor wafer 10 and the handle wafer 20 must be a combination that enables eventually forming an SOI structure (a structure where an SOI layer is formed on an insulator) based on bonding.
  • FIG. 2 ( 1 ) shows an example of using a single-crystal silicon wafer as the donor wafer 10 and a single-crystal silicon wafer having a silicon oxide film 20 b formed on a surface of single-crystal silicon 20 a (a single-crystal silicon wafer having an oxide film) as the handle wafer 20 .
  • a hydrogen ion is implanted into the donor wafer 10 from a surface (an ion implanted surface) 12 thereof to form an ion implanted layer 11 (Step 2 ).
  • a rare gas ion or both the hydrogen ion and the rare gate ion may be implanted.
  • Other ion implantation conditions e.g., an injection energy, an injection dose, an injection temperature, and others can be appropriately selected so as to obtain a thin film having a predetermined thickness.
  • a temperature of the wafer at the time of injection is set to 250 to 350° C.
  • an ion implantation depth is set to 0.5 ⁇ m
  • an injection energy is set to 20 to 100 keV
  • an injection dose is set to 1 ⁇ 10 16 to 1 ⁇ 10 7 /cm 2 , but the present invention is not restricted thereto.
  • the ion implanted surface 12 of the donor wafer 10 is bonded to a bonding surface 22 of the handle wafer 20 (Step 3 ).
  • the wafers can be bonded to each other without using, e.g., an adhesive.
  • pressing the donor wafer 10 and the handle wafer 20 against each other at a room temperature at this bonding step can suffice.
  • delaminating the donor wafer 10 at the ion implanted layer 11 enables reducing a film thickness of the donor wafer 10 , thereby providing an SOI layer 31 (Step 4 ).
  • the donor wafer 10 can be delaminated at the ion implanted layer 11 based on rearrangement of a crystal and agglomeration of air bubbles.
  • this bonding heat treatment for increasing a bonding power of the donor wafer 10 and the handle wafer 20 is carried out.
  • this bonding heat treatment can be effected in an inert gas atmosphere or a slightly oxidizing gas atmosphere at 1000° C. to 1250° C. in the range of 30 minutes to 4 hours.
  • delamination heat treatment and the bonding heat treatment can be simultaneously performed.
  • the SOI layer 31 is etched to reduce a thickness of the SOI layer 31 (Step 5 ). Further, the present invention is characterized in that this etching step is performed through the following respective stages.
  • FIG. 1 is a flow diagram showing each stage effected during the etching step (FIG. 2 ( 5 )) in the method for manufacturing an SOI wafer according to the present invention.
  • the SOI layer 31 consisting of single-crystal silicon is formed on the handle wafer 20 . Furthermore, an ion implantation damage layer 31 a is formed near a surface of the SOI layer 31 (a region close to the ion implanted layer). A thickness of the ion implantation damage layer 31 a is usually approximately 0.1 to 0.12 ⁇ m. An object of etching the SOI layer 31 to reduce a thickness thereof is obtaining the thin SOI layer 31 as well as removing this ion implantation damage layer 31 a.
  • the SOI wafer 30 is put into a wet etching device, and the SOI layer 31 is subjected to rough etching based on wet etching (Stage b).
  • An etchant in wet etching is not restricted in particular as long as a certain degree of film thickness uniformity can be obtained, and a usually utilized etchant can be used.
  • a usually utilized etchant can be used.
  • an etching removal on this rough etching stage can be controlled based on an etching rate determined by a type of an etchant or an etching temperature, a time for performing etching, and others.
  • a film thickness of the SOI layer 31 can be reduced at a relatively high etching rate.
  • the film thickness distribution of the SOI layer 31 after rough etching is measured (Stage c).
  • the film thickness distribution can be highly accurately measured based on, e.g., an optical interference method or an electrostatic capacitance method.
  • the next precise etching stage using dry etching is carried out based on data of the thus measured film thickness distribution.
  • the SOI wafer 30 is put into a dry etching device, and precise etching using dry etching is carried out based on the film thickness distribution of the SOI layer measured on Stage c (Stage d).
  • An etching technique on this precise etching stage is a technique that can precisely correct film thickness uniformity, e.g., a PACE method or a GCIB method.
  • the PACE method is a method for uniforming a thickness of a wafer (a film thickness of the SOI layer) while locally etching the surface of the wafer by using a plasma gas, and the wafer surface can have a high flatness degree by measuring a thickness distribution of the wafer based on the optical interference method or the electrostatic capacitance method and then controlling an amount of etching removal using the plasma gas in accordance with this thickness distribution.
  • the GCIB method is a method for forming a massive atom cluster of a gaseous material (a gas cluster) at an ordinary temperature and an ordinary pressure, using an accelerating voltage to accelerate a gas cluster ion generated by applying electrons to this massive atom cluster, and irradiating the wafer surface with this accelerated ion.
  • the wafer surface can have a high flatness degree by measuring a thickness distribution of the wafer based on, e.g., the optical interference method or the electrostatic capacitance method and then controlling an amount of etching removal using the gas cluster ion in accordance with this thickness distribution.
  • an etching gas used on the precise etching stage based on dry etching is not restricted in particular, but both the PACE method and the GCIB method can be carried out by using a gas containing at least one of SF 6 , NF 3 , CF 4 , CHF 3 , HBr, Cl 2 , O 2 , and H 2 .
  • an etching removal on this precise etching stage can be controlled based on a type of the etching gas, a concentration of the etching gas, a pressure, and others or a time for performing etching.
  • a lower limit that enables sufficiently correcting film thickness uniformity of the SOI layer 31 can suffice, and it can be set to, e.g., 10 nm or above, though this value varies depending on a degree of film thickness uniformity of the SOI layer after end of the rough etching stage.
  • lowering an upper limit as much as possible is preferable in order to improve productivity of the entire etching step, and it can be set to, e.g., 100 nm or below, though this value likewise varies depending on a degree of film thickness uniformity of the SOI layer after end of the rough etching stage.
  • film thickness uniformity of the SOI layer 31 is improved as compared with that obtained after end of the rough etching stage.
  • sequentially carrying out the rough etching stage and the precise etching stage enables performing etching at a relatively high etching rate on the rough etching stage and increasing film thickness uniformity of the SOI layer 31 on the precise etching stage.
  • a high polishing rate and high film thickness uniformity can be obtained at the entire etching step for the SOI layer, and hence the SOI wafer 30 having the SOI layer 31 with high film thickness uniformity can be manufactured with excellent productivity (with a high throughput).
  • an etching removal on each of the rough etching stage as Stage b and the precise etching stage as Stage d can be appropriately optimized based on a total time required for the etching step, film thickness uniformity of the finally obtained SOI layer, and others.
  • the etching removal on the precise etching stage is set smaller than the etching removal on the rough etching stage, the SOI wafer having the SOI layer with high film thickness uniformity can be further efficiently manufactured, which is preferable.
  • the etching removal-based on rough etching can be set to 120 nm corresponding to 80% of the total etching removal, and the etching removal based on precise etching can be set to 30 nm corresponding to 20% of the total etching removal.
  • the SOI wafer 30 in which a film thickness of the SOI layer 31 is as very thin as, e.g., 100 nm or below and the SOI layer 31 has high film thickness uniformity can be manufactured with excellent productivity.
  • a film thickness of approximately 2 ⁇ m or below can be previously given to the SOI layer after end of the delamination step and before the etching step.
  • the etching removal at the etching step can be set to a minimum value. Therefore, a time required for the etching step is short, thus increasing productivity.
  • the donor wafer 10 may be delaminated by applying a mechanical external force. Such an example will now be explained hereinafter.
  • Step 2 After end of the ion implantation step (Step 2 ), a surface activation treatment is performed with respect to the ion implanted surface 12 of the donor wafer 10 and the bonding surface 22 of the handle wafer 20 .
  • the surface activation treatment may be performed with respect to one of the ion implanted surface 12 of the donor wafer 10 and the bonding surface 22 of the handle waver 20 .
  • the surface activation treatment based on at least one of a plasma treatment and an ozone treatment.
  • the surface activation treatment is carried out based on at least one of the plasma treatment and the ozone treatment, the surface subjected to the surface activation treatment is activated. For example, OH groups of this surface are increased. Therefore, when the ion implanted surface 12 of the donor wafer is pressed against the bonding surface 22 of the handle wafer in this state, the wafers can be more firmly bonded to each other based on, e.g., hydrogen bonding.
  • a plasma gas is introduced, and then the wafer is exposed to a high-frequency plasma of approximately 100 W for approximately 5 to 30 seconds to perform a plasma treatment with respect to a surface thereof.
  • the plasma gas it is possible to use a plasma of an oxygen gas when processing a single-crystal silicon wafer having an oxide film formed on a surface thereof, or a hydrogen gas, an argon gas, a mixed gas of these gases, or a mixed gas of the hydrogen gas and a helium gas when processing a single-crystal silicon wafer having no oxide film formed on a surface thereof.
  • a nitrogen gas as an inert gas may be used.
  • a wafer subjected to cleaning e.g., RCA cleaning is set in a chamber having atmospheric air introduced therein, a plasma gas, e.g., a nitrogen gas or an argon gas is introduced, a high-frequency plasma is produced, and oxygen in the atmospheric air is converted into an ozone, thereby performing the ozone treatment with respect to a surface of the wafer.
  • a plasma gas e.g., a nitrogen gas or an argon gas
  • Step 3 the ion implanted surface 12 of the donor wafer is pressed against the bonding surface 22 of the handle wafer.
  • both the wafers can be sufficiently firmly bonded to each other so that they can resist subsequent mechanical delamination even if a high-temperature treatment is not performed.
  • a heat treatment step for performing a heat treatment with respect to the appressed wafers at 100 to 400° C. may be effected after the step of pressing the donor wafer and the handle wafer against each other.
  • bonding strength of the donor wafer and the handle wafer can be increased.
  • a heat treatment temperature is 100 to 300° C.
  • a possibility of occurrence of thermal damages, cracks, delamination, and others due to a difference between thermal expansion coefficients is low even if different material types of wafers are bonded to each other.
  • Increasing the bonding strength enables reducing occurrence of failures at the delamination step.
  • Step 4 a mechanical external force is applied to the bonded wafers to delaminate the donor wafer 10 , and a film thickness of the donor wafer 10 is reduced to provide the SOI layer 31 (Step 4 ).
  • the donor wafer 10 and a back surface of the handle wafer 20 are held by holding jigs, an external impact shock is given to a position near the ion implanted layer 11 by, e.g., a wedge-shaped member or a high-pressure fluid such as air, a nitrogen gas, or pure water to start delamination of the donor wafer 10 while applying a force that can separate both the holding jigs from each other, and both the holding jigs are relatively separated from each other. Consequently, the donor wafer 10 is gradually separated from the handle wafer 20 at the ion implanted layer 11 from one end portion to which the external impact shock has been given toward the other end portion, thereby delaminating the donor wafer 10 .
  • a wedge-shaped member or a high-pressure fluid such as air, a nitrogen gas, or pure water
  • the etching step (Step 5 ) is effected by sequentially performing wet etching and dry etching like the example where delamination is performed based on the heat treatment.
  • An SOI wafer was manufactured by a method of performing delamination of a donor wafer based on a heat treatment as follows in accordance with the method for manufacturing an SOI wafer of the present invention depicted in FIGS. 2 and 1 .
  • Step 1 a mirror-polished single-crystal silicon wafer having a diameter of 200 nm was prepared as a donor wafer 10 . Further, a silicon oxide film layer having a thickness of 100 nm was formed on a surface of the donor wafer by thermal oxidation.
  • a single-crystal silicon wafer having a diameter of 200 mm was prepared as a handle wafer 20 .
  • a silicon oxide film 20 b having a thickness of 1 ⁇ m was formed on a surface of the handle wafer by thermal oxidation.
  • a hydrogen ion was implanted into the donor wafer 10 through the silicon oxide film layer formed thereon, thereby forming a micro bubble layer (an ion implanted layer) 11 at an average progress depth of the ion in parallel with the surface (Step 2 ).
  • an implantation energy is 35 keV
  • an implantation dose is 9 ⁇ 10 16 /cm 2
  • an implantation depth is 0.3 ⁇ m.
  • Step 3 an ion implanted surface 12 of the donor wafer 10 was brought into contact with and bonded to the handle wafer 20 through the silicon oxide film 20 b in a clean atmosphere at an ordinary temperature (Step 3 ).
  • Step 4 a heat treatment was applied in an Ar gas atmosphere at 500° C. for 30 minutes to delaminate the donor wafer 10 at the ion implanted layer 11 (Step 4 ). That is, a delamination step was carried out based on the heat treatment.
  • a bonding heat treatment was effected in an Ar gas atmosphere containing 1% of oxygen at 1000° C. to 1250° C. for 1 hour, thereby increasing a bonding power of the donor wafer 10 and the handle wafer 20 .
  • Step 5 an etching step as Step 5 was carried out through the following stages.
  • a rough etching stage based on wet etching using a KOH liquid solution was carried out to etch an SOI layer 31 for approximately 120 nm (a stage a).
  • the SOI layer was etched for approximately 150 nm in total.
  • a delamination step as Step 4 was carried out in the form of delamination based on a heat treatment, but a dry etching step as Stage c in an etching step as Step 5 was performed by using a GCIB method, thereby manufacturing an SOI wafer.
  • an ion implanted donor wafer 10 was put in a plasma treatment device, nitrogen was introduced as a plasma gas, and then a high frequency of 13.56 MHz was applied to a space between parallel plate electrodes each having a diameter of 300 mm under conditions of a reduced pressure of 2 Torr (270 Pa) and a high-frequency power of 50 W, thereby effecting a high-frequency plasma treatment to an ion implanted surface for 10 seconds.
  • the ion implanted surface of the donor wafer 10 was subjected to a surface activation treatment.
  • a handle wafer 20 was put in a plasma treatment device, a nitrogen gas as a plasma gas was introduced into a space between narrow electrodes, and then a high frequency was applied to the space between the electrodes to generate a plasma, thereby performing a high-frequency plasma treatment for 10 seconds. In this manner, a bonding surface of the handle wafer 20 was also subjected to a surface activation treatment.
  • a wafer in which the donor wafer 10 is appressed against the handle wafer 20 was subjected to a heat treatment at 300° C. for 30 minutes in order to increase bonding strength.
  • the donor wafer 10 and the back surface of the handle wafer 20 were held by holding jigs, an external impact shock was given to a position near the ion implanted layer 11 by a gas fluid to start delamination of the donor wafer 10 while applying a force that can separate both the holding jigs from each other, and both the holding jigs were relatively separated from each other. Consequently, the donor wafer 10 was gradually separated from the handle wafer 20 at the ion implanted layer 11 from one end portion having the external impact shock given thereto toward the other end portion, thereby delaminating the donor wafer 10 by the mechanical external force (Step 4 ).
  • an etching step as Step 5 was carried out by effecting a wet etching stage, then measuring a film thickness distribution of an SOI layer, and carrying out a dry etching step based on the PACE method like Example 1.
  • a delamination step as Step 4 was performed in the form of delamination using a mechanical external force like Example 3, but a dry etching step as Stage c in an etching step as Step 5 was performed by using a GCIB method, thereby manufacturing an SOI wafer.
  • a delamination step as Step 4 was carried out in the form of delamination using a heat treatment like Example 1, but an etching step as Step 5 was carried out based on a wet etching stage alone using a KOH liquid solution without adopting such a stage as depicted in FIG. 1 , thereby manufacturing an SOI wafer.
  • a delamination step as Step 4 was performed in the form of delamination using a mechanical external force like Example 3, but an etching step as Step 5 was effected based on a wet etching stage alone using a KOH liquid solution without adopting such a stage as depicted in FIG. 1 , thereby manufacturing an SOI wafer.
  • a delamination step as Step 4 was performed in the form of delamination based on a heat treatment like Example 1, but an etching step as Step 5 was carried out based on a dry etching stage alone adopting the PACE method (Comparative Example 3) or the GCIB method (Comparative Example 4) using an SF 6 gas without using such a stage as depicted in FIG. 1 , thereby manufacturing an SOI wafer.
  • a delamination step as Step 4 was carried out by using a mechanical external force like Example 3, but an etching step as Step 5 was performed based on a dry etching stage alone adopting the PACE method (Comparative Example 5) or the GCIB method (Comparative Example 6) using an SF 6 gas without utilizing such a stage as depicted in FIG. 1 , thereby manufacturing an SOI wafer.
  • Table 1 collectively shows a method for manufacturing an SOI wafer, a total time required for the etching step as Step 5 , and film thickness uniformity of an SOI layer in each of Examples 1 to 4 and Comparative Examples 1 to 6.
  • a total time required for the etching step is a period from a moment at which an SOI wafer is put into a wet etching device to a moment at which the SOI wafer is carried out from a dry etching device in Examples 1 to 4.
  • a total time required for the etching step is a period from a moment at which the SOI wafer is put into each etching device to a moment at which the SOI wafer is carried out from each etching device in Comparative Examples 1 to 6.
  • Examples 1 to 4 conforms to the present invention where the etching step is carried out on two stages, i.e., wet etching and dry etching (the PACE method or the GCIB method), and was able to obtain high film thickness uniformity of approximately 5%. Further, although the wafer must again put into the dry etching device from the wet etching device, a time required for the etching step where the SOI layer is etched for 150 nm is as short as approximately 15 minutes in each of these examples.
  • wet etching and dry etching the PACE method or the GCIB method
  • the etching step was performed based on wet etching alone, and a time required for the etching step was as short as approximately five minutes as compared with Examples 1 to 4, but film thickness uniformity of approximately 3% with a great fluctuation was obtained.
  • the etching step was performed based on dry etching (the PACE method or the GCIB method) alone, and film thickness uniformity was approximately 5% which is equivalent to that in each of Examples 1 to 4, but productivity was poor since a time required for the etching step was as long as approximately 60 minutes.
  • the SOI wafer having the SOI layer with high film thickness uniformity which is substantially equivalent to that of an SOI layer etched based on dry etching like the PACE method or the GCIB method can be manufactured with far better productivity than that in the conventional examples.

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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5277975B2 (ja) * 2009-01-14 2013-08-28 株式会社村田製作所 複合基板の製造方法
SG163481A1 (en) * 2009-01-21 2010-08-30 Semiconductor Energy Lab Method for manufacturing soi substrate and semiconductor device
JP5643488B2 (ja) * 2009-04-28 2014-12-17 信越化学工業株式会社 低応力膜を備えたｓｏｉウェーハの製造方法
JP2010278341A (ja) * 2009-05-29 2010-12-09 Shin-Etsu Chemical Co Ltd 貼り合わせｓｏｓ基板
US20110269295A1 (en) * 2010-04-30 2011-11-03 Hopper Peter J Method of Forming a Semiconductor Wafer that Provides Galvanic Isolation
US20120129318A1 (en) * 2010-11-24 2012-05-24 Semiconductor Energy Laboratory Co., Ltd. Atmospheric pressure plasma etching apparatus and method for manufacturing soi substrate
FR2978605B1 (fr) * 2011-07-28 2015-10-16 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice comprenant une couche fonctionnalisee sur un substrat support
JP5664592B2 (ja) * 2012-04-26 2015-02-04 信越半導体株式会社 貼り合わせウェーハの製造方法
CN102832105B (zh) * 2012-09-10 2015-08-19 豪威科技(上海)有限公司 晶圆减薄方法
TWI629753B (zh) * 2013-04-26 2018-07-11 日本碍子股份有限公司 半導體用複合基板之操作基板
JP6213046B2 (ja) 2013-08-21 2017-10-18 信越半導体株式会社 貼り合わせウェーハの製造方法
JP6152829B2 (ja) * 2014-06-17 2017-06-28 信越半導体株式会社 Ｓｏｉウェーハの製造方法
US9543440B2 (en) * 2014-06-20 2017-01-10 International Business Machines Corporation High density vertical nanowire stack for field effect transistor
DE102014114683B4 (de) * 2014-10-09 2016-08-04 Infineon Technologies Ag Verfahren zur herstellung eines halbleiter-wafers mit einer niedrigen konzentration von interstitiellem sauerstoff
US10332781B2 (en) * 2014-12-19 2019-06-25 Globalwafers Co., Ltd. Systems and methods for performing epitaxial smoothing processes on semiconductor structures
JP6525046B1 (ja) * 2017-12-19 2019-06-05 株式会社Sumco 半導体ウェーハの製造方法
KR101969679B1 (ko) 2018-07-27 2019-04-16 한양대학교 산학협력단 Soi 웨이퍼와 열처리 공정을 이용한 박막 형성 및 전사 방법
US10658474B2 (en) 2018-08-14 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming thin semiconductor-on-insulator (SOI) substrates
CN113889431A (zh) * 2020-07-01 2022-01-04 中芯集成电路（宁波）有限公司上海分公司 绝缘体上半导体结构的制造方法

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0514046A1 (en) 1991-05-07 1992-11-19 Hughes Aircraft Company System for controlling and executing the etching of a wafer
JPH08293483A (ja) 1994-09-06 1996-11-05 Res Dev Corp Of Japan ガスクラスターイオンビームによる固体表面の 平坦化方法
JPH09252100A (ja) 1996-03-18 1997-09-22 Shin Etsu Handotai Co Ltd 結合ウェーハの製造方法及びこの方法により製造される結合ウェーハ
JPH09260620A (ja) 1996-03-25 1997-10-03 Shin Etsu Handotai Co Ltd 結合ウエーハの製造方法およびこの方法で製造される結合ウエーハ
WO1998009804A1 (en) 1996-09-04 1998-03-12 Sibond L.L.C. Flattening process for bonded semiconductor substrates
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
JPH11145438A (ja) 1997-11-13 1999-05-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
US6263941B1 (en) 1999-08-10 2001-07-24 Silicon Genesis Corporation Nozzle for cleaving substrates
US6537606B2 (en) * 2000-07-10 2003-03-25 Epion Corporation System and method for improving thin films by gas cluster ion beam processing
US6582999B2 (en) 1997-05-12 2003-06-24 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid
US20040137698A1 (en) * 2002-08-29 2004-07-15 Gianni Taraschi Fabrication system and method for monocrystaline semiconductor on a substrate
US20040248380A1 (en) 2003-06-06 2004-12-09 Cecile Aulnette Method of producing a semiconductor structure having at least one support substrate and an ultrathin layer
JP2005005674A (ja) 2003-05-21 2005-01-06 Canon Inc 基板製造方法及び基板処理装置
EP1635396A1 (en) 2003-04-02 2006-03-15 SUMCO Corporation Laminated semiconductor substrate and process for producing the same
JP2007073878A (ja) 2005-09-09 2007-03-22 Shin Etsu Chem Co Ltd Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57149301A (en) 1981-03-11 1982-09-14 Daiichi Togyo Kk Novel polysaccharide having coagulating property

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0514046A1 (en) 1991-05-07 1992-11-19 Hughes Aircraft Company System for controlling and executing the etching of a wafer
JPH05160074A (ja) 1991-05-07 1993-06-25 Hughes Aircraft Co ウエハから材料を除去するシステム
US5254830A (en) 1991-05-07 1993-10-19 Hughes Aircraft Company System for removing material from semiconductor wafers using a contained plasma
JPH08293483A (ja) 1994-09-06 1996-11-05 Res Dev Corp Of Japan ガスクラスターイオンビームによる固体表面の 平坦化方法
US6004866A (en) 1996-03-18 1999-12-21 Shin-Etsu Handotai, Co., Ltd. Method for manufacturing bonded wafer and bonded wafer manufactured thereby
JPH09252100A (ja) 1996-03-18 1997-09-22 Shin Etsu Handotai Co Ltd 結合ウェーハの製造方法及びこの方法により製造される結合ウェーハ
EP0797248A2 (en) 1996-03-18 1997-09-24 Shin-Etsu Handotai Kabushiki Kaisha Method for manufacturing a bonded wafer
JPH09260620A (ja) 1996-03-25 1997-10-03 Shin Etsu Handotai Co Ltd 結合ウエーハの製造方法およびこの方法で製造される結合ウエーハ
WO1998009804A1 (en) 1996-09-04 1998-03-12 Sibond L.L.C. Flattening process for bonded semiconductor substrates
US6582999B2 (en) 1997-05-12 2003-06-24 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
JPH11145438A (ja) 1997-11-13 1999-05-28 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
US6263941B1 (en) 1999-08-10 2001-07-24 Silicon Genesis Corporation Nozzle for cleaving substrates
US6513564B2 (en) 1999-08-10 2003-02-04 Silicon Genesis Corporation Nozzle for cleaving substrates
US6537606B2 (en) * 2000-07-10 2003-03-25 Epion Corporation System and method for improving thin films by gas cluster ion beam processing
US20040137698A1 (en) * 2002-08-29 2004-07-15 Gianni Taraschi Fabrication system and method for monocrystaline semiconductor on a substrate
EP1635396A1 (en) 2003-04-02 2006-03-15 SUMCO Corporation Laminated semiconductor substrate and process for producing the same
JP2005005674A (ja) 2003-05-21 2005-01-06 Canon Inc 基板製造方法及び基板処理装置
US20040248380A1 (en) 2003-06-06 2004-12-09 Cecile Aulnette Method of producing a semiconductor structure having at least one support substrate and an ultrathin layer
JP2007073878A (ja) 2005-09-09 2007-03-22 Shin Etsu Chem Co Ltd Ｓｏｉウエーハおよびｓｏｉウエーハの製造方法

Non-Patent Citations (9)

* Cited by examiner, † Cited by third party
Title
"Science of SOI", Chapter 2. Rearize Corporation. Apr. 19, 2000. A. Matsumura (pp. 7-15); T. Nakai (pp. 16-25); T. Katayama (pp. 26-30); T. Yonehara & K. Sakaguchi (pp. 31-58); N. Tate (pp. 59-66); M. Nakano (pp. 67-74); T. Katayama (pp. 75-78).
A.J. Auberton-Herve et al; "Smart Cut Technology: Inudstrial Status of SOI Wafer Production and New Material Developments". Electrochemical Society Proceedings vol. 99-3, pp. 93-106. 1999.
Aug. 14, 2012 Notification of Reasons for Refusal issued in Japanese Application No. 2007-144075 with partial English-language translation.
Dec. 30, 2013 Taiwanese Office Action issued in Taiwanese Application No. 097119148 with partial English-language translation.
European Search Report dated Jul. 8, 2010 in European Patent Application No. 08009379.2.
Jan. 22, 2013 Notification of Reasons for Refusal issued in Japanese Application No. 2007-144075 with partial English-language translation.
Jun. 11, 2013 Decision of Refusal issued in Japanese Application No. 2007-144075 with partial English-language translation.
Jun. 22, 2011 Search Report issued in European Patent Application No. 08 009 379,2.
May 14, 2014 Korean Office Action issued in Korean Patent Application No. 10-2008-0049695 (with partial English translation).

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TWI462221B (zh) 2014-11-21
TW200915480A (en) 2009-04-01
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KR20080106038A (ko) 2008-12-04

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