US8462087B2 - Organic light emitting diode display - Google Patents

Organic light emitting diode display Download PDF

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US8462087B2
US8462087B2 US11/880,734 US88073407A US8462087B2 US 8462087 B2 US8462087 B2 US 8462087B2 US 88073407 A US88073407 A US 88073407A US 8462087 B2 US8462087 B2 US 8462087B2
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voltage
data
light emitting
emitting diode
organic light
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US20080100609A1 (en
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Hong Koo Lee
Sang Hoon Jung
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LG Display Co Ltd
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LG Display Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing

Definitions

  • the present invention relates to an organic light emitting diode display device, and more particularly to an organic light emitting diode display device and the driving method thereof that is adaptive for increasing display quality.
  • the flat panel display device includes a liquid crystal display (hereinafter, referred to as “LCD”) device, a field emission display FED device, a plasma display panel (hereinafter, referred to as “PDP”), an electroluminescence EL device and the like.
  • LCD liquid crystal display
  • FED field emission display
  • PDP plasma display panel
  • electroluminescence EL device an electroluminescence EL device and the like.
  • the PDP among them is simple in its structure and fabrication process, thus the PDP is light, thin, short and small and has been paid attention to as a display device which is most advantageous in being made large-sized, but there is a big disadvantage in that the luminous efficiency and brightness thereof is low and the power consumption thereof is high.
  • An active matrix LCD to which a thin film transistor (hereinafter, referred to as “TFT”) is applied as a switching device is difficult to be made large-sized because a semiconductor process is used. But, the demand for the LCD is continuously increasing since the LCD is mainly used as a display device of a notebook computer.
  • the electroluminescence device is broadly classified into an inorganic electroluminescence device and organic electroluminescence device in accordance with a material of a luminous layer thereof.
  • the electroluminescence device is a self-luminous device which emits light on its own, and has an advantage in that its response speed is fast and its luminous efficiency, brightness and viewing angle are high.
  • An organic light emitting diode device includes an organic compound layer HIL, HTL, EML, ETL, EIL formed between an anode electrode and a cathode electrode, as in FIG. 1 .
  • the organic compound layer includes a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL and an electron injection layer EIL.
  • the organic light emitting diode device is classified into a passive matrix type display device and an active matrix type display device using a TFT as a switching device.
  • the passive matrix type selects light emission cells in accordance with currents applied to the anode electrodes and the cathode electrodes which perpendicularly cross each other.
  • the active matrix type selectively turns on the TFT being an active device to select the light emission cell, and maintains the luminescence of the light emission cell with the voltage kept in a storage capacitor.
  • FIG. 2 is a circuit diagram equivalently representing one pixel in an active matrix type organic light emitting diode display device.
  • the pixel of the active matrix type organic light emitting diode display device includes an organic light emitting diode OLED; a data line DL and a gate line GL which cross each other; a switch TFT T 1 ; a drive TFT T 2 ; and a storage capacitor Cst.
  • the switch TFT T 1 and the drive TFT T 2 are realized in a p-type MOS-FET.
  • the switch TFT T 1 is turned on in response to a gate low voltage (or scan voltage) from the gate line GL to form a current path between its own source electrode and drain electrode, and maintains an off-state when a voltage of the gate line GL is the gate high voltage which is higher than its own threshold voltage Vth.
  • the on-time interval of the switch TFT T 1 the data voltage from the data line DL is applied to the storage capacitor Cst and the gate electrode of the drive TFT T 2 through the source electrode and the drain electrode of the switch TFT T 1 .
  • the current path between the source electrode and the drain electrode of the switch TFT T 1 is opened so that no data voltage is applied to the drive TFT T 2 and the storage capacitor Cst.
  • the source electrode of the drive TFT T 2 is connected to one side electrode of the storage capacitor Cst and a high level power supply voltage source VDD and the drain electrode thereof is connected to the anode electrode of the organic light emitting diode OLED.
  • the gate electrode of the drive TFT T 2 is connected to the drain electrode of the switch TFT T 1 .
  • the drive TFT T 2 controls the current between the source electrode and the drain electrode in accordance with the gate voltage, i.e., data voltage, supplied to the gate electrode, thereby making the organic light emitting diode OLED emit light at a brightness corresponding to the data voltage.
  • the storage capacitor Cst stores a difference voltage between the data voltage and the high level power supply voltage VDD to fixedly maintain the voltage applied to the gate electrode of the drive TFT T 2 for one frame period.
  • the organic light emitting diode OLED is realized in a structure, as in FIG. 1 , and includes an anode electrode connected to the drain electrode of the drive TFT, T 2 and a cathode electrode connected to a low level drive voltage source VSS.
  • the brightness of the pixel is proportional to the current flowing in the organic light emitting diode OLED and the current is controlled by the gate voltage of the drive TFT T 2 . That is to say, in order to increase the brightness of the pixel, a gate-source voltage
  • the active matrix type organic light emitting diode display device as in FIG. 2 , has a problem in that image sticking might be easily generated though its aperture ratio is relatively better than that of the organic light emitting diode display device where three or more TFTs are formed for each pixel.
  • FIG. 3 shows an example of a residual image appearing when applying the test data of an intermediate gray level to pixels of the previous screen after applying the data of a residual image test image (left image), which is made by combining a white gray level and a black gray level into a chess board image, to the organic light emitting diode display device for about 9 seconds.
  • the residual image of the organic light emitting diode display device is classified into a recoverable residual image which disappears when time elapses, and an image burning which is left there forever.
  • the recoverable residual image is mainly shown because of the TFT characteristic deterioration of pixels, and the image burning is mainly shown because of the deterioration of organic compound layers HIL, HTL, EML, ETL, EIL.
  • FIGS. 4 and 5 represent an experiment reproducing a residual image effect of a chess board image which appears in an organic light emitting diode display device of the related art, as in FIG. 2 .
  • FIG. 6 shows a cross sectional of a drive TFT T 2 .
  • a drain-source current Ids of the drive TFT T 2 is measured when the voltage (gate voltage) of the gate electrode is changed to ⁇ 5V being the intermediate gray level voltage after applying 0V being a black gray level voltage or ⁇ 7V being a white gray level voltage to the gate electrode of the drive TFT T 2 for 16.7 msec.
  • 0V is applied to the source electrode of the drive TFT T 2 and ⁇ 7V is applied to the drain electrode.
  • a solid line represents a change of the drain-source current Ids of the drive TFT T 2 when the gate voltage of the drive TFT T 2 is changed from the black gray level voltage to the intermediate gray level voltage.
  • a dotted line represents a change of the drain-source current Ids of the drive TFT T 2 when the gate voltage of the drive TFT T 2 is changed from the white gray level voltage to the intermediate gray level voltage.
  • the dashed-dotted line represents the change of the drain-source current Ids of the drive TFT T 2 when maintaining the gate voltage of the drive TFT T 2 at the intermediate gray level voltage, i.e., ⁇ 5V.
  • the charge amount Qgate of the gate electrode is instantly increased, and the charge amount Qsemiconductor of a semiconductor layer 62 is also increased.
  • the charge amount Qinsulator of the insulating layer 61 is not increased rapidly, but the charge amount Qinsulator of the insulating layer 61 is increased as time elapses.
  • the charge amount Qsemiconductor of the semiconductor layer 62 is reduced as much as the charge amount Qgate of the gate voltage reduced by the white gray level voltage to decrease the drain-source current Ids, and the charge amount Qinsulator of the insulating layer 61 affected by the electric field between the gate electrode and the semiconductor layer 62 is reduced to increase the drain-source current Ids.
  • the charges are changed to the state of equilibrium as time elapses, thus the drain-source currents Ids become the same.
  • the residual image is a result that the difference between the drain-source currents Ids appears as the brightness of the organic light emitting diode display device when the gate voltage of the drive TFT T 2 is changed from the white gray level voltage to the intermediate gray voltage or from the black gray level voltage to the intermediate gray voltage. If the difference between the drain-source currents Ids of the drive TFT T 2 which appears when the gate voltage of the drive TFT T 2 is changed is reduced, then the residual image can be reduced.
  • an organic light emitting diode display device includes a display panel where pixels having an organic light emitting diode device are arranged in a matrix and a data driver that supplies a data voltage to the pixels, and supplies an inverted voltage to the pixels, wherein the inverted voltage is symmetric to the data voltage relative to a reference voltage.
  • a driving method of an organic light emitting diode display device where pixels including an organic light emitting diode device are arranged in a matrix includes providing a drive device configured to drive the organic light emitting diode in accordance with a gate voltage applied to a gate electrode and supplying a data voltage and an inverted voltage to the gate electrode of the drive device, wherein the inverted voltage is symmetric to the data voltage on the basis of a reference voltage.
  • FIG. 1 is a schematic diagram showing a structure of an organic light emitting diode of the related art
  • FIG. 2 is a circuit diagram showing a pixel in an active matrix type organic light emitting diode display device of the related art
  • FIG. 3 is a diagram showing a residual image according to the related art
  • FIG. 4 is a diagram and a plot showing a gate voltage of a drive TFT in an experiment for reproducing the residual image, as in FIG. 3 ;
  • FIG. 5 is a waveform diagram showing a drain-source current of a drive TFT changed by a gate voltage, as in FIG. 4 ;
  • FIG. 6 is a cross sectional diagram showing a drive TFT, in detail according to the related art
  • FIG. 7 is a block diagram illustrating an organic light emitting diode display device according to an embodiment of the present invention.
  • FIG. 8 is a waveform diagram illustrating a first embodiment of a drive waveform according to the present invention.
  • FIG. 9 is a diagram illustrating polarity patterns of the black gray level voltage and the real data voltage, which are supplied to pixels, as the drive waveform in FIG. 8 is applied to a display panel;
  • FIG. 10 is a waveform diagram illustrating a second embodiment of a drive waveform according to the present invention.
  • FIG. 11 is a diagram illustrating polarity patterns of the black gray level voltage and the real data voltage, which are supplied to pixels, as the drive waveform in FIG. 10 is applied to a display panel;
  • FIG. 12 is a waveform diagram illustrating a third embodiment of a drive waveform according to the present invention.
  • FIG. 13 is a diagram illustrating polarity patterns of the black gray level voltage and the real data voltage, which are supplied to pixels, as the drive waveform in FIG. 12 is applied to a display panel;
  • FIG. 14 is a diagram illustrating a first embodiment of the pixel illustrated in FIG. 7 ;
  • FIG. 15 is a waveform diagram illustrating a first embodiment of a drive waveform applied to the pixel, as in FIG. 14 ;
  • FIG. 16 is a waveform diagram illustrating a second embodiment of a drive waveform applied to the pixel, as in FIG. 14 ;
  • FIG. 17 is a diagram illustrating a second embodiment of the pixel shown in FIG. 7 ;
  • FIG. 18 is a waveform diagram illustrating a first embodiment of a drive waveform applied to the pixel, as in FIG. 17 ;
  • FIG. 19 is a waveform diagram illustrating a second embodiment of a drive waveform applied to the pixel, as in FIG. 17 ;
  • FIG. 20 is a circuit diagram illustrating an integrated circuit of a data driver shown in FIG. 7 , in detail;
  • FIG. 21 is a circuit diagram illustrating a digital/analog converter shown in FIG. 20 , in detail.
  • FIG. 22 is a circuit diagram illustrating a multiplexer according to an embodiment of the invention that selects a data voltage and an inversed voltage to output them in accordance with a polarity control signal of which a logical value is inversed by a horizontal period.
  • FIGS. 23 to 25 are graphs illustrating experiment results for verifying the effect of the present invention.
  • an organic light emitting diode display device includes a display panel 70 where m ⁇ n number of pixels 74 are formed; a data driver 72 for supplying data voltages to m number of data lines D 1 to Dm; a scan driver 73 for sequentially supplying scan pulses to n number of scan lines S 1 to Sn; and a timing controller 71 for controlling the drivers 72 , 73 .
  • pixels 74 are formed in pixel areas defined by the crossing of the scan lines S 1 to Sn, E 1 to En of the data lines D 1 to Dm.
  • VDD high level power supply voltage
  • VSS low level power supply voltage
  • the data driver 72 converts digital video data RGB from the timing controller 71 into analog gamma compensation voltages. And, a first embodiment of the data driver 72 supplies inverted data voltages to the data lines D 1 to Dm for a 1 ⁇ 2 frame period in response to control signals DDC(INV) from the timing controller 71 , and then supplies non-inverted data voltages to the data lines D 1 to Dm for the remaining 1 ⁇ 2 frame period.
  • a second embodiment of the data driver 72 supplies the non-inverted data voltages to the data lines D 1 to Dm for a 1 ⁇ 2 frame period in response to control signals DDC(POL) from the timing controller 71 , and then supplies the inverted data voltages to the data lines D 1 to Dm for the remaining 1 ⁇ 2 frame period.
  • a third embodiment of the data driver 72 supplies a non-inverted data voltage to any one pixel 74 of two pixels 74 , which are adjacent to each other in a vertical and horizontal directions, and supplies an inverted data voltage to the other pixel 74 in response to a control signal (DDC(POL 2 )) from the timing controller 71 .
  • DDC(POL 2 ) a control signal
  • the non-inverted data voltage and the inverted data voltage, which are supplied to the adjacent pixels 74 are inversed by a 1 ⁇ 2 frame period unit.
  • the scan driver 73 sequentially supplies scan pulses to the scan lines S 1 to Sn for a 1 ⁇ 2 frame period in response to control signals SDC from the timing controller 71 , and then sequentially supplies the scan pulses to the scan lines S 1 to Sn for the remaining 1 ⁇ 2 frame period. That is to say, the scan driver 73 supplies the scan pulses to each of the scan lines S 1 to Sn two times.
  • the scan driver 73 and the data driver are driven with a frequency having a double speed (for example, 120 Hz) compared to the related art.
  • the timing controller 71 supplies the digital video data RGB to the data driver 72 , and generates the control signals DDC(POL), SDC for controlling the operation timing of the data driver 72 and the scan driver 73 using vertical/horizontal synchronous signals and clock signal and the like. Furthermore, the present invention includes a frame memory that stores and delays the digital video data RGB corresponding to one frame for one frame period. The frame memory stores and delays the digital video data RGB corresponding to a (n+1)th frame during the digital video data corresponding to a nth frame is supplied to the data driver 72 , and then supplies them to the timing controller 71 .
  • a frame memory may be mounted in the timing controller 71 .
  • FIG. 8 represents a first embodiment of a drive waveform outputted from the data driver 72 and a scan pulse outputted from the scan driver 73 .
  • the data driver 72 supplies the black gray level voltages /Vdata, which are inverted, to the data lines D 1 to Dm for the first half frame period of one frame period, and then supplies real data voltages Vdata, which are to be displayed, to the data lines D 1 to Dm for the second half frame period.
  • the black gray level voltage /Vdata is a voltage which is symmetric to the real data voltage Vdata on the basis of a reference voltage corresponding to the lowest gray level. Accordingly, a voltage difference between the black gray level voltage /Vdata and the reference voltage is the same as a voltage difference between the real data voltage Vdata and the reference voltage.
  • the scan driver 73 sequentially supplies the scan pulses to each of the scan lines S 1 to Sn two times so as to be synchronized with each of the black gray level voltage /Vdata and the real data voltage Vdata to be displayed.
  • an image is realized by the black gray level voltage /Vdata for the first half frame period of one frame period, and an image is realized by the real data voltage Vdata for the second half frame period of one frame period as shown in FIG. 9 .
  • a black image is realized by the black gray level voltage /Vdata for the first half frame period of one frame period, and a normal image, which is required by the user, is realized by the real data voltage Vdata.
  • FIG. 10 represents a second embodiment of a drive waveform outputted from the data driver 72 and a scan pulse outputted from the scan driver 73 .
  • the data driver 72 supplies the real data voltages Vdata to the data lines D 1 to Dm for the first half frame period of one frame period, and then supplies the black gray level voltages /Vdata to the data lines D 1 to Dm for the second half frame period.
  • the black gray level voltage /Vdata is a voltage which is symmetric to the data voltage Vdata to be displayed on the basis of a reference voltage corresponding to the lowest gray level.
  • the scan pulses are supplied to each of the scan lines S 1 to Sn two times so as to be synchronized with each of the black gray level voltage /Vdata and the real data voltage Vdata to be displayed.
  • an image is realized by the real data voltage Vdata for the first half frame period of one frame period, and an image is realized by the black gray level voltage /Vdata for the second half frame period of one frame period as shown in FIG. 11 .
  • the real data voltage Vdata or the black gray level voltage /Vdata is uniformly supplied to all pixels for a frame period.
  • FIG. 12 shows a third embodiment of a scanning pulse, which is outputted from the scan driver 73 , and a drive waveform, which is outputted from the data driver 72 .
  • the real data voltage Vdata and the black gray level voltage /Vdata are simultaneously supplied to the data lines D 1 to Dm by a dot inversion method.
  • a dot inversion method supplies a data signal, which has an inversed polarity compared to a data signal which is supplied to the pixels 74 which are adjacent from a vertical/horizontal directions, to each of the pixels 74 on the display panel 70 , and inverses polarities of data signals with which all pixels 74 on the display panel 70 are supplied for each frame.
  • the data driver 72 supplies the real data voltage Vdata to any one pixel 74 of two pixel 74 , which are adjacent in a vertical and horizontal directions, and supplies the black gray level voltage /Vdata to the other pixel 74 for the first half frame period of one frame period.
  • the data driver 72 supplies the black gray level voltage /Vdata to pixels 74 , which are supplied with the real data voltage Vdata for the first half frame period, and supplies the real data voltage Vdata to the pixels 74 , which are supplied with the black gray level voltage /Vdata for the first half frame period, for the second half frame period of one frame period.
  • the black gray level voltage /Vdata is a voltage, which is symmetric to the real data voltage Vdata on the basis of the reference voltage corresponding to a minimum gray level. Accordingly, a voltage difference between the black gray level voltage /Vdata and the reference voltage is the same as a voltage difference between the real data voltage Vdata and the reference voltage.
  • the scan driver 73 sequentially supplies the scan pulses to each of the scan lines S 1 to Sn two times so as to be synchronized with a data voltage, which is supplied for the first half 1 ⁇ 2 frame period, and a data voltage, which is supplied for the second half 1 ⁇ 2 frame period.
  • the third embodiment of the present invention alternately supplies data voltages, which have the same level and a different polarity, to each pixel 74 for one frame period similar to the first and second embodiments.
  • the third embodiment of the present invention realizes an image using the real data voltage Vdata for one frame period to realize an image having credibility compared to the first and second embodiments that realize an image using the real data voltage Vdata for only frame period of one frame period
  • the organic light emitting diode display device periodically applies the black gray level voltage /Vdata, which is symmetric to the real data voltage Vdata on the basis of the reference voltage, to the gate electrode of the drive TFT included in each pixel, thereby making DC biases not to be applied to the gate electrode of the drive TFT continuously.
  • the charges trapped in an interface between the gate electrode and an insulating layer and an interface between the insulating layer and a semiconductor layer are periodically de-trapped under the control of the gate voltage of the drive TFT to prevent an adverse effect for the electrical characteristic of the drive TFT caused by the charges trapped in the interface, which are a cause of residual images.
  • the organic light emitting diode display device alternately applies opposite polarity voltages of the same size to the gate electrode of the drive TFT for one frame period, thus even though the charges are accumulated in the insulating layer, the charges are offset with the electric fields of the polarities opposite to each other for one frame period.
  • FIG. 14 represents a first embodiment of the pixel 74 .
  • the first embodiment of the pixel 74 includes a switch TFT pT 1 and a drive TFT pT 2 each realized in a p-type MOS-FET; a storage capacitor C 1 for maintaining the gate voltage of the drive TFT pT 2 ; and an organic light emitting diode OLED driven by the drive TFT pT 2 .
  • the pixel 74 is substantially the same as the pixel of FIG. 2 in an aspect of configuration, but the pixel 74 is conspicuously different from the pixel of FIG. 2 by the drive waveform of FIG. 8 , FIG. 10 , and FIG. 12 in an aspect of operation and action effect.
  • the scan signal is generated to be a low logic voltage which is not higher than the threshold voltage of the switch TFT pT 1 .
  • the data voltage for making the organic light emitting diode OLED emit light by generating the drain-source current in the drive TFT pT 2 is generated to be a voltage which is not higher than the reference voltage.
  • FIG. 15 represents a first embodiment of a drive waveform applied to the pixel 74 , as in FIG. 14 .
  • the data driver 72 supplies the black gray level voltages /Vdata to the data lines D 1 to Dm for the 1 ⁇ 2 frame period, and then supplies the real data voltages Vdata, which are to be displayed, to the data lines D 1 to Dm for the second half frame period.
  • the black gray level voltages /Vdata and the real data voltages Vdata supplied to the data lines D 1 to Dm are supplied to the gate electrode of the drive TFT pT 2 when the switch TFT pT 1 is turned on by the scan pulses.
  • the drive TFT pT 2 maintains the off-state when the black gray level voltages /Vdata are applied to the gate electrode, and forms the drain-source channel when the real data voltages Vdata are applied to the gate electrode, thereby supplying the currents to the organic light emitting diode OLED so that the organic light emitting diode OLED is made to emit light at the brightness corresponding to the gray level of the data.
  • the black gray level voltage /Vdata of a positive voltage which is higher than the reference voltage Vref and the real data voltage Vdata of a negative voltage which is lower than the reference voltage Vref have a voltage difference which is symmetric on the basis of the reference voltage Vref. That is to say, the voltage difference between the black gray level voltage /Vdata and the real data voltage Vdata is substantially the same as the voltage difference between the real data voltage Vdata and the reference voltage Vref.
  • the storage capacitor C 1 stores the real data voltage Vdata for the second half frame period to fixedly maintain the voltage of the drive TFT pT 2 .
  • the reference voltage Vref is a voltage corresponding to the lowest gray level, and is the same as the high level power supply voltage VDD.
  • FIG. 16 represents a second embodiment of a drive waveform applied to the pixel 74 , as in FIG. 14 .
  • the data driver 72 supplies the real data voltages Vdata to the data lines D 1 to Dm for the 1 ⁇ 2 frame period, and then supplies the black gray level voltages /Vdata, which are to be displayed, to the data lines D 1 to Dm for the second half frame period.
  • the real data voltages Vdata and the black gray level voltages /Vdata supplied to the data lines D 1 to Dm are supplied to the gate electrode of the drive TFT pT 2 when the switch TFT pT 1 is turned on by the scan pulses.
  • the drive TFT pT 2 forms the drain-source channel when the real data voltages Vdata are applied, thereby supplying the currents to the organic light emitting diode OLED so that the organic light emitting diode OLED is made to emit light at the brightness corresponding to the gray level of the data. And then, the drive TFT pT 2 is turned off when the black gray level voltage /Vdata is applied.
  • the black gray level voltage /Vdata of a positive voltage and the real data voltage Vdata of a negative voltage have a voltage difference which is symmetric on the basis of the reference voltage Vref.
  • the storage capacitor C 1 stores the real data voltage Vdata for the first half frame period to fixedly maintain the voltage of the drive TFT pT 2 .
  • FIG. 17 represents a second embodiment of the pixel 74 .
  • the second embodiment of the pixel 74 includes a switch TFT nT 1 and a drive TFT nT 2 each realized in a n-type MOS-FET; a storage capacitor C 2 for maintaining the gate voltage of the drive TFT nT 2 ; and an organic light emitting diode OLED driven by the drive TFT nT 2 .
  • the scan signal for controlling the switch TFT nT 1 of the pixel 74 is generated to be a high logic voltage which is not lower than the threshold voltage of the switch TFT nT 1 .
  • the data voltage for making the organic light emitting diode OLED emit light by generating the drain-source current in the drive TFT nT 2 is generated to be a voltage which is not lower than the reference voltage.
  • FIG. 18 represents a first embodiment of a drive waveform applied to the pixel 74 , as in FIG. 17 .
  • the data driver 72 supplies the black gray level voltages /Vdata, which are negative voltages lower than the reference voltage Vref, to the data lines D 1 to Dm for the 1 ⁇ 2 frame period, and then supplies the real data voltages Vdata, which are positive voltages higher than the reference voltage Vref, to the data lines D 1 to Dm for the second half frame period.
  • the black gray level voltages /Vdata and the real data voltages Vdata supplied to the data lines D 1 to Dm are supplied to the gate electrode of the drive TFT nT 2 when the switch TFT nT 1 is turned on by the scan pulses.
  • the drive TFT nT 2 maintains the off-state when the black gray level voltages /Vdata are applied, and opens the drain-source channel when the real data voltages Vdata are applied, thereby supplying the currents to the organic light emitting diode OLED so that the organic light emitting diode OLED is made to emit light at the brightness corresponding to the gray level of the data.
  • the black gray level voltage /Vdata and the real data voltage Vdata have a voltage difference which is symmetric on the basis of the reference voltage Vref.
  • the storage capacitor C 2 stores the real data voltage Vdata for the second half frame period to fixedly maintain the voltage of the drive TFT nT 2 .
  • the reference voltage Vref is a voltage corresponding to the lowest gray level, and is the same as the high level power supply voltage VDD.
  • FIG. 19 represents a second embodiment of a drive waveform applied to the pixel 74 , as in FIG. 17 .
  • the data driver 72 supplies the real data voltages Vdata, which are the positive voltages higher than the reference voltage Vref, to the data lines D 1 to Dm for the 1 ⁇ 2 frame period, and then supplies the black gray level voltages /Vdata, which are the negative voltages lower than the reference voltage Vref, to the data lines D 1 to Dm for the second half frame period.
  • the real data voltages Vdata and the black gray level voltages /Vdata supplied to the data lines D 1 to Dm are supplied to the gate electrode of the drive TFT nT 2 when the switch TFT nT 1 is turned on by the scan pulses.
  • the drive TFT nT 2 opens the drain-source channel when the real data voltages Vdata are applied, thereby supplying the currents to the organic light emitting diode OLED so that the organic light emitting diode OLED is made to emit light at the brightness corresponding to the gray level of the data. And then, the drive TFT nT 2 is turned off when the black gray level voltage /Vdata is applied.
  • the black gray level voltage /Vdata and the real data voltage Vdata have a voltage difference which is symmetric on the basis of the reference voltage Vref.
  • the storage capacitor C 2 stores the real data voltage Vdata for the first half frame period to fixedly maintain the voltage of the drive TFT nT 2 .
  • FIG. 14 to FIG. 19 A case where the switch TFT T 1 and the drive TFT T 2 are realized as the same type MOS-FET, is shown in FIG. 14 to FIG. 19 .
  • the switch TFT T 1 and the drive TFT T 2 may be realized as a different type MOS-FET.
  • the switch TFT T 1 may be realized as a n-type MOS-FET and the drive TFT T 2 may be realized as a p-type MOS-FET, or the switch TFT T 1 may be realized as a p-type MOS-FET and the drive TFT T 2 may be realized as a n-type MOS-FET.
  • FIGS. 20 and 22 are circuit diagrams representing an integrated circuit of the data driver 72 , in detail.
  • the data driver 72 includes a plurality of integrated circuits IC which each drive k (k is an integer less than m) number of data lines S 1 to Sk.
  • Each of the integrated circuits includes a shift register 101 connected in cascade between the timing controller 71 and the data line S 1 to Sk; a data register 102 ; a first latch 103 ; a second latch 104 ; a digital/analog converter (hereinafter, referred to as “DAC”) 105 ; and an output circuit 109 .
  • DAC digital/analog converter
  • the shift register 101 shifts source start pulses SSP from the timing controller 71 in accordance with source shift clocks SSC to generate sampling signals. Further, the shift register 101 shifts the source start pulses SSP to transmit carry signals CAR to the shift register 101 of the next stage integrated circuit.
  • the data register 102 temporarily stores digital video data RGB from the timing controller 71 and supplies the stored data RGB to the first latch 103 .
  • the first latch 103 samples the digital video data RGB from the data register 102 in response to the sampling signals sequentially inputted from the shift register 101 , latches the sampled data by the unit of one horizontal line, and then simultaneously outputs the data of one horizontal line.
  • the second latch 104 latches the data inputted from the first latch 103 , and then outputs the digital video data, which are latched at the same time as the second latches 104 of other integrated circuits, in response to source output signals SOE from the timing controller 71 .
  • the DAC 105 includes a p-decoder PDEC 106 to which positive gamma reference voltages GH are supplied; a n-decoder NDEC 107 to which negative gamma reference voltages GL are supplied; and a multip to output the positive gamma compensation voltages corresponding to the gray level values of the data, and the n-decoder 107 decodes the digital video data inputted from the second latch 104 to output the negative gamma compensation voltages corresponding to the gray level values of the data.
  • the multiplexer 108 of the first and second embodiments alternately selects a gamma compensation voltage of positive polarity and a gamma compensation voltage of negative polarity and outputs selected gamma compensation voltages of positive polarity/negative polarity as analog data voltages in response to a first polarity control signal POLL.
  • a logical value of the first polarity control signal POL 1 is inversed by a 1 ⁇ 2 frame period unit so as to uniformly supply the black gray level voltage /Vdata or the real data voltage Vdata to all pixels for a 1 ⁇ 2 frame period.
  • the multiplexer 108 of the third embodiment alternately selects a gamma compensation voltage of positive polarity and a gamma compensation voltage of negative polarity and outputs selected gamma compensation voltages of positive polarity/negative polarity as analog data voltages in response to a second polarity control signal POL 2 .
  • the second polarity control signal POL 2 indicates polarities of the real data voltage Vdata and the black gray level voltage /Vdata, which are supplied to each of the pixels, and a logical value thereof is inversed by a horizontal period unit as shown in FIG. 12 .
  • an inverter 54 is connected to a selective signal input terminal of the even numbered multiplexer 108 as shown in FIG. 22 .
  • the inverter 54 plays a role to inverse the second polarity control signal POL 2 from the timing controller 74 .
  • the real data voltage Vdata and the black gray level voltage /Vdata are supplied from the data driver 72 to the display panel 70 by a dot inversion method.
  • the output circuit 109 includes a buffer to minimize the signal attenuation of the analog data voltage supplied to the data line S 1 to Sk.
  • the negative gamma compensation voltage outputted from the n-decoder 107 is the real data voltage Vdata
  • the positive gamma compensation voltage outputted from the p-decoder 106 is the black gray level voltage /Vdata.
  • the positive gamma compensation voltage outputted from the p-decoder 106 is the real data voltage Vdata
  • the negative gamma compensation voltage outputted from the n-decoder 107 is the black gray level voltage /Vdata.
  • FIGS. 23 to 25 represent experiment results for verifying the effect of the present invention.
  • FIG. 23 represents the change of the drain-source current of the drive TFT pT 2 when the black gray level voltage /Vdata and the real data voltage Vdata, as in FIGS. 15 and 16 , are alternately applied to the drive TFT pT 2 , but the real data voltage Vdata is changed from ⁇ 7V corresponding to the white gray level to ⁇ 5V corresponding to the intermediate gray level and from 0V corresponding to the black gray level to ⁇ 5V corresponding to the intermediate gray level.
  • the reference voltage Vref i.e., the high level drive voltage VDD, is supplied at 0V in the experiment of FIG. 23 .
  • FIG. 23 As can be known in FIG.
  • the error of the current Ids of the drive TFT pT 2 is reduced to about 2.6 nA when the real data voltage Vdata is changed from the black gray level to the intermediate gray level or from the white gray level to the intermediate gray level.
  • the error of the current Ids of the drive TFT pT 2 is about 20 nA, as in FIG. 5 .
  • FIG. 24 represents the change of the drain-source current Ids of the drive TFT pT 2 when the reference voltage Vref is adjusted to +1.8V and the other experiment conditions are made to be the same as the experiment of FIG. 23 .
  • the black gray level voltage /Vdata and the real data voltage Vdata are alternately applied to the drive TFT pT 2 , but the real data voltage Vdata is changed from ⁇ 7V corresponding to the white gray level to ⁇ 5V corresponding to the intermediate gray level and from 0V corresponding to the black gray level to ⁇ 5V corresponding to the intermediate gray level.
  • the reference voltage Vref i.e., the high level drive voltage VDD
  • the reference voltage Vref can be optimized to be 1.8V, as in FIG. 25 , but the device characteristic of the drive TFT pT 2 might be different for each panel and for each model, thus the reference voltage Vref might be changed in accordance with the characteristic of the drive TFT pT 2 .
  • a data sampling time is set to be a thousand fold the data sampling time of the original display device, and the inverted black gray level voltage /Vdata and the real data voltage Vdata are alternately applied.
  • the insulating layer charge ⁇ Qinsulator of the drive TFT pT 2 is almost 0. Because of lexer 108 for selecting any one of the output of the p-decoder 106 and the output of the n-decoder 107 , as in FIG. 21 .
  • the p-decoder 106 decodes the digital video data inputted from the second latch 104 this, after the gate voltage is applied, the current is decreased for a few seconds due to the increase of the insulating layer charge Qinsulator, but the inverted black gray level voltage /Vdata is applied to reduce the insulating layer charge Qinsulator of the same amount, thus the current characteristic of the drive TFT becomes the same in the next frame period as in the previous frame period.
  • the organic light emitting diode display device decodes the digital video data to the positive voltage and the negative voltage so as to generate the black gray level voltage and the real data voltage which are symmetric on the basis of the reference voltage, and alternately supplies the voltages to the gate electrode of the drive TFT, thereby minimizing the deterioration of the electrical characteristic of the drive TFT and the residual image thereof.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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