US7660134B2 - DC-DC converter and control method thereof - Google Patents

DC-DC converter and control method thereof Download PDF

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US7660134B2
US7660134B2 US11/586,861 US58686106A US7660134B2 US 7660134 B2 US7660134 B2 US 7660134B2 US 58686106 A US58686106 A US 58686106A US 7660134 B2 US7660134 B2 US 7660134B2
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terminal
circuit
potential
switching element
element connected
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US20070090821A1 (en
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Takakazu Imai
Takeo Gokita
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TDK Corp
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TDK Corp
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to a DC-DC converter and a control method thereof.
  • the present invention relates to a DC-DC converter which produces no backward current, which flows from a smoothing circuit to a synchronous rectifying circuit, when the load becomes light, and a control method thereof.
  • a switching circuit is switched on and off in response to a pulse signal, to intermittently supply a DC voltage to an inductance element.
  • a DC-DC converter adopts a synchronous rectifying method of supplying a returning current, which flows into the inductance element while no electricity is supplied thereto, to the load through the switching element.
  • FIG. 8 shows one example of circuit structure of an assumable DC (direct current)-DC (direct current) converter of a synchronous rectifying type.
  • This DC-DC converter comprises a light load detecting circuit which switches off a synchronous rectifying switching element, in accordance with whether the load is large or small.
  • a control circuit 10 detects the difference between an output voltage Vout from the DC-DC converter and a reference voltage E 11 , and sends a difference voltage Vd to a comparator 20 .
  • the comparator 20 compares the difference voltage Vd with a voltage V 1 , which corresponds to (for example, is proportional to) the current value of an inductance current (a current flowing from a switching circuit 40 to an inductor L 51 ).
  • the comparator 20 outputs a high level signal in a case where the voltage V 1 is higher than the difference Vd, and outputs a low level signal in a case where the voltage V 1 is lower than the difference voltage Vd.
  • a clock signal CLK having a constant frequency is input to a D-type flip flop circuit (hereinafter referred to as D-FF) 30 from a clock circuit 1 .
  • the D-FF 30 latches a power source voltage VDD supplied to its data input terminal (hereinafter referred to as D terminal) at a rising edge of the clock signal CLK, and outputs a high level signal from its output terminal (hereinafter referred to as Q terminal).
  • the D-FF 30 is reset by a high level signal from the comparator 20 .
  • the D-FF 30 continues outputting a high level signal from its Q terminal from when the clock signal CLK rises until when the output from the comparator 20 becomes high level.
  • a voltage of ON level (high level) is applied, through a level shift circuit 5 , to an N-MOSFET (N-channel MOSFET; MOSFET:Metal Oxide Semiconductor Field Effect Transistor) 41 , which is at the high side of the switching circuit 40 .
  • N-MOSFET N-channel MOSFET; MOSFET:Metal Oxide Semiconductor Field Effect Transistor
  • the logical AND of a voltage of OFF level (low level) having been inverted by an inverter 2 and an output signal from a light load detecting circuit 60 is applied, through an AND circuit 4 , to the gate of an N-MOSFET 42 at the low side.
  • the N-MOSFET 41 at the high side is switched on, and the N-MOSFET 42 at the low side is switched off. Then, a current flows from a power source VCC into the inductor L 51 and charges a smoothing capacitor C 51 .
  • a voltage of OFF level (low level) is applied to the gate of the N-MOSFET 41 at the high side of the switching circuit 40 .
  • a voltage of ON level (high level) inverted by the inverter 2 is applied through the AND circuit 4 to the N-MOSFET 42 at the low side. Therefore, the N-MOSFET 41 at the high side is switched off and the N-MOSFET 42 at the low side is switched on. Then, the current flowing in the inductor L 51 flows through the N-MOSFET 42 at the low side.
  • the difference voltage Vd obtained by the control circuit 10 decreases and the pulse width of the pulse signal output from the comparator 20 widens.
  • the pulse width of the pulse signal widens, the period during which the D-FF 30 is reset becomes longer and the pulse width of the pulses output from the Q terminal becomes narrower. Accordingly, the ON period of the N-MOSFET 41 becomes shorter and the energy to be supplied from the power source VCC to the inductor L 51 decreases, thereby to reduce the output voltage Vout.
  • the difference voltage Vd obtained by the control circuit 10 increases and the pulse width of the pulse signal output from the comparator 20 becomes narrower.
  • the pulse width of the pulse signal becomes narrower, the period during which the D-FF 30 is reset becomes shorter and the pulse width of the pulse signal output from the Q terminal becomes wider. Accordingly, the ON period of the N-MOSFET 41 becomes longer. Further, the energy to be supplied from the power source VCC to the inductor L 51 increases and the output voltage Vout also increases.
  • the light load detecting circuit 60 is provided.
  • the load current decreases and the voltage V 1 corresponding to the load current also decreases.
  • the voltage signal V 1 supplied to the positive input terminal (+) of a comparator 61 which constitutes the light load detecting circuit 60 , decreases to become smaller than a reference voltage E 61 .
  • the comparator 61 supplies a low level signal to the AND circuit 4 , and the AND circuit 4 controls the N-MOSFET 42 at the low side to be kept off all time. Therefore, only the N-MOSFET 41 at the high side is switched on and off and no returning current flows backward from the inductor L 51 . Thus, it is possible to prevent a switching loss at the N-MOSFET 42 and save the power to be consumed.
  • the N-MOSFET 41 at the high side is kept switched off, and the N-MOSFET 42 at the low side is kept switched on.
  • the light load detecting circuit 60 detects the change of the load to a light one and the decrease of the load current I 1 (if the comparator 61 outputs a low level signal), the AND circuit 4 outputs a low level signal and the N-MOSFET 42 at the low side is switched off.
  • the time constant of the light load detecting circuit 60 is large (generally, the time constant of the light load detecting circuit 60 >>the time constant of the control circuit 10 ) in order to secure operation stability, the control to switch off the N-MOSFET 42 is delayed. Because of this, the state that the N-MOSFET 41 at the high side is off and the N-MOSFET 42 at the low side is on is maintained.
  • a method of sensing a pulse waveform of the output voltage and detecting an abnormal state of the waveform is known.
  • the method is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2005-210819.
  • This method detects the pulse width and pulse interval of the pulse waveform, which appears at the output terminal of the section prior to the smoothing circuit, i.e., the output terminal of the switching circuit, and detects an abnormal state of the power source. After this, the circuit according to this method outputs an abnormal state detection signal representing the detected abnormality.
  • the abnormal state detecting method disclosed in the publication cannot prevent a backward current.
  • An object of the present invention is to provide a DC-DC converter which produces reduced backward current when the load is light, and a control method thereof.
  • Another object of the present invention is to provide a DC-DC converter which can be adapted to the changes of the loads, and a control method thereof.
  • a first switching element connected between a terminal to which a first potential is applied and a first intermediate terminal
  • a PWM control circuit which detects a voltage of the output terminal, and outputs a pulse signal having a pulse width determined based on the voltage of the output terminal;
  • a first driver circuit which drives the first and second switching elements based on the pulse signal
  • a first pulse skipping detecting circuit which switches off the second switching element, when detecting that the PWM control circuit has stopped outputting the pulse signal for a predetermined period or longer.
  • the DC-DC converter may have a first light load detecting circuit which switches off the second switching element, when detecting that a current flowing in the first inductance element becomes equal to or smaller than a predetermined current value.
  • the first pulse skipping detecting circuit may switch off the second switching element before the first light load detecting circuit switches off the second switching element.
  • the first pulse skipping detecting circuit detects a period during which outputting of the pulse signal is stopped, by counting a first clock which is synchronous with the pulse signal.
  • the first pulse skipping detecting circuit may detect a period during which outputting of the pulse signal is stopped, by counting a second clock which is asynchronous with the pulse signal.
  • a third switching element connected between a terminal to which a third potential is applied and a second intermediate terminal
  • a transformer having a primary winding whose terminals are connected to the second intermediate terminal and the third intermediate terminal respectively;
  • a seventh switching element connected between a first terminal of a secondary winding of the transformer and a terminal to which a fifth potential is applied;
  • a second inductance element connected between a tap of the secondary winding of the transformer and an output terminal
  • a PWM control circuit which detects a voltage of the output terminal, and outputs a pulses signal having a pulse width determined based on the voltage of the output terminal;
  • a second pulse skipping detecting circuit which switches off the seventh and eighth switching elements, when detecting that the PWM control circuit has stopped outputting the pulse signal for a predetermined period or longer.
  • the DC-DC converter may have a second light load detecting circuit which switches off the seventh and eighth switching elements, when detecting that a current flowing in the second inductance element becomes equal to or smaller than a predetermined current value.
  • the second pulse skipping detecting circuit may switch off the seventh and eighth switching elements before the second light load detecting circuit switches off the seventh and eighth switching elements.
  • the second pulse skipping detecting circuit detects a period during which outputting of the pulse signal is stopped, by, for example, counting a first clock which is synchronous with the pulse signal, or counting a second clock which is asynchronous with the pulse signal.
  • a control method of a DC-DC converter having a synchronous rectifying circuit according to a third aspect of the present invention comprises:
  • FIG. 1 is a circuit diagram of a DC-DC converter according to a first embodiment of the present invention
  • FIG. 2A to FIG. 2J are timing charts for explaining the operation of the DC-DC converter shown in FIG. 1 ;
  • FIG. 3 is a circuit diagram of a DC-DC converter according to a second embodiment of the present invention.
  • FIG. 4A to FIG. 4K are timing charts for explaining the operation of the DC-DC converter shown in FIG. 3 ;
  • FIG. 5 is a diagram showing another example of the structure of a pulse skipping detecting circuit
  • FIG. 6 is a diagram showing another example of the structure of the pulse skipping detecting circuit
  • FIG. 7 is a circuit diagram of an insulating DC-DC converter
  • FIG. 8 is a circuit diagram of an assumable DC-DC converter.
  • a DC (direct current)-DC (direct current) converter 100 comprises a control circuit 10 , a comparator 20 , a D type flip flop circuit 30 (hereinafter referred to as D-FF 30 ), a switching circuit 40 , a smoothing circuit 50 , a light load detecting circuit 60 , a pulse skipping detecting circuit 70 , a clock circuit 1 , a NOT circuit 2 , an AND circuit 3 , an AND circuit 4 , a level shift circuit 5 , and a load current detecting circuit 6 .
  • D-FF 30 D type flip flop circuit 30
  • the control circuit 10 comprises voltage dividing circuits (resistors) R 11 and R 12 , a high-pass capacitor C 11 , an integrating circuit including an error amplifier 11 , a high-pass capacitor C 12 , a capacitor C 13 for integration, and a resistor R 13 , and a reference power source E 11 .
  • the output terminal Tout of the DC-DC converter 100 is connected to one end of the resistor R 11 .
  • the other end of the resistor R 11 is connected to one end of the resistor R 12 .
  • the other end of the resistor R 12 is grounded.
  • the high-pass capacitor C 11 is connected between both the ends of the resistor R 11 .
  • the connection node between the resistor R 11 and the resistor R 12 is connected to the inverting input terminal ( ⁇ ) of the error amplifier 11 .
  • the connection node between the resistor R 11 and the resistor R 12 is connected to one end of the high-pass capacitor C 12 .
  • the connection node between the resistor R 11 and the resistor R 12 is further connected to one end of the capacitor C 13 for integration.
  • the positive voltage output terminal of the reference power source E 11 is connected to the non-inverting input terminal (+) of the error amplifier 11 .
  • the negative voltage output terminal of the reference power source E 11 is grounded.
  • One end of the resistor R 13 is connected to the other end of the capacitor C 13 .
  • the output end of the error amplifier 11 is connected to the other end of the capacitor C 12 and to the other end of the resistor R 13 .
  • the output end of the error amplifier 11 is connected to the inverting input terminal ( ⁇ ) of the comparator 20 .
  • a voltage (voltage signal) V 1 corresponding to (for example, proportional to) a load current I 1 is supplied to the non-inverting input terminal (+) of the comparator 20 .
  • a signal output from the comparator 20 is supplied to the reset terminal of the D-FF 30 .
  • the signal output from the comparator 20 is further supplied to the data terminal D of a D-FF 71 which constitutes the pulse skipping detecting circuit 70 .
  • the D-FF 71 , a D-FF 72 , and a NAND circuit 73 detect that the comparator 20 has output a reset signal of high level for a two-clock period or longer. That is, the D-FF 71 , the D-FF 72 , and the NAND circuit 73 constitute a circuit for detecting that a PWM signal, which should be periodically output from the D-FF 30 , has been omitted (skipped) continually for two pulses or more.
  • the Q terminal of the D-FF 71 is connected to the data terminal D of the D-FF 72 .
  • the Q terminal of the D-FF 71 is also connected to one input end of the NAND circuit 73 .
  • the Q terminal of the D-FF 72 is connected to the other input end of the NAND circuit 73 .
  • the control circuit 10 , the comparator 20 , and the D-FF 30 constitute a PWM modulating circuit.
  • the PWM modulating circuit In accordance with the output voltage Vout and the load current I 1 , the PWM modulating circuit generates a PWM (Pulse Width Modulated) signal for controlling the switching operation of the switching circuit 40 such that a stable output voltage can be obtained.
  • PWM Pulse Width Modulated
  • the clock output terminal of the clock circuit 1 is connected to the clock input terminal of the D-FF 30 and to the clock input terminals of the D-FF 71 and D-FF 72 .
  • a power source voltage VDD is applied to the data terminal D of the D-FF 30 .
  • the output end of the D-FF 30 is connected to the input end of the level shift circuit 5 . Further, the output end of the D-FF 30 is connected to the input end of the NOT circuit 2 .
  • the output of the NOT circuit 2 is connected to the AND circuit 3 .
  • the output of the NAND circuit 73 is further connected to the AND circuit 3 .
  • the output end of the level shift circuit 5 is connected to the gate of an N-MOSFET 41 , which constitutes a switching element at the high side.
  • the control end of the level shift circuit 5 is connected to the source of the N-MOSFET 41 .
  • a power source voltage VCC is applied to the drain of the N-MOSFET 41 .
  • the source of the N-MOSFET 41 is connected, through an intermediate terminal (connection node), to the drain of an N-MOSFET 42 , which constitutes a switching element at the low side.
  • the source of the N-MOSFET 42 is grounded.
  • the output end of the AND circuit 4 is connected to the gate of the N-MOSFET 42 .
  • the output end of the switching circuit 40 i.e., the connection node (intermediate terminal) between the source of the N-MOSFET 41 and the drain of the N-MOSFET 42 is connected to one end of an inductor (choke coil) L 51 in the smoothing circuit 50 .
  • the other end of the inductor L 51 is connected to the output terminal Tout of the DC-DC converter 100 .
  • the other end of the inductor L 51 is also connected to one end of a smoothing capacitor C 51 .
  • the other end of the smoothing capacitor C 51 is grounded.
  • the output terminal Tout is connected to the load and also connected to one end of the resistor R 11 .
  • the load current detecting circuit 6 comprises a transformer, a hall element, etc.
  • the load current detecting circuit 6 outputs a voltage (voltage signal) V 1 , which corresponds to (for example, is proportional to) the load current I 1 .
  • the output end of the load current detecting circuit 6 is connected to the non-inverting input terminal (+) of the comparator 20 . Further, the output end of the load current detecting circuit 6 is connected to one end of a resistor R 61 in the light load detecting circuit 60 .
  • the other end of the resistor R 61 is connected to the other end of a capacitor C 61 , whose one end is grounded.
  • the output terminal of the load current detecting circuit 6 is connected to the non-inverting input terminal (+) of a comparator 61 .
  • the positive voltage output end of a reference power source E 61 is connected to the inverting input terminal ( ⁇ ) of the comparator 61 .
  • the negative voltage output end of the reference power source E 61 is grounded.
  • the output of the comparator 61 is connected to the other input end of the AND circuit 4 .
  • the heavy load herein is such a heavy load as will require both the N-MOSFETs 41 and 42 constituting the switching circuit 40 to be switched.
  • the D-FF 30 latches the power source voltage VDD.
  • the D-FF 30 outputs a high-side gate signal GH (a signal output from the Q terminal) of high level, as shown in FIG. 2B (at this time, a reset signal COMP from the comparator 20 is at low level, as shown in FIG. 2D ).
  • the level shift circuit 5 shifts (converts) the high level signal GH of the signaling system, which is from the D-FF 30 , into a high level signal of the driving system.
  • the level shift circuit 5 supplies the shifted signal to the gate of the N-MOSFET 41 . In response to this, the N-MOSFET 41 at the high side is switched on.
  • the gate signal GH from the D-FF 30 is inverted by the NOT circuit 2 to a low level signal.
  • the AND circuit 3 closes its gate and outputs a low level signal.
  • the AND circuit 4 outputs a low-side gate signal GL of low level, as shown in FIG. 2C .
  • the N-MOSFET 42 at the low side is switched off.
  • the N-MOSFET 41 at the high side is switched on. Further, almost in synchronization with the rise of the clock signal CLK, the N-MOSFET 42 at the low side is switched off.
  • the load current detecting circuit 6 generates a voltage signal V 1 , which is almost proportional to the load current I 1 .
  • the load current detecting circuit 6 supplies the voltage signal V 1 to the non-inverting input terminal of the comparator 20 .
  • the control circuit 10 outputs a relatively stable difference voltage Vd.
  • the difference voltage Vd supplied to the inverting input terminal of the comparator 20 is relatively stable.
  • the comparator 20 outputs a reset signal COMP of high level, as shown in FIG. 2D .
  • the timing of this output is T 2 .
  • the D-FF 30 is reset and a high-side gate signal GH of low level (OFF level) is applied to the gate of the N-MOSFET 41 at the high side, as shown in FIG. 2B .
  • a low-side gate signal GL of high level (ON level) is applied to the gate of the N-MOSFET 42 at the low side, as shown in FIG. 2C .
  • the N-MOSFET 41 at the high side is switched off, and the N-MOSFET 42 at the low side is switched on.
  • the inductor L 51 continues flowing the load current I 1 to the load through the N-MOSFET 42 that is switched on, by the electromagnetic energy stored therein.
  • the load current I 1 gradually decreases as the time passes. Then, at the timing at which the voltage signal V 1 becomes smaller than the difference voltage Vd, the reset signal COMP output from the comparator 20 becomes low level.
  • the load current I 1 is also large to some extent and the voltage signal V 1 is also relatively large. Therefore, as shown in FIG. 2F , a state that an input LLDIN supplied to the non-inverting input end of the comparator 61 is larger than the reference voltage LLDVTH supplied from the reference power source E 11 continues. Therefore, the output signal LLD from the comparator 61 is stably maintained at high level, as shown in FIG. 2G . Accordingly, a high level signal is applied to one input end of the AND circuit 4 to thereby keep the gate of the AND circuit 4 open. In this case, the output from the NOT circuit 2 is supplied, without being changed, to the N-MOSFET 42 at the low side.
  • the output from the comparator 20 is stably at low level at the timings at which the clock signal CLK rises as shown in FIGS. 2A and 2D , and the D-FF 71 and the D-FF 72 continuously store and output low level signals as shown in FIGS. 2H and 2I .
  • the signal Q 1 and the signal Q 2 input to the NAND circuit 73 are both at low level.
  • the NAND circuit 73 outputs a signal PSD of high level, as shown in FIG. 2J . Therefore, a high level signal is supplied to one input end of the AND circuit 30 to keep the gate of the AND circuit 3 open. Therefore, the output from the NOT circuit 2 is supplied, without being changed, to one input end of the AND circuit 3 . Accordingly, it is the voltage level of the signal output from the Q terminal of the D-FF 30 that controls the switching on/off of the N-MOSFET 42 at the low side.
  • the switching circuit 40 performs the switching operation in accordance with the PWM signal output from the D-FF 30 .
  • the load current is smaller than it is when the load is heavy. Therefore, the charging voltage LLDIN of the capacitor C 61 becomes smaller than the voltage LLDVTH of the reference power source E 61 of the comparator 61 .
  • the comparator 61 outputs a low level signal.
  • the AND circuit 4 is closed and a low level signal is constantly supplied to the gate of the N-MOSFET 42 . Accordingly, the N-MOSFET 42 is kept switched off and only the N-MOSFET 41 at the high side performs the switching operation. As a result, the load current decreases and the synchronous rectification is stopped.
  • the N-MOSFET 42 at the low side which constitutes the switching circuit 40 , is constantly switched off.
  • the N-MOSFET 41 at the high side performs the switching operation in accordance with the PWM signal output from the D-FF 30 .
  • the output voltage Vout increases and the difference voltage Vd output from the error amplifier 11 decreases.
  • the comparator 20 continuously outputs a reset signal COMP of high level, as shown in FIG. 2D .
  • the D-FF 30 is reset by this high level reset signal COMP, and its Q output becomes low level.
  • a high-side gate signal GH of low level is applied to the gate of the N-MOSFET 41 at the high side, as shown in FIG. 2B .
  • a low-side gate signal GL of high level is applied to the gate of the N-MOSFET 42 at the low side, as shown in FIG. 2C .
  • This low-side gate signal GL of high level switches on the N-MOSFET 42 at the low side.
  • the load current I 1 keeps flowing into the inductor L 51 . Since the load has become light, most of the load current I 1 becomes the charging current of the smoothing capacitor C 51 . Thus, the charging voltage of the smoothing capacitor C 51 increases.
  • the current begins to flow in the reverse direction, as shown in FIG. 2E .
  • the current in the reverse direction backward current gradually increases, it will give a large stress on the N-MOSFET 42 .
  • the D-FF 71 stores the reset signal COMP of high level shown in FIG. 2D , output from the comparator 20 , as shown in FIG. 2H .
  • the D-FF 71 stores the reset signal COMP of high level output from the comparator 20 . Then, the D-FF 72 latches the signal Q 1 of high level, which is the output from the D-FF 71 .
  • the low-side gate signal GL or the output signal from the AND circuit 4 becomes low level.
  • the N-MOSFET 42 at the low side is switched off, and the load current I 1 ceases to flow as shown in FIG. 2E .
  • the pulse skipping detecting circuit 70 detects this omission and outputs a signal PSD of low level. Due to the signal PSD of low level, the N-MOSFET 42 at the low side is switched off.
  • the pulse skipping detecting circuit 70 since the N-MOSFET 42 at the low side is switched off, a situation in which the N-MOSFET 42 at the low side is destroyed is prevented.
  • the pulse skipping detecting circuit 70 is structured to operate in accordance with the same clock signal as the clock signal CLK supplied to the D-FF 30 (structured to operate synchronously). However, the pulse skipping detecting circuit 70 needs at least to be able to detect that the D-FF 30 maintains a low level signal without outputting the pulse signal, which should originally be output, for some time or longer (or that the D-FF 30 continues to be reset). In other words, the making of the pulse skipping circuit 70 is arbitrary, as long as it can directly or indirectly measure the period during which the outputting of the pulse signal is stopped.
  • FIG. 3 shows an example of a DC-DC converter 200 , which comprises a D-FF 71 , a D-FF 72 , and a pulse skipping detecting circuit 70 which operate in synchronization with a clock signal CLK 2 independent from the clock signal CLK 1 controlling the D-FF 30 .
  • FIG. 4A to FIG. 4J The operation timing charts of the DC-DC converter 200 shown in FIG. 3 are shown in FIG. 4A to FIG. 4J .
  • the timing charts of FIG. 4A to FIG. 4J are the same as the timing charts according to the first embodiment shown in FIG. 2A to FIG. 2J , except that the D-FF 71 and the D-FF 72 operate in synchronization with the clock signal CLK 2 .
  • FIG. 5 shows an example that the input signal to the D-FF 71 constituting the pulse skipping detecting circuit 70 is the output signal from the D-FF 30 .
  • the input signal to the D-FF 72 is the output signal from the D-FF 71 .
  • the circuit shown in FIG. 5 comprises a NOT circuit 74 .
  • the input signal to the NOT circuit 74 is the output signal from the clock circuit 1 .
  • the input signal to the clock input terminals of the D-FF 71 and D-FF 72 is the output signal from the NOT circuit 74 .
  • the circuits shown in FIG. 1 and FIG. 3 measure the period during which no pulses are output from the D-FF 30 , by measuring the period during which the D-FF 30 is reset.
  • the pulse skipping detecting circuit 70 directly measures the period during which no pulses are output from the D-FF 30 . Then, when the pulse skipping detecting circuit 70 detects the absence of the output, which lasts for a certain period (a two-clock period), it closes the AND circuit 3 .
  • FIG. 6 shows an example that the pulse skipping detecting circuit 70 is constituted by m stages of D-FFs.
  • the pulse skipping detecting circuit 70 outputs a signal for switching off the switching element at the low side, when pulses are not output for an m-clock period continually.
  • the present invention can also be applied to an insulating DC-DC converter 300 as shown in FIG. 7 .
  • This DC-DC converter 300 switches a bridge circuit 43 comprising four N-MOSFETs 43 a to 43 d , which are bridge-connected through intermediate terminals Tm 1 and Tm 2 , by means of two driver circuits 44 a and 44 b .
  • the DC-DC converter 300 supplies ⁇ an input voltage Vin (+)—an input voltage Vin ( ⁇ ) ⁇ to a primary winding W 1 of an insulating transformer TR 1 .
  • the DC-DC converter 300 has the center tap of a secondary winding W 2 connected to a smoothing circuit 50 .
  • the DC-DC converter 300 rectifies the input voltage by switching N-MOSFETs 46 a and 46 b by means of driver circuits 45 a and 45 b .
  • the DC-DC converter 300 supplies the rectified input voltage to the smoothing circuit 50 .
  • a control circuit 10 Based on the output voltage Vout from the smoothing circuit 50 and a load current I 1 supplied to the smoothing circuit 50 , a control circuit 10 , a comparator 20 , and a D-FF 30 generate a PWM signal.
  • the generated PWM signal is supplied to the driver circuits 44 a and 44 b through a logical circuit 48 , an insulating transformer TR 2 , and a DC component cutting capacitor CC.
  • the PWM signal is further supplied to the driver circuits 45 a and 45 b through a logical circuit 49 .
  • a light load detecting circuit 60 When detecting a light load, a light load detecting circuit 60 supplies a low level signal to the logical circuit 49 through an AND circuit 4 . By supplying this low level signal, the light load detecting circuit 60 closes an AND circuit, which constitutes the logical circuit 49 . Then, the light load detecting circuit 60 instructs the driver circuits 45 a and 45 b at the secondary side to switch off the N-MOSFETs 46 a and 46 b , which are the synchronous rectifying switching elements.
  • a pulse skipping detecting circuit 70 supplies a low level signal to the driver circuits 45 a and 45 b through the AND circuit 4 and the logical circuit 49 .
  • the pulse skipping detecting circuit 70 switches off the synchronous rectifying N-MOSFETs 46 a and 46 b , which constitute a switching circuit 46 at the secondary side.
  • the pulse skipping detecting circuit 70 switches off the synchronous rectifying switching elements 46 a and 46 b . By doing so, the pulse skipping detecting circuit 70 can prevent the back flow of the current from the smoothing capacitor C 51 to the synchronous rectifying switching elements 46 a and 46 b through the inductor L 51 .
  • the structures of the pulse skipping detecting circuit 70 shown in FIG. 3 , FIG. 5 , and FIG. 6 can also be applied to the insulating DC-DC converter 300 shown in FIG. 7 .
  • the switching circuit 40 , the components 43 a to 43 d , and the components 44 a and 44 b are constituted by an N-MOSFET. This is not the only case, but they may be constituted by a P-MOSFET or other types of switching element.
  • the power source voltages VCC and VDD may not necessarily be a power source voltage supplied from the outside, but a voltage internally stepped down or stepped up. That is, the power source voltages VCC and VDD are a general voltage, which serves as the reference of operations.
  • the grounding voltage an arbitrary voltage such as the grounding voltage of a chip, the grounding voltage of a substrate, the grounding voltage of a chassis, etc., which will serve as the reference of operations of a circuit, may be set as the grounding voltage.
  • no physical “terminals” need to be present, but the site at which a wire and another wire are connected or at which a wire and another wire cross may be such terminals.
  • the numerical values shown in the above-described embodiments may arbitrarily be changed.
US11/586,861 2005-10-26 2006-10-26 DC-DC converter and control method thereof Active 2028-04-10 US7660134B2 (en)

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JP2007124749A (ja) 2007-05-17

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