US7638418B2 - Wiring substrate of a semiconductor component comprising rubber-elastic pads embedded in said wiring substrate and method for producing the same - Google Patents

Wiring substrate of a semiconductor component comprising rubber-elastic pads embedded in said wiring substrate and method for producing the same Download PDF

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Publication number
US7638418B2
US7638418B2 US11/676,869 US67686907A US7638418B2 US 7638418 B2 US7638418 B2 US 7638418B2 US 67686907 A US67686907 A US 67686907A US 7638418 B2 US7638418 B2 US 7638418B2
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Prior art keywords
rubber
baseplate
wiring substrate
elastic material
external contact
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US11/676,869
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US20070194459A1 (en
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Michael Bauer
Rainer Steiner
Holger Woerner
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Infineon Technologies AG
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/111—Pads for surface mounting, e.g. lay-out
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Definitions

  • the invention relates to a wiring substrate of a semiconductor component comprising external contact pads for external contacts, and to methods for producing the same.
  • solder balls optionally can be applied as external contacts to the external contact pads.
  • Wiring substrates of this type are used for semiconductor component housings, also known as BGA housings (ball grid array) or as LBGA housings (large ball grid array).
  • BGA housings ball grid array
  • LBGA housings large ball grid array
  • One of the problems of the wiring substrates is the reliability with which a connection between the external contact pads of the wiring substrate and a superordinate circuit board can be produced.
  • cyclic thermal loadings cyclic mechanical shear loadings are exerted on the solder connections on account of the presence of different materials having different coefficients of thermal expansion.
  • vibration loadings pressure fluctuations occur in addition to the shear loadings of the cyclic thermal stresses, and may in total lead to microcracks or to the failure of the connection.
  • Flip-chip components, semiconductor chip size housings, and BGA housings have been proposed, which have solder balls which are arranged over an air-filled cavity or are arranged over a cavity filled with an elastic material.
  • So-called “floating pad” solder balls of this type require a very complex cost-intensive fabrication method based on a specific military application and are therefore likewise not suitable for mass production.
  • the cavities or the elastomer-filled cavities are realized by application of additional complex layers to the wiring substrate.
  • the invention provides a wiring substrate of a semiconductor component comprising external contact pads for external contacts, and a method for producing the same by which it is possible to increase the reliability for components with solder balls as external contacts. Moreover, the invention provides a method which is suitable for the mass production of inexpensive semiconductor components.
  • a wiring substrate of a semiconductor component includes: an underside with a wiring structure, a top side with cutouts, a rubber-elastic material arranged in the cutouts, and external contact pads arranged on the rubber-elastic material and configured to be coupled to external contacts.
  • a method for producing a wiring substrate of this type involves pressing the rubber-elastic material pads into a precursor of a polymer plastic during the production process.
  • FIG. 1 shows a schematic cross section through a portion of a wiring substrate according to an exemplary embodiment of the invention
  • FIG. 2 shows a schematic cross section through a baseplate of a precursor of a polymer plastic
  • FIG. 3 shows a schematic cross section through the baseplate in accordance with FIG. 1 after application of rubber-elastic material pads
  • FIG. 4 shows a schematic cross section through the baseplate in accordance with FIG. 2 after application of a metal film
  • FIG. 5 shows a schematic cross section through the baseplate in accordance with FIG. 4 after pressing of the rubber-elastic material pads into the baseplate;
  • FIG. 6 shows a schematic cross section through the baseplate after structuring of the metal film to form cutout pads and feed lines
  • FIG. 7 shows a schematic cross section through a wiring substrate according to an exemplary embodiment of the invention.
  • FIG. 8 shows a schematic cross section through a portion of a semiconductor component of an exemplary embodiment of the invention, mounted onto a superordinate circuit board;
  • FIG. 9 shows a schematic cross section through a portion of a semiconductor component of another exemplary embodiment of the invention, mounted onto a superordinate circuit board.
  • the invention provides a wiring substrate of a semiconductor component comprising external contact pads for fitting external contacts.
  • the rigid wiring substrate comprises an underside with a wiring structure and a top side with cutouts.
  • a rubber-elastic material is arranged in the cutouts, wherein external contact pads are arranged on the rubber-elastic material.
  • This wiring substrate according to the invention differs from the previous solutions by virtue of the fact that no additional layers are to be applied to the wiring substrate. Rather, the wiring substrate itself serves to provide cutouts which can be filled with a corresponding rubber-elastic material, on the top side of which metallic external contact pads can be provided, which are also permitted to take up rigid external contacts and nevertheless enable the external contacts to yield to pressure cyclic loadings and cyclic thermal loadings by virtue of the fact that the rubber-elastic material in the cutouts is compressed and extended, and is likewise able to react to shear loadings by virtue of the fact that the rubber-elastic material in the cutouts permits tilting movements of the metallic contact pads.
  • the top side of the rubber-elastic material together with the top side of the wiring substrate forms a coplanar area.
  • the coplanar area has the advantage that, without transitions, it is possible to produce an arbitrary wiring structure and feed lines to external contact pads, to contact pads and/or to through contacts with high precision and without additional fabrication steps.
  • the cutouts in the substrate can be provided by simply pressing rubber-elastic material pads at the positions provided for external contacts into a precursor of the substrate.
  • the substrate material of the precursor is merely preheated to form a composition having a high viscosity. Consequently, the formation of cutouts and the filling thereof can be realized by simple printing technology and do not require complicated lithographic coating, alignment, exposure, development, fixing and mounting methods.
  • the rubber-elastic material comprises silicones, silicone elastomers, and/or gels, and closed-pore soft-porous materials. These materials have the advantage that they can securely anchor the metallic external contact pads, on the one hand, and the advantage, on the other hand, that they have a compliance and can therefore compensate for inaccuracies and differences in diameter of the solder balls. Moreover, they can withstand impacts, pressure cyclic loadings, and also shear loadings, during corresponding thermal cyclic tests.
  • the cutouts it is relatively unimportant what form the cutouts assume when the elastic material is pressed into the top side of the high-viscosity precursor of the substrate material. It may even be advantageous for the cutouts of a single wiring substrate to have different depths. Where the pressure cyclic loading or the shear cyclic loading is particularly high, it is possible to provide deeper cutouts in the substrate by preparing rubber-elastic material pads having a larger volume prior to being pressed into the high-viscosity material of the substrate.
  • a further feature of the present invention is that the areal extent of the cutout filled with rubber-elastic material is greater than the areal extent of the metallic external contact pads.
  • the effect of the rubber-elastic material is increased further since a compliance between the edge of the metallic contact pads and the edge of the cutouts is also ensured.
  • the wiring substrate has feed lines from the wiring structure to the external contact pads.
  • the feed lines can be made smaller in comparison with the areal extent of the external contact pads, with the result that they can follow the compliance of the rubber-elastic material in the cutouts without tearing or breaking.
  • the wiring substrate may have through contacts through the wiring substrate which are connected to the feed lines and thus enable an electrical access to the external contact pads. Since the elasticity of the passage lines is not so great that they can follow a rubber-elastic deformation, these relatively rigid through contacts are arranged in the vicinity of the rubber-elastic material pads. The through contacts are then connected to the external contact pads via the feed lines.
  • a further possibility for broadening the applicability of the rubber-elastic material under an external contact pad involves accommodating conductive particles in the rubber-elastic material.
  • the conductive particles must firstly have a high deformability, must additionally have a high compliance, and, finally, they must adapt to the expected great movements of the external contact pads.
  • So-called “carbon nanotubes” are suitable for such a contact-making task, without impairing the rubber-elastic properties of the material below the external contact pads.
  • Such carbon nanotubes are hollow tubes having a single-walled or multiwalled hexagonal arrangement of carbon atoms and have a diameter of between a few nanometers and a few hundred nanometers. Since carbon nanotubes have no grain boundaries over their length of ten nanometers to a few millimeters, their deformability and elasticity and compliance are significantly greater than in the case of metal particles that are incorporated in customary electrically conductive plastic connections. The current-carrying capacity of the carbon nanotubes, with a value of 1 ⁇ 10 9 A/cm 2 , is significantly greater as well.
  • the tensile strength is extremely high and, with a value of between 5 ⁇ 10 10 Pa to 5 ⁇ 10 13 Pa, is two or more orders of magnitude higher than in the case of customary metal particles, with the result that an interruption of the contact capability, if such carbon nanotubes are mixed with a rubber-elastic material, extremely low.
  • a further embodiment of the invention provides for the external contact pads to have a solder coating of a lead-free soldering material.
  • the lead-free soldering material firstly improves the environmental compatibility and facilitates the recycling of such wiring substrates, and furthermore has the advantage that external contacts composed of solder balls can be connected to the external contact pads in an extremely simple manner.
  • a semiconductor chip is arranged on the wiring structure of the wiring substrate, which semiconductor chip can be connected by its flip-chip contacts directly to contact pads of the wiring structure.
  • the contact areas with the wiring structure are electrically connected to the wiring structure of the wiring substrate via corresponding bonding connections.
  • the substrate carrying the external contact areas is mechanically closely connected to the semiconductor chip via the plastic housing composition, so that expansion differences between the semiconductor material and the superordinate circuit board, which usually comprises a fiber-reinforced epoxy resin, also affects the solder connection between the wiring substrate of the semiconductor component and the superordinate circuit board.
  • a rubber-elastic compliance according to the invention of the external contact pads can alleviate the mechanical stress between semiconductor component and superordinate circuit board to an extent such that the risk of a faulty contact or of a tearing away of an external contact is avoided.
  • a method for producing a wiring substrate of a semiconductor component comprising external contact pads for fitting external contacts has the following method steps.
  • the first step involves producing a baseplate with through contacts at predetermined positions, wherein the baseplate comprises a precursor of a polymer plastic.
  • a layer composed of rubber-elastic material is selectively applied to a top side of the baseplate, wherein the layer comprises rubber-elastic material pads that are spaced apart from one another.
  • a copper film is then laminated with pressing in of the rubber-elastic material pads with the aid of the external contact pads onto the precursor of the polymer plastic of the baseplate. During this lamination, a coplanar interface is formed between copper film and top side of the baseplate.
  • the copper film can be structured to form external contact pads and feeds to the through contacts. This structuring is effected via lithography and etching technology.
  • the polymer plastic of the baseplate is then cured with formation of a rigid self-supporting wiring substrate.
  • This method has the advantage that the rubber-elastic material pads can be realized by relatively coarse application techniques, such as printing techniques.
  • printing techniques are known as jet printing technique, as screen printing technique or as stencil printing technique and yield a pattern of rubber-elastic material pads on the baseplate.
  • the copper film is supported by corresponding lamination tools during the pressing of the rubber-elastic material pads into the high-viscosity plastic composition of the baseplate.
  • the thickness of the plastic film can therefore correspond to the thickness of the external contact pads.
  • the copper film can practically be structured into the feeds and external contact pads.
  • the polymer plastic of the baseplate Prior to this structuring or else after this structuring, the polymer plastic of the baseplate is cured with formation of a rigid self-supporting wiring substrate. During this curing, the chain molecules of the polymer crosslink to form a spatial pattern that is mechanically extremely stable.
  • the first step likewise involves providing a baseplate with through contacts at predetermined positions.
  • the baseplate represents a precursor of a polymer plastic.
  • Such precursors are polymer plastics which are not yet completely crosslinked and therefore have, at relatively low temperatures, a softening point at which the rigid precursor of a polymer plastic undergoes transition to a composition having a high viscosity.
  • the precursor is solid at room temperature, with the result that a layer composed of rubber-elastic material can be selectively applied to the baseplate, to the top side of the baseplate.
  • the layer has rubber-elastic material pads which are spaced apart from one another and are arranged at predetermined positions of the baseplate.
  • a copper-coated film is then prepared, the metal coating of which has already been structured and has metallic external contact pads.
  • the arrangement of the external contact pads on the film corresponds to the arrangement of the rubber-elastic material pads on the baseplate, with which the structured metal-coated film is then aligned.
  • the film material itself it is advantageous for the film material itself to have a transparent plastic, thereby facilitating the alignment.
  • the rubber-elastic material pads on the top side of the baseplate and the external contact pads are pressed into the precursor of the polymer plastic of the baseplate.
  • the baseplate is heated to the softening point of the precursor of the polymer plastic.
  • a coplanar boundary layer arises between film and top side of the base layer in the process.
  • the external contact connection areas of the external contact pads are uncovered. This can be effected, on the one hand, by the corresponding regions of the copper-coated film being uncovered by the carrier film being resolved at the locations of the external contact pads through photolithographic steps, or by stripping the carrier film from the coplanar boundary layer.
  • the polymer plastic of the baseplate can be cured with formation of a rigid self-supporting wiring substrate. During this curing, the precursor of the polymer plastic is crosslinked to a greater extent and thus acquires a greater dimensional stability.
  • the rubber-elastic material pads are not prepared on the baseplate, but rather are applied on corresponding prepared metallic external contact pads of a structured metal-coated and possibly transparent plastic carrier film.
  • This composite film which already has external contact pads and the rubber-elastic material pads, can then be laminated onto the surface, with penetration of the rubber-elastic material pads into the precursor of the polymer plastic of the baseplate.
  • the transparent plastic carrier film can subsequently be stripped from the coplanar boundary layer that is formed between film and top side of the baseplate.
  • a self-supporting wiring substrate finally arises on whose underside a wiring structure can be applied which is connected to the through contacts and enables bondings to a semiconductor chip to be applied.
  • soldering resist layers can be applied both on the top side and on the underside of the self-supporting wiring substrate in order to leave free only the external contact pads on the top side and corresponding contact pads for connections to the semiconductor chips to be applied.
  • These contact pads are arranged differently on the wiring substrate depending on whether a semiconductor chip is to be connected directly by its flip-chip contacts on the wiring structure, or whether a semiconductor chip is to be connected via bonding connections to the wiring substrate and the wiring structure situated thereon.
  • wiring substrates which do not require any additional rubber-elastic structures that increase the thickness of the substrate can be produced by cost-effective method steps, and a mechanical decoupling between semiconductor component and superordinate circuit board is nevertheless made possible. Since the dimensions of the rubber-elastic material pads can be chosen freely, it is also possible to attain different depths of the cutouts filled with rubber-elastic material in the wiring substrate.
  • the rubber-elastic layer below the external contact pads permits a limited excursion, preferably in the Z-direction, and thus enables stress absorption or damping in the event of vibration loadings.
  • the thickness of the rubber-elastic layer can be varied depending on the required stress, in order thus to achieve an optimum balance between robustness and flexibility of the connection. Within a component, too, it is possible to vary the thickness in order to relieve the loading on relatively highly stressed contacts, e.g., external contacts in the corners of a wiring substrate.
  • FIG. 1 shows a schematic cross section through a portion of a wiring substrate 5 .
  • the wiring substrate 5 has a baseplate 24 having a top side 7 and an underside 6 .
  • a rubber-elastic material 9 is introduced into the baseplate 24 from the top side 7 , which material forms a rubber-elastic material pad 25 and fills a cutout 8 in the top side 7 of the wiring substrate 5 .
  • the rubber-elastic material pad 25 incorporated into the baseplate 24 has a top side 10 forming a coplanar area 11 with the top side 7 of the wiring substrate 5 .
  • a metallic external contact pad 3 is arranged on the coplanar area 11 of the wiring substrate 5 in the region of the rubber-elastic material pads 25 .
  • the areal extent 13 of the external contact pad 3 is less than the areal extent 12 of the rubber-elastic material pad 25 .
  • the rubber-elastic material pad 25 is compliant, shear loadings on account of thermal strains or vibration loadings which act on the external contact pads 3 can be reduced and/or damped.
  • the depth t of the cutouts 8 of a wiring substrate 5 of a semiconductor component can be adapted to the expected loadings, with the result that, for example, corner contacts are buffered with a thicker rubber-elastic layer than external contacts 4 in the center of the semiconductor component.
  • a feed line (not visible in the cross section shown in FIG. 1 ) connects the external contact pad 3 , and thus the external contact 4 fitted onto the latter, to a wiring structure 15 arranged on the underside 6 of the wiring substrate 5 .
  • the top side 7 of the wiring substrate 5 is covered with an upper soldering resist layer 28 such that it leaves free the external contact pads 3 carrying the external contacts 4 .
  • the wiring structure 15 is protected against damage by a lower soldering resist layer 29 .
  • FIGS. 2 to 7 show schematic cross sections through individual components during the production of a wiring substrate for semiconductor components. Components having the same functions as in FIG. 1 are identified by identical reference symbols in FIGS. 1 to 7 and are not discussed separately.
  • the production of such wiring substrates can be undertaken independently of semiconductor chip manufacturers by supplier companies that have previously supplied metallic leadframes.
  • FIG. 2 shows a schematic cross section through a baseplate 24 composed of a precursor of a polymer plastic.
  • the baseplate 24 has a top side 7 and an underside 6 . From the top side 7 to the underside 6 , through contacts 16 are arranged at envisaged positions in the baseplate 24 .
  • the through contacts 16 serve for connecting the external contact pads to be produced on the top side 7 of the baseplate 24 to a wiring structure to be produced on the underside 6 of the baseplate 24 .
  • FIG. 3 shows a schematic cross section through the baseplate 24 in accordance with FIG. 1 after application of rubber-elastic material pads 25 .
  • the rubber-elastic material pads 25 may have a different thickness in order thus to produce cutouts of different depths in the baseplate 24 which are filled with rubber-elastic material 9 .
  • FIG. 4 shows a schematic cross section through the baseplate 24 in accordance with FIG. 2 after application of a metal film 26 .
  • the metal film 26 is applied in order subsequently to be laminated onto the surface 7 of the baseplate 24 .
  • the baseplate 24 composed of a precursor of a polymeric plastic is heated to form a composition having high viscosity and the metal film 26 is laminated on with pressing of the rubber-elastic metal pads 25 into the baseplate 24 .
  • a connection between the through contact 16 and the metal film 26 is also provided in the process.
  • FIG. 5 shows a schematic cross section through the baseplate 24 in accordance with FIG. 4 after pressing of the rubber-elastic material pads 25 into the baseplate 24 , giving rise to a coplanar surface 11 comprising the top sides 10 of the rubber-elastic material pads 25 and the top side 7 of the baseplate 24 .
  • the rubber-elastic material pads 25 are pressed into the high-viscosity precursor of the polymer plastic of the baseplate 24 , the rubber-elastic metal pads 25 penetrate into the baseplate 24 as far as a depth t. Even though the depth t is identical in this example for the three rubber-elastic metal pads 25 shown, it can nevertheless, as already mentioned above, also be different and depend on the expected loading of the external contact pads 3 to be fitted.
  • FIG. 6 shows a schematic cross section through the baseplate 24 after structuring of the metal film 26 from FIG. 5 to form external contact pads 3 and feed lines 14 .
  • the feed lines 14 are narrow conductor tracks which connect the external contact pads 3 to corresponding through contacts 16 which are positioned such that they do not adversely affect the deformability of the rubber-elastic metal pads 25 .
  • the latter are produced from insulating silicones, silicone elastomers, gels or soft-porous insulating materials and are not suitable for the conduction of the electric current.
  • the pads may be filled with correspondingly compliantly electrically conductive particles, known as carbon nanotubes in the literature, with the result that through contacts 16 can also be provided underneath, i.e., in the region of the rubber-elastic metal pads 25 , in the baseplate 24 .
  • FIG. 7 shows a schematic cross section through a wiring substrate 5 in accordance with one embodiment of the invention.
  • the precursor of a wiring substrate 5 as shown in FIG. 6 is completed by the application of an upper soldering resist layer 28 to the top side 7 of the wiring plate 5 whilst leaving free the external contact pads 3 .
  • the wiring structure 15 is applied to the underside 6 and, for its part, can be protected against damage by a lower soldering resist layer 29 .
  • This lower wiring structure 15 serves to electrically connect the external contact pads 3 on the top side 7 of the wiring substrate to a semiconductor chip on the underside 6 of the wiring substrate 5 via the through contacts 16 .
  • FIG. 8 shows a schematic cross section through a portion of a semiconductor component 1 of a first embodiment of the invention, which is mounted onto a superordinate circuit board 30 .
  • the wiring substrate 5 with its rubber-elastically cushioned external contact pad 3 has an external contact 4 .
  • the external contact 4 is connected via the external contact pads 3 to a feed line 14 , and also a through contact 16 of a wiring structure 15 on the underside 6 of the wiring substrate 5 .
  • the wiring structure 15 has contact pads 27 , which are connected to a flip-chip contact 21 of a semiconductor chip 17 in this semiconductor component 1 of the first embodiment of the invention.
  • the external contact 4 for its part, is connected to a solder pad 31 of a conductor track structure 32 on the top side 33 of the superordinate circuit board 30 .
  • a solder pad 31 of a conductor track structure 32 on the top side 33 of the superordinate circuit board 30 As a result of the rubber-elastic material pad 25 buried in the wiring substrate 5 of the semiconductor component 1 , pressure cyclic loadings in the form of vibrations and shear loadings as a result of thermal stresses can be rubber-elastically cushioned and absorbed, with the result that this connection between the semiconductor component 1 and the superordinate circuit board 30 via such a rubber-elastically cushioned external contact 4 have a higher reliability.
  • FIG. 9 shows a schematic cross section through a portion of a semiconductor component 2 of a second embodiment of the invention, which is mounted onto a superordinate circuit board 30 .
  • Components having the same functions as in FIG. 8 are identified by identical reference symbols and are not discussed separately.
  • This second embodiment of a semiconductor component 2 according to the invention differs from the semiconductor component shown in FIG. 8 by virtue of the fact that the active top side 22 of the semiconductor chip 18 has contact areas 23 which are connected via a bonding connection 19 to the contact pad 27 of the wiring structure 15 on the underside 6 of the wiring substrate 5 . Furthermore, the rear side 34 of the semiconductor chip 18 is mechanically connected to the wiring substrate 5 via an adhesive layer 35 . The semiconductor chip 18 with the bonding connection 19 , and also the structures on the underside 6 of the wiring substrate 5 are surrounded by a plastic housing composition 20 that protects the entire construction of the semiconductor component 2 against damage.

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
US11/676,869 2004-08-19 2007-02-20 Wiring substrate of a semiconductor component comprising rubber-elastic pads embedded in said wiring substrate and method for producing the same Expired - Fee Related US7638418B2 (en)

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DE102004040414.3 2004-08-19
DE102004040414A DE102004040414B4 (de) 2004-08-19 2004-08-19 Verfahren zur Herstellung eines Verdrahtungssubstrats eines Halbleiterbauteils mit Außenkontaktanschlussflecken für Außenkontakte
PCT/DE2005/001278 WO2006017998A2 (fr) 2004-08-19 2005-07-20 Support de cablage d'un element semi-conducteur comportant des zones de raccordement pour des contacts externes et procede de realisation associe

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110062575A1 (en) * 2009-09-11 2011-03-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Cavity in PCB Containing Encapsulant or Dummy Die Having CTE Similar to CTE of Large Array WLCSP
US9960130B2 (en) 2015-02-06 2018-05-01 UTAC Headquarters Pte. Ltd. Reliable interconnect
WO2022236216A1 (fr) * 2021-05-06 2022-11-10 Qualcomm Technologies, Inc. Dissipateur thermique de puce à haute puissance avec broche thermique verticale
US11929299B2 (en) 2021-05-06 2024-03-12 Qualcomm Incorporated High-power die heat sink with vertical heat path
US11948853B2 (en) 2021-05-06 2024-04-02 QUALCOMM Technologies Incorporated High-power die heat sink
US11967578B2 (en) 2021-01-29 2024-04-23 Samsung Electronics Co., Ltd. Semiconductor package including post

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114980492A (zh) * 2022-06-28 2022-08-30 昆山国显光电有限公司 线路板组件、显示屏及电子设备

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5759047A (en) 1996-05-24 1998-06-02 International Business Machines Corporation Flexible circuitized interposer with apertured member and method for making same
US5900674A (en) 1996-12-23 1999-05-04 General Electric Company Interface structures for electronic devices
US6020220A (en) 1996-07-09 2000-02-01 Tessera, Inc. Compliant semiconductor chip assemblies and methods of making same
US6265245B1 (en) 1991-06-04 2001-07-24 Micron Technology, Inc. Compliant interconnect for testing a semiconductor die
US20020025587A1 (en) 2000-06-27 2002-02-28 Seiko Epson Corporation Semiconductor device and method for manufacturing the same
US20020030288A1 (en) 1998-03-23 2002-03-14 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US6358836B1 (en) * 2000-06-16 2002-03-19 Industrial Technology Research Institute Wafer level package incorporating elastomeric pads in dummy plugs
US6399896B1 (en) 2000-03-15 2002-06-04 International Business Machines Corporation Circuit package having low modulus, conformal mounting pads
US6417029B1 (en) 1996-12-12 2002-07-09 Tessera, Inc. Compliant package with conductive elastomeric posts
US20020192865A1 (en) 1997-03-27 2002-12-19 Hitachi, Ltd. And Hitachi Hokkai Semiconductor, Ltd. Process for mounting electronic device and semiconductor device
DE10134011A1 (de) 2001-07-12 2003-01-30 Infineon Technologies Ag Trägersubstrat, das zur Kontaktierung mit einer integrierten Schaltung vorgesehen ist
US20030121698A1 (en) 2001-12-27 2003-07-03 Nec Corporation Semiconductor device and printed wiring board having electrode pads
US20030127747A1 (en) * 2001-12-26 2003-07-10 Ryoichi Kajiwara Semiconductor device and manufacturing method thereof
US20030168748A1 (en) * 2002-03-08 2003-09-11 Mitsuaki Katagiri Semiconductor device
US20030201534A1 (en) 2000-02-10 2003-10-30 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US20040147060A1 (en) 2003-01-29 2004-07-29 Jeong-Woo Seo Ball grid array package having improved reliability and method of manufacturing the same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6433948A (en) * 1987-07-29 1989-02-03 Hitachi Chemical Co Ltd Wiring board for mounting semiconductor element
JPH0846084A (ja) * 1994-08-02 1996-02-16 Shinko Electric Ind Co Ltd 表面実装型半導体パッケージ及びその製造方法並びに半導体装置
JP2001094227A (ja) * 1999-09-20 2001-04-06 Shinko Electric Ind Co Ltd 半導体チップ実装用の配線基板と該基板を用いた半導体チップの実装方法
JP2001217514A (ja) * 2000-02-03 2001-08-10 Denso Corp 多層配線基板
US6417019B1 (en) * 2001-04-04 2002-07-09 Lumileds Lighting, U.S., Llc Phosphor converted light emitting diode
JP4105409B2 (ja) * 2001-06-22 2008-06-25 株式会社ルネサステクノロジ マルチチップモジュールの製造方法
JP3952375B2 (ja) * 2002-03-25 2007-08-01 富士通株式会社 チップ実装体、チップ実装体の製造方法、及び、電子機器
JP2003318322A (ja) * 2002-04-25 2003-11-07 Matsushita Electric Ind Co Ltd インターポーザ基板およびその製造方法、ならびに半導体装置およびその製造方法
JP2004128364A (ja) * 2002-10-07 2004-04-22 Renesas Technology Corp 半導体パッケージおよび半導体パッケージの実装構造体
JP3905032B2 (ja) * 2002-12-20 2007-04-18 シャープ株式会社 半導体装置、および、その製造方法

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6265245B1 (en) 1991-06-04 2001-07-24 Micron Technology, Inc. Compliant interconnect for testing a semiconductor die
US5759047A (en) 1996-05-24 1998-06-02 International Business Machines Corporation Flexible circuitized interposer with apertured member and method for making same
US6020220A (en) 1996-07-09 2000-02-01 Tessera, Inc. Compliant semiconductor chip assemblies and methods of making same
US6417029B1 (en) 1996-12-12 2002-07-09 Tessera, Inc. Compliant package with conductive elastomeric posts
US5900674A (en) 1996-12-23 1999-05-04 General Electric Company Interface structures for electronic devices
US20020192865A1 (en) 1997-03-27 2002-12-19 Hitachi, Ltd. And Hitachi Hokkai Semiconductor, Ltd. Process for mounting electronic device and semiconductor device
US20020030288A1 (en) 1998-03-23 2002-03-14 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument
US20030201534A1 (en) 2000-02-10 2003-10-30 Epic Technologies, Inc. Compliant, solderable input/output bump structures
US6399896B1 (en) 2000-03-15 2002-06-04 International Business Machines Corporation Circuit package having low modulus, conformal mounting pads
US6358836B1 (en) * 2000-06-16 2002-03-19 Industrial Technology Research Institute Wafer level package incorporating elastomeric pads in dummy plugs
US20020025587A1 (en) 2000-06-27 2002-02-28 Seiko Epson Corporation Semiconductor device and method for manufacturing the same
DE10134011A1 (de) 2001-07-12 2003-01-30 Infineon Technologies Ag Trägersubstrat, das zur Kontaktierung mit einer integrierten Schaltung vorgesehen ist
US20030127747A1 (en) * 2001-12-26 2003-07-10 Ryoichi Kajiwara Semiconductor device and manufacturing method thereof
US20030121698A1 (en) 2001-12-27 2003-07-03 Nec Corporation Semiconductor device and printed wiring board having electrode pads
US20030168748A1 (en) * 2002-03-08 2003-09-11 Mitsuaki Katagiri Semiconductor device
US20040147060A1 (en) 2003-01-29 2004-07-29 Jeong-Woo Seo Ball grid array package having improved reliability and method of manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Ray Fillion, Laura Meyer, Kevin Durocher, Slawomir Rubinsztajn, David Shaddock, "Stress Free Area Array Structures for Flip Chips and Chip Scale Devices," 14th European Microelectronics and Packaging Conference & Exhibition Friedrichshafen, Germany, Jun. 23-25, 2003, GE Global Research Center, Niskayuna, NY.

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110062575A1 (en) * 2009-09-11 2011-03-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Cavity in PCB Containing Encapsulant or Dummy Die Having CTE Similar to CTE of Large Array WLCSP
US8895358B2 (en) * 2009-09-11 2014-11-25 Stats Chippac, Ltd. Semiconductor device and method of forming cavity in PCB containing encapsulant or dummy die having CTE similar to CTE of large array WLCSP
US9960130B2 (en) 2015-02-06 2018-05-01 UTAC Headquarters Pte. Ltd. Reliable interconnect
US11967578B2 (en) 2021-01-29 2024-04-23 Samsung Electronics Co., Ltd. Semiconductor package including post
WO2022236216A1 (fr) * 2021-05-06 2022-11-10 Qualcomm Technologies, Inc. Dissipateur thermique de puce à haute puissance avec broche thermique verticale
US11929299B2 (en) 2021-05-06 2024-03-12 Qualcomm Incorporated High-power die heat sink with vertical heat path
US11948853B2 (en) 2021-05-06 2024-04-02 QUALCOMM Technologies Incorporated High-power die heat sink

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US20070194459A1 (en) 2007-08-23
DE102004040414B4 (de) 2006-08-31
WO2006017998A2 (fr) 2006-02-23
EP1779428A2 (fr) 2007-05-02
EP1779428B1 (fr) 2015-05-27
WO2006017998A3 (fr) 2006-08-03
JP5059607B2 (ja) 2012-10-24
CN101048866A (zh) 2007-10-03
DE102004040414A1 (de) 2006-03-02
KR20070042580A (ko) 2007-04-23
CN100530625C (zh) 2009-08-19
JP2008510309A (ja) 2008-04-03
KR100889840B1 (ko) 2009-03-20

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