US7376801B2 - Power saving data storage circuit, data writing method in the same, and data storage device - Google Patents

Power saving data storage circuit, data writing method in the same, and data storage device Download PDF

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US7376801B2
US7376801B2 US10/505,431 US50543104A US7376801B2 US 7376801 B2 US7376801 B2 US 7376801B2 US 50543104 A US50543104 A US 50543104A US 7376801 B2 US7376801 B2 US 7376801B2
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data
control signal
new data
write
section
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US20050235118A1 (en
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Katsutoshi Moriyama
Hironobu Mori
Hisanobu Tsukazaki
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Sony Corp
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Sony Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2263—Write conditionally, e.g. only if new data and old data differ

Definitions

  • the present invention relates to a data storage circuit for storing predetermined data, a data writing method in the data storage circuit, and a data storage device.
  • a data storage circuit composed of a combination of a large number of storage elements is provided in a semiconductor device such as a CPU and a memory IC. Data are stored in the data storage circuit so as to execute various types of processing.
  • the storage elements in such a data storage circuit are normally configured so that 1-bit data is stored in each of the storage elements. More specifically, the storage element is capable of keeping two different states. When one state is represented by “0” and the other state by “1”, data of “0” or “1” is stored by keeping any one of the states. A large number of such storage elements are provided to enable the storage of data in an amount corresponding to the number of provided storage elements.
  • Storage elements having a wide variety of structures are known as such storage elements.
  • a storage element of a flash memory which consists of a N-channel MOSFET (Metal Oxide Silicon Field Effect Transistor), is capable of storing data “0” and “1” while a state where charges are accumulated in a floating gate layer provided for a gate electrode section is represented by “1” and a state where no charge is accumulated in the floating gate layer is represented by “0” or vice versa.
  • MOSFET Metal Oxide Silicon Field Effect Transistor
  • a storage element of a MRAM Magnetic Random Access Memory
  • MRAM Magnetic Random Access Memory
  • a storage element of a MRAM Magnetic Random Access Memory
  • MRAM Magnetic Random Access Memory
  • a state where the direction of magnetization of a free magnetization layer is anti-parallel to that of a fixed magnetization layer is represented by “1” and a parallel state by “0” or vice versa.
  • a state of change is induced by application of a predetermined voltage to the storage element or by allowing a current to pass therethrough.
  • the storage element is forced into a predetermined state by application of a predetermined voltage to the storage element or by allowing a current to pass therethrough, regardless of whether existing data that is previously stored in the storage element is “0” or “1”, thereby storing new data.
  • the storage element used for the flash memory or the MRAM described above requires a considerable amount of electric power in view of its structure to cause a change of state in order to write new data. Therefore, wasteful power consumption is increased in the data storage circuit, such as the flash memory or the MRAM, by the corresponding amount to further hinder power saving.
  • a data storage circuit of the present invention is configured to have a comparison section for reading out existing data stored in a storage element to compare the existing data and new data with each other prior to writing of the new data to the storage element, and so that, in the comparison section, if the exiting data and the new data are identical with each other, the writing to the storage element is not performed, and if the existing data and the new data are not identical with each other, the new data is written to the storage element.
  • the data storage circuit is also characterized by including a control signal generating section for generating a readout control signal for performing readout control of the existing data and a write control signal for performing write control of the new data, and being configured so that the existing data and the new data are compared with each other in the comparison section in accordance with the control signal from the control signal generating section.
  • a data writing method in the data storage circuit of the present invention it is arranged so that readout processing for reading out existing data stored in a predetermined storage element is performed prior to write processing of new data to the storage element so as to compare the exiting data and the new data with each other, and if the existing data and the new data are identical with each other, the write processing to the storage element is not performed, and if the data not identical, the write processing of the new data to the storage element is performed.
  • the data writing method is also characterized by generating a readout control signal and a write control signal in accordance with a write signal input to the data storage circuit so as to read out the existing data in accordance with the readout control signal and to compare it with the new data in accordance with the write control signal.
  • a data storage device of the present invention is provided with a comparison section for reading out existing data stored in a storage element to compare the existing data and new data with each other prior to writing of the new data to the storage element, and the device is configured so that, in the comparison section, if the exiting data and the new data are identical with each other, the writing to the storage element is not performed, and if the existing data and the new data are not identical with each other, the new data is written to the storage element.
  • the data storage device is also characterized by being provided with a control signal generating section for generating a readout control signal for performing readout control of the existing data and a write control signal for performing write control of the new data, and in that the existing data and the new data are compared with each other in the comparison section in accordance with the control signal from the control signal generating section.
  • the data storage device is also characterized in that the comparison section thereof is provided with: a new data retention section for temporarily retaining the new data; an existing data retention section for temporarily retaining the existing data; and a write enable signal generating section for comparing the new data retained in the new data retention section and the exiting data retained in the existing data retention section with each other to control an output of the write enable signal, and the new data is temporarily retained in the new data retention section while the existing data is temporarily retained in the exiting data retention section in accordance with the readout control signal output from the control signal generating section so as to compare the new data retained in the new data retention section and the existing data retained in the existing data retention section with each other in accordance with the write control signal output from the control signal generating section.
  • FIG. 1 is a block diagram showing a data storage circuit according to the present invention.
  • FIG. 2 is a circuit diagram explaining a configuration of a control signal generating section.
  • FIG. 3 is an explanatory view of a readout control signal and a write control signal generated at the control signal generation section.
  • FIG. 4 is a circuit diagram explaining a configuration of a comparison section.
  • FIG. 5 is a flow chart of a data writing process in the data storage circuit.
  • a data storage circuit and a data storage device formed so as to include the data storage circuit according to the present invention respectively include a storage section consisting of a combination of a plurality of storage elements. If data is written to the data storage circuit and the data storage device, existing data already stored in a predetermined storage element is read out in advance before new data is stored in the storage element so as to compare the existing data and the new data with each other. If they are identical with each other, the new data is not written; only if the dates are not identical with each other, the new data is written.
  • the power required to write the data to the storage element can be approximately halved, which greatly contributes to the power saving of the data storage circuit and the data storage device.
  • the data storage device is formed by providing the data storage circuit on a semiconductor substrate.
  • an explanation regarding the data storage circuit provided on the semiconductor substrate also serves as an explanation regarding the data storage device.
  • the data storage circuit is not limited to those provided on the semiconductor substrate; it may be provided on an appropriate substrate other than the semiconductor substrate.
  • the structural form of the data storage device is not limited to that in which the data storage circuit is provided on a single semiconductor substrate; necessary circuits may be provided on a plurality of semiconductor substrates so as to be connected through an appropriate electric wiring.
  • a comparison for determining if the exiting data and the new data are identical with each other or not is performed in the comparison section provided in the data storage circuit. After the existing data and the new data are fetched into the comparison section, comparison processing is executed.
  • a control signal generating section for detecting a write signal so as to generate a control signal described below is provided in the data storage circuit.
  • the write signal is a so-called write enable signal.
  • control signal generating section generates a readout control signal for performing readout control of the existing data and a write control signal for performing write control of the new data as a result of the detection of the write signal.
  • control signal generating section first outputs the readout control signal so as to read out the existing data in the predetermined storage element and to fetch it into the comparison section. Subsequently, the control signal generating section outputs the write control signal to compare the existing data and the new data fetched into the comparison section with each other. If the existing data and the new data are not identical with each other, the comparison section outputs the write enable signal so as to execute writing of the new data to the storage element.
  • the comparison section does not output the write enable signal. Accordingly, the writing of new data to the storage element is not executed, so that wasteful power consumption is suppressed.
  • FIG. 1 is a block diagram showing a data storage circuit 1 according to this embodiment.
  • the data storage circuit 1 includes: a storage section 3 having a storage element area 2 in which a plurality of storage elements M are appropriately arranged; a control signal generating section 4 for detecting a write signal 7 s that brings the storage section 3 into an input receiving state of new data; and a comparison section 5 for performing write control of the new data, which is stored in a predetermined one of the storage elements M of the storage section 3 , to the storage element M in accordance with the detection of the write signal 7 s.
  • a new data input line 6 for inputting the new data to the storage section 3 is connected while a write signal line 7 for inputting a write signal 7 s to the control signal generating section 4 is also connected.
  • a ferromagnetic tunnel junction element is used as each of the storage elements M.
  • the ferromagnetic tunnel junction elements are provided at the crossing points between a plurality of word lines 8 and bit lines 9 provided in a grid pattern in the storage element area 2 .
  • sense lines for reading-out are provided in parallel to the word lines 8 so as to read out data stored in the ferromagnetic tunnel junction elements.
  • the storage element M is a ferromagnetic tunnel junction element
  • the storage element M is not limited to the ferromagnetic tunnel junction element.
  • a known storage element such as a N-channel MOSFET constituting a flash memory may also be used.
  • the word lines 8 and the bit lines 9 may be appropriately provided in accordance with a writing mode and a reading-out mode of the data to/from the storage elements M.
  • Column drive control sections 10 are connected to an end of each of the word lines 8 and an end of each of the sense lines. Each of the column drive control sections 10 is connected to a column decoder 11 so as to operate in accordance with a control signal from the column decoder 11 . Moreover, a row drive control section 12 is connected to an end of each of the bit lines 9 . Each of the row drive control sections 12 is connected to a row decoder 13 so as to operate in accordance with a control signal from the row decoder 13 .
  • a column address data output section 14 is connected to the column decoder 11 , whereas a row address data output section 15 is connected to the row decoder 13 .
  • An external input signal for specifying a predetermined one of the storage elements M is configured to be input from the column address data output section 14 to the column decoder 11 as a column address data signal 14 s and to be input from the row address data output section 15 to the row address decoder 13 as a row address data signal 15 s.
  • the data storage circuit 1 may be configured to include the column address data output section 14 and the row address data output section 15 .
  • the column decoder 11 performs decoding in accordance with the input column address data signal 14 s so as to operate any one of the column drive control sections 10 connected to the column decoder 11 .
  • the row decoder 13 performs decoding in accordance with the input row address data signal 15 s so as to operate any one of the row drive control sections 12 connected to the row decoder 13 .
  • the storage element M which is positioned at a crossing point between the word line 8 or the sense line connected to the column drive control section 10 currently being operated and the bit line 9 connected to the row drive control section 12 similarly currently being operated, is brought into an operating state so as to enable the write/readout of data to/from the storage element M.
  • the column address data signal 14 s output from the column address data output section 14 and the row address data signal 15 s output from the row address data output section 15 bring the storage element M, to/from which writing or reading-out is performed, into an operating state in advance.
  • the new data input lines 6 are connected to the row drive control sections 12 , respectively. Then, the predetermined storage element M is brought into an operating state as described above and a new data signal 6 s is input to the row drive control section 12 through the new data input line 6 , so that the row drive control section 12 allows a current to pass through the bit line 9 in a predetermined direction, thereby writing the new data to the storage element M.
  • the storage element M for reading out the existing data stored in the storage element M, the storage element M, from which reading-out is performed, is brought into an operating state as described above.
  • a resistance value of the storage element M is detected by using the sense line so as to generate an existing data signal in accordance with the resistance value detected in the column drive control section 10 and to output it to the column decoder 11 .
  • the data storage circuit 1 is normally in a protected state where a storage state in the storage element M is prevented from being automatically varied by an erroneous input of a noise and the like.
  • the storage section 3 of the data storage circuit 1 allows the input of the new data only when the write signal 7 s is input to enable the writing of the new data.
  • a readout control signal 16 s and a write control signal 17 s are generated in the control signal generating section 4 for detecting the write signal 7 s in the data storage circuit 1 .
  • the readout control signal 16 s is a control signal for performing reading-out of the existing data from the storage element M to which the new data is to be stored.
  • the write control signal 17 s is a control signal for performing writing of the new data to the storage element M.
  • a readout control signal generating section 18 and a write control signal generating section 19 are provided in parallel in the control signal generating section 4 so as to generate the readout control signal 16 s and the write control signal 17 s from the write signal 7 s.
  • the write signal line 7 is branched into a readout control signal generating line 20 and a write control signal generating line 21 so as to input the write signal 7 s to the readout control signal generating section 18 and the write control signal generating line 19 , respectively.
  • the readout control signal 16 s is generated in the readout control signal generating section 18
  • the write control signal 17 s is generated in the write control signal generating section 19 .
  • the readout-control signal generating line 20 is further branched into a first readout control signal generating line 20 a and a second readout control signal generating line 20 b .
  • the first readout control signal generating line 20 a and the second readout control signal generating line 20 b are connected to an AND gate 22 which generates the readout control signal 16 s.
  • a NOT gate 23 is provided in the middle of the second readout control signal generating line 20 b . Furthermore, a resistor 24 is provided on the output side of the NOT gate 23 to which an end of a capacitor 25 is connected.
  • the readout control signal generating section 18 detects a rise of the write signal 7 s to generate the readout control signal 16 s so as to output it from the readout control signal line 16 connected to the AND gate 22 .
  • the write control signal generating line 21 is also further branched into a first write control signal generating line 21 a and a second write control signal generating line 21 b .
  • the first write control signal generating line 21 a and the second write control signal generating line 21 b are connected to a NOR gate 26 which generates the write control signal 17 s.
  • a NOT gate 27 is provided in the middle of the second write control signal generating line 21 b . Furthermore, a resistor 28 is provided on the output side of the NOT gate 27 , to which an end of a capacitor 29 is connected. As a result, as shown in FIG. 3 , the write control signal generating section 19 detects a fall of the write signal 17 s to generate the write control signal 17 s so as to output it from the write control signal line 17 connected to the NOR gate 26 .
  • the readout control signal 16 s and the write control signal 17 s can be generated from the same write signal 7 s , the readout control signal 16 s and the write control signal 17 s , which have a predetermined difference in time therebetween, can be generated with good accuracy with an extremely simple structure. Therefore, the control of the comparison section 5 described below by the readout control signal 16 s and the write control signal 17 s can be ensured.
  • the readout control signal line 16 and the write control signal line 17 are connected to the column decoder 11 and the row decoder 13 so as to control the column decoder 11 and the row decoder 13 in accordance with the readout control signal 16 s and the write control signal 17 s in a manner described below. Furthermore, the readout control signal line 16 and the write control signal line 17 are respectively connected to each of the column drive control sections 10 and each of the row drive control sections 12 so as to control the column drive control sections 10 and the row drive control sections 12 in accordance with the readout control signal 16 s and the write control signal 17 s in a manner described below.
  • the readout control signal line 16 and the write control signal line 17 are also connected to the comparison section 5 so that the readout control signal 16 s and the write control signal 17 s are input to the comparison section 5 to control the comparison section 5 .
  • the new data input line 6 and an existing data input line 30 that is connected to the row decoder 11 are connected to the comparison section 5 so as to input thereto the new data signal 6 s and an existing data signal 30 s to be compared with each other.
  • the comparison section 5 is configured with a new data signal retention section 31 for temporarily retaining the new data signal 6 s input through the new data input line 6 ; an existing data signal retention section 32 for temporarily retaining the existing data signal 30 s input through the existing data input line 30 ; and a write enable signal generating section 33 for comparing the new data signal 6 s retained in the new data signal retention section 31 and the existing data signal 30 s retained in the existing data signal retention section 32 with each other.
  • the new data signal retention section 31 is configured with an input control transistor 34 for controlling an input of the new data signal 6 s to the new data signal retention section 31 ; and a retention section 35 for retaining the new data signal 6 s input to the new data signal retention section 31 .
  • the readout control signal line 16 is connected to a gate electrode of the input control transistor 34 .
  • the readout control signal 16 s is input to the gate electrode so that the new data signal 6 s is input from the new data input line 6 connected to the input control transistor 34 to the retention section 35 connected to the input control transistor 34 .
  • the retention section 35 is a simple storage circuit consisting of a latch composed of the combination of two inverters 36 , which is capable of retaining the new data signal 6 s for a certain period of time.
  • the existing data signal retention section 32 is also configured with an input control transistor 37 for controlling an input of the existing data signal 30 s to the existing data signal retention section 32 ; and a retention section 38 for retaining the existing data signal 30 s input to the existing data signal retention section 32 .
  • the readout control signal line 16 is connected to a gate electrode of the input control transistor 37 .
  • the readout control signal 16 s is input to the gate electrode so that the existing data signal 30 s is input from the existing data input line 30 connected to the input control transistor 37 to the retention section 38 connected to the input control transistor 37 .
  • the retention section 38 is a simple storage circuit consisting of a latch composed of a combination of two inverters 40 , 40 , which is capable of retaining the existing data signal 30 s for a certain period of time.
  • the write enable signal generating section 33 is configured with an output control transistor 41 for controlling an output of the new data signal 6 s from the new data signal retention section 31 ; an output control transistor 42 for controlling an output of the existing data signal 30 s from the existing data signal retention section 32 ; and an XOR gate 43 for inputting the new data signal 6 s and the existing data signal 30 s output respectively from the retention sections 35 and 38 by the output control transistors 41 and 42 thereto.
  • the write control signal line 17 is connected to gate electrodes of the output control transistors 41 and 42 , respectively.
  • the write control signal 17 s is input to the output control transistors 41 and 42 through the write control signal line 17 so as to output the new data signal 6 s and the existing data signal 30 s from the retention sections 35 and 38 to the XOR gate 43 .
  • the XOR gate 43 outputs the write enable signal 44 s from the write enable signal line 44 connected to the XOR gate 43 .
  • the new data signal 6 s and the existing data signal 30 s are identical with each other, it does not output the write enable signal 44 s.
  • an erroneous operation protect signal is input to the XOR gate 43 so as to prevent the XOR gate 43 from erroneously outputting the write enable signal 44 s .
  • the control transistors 41 , 42 and 45 are used to control the erroneous operation protect signal.
  • the write enable signal line 44 is configured so that it is connected to each of the column drive control sections 10 and each of the row drive control sections 12 so as to input the write enable signal 44 s to each of the column drive control sections 10 and each of the row drive control sections 12 .
  • step S 1 an operation for storing the new data in the data storage circuit 1 configured as described above.
  • the new data signal 6 s is input from the new data input line 6 (step S 2 ) while the write signal 7 s is input from the write signal line 7 (step S 3 ).
  • the control signal generating section 4 first outputs the readout control signal 16 s through the readout control signal line 16 (step S 4 ) so as to input it to the column decoder 11 , the row decoder 13 , each of the column drive control sections 10 , and each of the row drive control sections 12 , thereby reading out the existing data stored in the predetermined storage element M to the column decoder 11 .
  • the column decoder 11 outputs the readout existing data as the existing data signal 30 s to the existing data input line 30 connected to the column decoder 11 (step S 5 ). This corresponds to readout processing.
  • the control signal generating section 4 also inputs the readout control signal 16 s to the comparison section 5 .
  • the comparison section 5 in response to the input of the readout control signal 16 s , the new data signal 6 s is input to the new data signal retention section 31 of the comparison section 5 so as to be temporarily retained therein, whereas the existing data signal 30 s is input to the existing data signal retention section 32 so as to be temporarily retained therein (step S 6 ).
  • the control signal generating section 4 After a predetermined period of time, the control signal generating section 4 generates the write control signal 17 s in accordance with the write signal 7 s so as to input the write control signal 17 s to the comparison section 5 (step S 7 ).
  • the write control signal 17 s regulates the write signal 7 s so that it is output from the control signal generating section 4 after an elapse of a sufficient period of time to input the new data signal 6 s and the existing data signal 30 s to the comparison section 5 by the readout control signal 16 s.
  • the comparison section 5 outputs and compares the new data signal 6 s retained in the new data signal retention section 31 and the exiting data signal 30 s retained in the existing data signal retention section 32 in accordance with the input write control signal 17 s (step S 8 ).
  • the comparison section 5 outputs the write enable signal 44 s (step S 9 ).
  • the write control signal 17 s output from the control signal generating section 4 is also input to the column decoder 11 , the row decoder 13 , each of the column drive control sections 10 and each of the row drive control sections 12 through the write control signal line 17 .
  • the write enable signal 44 s output from the comparison section 5 is input to each of the column drive control sections 10 and each of the row drive control sections 12 through the write enables signal line 44 , so that the storage section 3 writes the new data to the predetermined storage element M (step S 10 ). This corresponds to write processing.
  • step S 8 in the comparison between the new data signal 6 s and the existing data signal 30 s in the comparison section 5 (step S 8 ), in a case where the new data signal 6 s and the existing data signal 30 s are identical with each other, that is, in a case where the new data and the existing data are identical with each other, the comparison section 5 does not output the write enable signal 44 s .
  • the write processing is terminated while the storage section 3 does not write the new data to the predetermined storage element M.
  • the new data to be stored in the storage element M is identical with the existing data already stored in the storage element M to which the new data is to be written, the new data is not written.
  • the power consumption which would otherwise be generated by writing the new data, can be reduced, thereby achieving a power saving.
  • a data storage device By providing the above-described data storage circuit 1 on a semiconductor substrate, a data storage device achieving a power reduction can be formed.
  • a CPU including an IC memory or a storage area with a power reduction can be formed.
  • the data storage circuit with a control signal generating section for generating a readout control signal for performing readout control of the existing data and a write control signal for performing write control of the new data, and by configuring the data storage circuit so that the existing data and the new data are compared with each other in the comparison section in accordance with the control signal from the control signal generating section, the readout control signal and the write control signal generated with good accuracy can surely perform control of the data storage circuit and avoid erroneous operation to prevent excess power consumption.
  • a comparison section for reading out existing data stored in a storage element to compare the existing data and new data with each other prior to writing of the new data to the storage element, and configuring so that, in the comparison section, in a case where the existing data and the new data are identical with each other, the writing to the storage element is not performed, and in a case where the existing data and the new data are not identical with each other, the new data is written to the storage element, similarly to the invention as described in claim 1 , it is possible to substantially reduce the number of times of execution of writing to the storage element so that power consumption brought by the writing of the new data can be suppressed to accomplish a power saving.
  • the data storage device by providing the data storage device with a control signal generating section for generating a readout control signal for performing readout control of the existing data and a write control signal for performing write control of the new data, and by configuring the data storage circuit so that the existing data and the new data are compared with each other in the comparison section in accordance with the control signal from the control signal generating section, similarly to the invention as described in claim 2 , the readout control signal and the write control signal generated with good accuracy can surely perform control of the data storage circuit and avoid erroneous operation to prevent excess power consumption.
  • the comparison section by providing the comparison section with a new data retention section for temporarily retaining the new data; an existing data retention section for temporarily retaining the existing data; and a write enable signal generating section for comparing the new data retained in the new data retention section and the exiting data retained in the existing data retention section with each other to control an output of the write enable signal, and configuring so that the new data is temporarily retained in the new data retention section while the existing data is temporarily retained in the exiting data retention section in accordance with the readout control signal output from the control signal generating section so as to compare the new data retained in the new data retention section and the existing data retained in the existing data retention section with each other in accordance with the write control signal output from the control signal generating section, it is possible to compare the new data and the existing data after correctly obtaining them, respectively, so as to avoid an erroneous operation so that excessive power consumption can be prevented.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
  • Non-Volatile Memory (AREA)
US10/505,431 2002-03-20 2003-03-17 Power saving data storage circuit, data writing method in the same, and data storage device Expired - Fee Related US7376801B2 (en)

Applications Claiming Priority (3)

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JP2002-79528 2002-03-20
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US20110105103A1 (en) * 2009-10-30 2011-05-05 Immersion Corporation Interfacing a Mobile Device with a Computer
US10311931B2 (en) 2017-09-20 2019-06-04 Toshiba Memory Corporation Semiconductor memory device
USRE47639E1 (en) * 2012-01-16 2019-10-08 Toshiba Memory Corporation Nonvolatile semiconductor storage device equipped with a comparison buffer for reducing power consumption during write

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JPWO2007074504A1 (ja) * 2005-12-26 2009-06-04 富士通株式会社 不揮発性半導体記憶装置及びその書き込み方法
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JP6030485B2 (ja) * 2013-03-21 2016-11-24 日立オートモティブシステムズ株式会社 電子制御装置
CN105244057B (zh) * 2015-09-29 2019-12-13 北京兆易创新科技股份有限公司 一种非易失性存储器写状态寄存器的方法
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CN113257307B (zh) * 2020-02-13 2024-04-26 华邦电子股份有限公司 存储器装置及数据写入方法

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US10311931B2 (en) 2017-09-20 2019-06-04 Toshiba Memory Corporation Semiconductor memory device

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KR20040111374A (ko) 2004-12-31
EP1486984A1 (en) 2004-12-15
WO2003079365A1 (fr) 2003-09-25

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