US6346489B1 - Precleaning process for metal plug that minimizes damage to low-κ dielectric - Google Patents

Precleaning process for metal plug that minimizes damage to low-κ dielectric Download PDF

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US6346489B1
US6346489B1 US09/388,991 US38899199A US6346489B1 US 6346489 B1 US6346489 B1 US 6346489B1 US 38899199 A US38899199 A US 38899199A US 6346489 B1 US6346489 B1 US 6346489B1
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dielectric
workpiece
gas mixture
metal conductor
exposing
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English (en)
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Barney M. Cohen
Suraj Rengarajan
Kenny King-Tai Ngan
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Applied Materials Inc
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Applied Materials Inc
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Assigned to APPLIED MATERIALS, INC. reassignment APPLIED MATERIALS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: COHEN, BARNEY M., RENGARAJAN, SURAJ, KING-TAI NGAN, KENNY
Priority to US09/388,991 priority Critical patent/US6346489B1/en
Priority to KR1020000050996A priority patent/KR20010050283A/ko
Priority to EP00307472A priority patent/EP1081750A3/en
Priority to SG200004970A priority patent/SG93261A1/en
Priority to TW089117952A priority patent/TW473846B/zh
Priority to EP00307537A priority patent/EP1081751A3/en
Priority to JP2000306813A priority patent/JP4932075B2/ja
Priority to SG200005008A priority patent/SG90747A1/en
Priority to KR1020000051840A priority patent/KR100842463B1/ko
Priority to JP2000267614A priority patent/JP2001168075A/ja
Priority to TW089117956A priority patent/TW476131B/zh
Priority to US10/075,510 priority patent/US6589890B2/en
Publication of US6346489B1 publication Critical patent/US6346489B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors

Definitions

  • the invention relates generally to processes for manufacturing integrated circuits and other electronic devices. More specifically, the invention relates to precleaning processes for removing native oxide from an area of a metal layer that is exposed by an opening in an overlying dielectric, so that the opening subsequently can be filled by a metal plug.
  • a common process sequence in manufacturing integrated circuits and other electronic devices is to deposit a number of metal conductors on a substrate, then cover the metal with a dielectric layer, then etch a number of openings in the dielectric so that each opening exposes a contact area on one of the metal conductors, then deposit a metal plug in each opening so as to make electrical contact with the contact area. If the substrate is exposed to the ambient atmosphere or any other source of oxygen after the openings are formed, the surface of the semiconductor or metal layer exposed in each opening will become oxidized. This native oxide must be removed or “cleaned” before depositing the metal plug in order to achieve good electrical contact between the plug and the contact area. The process of removing native oxide from a metal conductor before depositing a metal plug is commonly termed “precleaning”.
  • a serious shortcoming of conventional precleaning processes for metal conductors is that the precleaning process can damage the dielectric.
  • Particularly susceptible to damage are “low- ⁇ ” dielectric materials that incorporate carbon atoms to reduce their dielectric constant “ ⁇ ”. We have measured an increase in the dielectric constant of such materials after performing a precleaning process.
  • the invention is a precleaning process suitable for fabricating metal plugs in a low- ⁇ , carbon-containing dielectric. More specifically, the invention is a process for cleaning a contact area of a metal conductor on a semiconductor workpiece so as to minimize damage to a carbon-containing dielectric overlying the metal. After forming contact openings in the dielectric so as to expose contact areas on the underlying metal conductor, the contact areas are cleaned by exposing the workpiece to a plasma formed from a mixture of hydrogen-containing and helium gases.
  • our hydrogen-helium plasma process can repair damage to the dielectric caused by preceding process steps. Accordingly, another aspect of our invention is a method of using such plasma process to repair damage to a carbon-containing dielectric on a semiconductor workpiece caused by an oxygen plasma process for stripping resist from the surface of the dielectric.
  • FIG. 1 is a sectional view of a semiconductor workpiece on which the processes of the invention may be performed.
  • FIG. 2 is a flow chart of a photoresist ashing process and preclean process according to our invention.
  • FIG. 3 is a partially schematic, sectional view of a plasma chamber suitable for performing the preclean process of the invention.
  • Our precleaning process is one segment of a sequence of process steps for forming a metal plug or via in a low- ⁇ , carbon-containing dielectric on a semiconductor workpiece.
  • a low- ⁇ dielectric has a dielectric constant “ ⁇ ” that is less than 3.8, preferably less than or equal to 3.0.
  • ⁇ dielectric constant
  • An example of a low- ⁇ , carbon-containing, silicon oxide dielectric and a process for forming it on a silicon wafer is described in commonly assigned U.S. patent application Ser. No. 09/247,381 filed Feb. 10, 1999 by Cheung et al., the entire content of which is hereby incorporated by reference into this patent specification.
  • This type of carbon-containing silicon oxide has a dielectric constant less than that of conventional, non-carbon-containing silicon dioxide because it incorporates carbon atoms in the silicon oxide material.
  • the carbon atoms typically are incorporated in the silicon oxide in the form of C—H bonds or C—F bonds.
  • the dielectric preferably has a carbon content of at least 1% by weight, more preferably at least 5 %.
  • FIG. 1 shows a conventional semiconductor workpiece or substrate 10 on which the processes of the invention may be performed.
  • the substrate typically is a silicon wafer on which integrated circuits are to be formed or a glass substrate on which electronic video display devices and circuits are to be formed.
  • the substrate is depicted as a silicon wafer in all of the following examples.
  • the workpiece or substrate 10 includes one or more regions 12 composed of a metal conductor such as copper or tungsten.
  • the metal regions can be formed by any conventional metal deposition and patterning processes (FIG. 2, Step 101 ).
  • a low- ⁇ , carbon-containing dielectric layer 14 overlies the metal regions.
  • the dielectric 14 is patterned with a number of openings 16 so that each opening exposes an area 17 of one of the metal regions 12 , this area 17 being termed the “contact area”, “exposed area” or “exposed surface” of the metal region. (We define all portions of the metal regions 12 that are not covered by dielectric 14 as being “exposed” even though the exposed surface may be covered by thin layer of native oxide as a result of exposure of the metal to oxygen, such as oxygen in the ambient atmosphere.)
  • Each opening 16 subsequently will be filled with a metal material to form a “plug” or “via” that makes electrical contact with the underlying metal region 12 .
  • the typical process for creating openings 16 in the dielectric is to deposit a blanket layer of dielectric 14 (Step 102 ), then employ a photo-lithographic process to form a pattern of photoresist 19 over all areas of the dielectric other than the areas where openings are desired (Step 103 ).
  • a plasma etch process then etches openings 16 in all portions of the dielectric that are not covered by photoresist (Step 104 ).
  • the exposed surface of each contact area generally will oxidize to form a thin layer of “native oxide” 18 .
  • oxygen exposure may occur in an “ashing” process for removing photoresist 19 after etching the openings in the dielectric (Step 105 ), or it may occur if the workpiece is exposed to ambient atmosphere while it is transported between two process chambers.
  • This native oxide must be removed or “cleaned” before depositing the metal plug in order to achieve good electrical contact between the plug and the contact area.
  • the process of removing such native oxide is termed “precleaning” because it precedes deposition of the metal plug.
  • the precleaning of the contact area 17 is performed by exposing the workpiece 10 to an atmosphere formed by plasma decomposition of a gas mixture that includes helium and at least one species of a hydrogen-containing gas.
  • a gas mixture that includes helium and at least one species of a hydrogen-containing gas.
  • our invention is not limited to a specific theory of operation, we believe that the plasma dissociates the hydrogen-containing gas to produce hydrogen radicals and ions that migrate from the plasma to the semiconductor workpiece.
  • the hydrogen radicals and ions react with the oxygen component of the native oxide to form volatile hydroxyls and water vapor that are exhausted from the chamber by the exhaust pump, thereby removing the native oxide 18 from the surface of the metal contact areas 12 .
  • the plasma by a method that minimizes electric fields at the workpiece position.
  • One suitable method of forming the plasma is in a conventional remote plasma source, which means that the plasma either is formed in a separate chamber from the vacuum chamber that holds the workpiece, or else the plasma is formed in a separate region of a common chamber such that the plasma body is a substantial distance from the workpiece.
  • an exhaust pump causes radicals and ions produced by decomposition of gases in the plasma to flow from the plasma body to the workpiece.
  • Conventional process chambers having remote plasma sources are described in commonly-assigned U.S. Pat. No. 5,346,579 to Cook et al. and U.S. Pat. No. 5,543,688 to Morita, the entire content of each of which is hereby incorporated by reference into this patent specification.
  • our currently preferred method of forming the plasma so as to avoid sputtering damage to the workpiece is in a plasma chamber having an inductively coupled plasma source, such as the commercially available preclean chamber 20 shown in FIG. 3 .
  • the upper portion of the chamber is bounded by an upper wall 22 composed of dielectric material, typically quartz, and the lower portion of the chamber is bounded by a lower wall 23 composed of either dielectric or conducting material, typically aluminum.
  • the hydrogen-helium gas mixture described above flows from a gas supply tank 24 at a flow rate regulated by a flow controller 26 , typically a mass flow controller, and then is injected into the upper portion of the chamber through one or more gas inlet ports 28 .
  • An exhaust pump not shown, exhausts chamber gases through exhaust port 30 and regulates the chamber pressure.
  • a primary RF power supply 32 supplies RF electrical power to an induction coil 34 that encircles the dielectric upper chamber wall 22 .
  • the electrical power is inductively coupled from the coil to the gases in the upper portion of the chamber so as to excite the gases to a plasma state.
  • the workpiece or substrate 10 is mounted in the lower portion of the chamber on a pedestal or susceptor 36 , typically composed of aluminum or titanium. All surfaces of the susceptor that are not covered by the substrate are covered by a dielectric 37 , typically quartz.
  • a second RF power supply 38 also called a bias RF power supply, supplies RF power to the pedestal.
  • the bias RF power supply can help ignite and sustain the plasma, and it can produce a DC bias voltage on the pedestal that in most cases is negative relative to the plasma body.
  • the negative bias voltage accelerates ions from the plasma toward the susceptor.
  • RF bias power increases the risk of damage to the dielectric by ion bombardment, we prefer using the lowest possible RF bias power. We believe we can successfully remove native oxide from the metal 12 without any RF bias power applied to the pedestal. However, in the illustrated inductively-coupled plasma chamber, some RF bias power usually is required to initiate or “strike” the plasma. In addition, a small amount of RF bias power can ensure that changing process conditions do not extinguish the plasma. Therefore, in our preferred implementation we program the controller 44 to command the bias RF power supply 38 to initially apply to the pedestal 40 watts of RF power at a frequency of 13.56 MHz in order to initiate or strike the plasma, and to then reduce the bias RF power to 10 watts throughout the precleaning process. At low power levels such as the preferred 10 watts, we find the DC bias voltage on the pedestal is close to zero, and even can be positive in the preferred chamber of FIG. 3 .
  • Our preferred hydrogen-containing gas is H 2 .
  • Alternative choices include NH 3 (ammonia) and SiH 4 (silane).
  • a preferred gas mixture is 5% H 2 and 95% He by molecular molar concentration, which is approximately the same concentration by gas volume. Since H 2 and He are diatomic and monatomic gases, respectively, this is equivalent to 10% H and 90% He by atomic molar concentration.
  • Our precleaning process is especially useful for cleaning metal regions 12 composed of copper, because copper oxide is readily reduced by hydrogen at temperatures below 100° C. Most other metals would require greater heating of the substrate in order to perform the reduction reaction. The feasibility of subjecting the substrate to the required temperature depends on whether the dielectric 14 and other structures on the substrate would be damaged.
  • the helium carrier gas advantageously enhances the dissociation of the hydrogen in the plasma. Because helium ions are very light, they will subject the dielectric 14 to little or no sputtering damage. In contrast, carrier gases composed of atomic species having a greater atomic mass, such as argon, would be more likely to damage the dielectric, as evidenced by the comparative test results described below. Therefore, to minimize sputtering of the dielectric, we recommend that the gas mixture does not include BCl 3 , argon, or any compound of any element having an atomic mass greater than the atomic mass of argon.
  • the hydrogen-containing plasma is maintained as long as necessary to remove the native oxide 18 .
  • 30 seconds was more than adequate to remove the thickest copper oxide film 18 we encountered.
  • process parameters in our preferred embodiment for precleaning a 200 mm silicon wafer include a 100 sccm flow rate for the H 2 —He gas mixture and a chamber pressure of 80 millitorr.
  • All process steps preferably are controlled by a programmable controller such as microcomputer 44 which controls the amount of power supplied by the RF power supplies 32 , 38 and controls the flow rate of the hydrogen-helium gas mixture provided by the flow controller 26 .
  • a programmable controller such as microcomputer 44 which controls the amount of power supplied by the RF power supplies 32 , 38 and controls the flow rate of the hydrogen-helium gas mixture provided by the flow controller 26 .
  • the low- ⁇ dielectric film was deposited on 200 mm diameter silicon wafers in with the dielectric deposition process described in the above-referenced patent application Ser. No. 09/247,381.
  • This process deposits a dielectric having a dielectric constant ⁇ of about 2.70 to 2.75.
  • the test data shown in Tables 1 and 2 shows the amount by which the tested preclean processes increased the dielectric constant above this value. The increase in dielectric constant indicates the degree of damage to the dielectric film.
  • Dielectric Constant Run Gas Induction Coil Duration Before Anneal After Anneal 1 Ar (Sputter) 300 W 30 sec. 0.16 0.21 (& 300 W bias) 2 5% H 2 /95% He 300 W 30 sec. 0.10 0.05 3 5% H 2 /95% He 300 W 60 sec. 0.17 0.12 4 5% H 2 /95% He 300 W 120 sec. 0.23 0.19 5 5% H 2 /95% He 450 W 60 sec. 0.19 0.14 6 10% H 2 /90% He 300 W 30 sec. 0.22 0.19 7 10% H 2 /90% He 300 W 60 sec. 0.26 0.20 8 10% H 2 /90% He 450 W 60 sec. 0.30 0.20
  • Run 1 shows that a conventional argon sputter cleaning process increased electric constant by 0.16.
  • Run 2 shows that our H 2 —He reactive cleaning process inflicted less damage to the dielectric, as it increased the dielectric constant by only 0.10.
  • Table 1 also shows that a subsequent anneal step is surprisingly synergistic with our H 2 —He process, in contrast with the detrimental effect of annealing after a conventional argon sputtering process.
  • annealing further exacerbated the increase in dielectric constant caused by argon sputtering.
  • Run 2 shows that the anneal step repaired the minor damage inflicted by our H 2 —He preclean process by reducing the dielectric constant to a value only 0.05 greater than that before the precleaning.
  • Runs 3 - 8 also show that the annealing step reduced the dielectric constant, which indicates that the annealing repaired some of the damage to the dielectric film caused by our H 2 —He plasma precleaning process.
  • the anneal temperature should be greater than 100° C., preferably at least 300° C., and most preferably in the range of 300° C. to 450° C. If the annealing is performed in a conventional thermal anneal chamber—i.e., a chamber that heats the workpiece primarily by thermal conduction and convection rather than radiation—the workpiece typically should be annealed for at least five minutes, and more preferably 30 minutes.
  • a radiant heating chamber commonly called a rapid thermal processing chamber, can radiantly heat the surface of the workpiece to a much higher temperature for a much shorter duration.
  • Runs 3 - 8 show that increasing the hydrogen concentration, the RF power to the induction coil, or the duration of the preclean process increases the damage to the dielectric. Therefore, the process parameters of Run 2 are preferred.
  • plasma ashing is conventionally performed prior to metal precleaning in order to remove various organic material from the surface of the dielectric.
  • organic material may include photoresist on the top surface of the dielectric, a “passivation layer” deposited on the side walls of the via openings during the etching of the vias, and other organic byproducts of the etch process.
  • oxygen plasma ashing the organic material is removed or “stripped” by exposing the workpiece to an atmosphere formed by plasma decomposition of oxygen, and optionally other gases.
  • Preferred parameters of a conventional oxygen plasma ashing process for stripping photoresist after patterning of a silicon oxide dielectric are 500 to 1000 sccm oxygen gas flow rate, with no carrier gas, 15 mT chamber pressure, and 3000 watts of RF power at 2 MHz applied to the induction coil of an inductively-coupled plasma chamber like that shown in FIG. 3 . No bias RF power is used during the ashing process so as to avoid sputtering damage to the dielectric.
  • Dielectric Constant Run Gas Induction Coil Duration Before Anneal After Anneal 0 None 0 0 0.25 0.32 (ashing only) 1 Ar (Sputter) 300 W 30 sec. 0.18 0.23 (+300 W bias) 2 5% H 2 /95% He 300 W 30 sec. 0.14 0.16 3 5% H 2 /95% He 300 W 60 sec. 0.16 0.19 4 5% H 2 /95% He 300 W 120 sec. 0.16 0.18 5 5% H 2 /95% He 450 W 60 sec. 0.17 0.21 6 10% H 2 /90% He 300 W 30 sec. 0.28 7 10% H 2 /90% He 300 W 60 sec. 0.28 8 10% H 2 /90% He 450 W 60 sec. 0.28
  • Table 2 shows the test results when wafers were subjected to the just described oxygen plasma ashing process prior to the previously described de-gas and preclean processes. Except for the ashing process, the test conditions were identical to those of the tests reported in Table 1.
  • Run 0 represents the substrate following the oxygen plasma ashing process, prior to the de-gas process and the precleaning process.
  • the increase in dielectric constant shown in Table 2 Run 0 is greater than the increase shown in Table 1, Run 1 . This result indicates that the oxygen plasma ashing process damaged the dielectric even more than the argon sputtering process reported in Table 1, Run 1 .
  • Table 2 shows that when oxygen plasma ashing is performed before precleaning, thermal annealing does not help repair the damage to the dielectric. In every test reported in Table 2, thermal annealing worsened the damage to the dielectric, as evidenced by an increase in the measured dielectric constant after annealing. Therefore, after precleaning wafers that have been subjected to oxygen plasma ashing, it is preferable to omit thermal annealing.

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
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US09/388,991 1999-09-02 1999-09-02 Precleaning process for metal plug that minimizes damage to low-κ dielectric Expired - Lifetime US6346489B1 (en)

Priority Applications (12)

Application Number Priority Date Filing Date Title
US09/388,991 US6346489B1 (en) 1999-09-02 1999-09-02 Precleaning process for metal plug that minimizes damage to low-κ dielectric
KR1020000050996A KR20010050283A (ko) 1999-09-02 2000-08-31 유전상수 ｋ가 낮은 유전체의 손상을 최소화하는, 금속플러그를 위한 예비세정 방법
EP00307472A EP1081750A3 (en) 1999-09-02 2000-08-31 Recleaning process for metal plug that minimizes damage to low K dielectric
SG200004970A SG93261A1 (en) 1999-09-02 2000-08-31 Precleaning process for metal plug that minimizes damage to low-k dielectric
JP2000306813A JP4932075B2 (ja) 1999-09-02 2000-09-01 低κ誘電体に対する損傷を最小にする金属プラグの事前清浄化方法
EP00307537A EP1081751A3 (en) 1999-09-02 2000-09-01 Methods of pre-cleaning dielectric layers of substrates
TW089117952A TW473846B (en) 1999-09-02 2000-09-01 Precleaning process for metal plug that minimizes damage to low-K dielectric
SG200005008A SG90747A1 (en) 1999-09-02 2000-09-01 Method of pre-cleaning dielectric layers of substrates
KR1020000051840A KR100842463B1 (ko) 1999-09-02 2000-09-02 기판의 유전체층을 사전 세정하기 위한 방법
JP2000267614A JP2001168075A (ja) 1999-09-02 2000-09-04 基板誘電層プレクリーニング方法
TW089117956A TW476131B (en) 1999-09-02 2000-09-15 Methods of pre-cleaning dielectric layers of substrates
US10/075,510 US6589890B2 (en) 1999-09-02 2002-02-12 Precleaning process for metal plug that minimizes damage to low-κ dielectric

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Cited By (36)

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US6573181B1 (en) 2000-10-26 2003-06-03 Applied Materials, Inc. Method of forming contact structures using nitrogen trifluoride preclean etch process and a titanium chemical vapor deposition step
US6630406B2 (en) 2001-05-14 2003-10-07 Axcelis Technologies Plasma ashing process
US20030219546A1 (en) * 2002-05-23 2003-11-27 Ebrahim Andideh Chemical vapor deposition chamber pre-deposition treatment for improved carbon doped oxide thickness uniformity and throughput
US20030235994A1 (en) * 2002-06-20 2003-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method of avoiding plasma arcing during RIE etching
US20040084412A1 (en) * 2001-05-14 2004-05-06 Carlo Waldfried Plasma ashing process
US20040118697A1 (en) * 2002-10-01 2004-06-24 Applied Materials, Inc. Metal deposition process with pre-cleaning before electrochemical deposition
US6759337B1 (en) * 1999-12-15 2004-07-06 Lsi Logic Corporation Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate
US20040132252A1 (en) * 2001-01-30 2004-07-08 Merchant Bruce D. Method of forming a field effect transistor having a lateral depletion structure
US6767834B2 (en) * 2000-11-24 2004-07-27 Samsung Electronics Co., Ltd. Method of manufacturing a contact of a semiconductor device using cluster apparatus having at least one plasma pretreatment module
US20040219789A1 (en) * 2003-02-14 2004-11-04 Applied Materials, Inc. Cleaning of native oxide with hydrogen-containing radicals
US20040242012A1 (en) * 2001-09-12 2004-12-02 Taro Ikeda Method of plasma treatment
US20050022839A1 (en) * 1999-10-20 2005-02-03 Savas Stephen E. Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing
US20050148292A1 (en) * 2001-09-21 2005-07-07 Samsung Electronics, Co., Ltd. Method and apparatus for polishing a copper layer and method for forming a wiring structure using copper
US20050170663A1 (en) * 2004-01-30 2005-08-04 Chartered Semiconductor Manufacturing Ltd. He treatment to improve low-K adhesion property
US7014887B1 (en) * 1999-09-02 2006-03-21 Applied Materials, Inc. Sequential sputter and reactive precleans of vias and contacts
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