US6025733A - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
US6025733A
US6025733A US09/018,055 US1805598A US6025733A US 6025733 A US6025733 A US 6025733A US 1805598 A US1805598 A US 1805598A US 6025733 A US6025733 A US 6025733A
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United States
Prior art keywords
semiconductor memory
pads
probe
wire
memory device
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US09/018,055
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English (en)
Inventor
Tuyoshi Saitoh
Akira Kitaguchi
Masaaki Matsuo
Makoto Hatakenaka
Toshio Nakano
Yuko Sudo
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Renesas Electronics Corp
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Mitsubishi Electric Corp
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Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MITSUBISHI DENKI KABUSHIKI KAISHA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Definitions

  • the present invention relates to a semiconductor memory device having a semiconductor memory circuit, a semiconductor test circuit, a semiconductor circuit other than the semiconductor memory circuit and the semiconductor test circuit, and a plurality of pads against which probes are respectively pressed upon testing the semiconductor memory circuits and to which wires for connecting lead terminals are respectively electrically connected upon packaging, all of which are provided on the same substrate.
  • FIG. 10 is a plan view showing a configuration of a conventional semiconductor memory device.
  • FIG. 10 illustrates the manner in which a semiconductor memory circuit is being tested while pressing probes against five first pads provided at one of a plurality of semiconductor memory devices formed on a semiconductor wafer, viewed through a window hole defined substantially in the center of a probe card.
  • the plurality of semiconductor memory devices formed on the semiconductor wafer are divided into respective semiconductor memory devices in the subsequent dicing process.
  • reference numeral 101 denotes a semiconductor memory circuit including an originally-used first memory circuit 101a and a second memory circuit 101b used in place of the first memory circuit 101a when the first memory circuit 101a fails to function properly.
  • Reference numeral 102 denotes a semiconductor test circuit for testing the semiconductor memory circuit 101.
  • Reference numeral 103 denotes a logical circuit for swapping data with the semiconductor memory circuit 101.
  • Reference numerals 104 respectively denote first pads against which probes are respectively pressed upon testing the semiconductor memory circuit 101 and to which wires for connecting to lead terminals are respectively electrically connected upon packaging.
  • Reference numerals 105 respectively denote second pads that are not in contact with the probes upon testing the semiconductor memory circuit 101 but electrically connected with wires for connecting to lead terminals upon packaging.
  • Reference numeral 106 denotes a substrate provided with the semiconductor memory circuit 101, the semiconductor test circuit 102, the logical circuit 103, and the first and second pads 104 and 105.
  • reference numeral 107 denotes a probe card and reference numerals 108 denote probes attached to the probe card 107.
  • reference numerals 105 are assigned only to parts of the second pads in FIG. 10. For brevity of illustration, the wires electrically connected to the second pads 105 are omitted and not shown in the drawing.
  • the conventional semiconductor memory device is shaped in the form of a square.
  • the five first pads 104 are divided into groups of two pads, one pad, one and one pad placed along the four sides of the outer periphery of the semiconductor memory device.
  • FIGS. 11A through 11C are respectively schematic side views showing the states of first pads 104 and probes 108 at the time that the probes 108 are respectively pressed against the first pads 104 in a test process of the semiconductor memory circuit.
  • FIGS. 12A through 12C are respectively schematic plan views showing the states of the first pads 104 at the time that the probes 108 are respectively pressed against the first pads 104 and thereafter the probes 108 are respectively removed from the first pads 104 in the test process of the semiconductor memory circuit.
  • the probes 108 are first respectively pressed against the first pads 104 placed along the four sides of the outer periphery of the semiconductor memory circuit. Next, a test is made as to whether the first memory circuit 101a operates properly. In this case, a first probe contact trace 111 is developed in the first pad 104 by pressing the probe 108 against the first pad 104 (see FIG. 11A). Therefore, when the probe 108 is removed from the first pad 104, the first probe contact trace 111 remains in the first pad 104 (see FIG. 12A).
  • the first memory circuit 101a fails to operate properly, the first memory circuit 101a is switched to the second memory circuit 101b and the probes 108 are respectively pressed against the first pads 104 disposed along the four sides of the outer periphery again.
  • a test is made as to whether the second memory circuit 101b operates properly.
  • a second probe contact trace 112 occurs in the first pad 104 by pressing the probe 108 against the first pad 104 (see FIG. 11B). Therefore, the second probe contact trace 112 thereafter remains in the first pad 104 when the probe 108 is removed from the first pad 104 (see FIG. 12B).
  • the probes 108 are respectively pressed against the first and second pads 104 and 105.
  • a test is made as to whether the entire semiconductor memory device operates properly.
  • a third probe contact trace 113 is developed in the first pad 104 by pressing the probe 108 against the first pad 104 (see FIG. 11C). Therefore, the third probe contact trace 113 thereafter remains in the first pad 104 when the probe 108 is removed from the first pad 104 (see FIG. 12C).
  • the conventional semiconductor memory device is constructed as described above, a problem arises in that in the test process of the semiconductor memory circuit, the probes 108 must be pressed against the first pads 104 placed along the four sides of the outer periphery thereof from four directions and a plurality of semiconductor memory devices cannot be tested simultaneously upon testing the semiconductor memory circuit.
  • FIG. 13 is a schematic view showing the state of the first pad 104 and the wire 114 at the time that the wire 114 for connecting to the lead terminal is electrically connected to the first pad 104, in which FIG. 13A is a side view and FIG. 13B is a plan view.
  • the present invention has been accomplished for solving the above-mentioned problems and it is an object of the present invention to provide a semiconductor memory device wherein when semiconductor memory circuits are tested, a plurality of semiconductor memory devices can be tested simultaneously.
  • a semiconductor memory device wherein a plurality of pads are placed in one or two rows in parallel with one side of the outer periphery of the semiconductor memory device.
  • an advantageous effect can be obtained in that since the plurality of pads are arranged in one or two rows in parallel with one side of the outer periphery of the semiconductor memory device, a plurality of semiconductor memory devices can be tested simultaneously when semiconductor memory circuits are tested.
  • a semiconductor memory device wherein a plurality of pads are placed in two or more rows in parallel with one side of the outer periphery of the semiconductor memory device so that row coordinates of the pads differ from each other.
  • an advantageous effect can be brought about in that since the plurality of pads are disposed in two or more rows in parallel with one side of the outer periphery of the semiconductor memory device so that the row coordinates of the pads are rendered different from each other, a plurality of semiconductor memory devices can be tested simultaneously when semiconductor memory circuits are tested.
  • each of pads comprises a probe region against which a probe is pressed and a wire region to which a wire is electrically connected.
  • each of the pads comprises the probe region against which the probe is pressed and the wire region to which the wire is electrically connected, the wire for connecting to a lead terminal is no longer hard to connect to the pad upon packaging.
  • a semiconductor memory device wherein a plurality of pads are placed in one or two rows in parallel with one side of the outer periphery of the semiconductor memory device and each of the pads comprises a probe region against which a probe is pressed and a wire region to which a wire is electrically connected.
  • an advantageous effect can be brought about in that since each of the pads is made up of the probe region against which the probe is pressed and the wire region to which the wire is electrically connected, the wire for connecting to a lead terminal is no longer hard to connect to the pad upon packaging.
  • a semiconductor memory device wherein a plurality of pads are placed in two or more rows in parallel with one side of the outer periphery of the semiconductor memory device so that row coordinates of the respective pads are made different from one another, and each of the pads comprises a probe region against which a probe is pressed and a wire region to which a wire is electrically connected.
  • each of the pads comprises the probe region against which the probe is pressed, and the wire region to which the wire is electrically connected, the wire for connecting to a lead terminal is no longer hard to connect the pad upon packaging.
  • a semiconductor memory device wherein a plurality of pads are placed in one or two rows in parallel with one side of the outer periphery of the semiconductor memory device, and each of the pads comprises a probe pad against which a probe is pressed and a wire pad to which a wire is electrically connected, both of which are electrically connected to each other.
  • each of the pads comprises the probe pad electrically connected to the wire pad, against which the probe is pressed, and the wire pad connected with the wire, the wire for connecting to a lead terminal is no longer hard to connect to the pad upon packaging.
  • a semiconductor memory device wherein a plurality of pads are arranged in two or more rows in parallel with one side of the outer periphery of the semiconductor memory device so that row coordinates of the respective pads are rendered different from one another, and each of the pads comprises a probe pad against which a probe is pressed and a wire pad to which a wire is electrically connected, both of which are electrically connected to one another.
  • each of the pads comprises the probe pad electrically connected to the wire pad, against which the probe is pressed, and the wire pad to which the wire is electrically connected, the wire for connecting to a lead terminal is no longer hard to connect to the pad upon packaging.
  • FIG. 1 is a plan view showing a configuration of a semiconductor memory device according to a first embodiment of the present invention
  • FIG. 2 is a plan view illustrating a configuration of a semiconductor memory device according to a second embodiment of the present invention
  • FIG. 3 plan view depicting a configuration of a semiconductor memory device according to a third embodiment of the present invention.
  • FIGS. 4A and 4B are schematic views showing the state of a first pad and a wire used to describe the third embodiment of the present invention at the time that the wire for connecting to a lead terminal is electrically connected to the first pad;
  • FIG. 5 is a plan view illustrating a configuration of a semiconductor memory device according to a fourth embodiment of the present invention.
  • FIG. 6 is a plan view depicting a configuration of a semiconductor memory device according to a fifth embodiment of the present invention.
  • FIG. 7 is a plan view showing a configuration of a semiconductor memory device according to a sixth embodiment of the present invention.
  • FIGS. 8A and 8B are schematic views illustrating the state of a first pad and a wire employed to describe the sixth embodiment of the present invention at the time that the wire for connecting to a lead terminal is electrically connected to the first pad;
  • FIG. 9 is a plan view depicting a configuration of a semiconductor memory device according to a seventh embodiment of the present invention.
  • FIG. 10 is a plan view showing a configuration of a conventional semiconductor memory device
  • FIGS. 11A through 11C are schematic side views illustrating the states of first pads and probes employed in the conventional description at the time that the probes are respectively pressed against the first pads in a test process of a semiconductor memory circuit;
  • FIGS. 12A through 12C are schematic plan views depicting the states of the first pads shown in FIGS. 11A through 11C at the time that in the test process of the semiconductor memory circuit, the probes are respectively pressed against the first pads and thereafter the probes are respectively removed from the first pads;
  • FIGS. 13A and 13B are schematic views showing the state of a first pad and a wire used for the conventional description at the time that the wire for connecting to a lead terminal is electrically connected to the first pad.
  • FIG. 1 is a plan view showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.
  • FIG. 1 shows the manner in which semiconductor memory circuits are being tested while pressing probes against five first pads respectively provided at two semiconductor memory devices of a plurality of semiconductor memory devices formed on a semiconductor wafer, viewed through a window slot or hole defined substantially in the center of a probe card.
  • the plurality of semiconductor memory devices formed on the semiconductor wafer are divided into respective semiconductor memory devices in the subsequent dicing process.
  • reference numerals 1 denote semiconductor memory circuits, each including an originally-used first memory circuit 1a and a second memory circuit 1b used in place of the first memory circuit 1a when the first memory circuit 1a fails to function properly.
  • Reference numerals 2 denote semiconductor test circuits for testing the semiconductor memory circuits 1, respectively.
  • Reference numerals 3 respectively denote logical circuits (semiconductor circuits) for swapping data with the semiconductor memory circuits 1.
  • Reference numerals 4 respectively denote first pads (pads) against which probes are respectively pressed upon testing the semiconductor memory circuits 1 and to which wires for connecting to lead terminals are respectively electrically connected upon packaging.
  • Reference numerals 5 denote second pads that are not in contact with the probes upon testing the semiconductor memory circuits 1 but are electrically connected with wires for connecting to lead terminals upon packaging.
  • Reference numerals 6 denote substrates, each provided with the semiconductor memory circuit 1, the semiconductor test circuit 2, the logical circuit 3, and the first and second pads 4 and 5.
  • reference numeral 7 denotes a probe card and reference numerals 8 respectively denote probes attached to the probe card 7.
  • reference numerals 5 are assigned only to parts of the second pads in FIG. 1. For brevity of illustration, the wires electrically connected to the second pads are omitted and not shown in the drawing.
  • the semiconductor memory device is shaped in the form of a square.
  • the five first pads 4 are classified or divided into two and three and arranged in two rows so as to run parallel with one side of the outer periphery of the semiconductor memory device. Since the semiconductor memory device is shaped in square form, the first pads 4 are disposed so as to run parallel to the opposite two sides of the outer periphery thereof as a result of the placement of the first pads 4 in parallel with one side of the outer periphery thereof.
  • the probes 8 are respectively pressed against the first pads 4 respectively disposed within the two semiconductor devices continuously located in the direction in which the first pads 4 are in a row. In this condition, the two semiconductor memory devices are simultaneously tested. Since the five first pads 4 are divided into groups of two and three and arranged in two rows parallel to one side of the outer periphery, the probes 8 are pressed against the respective semiconductor memory devices from two directions opposed to each other.
  • the first embodiment can obtain an advantageous effect in that since the five first pads 4 are divided into groups of two and three pads and disposed in two rows parallel to one side of the outer periphery, the two semiconductor memory devices can be simultaneously tested upon testing the semiconductor memory circuits.
  • FIG. 2 is a plan view showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.
  • FIG. 2 shows the manner in which semiconductor memory circuits are being tested while pressing probes against five first pads respectively provided at two semiconductor memory devices of a plurality of semiconductor memory devices formed on a semiconductor wafer, viewed through a window hole defined substantially in the center of a probe card.
  • the plurality of semiconductor memory devices formed on the semiconductor wafer are divided into individual semiconductor memory devices in the subsequent dicing process.
  • reference numerals 4a respectively denote first pads (pads) against which probes are respectively pressed upon testing semiconductor memory circuits 1 and to which wires for connecting to lead terminals are respectively electrically connected upon packaging.
  • Reference numeral 7a denotes a probe card and reference numerals 8a respectively denote probes attached to the probe card 7a. Since the second embodiment is identical or similar in other configuration to the first embodiment, its detailed description will be omitted.
  • the semiconductor memory device is shaped in the form of a square.
  • the five first pads 4a are divided into groups of two pads and three pad and arranged in two rows in parallel with one side of the outer periphery of the semiconductor memory device. Since the semiconductor memory device is shaped in square form, the first pads 4a are placed in parallel with the opposed two sides of the outer periphery thereof as a result of the placement of the first pads 4a in parallel with one side of the outer periphery thereof. Further, the five first pads 4a are disposed so that row coordinates (corresponding to coordinates in the direction indicated by X in FIG. 2) of the respective first pads 4a differ from each other.
  • the probes 8a are respectively pressed against the first pads 4a respectively disposed within the two semiconductor memory devices continuously located in the direction normal to the direction in which the first pads 4a are in a line. In this condition, the two semiconductor memory devices are simultaneously tested. Since the five first pads 4a are divided into groups of two and three and arranged in two rows parallel to one side of the outer periphery and the five first pads 4a are placed so that the row coordinates of the respective first pads 4a differ from each other, the probes 8a are pressed against one semiconductor memory device from one of the opposed two directions, whereas the probes 8a are pressed against the other semiconductor memory device from the other of the opposed two directions.
  • the second embodiment can obtain an advantageous effect in that since the five first pads 4a are divided into groups of two and three and disposed in two rows so as to run parallel with one side of the outer periphery and the five first pads 4a are placed so that the row coordinates of the respective first pads 4a differ from one another, the two semiconductor memory devices can be simultaneously tested upon testing the semiconductor memory circuits.
  • FIG. 3 is a plan view showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.
  • FIG. 3 illustrates the manner in which a semiconductor memory circuit is being tested while pressing probes against five first pads provided at one of a plurality of semiconductor memory devices formed on a semiconductor wafer, viewed through a window hole defined substantially in the center of a probe card.
  • the plurality of semiconductor memory devices formed on the semiconductor wafer are divided into individual semiconductor memory devices in the subsequent dicing process.
  • reference numerals 4b respectively denote first pads (pads) against which probes are respectively pressed upon testing a semiconductor memory circuit 1 and to which wires for connecting to lead terminals are respectively electrically connected upon packaging.
  • Reference numeral 7b denotes a probe card and reference numerals 8b respectively denote probes attached to the probe card 7b. Since the third embodiment is identical or similar in other configuration to the first embodiment, its detailed description will be omitted.
  • the semiconductor memory device is shaped in the form of a square.
  • the five first pads 4b are divided into groups of two pads, one pad, one pad and one pad arranged along the four sides of the outer periphery of the semiconductor memory device.
  • Each of the first pads 4b comprises a probe region 4b1 against which a probe is pressed upon testing the semiconductor memory circuit 1, and a wire region 4b2 to which a wire for connecting to the lead terminal is electrically connected upon packaging.
  • Each first pad 4b is greater than usual in area.
  • the probes 8b are respectively pressed against the probe regions 4b1 of the first pads 4b.
  • the semiconductor memory device is tested one by one. Since the five first pads 4b are divided into two, one, one and one and disposed along the four sides of the outer periphery of the semiconductor memory device in the semiconductor memory device, the probes 8b are pressed against the semiconductor memory device from four directions.
  • the third embodiment can bring about an advantageous effect in that since each of the first pads 4b comprises the probe region 4b1 against which the probe is pressed upon testing the semiconductor memory circuit 1 and the wire region 4b2 to which the wire for connecting to the lead terminal is electrically connected upon packaging, a wire 12 for connecting to the lead terminal can be electrically connected to the wire region 4b2 different from the probe region 4b1 provided with a probe contact trace 11 produced by pressing the probe against the probe region 4b1, and the wire 12 for connecting to the lead terminal is no longer hard to connect to the first pad 4b, as shown in FIGS. 4A and 4B. Incidentally, FIG.
  • FIG. 4 is a schematic view showing the state of the first pad 4b and the wire 12 at the time that the wire 12 for connecting to the lead terminal is electrically connected to the first pad 4b, wherein FIG. 4A is a side view and FIG. 4B is a plan view.
  • FIG. 5 is a plan view showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention.
  • FIG. 5 illustrates the manner in which semiconductor memory circuits are being tested while pressing probes against five first pads respectively provided at two of a plurality of semiconductor memory devices formed on a semiconductor wafer, viewed through a window hole defined substantially in the center of a probe card.
  • the plurality of semiconductor memory devices formed on the semiconductor wafer are divided into individual semiconductor memory devices in the subsequent dicing process.
  • reference numerals 4c respectively denote first pads (pads) against which probes are respectively pressed upon testing semiconductor memory circuits 1 and to which wires for connecting to lead terminals are respectively electrically connected upon packaging. Since the remaining configuration of the fourth embodiment is similar to the first embodiment, its detailed description will be omitted.
  • the semiconductor memory device is shaped in square form.
  • the five first pads 4c are divided into two and three and arranged in two rows to run parallel with one side of the outer periphery of the semiconductor memory device. Since the semiconductor memory device is square-shaped, the first pads 4c are disposed in parallel with the opposite two sides of the outer periphery thereof as a result of the placement of the first pads 4c in parallel with one side of the outer periphery thereof. Further, each of the first pads 4c comprises a probe region 4c1 against which a probe is pressed upon testing the semiconductor memory circuit 1, and a wire region 4c2 to which a wire for connecting to the lead terminal is electrically connected upon packaging. Each first pad 4c is greater than one employed in the prior art in area.
  • the probes 8 are respectively pressed against the probe regions 4c1 of the first pads 4c respectively disposed within the two semiconductor memory devices continuously located in the direction in which the first pads 4c are in a row. In this condition, the two semiconductor memory devices are simultaneously tested. Since the five first pads 4c are divided into groups of two and three pads arranged in two rows parallel to one side of the outer periphery in each semiconductor memory device, the probes 8 are pressed against the respective semiconductor memory devices from two directions opposed to each other.
  • the fourth embodiment can obtain an advantageous effect in that since the five first pads 4c are divided into groups of two and three pads disposed in two rows parallel to one side of the outer periphery, the two semiconductor memory devices can be simultaneously tested upon testing the semiconductor memory circuits.
  • the fourth embodiment can bring about an advantageous effect in that since each of the first pads 4c comprises the probe region 4c1 against which the probe is pressed upon testing the semiconductor memory circuit 1 and the wire region 4c2 to which the wire for connecting to the lead terminal is electrically connected upon packaging, the wire for connecting to the lead terminal can be electrically connected to the wire region 4c2 different from the probe region 4c1 provided with a probe contact trace produced by pressing the probe against the probe region 4c1, and the wire for connecting to the lead terminal is no longer hard to connect to the first pad 4c, in a manner similar to the third embodiment (see FIGS. 4A and 4B).
  • FIG. 6 is a plan view showing a configuration of a semiconductor memory device according to a fifth embodiment of the present invention.
  • FIG. 6 illustrates the manner in which semiconductor memory circuits are being tested while pressing probes against five first pads respectively provided at two of a plurality of semiconductor memory devices formed on a semiconductor wafer, is viewed through a window hole defined substantially in the center of a probe card.
  • the plurality of semiconductor memory devices formed on the semiconductor wafer are divided into individual semiconductor memory devices in the subsequent dicing process.
  • reference numerals 4d respectively denote first pads (pads) against which probes are respectively pressed upon testing semiconductor memory circuits 1 and to which wires for connecting to lead terminals are respectively electrically connected upon packaging. Since the fifth embodiment is identical or similar in other configuration to the second embodiment, its detailed description will be omitted.
  • the semiconductor memory device is shaped in the form of a square.
  • the five first pads 4d are divided into groups of two pads and three pads and disposed in two rows parallel to one side of the outer periphery of the semiconductor memory device. Since the semiconductor memory device is square-shaped, the first pads 4d are placed in parallel with the opposed two sides of the outer periphery of the semiconductor memory circuit as a result of the placement of the first pads 4d in parallel with one side of the outer periphery of the semiconductor memory circuit. Further, the five first pads 4d are disposed so that row coordinates (corresponding to coordinates in the direction indicated by X in FIG. 6) of the respective first pads 4d are different from each other.
  • each of the first pads 4d comprises a probe region 4d1 against which a probe is pressed upon testing the semiconductor memory circuit 1, and a wire region 4d2 to which a wire for connecting to the lead terminal is electrically connected upon packaging.
  • Each first pad 4d is greater than one employed in the prior art in area.
  • the probes 8a are respectively pressed against the first pads 4d respectively disposed within the two semiconductor devices continuously located in the direction normal to the direction in which the first pads 4d are in a line. In this condition, the two semiconductor memory devices are simultaneously tested. Since the five first pads 4d are divided into groups of two pads and three pads and arranged in two rows parallel to one side of the outer periphery and the five first pads 4d are placed so that the row coordinates of the respective first pads 4d differ from each other, the probes 8a are pressed against one semiconductor memory device from one of two directions opposed to each other, whereas the probes 8a are pressed against the other semiconductor memory device from the other of the opposed two directions.
  • the fifth embodiment can obtain an advantageous effect in that since the five first pads 4d are divided into the groups of two and three and disposed in two rows in parallel with one side of the outer periphery and the five first pads 4d are placed so that the row coordinates of the respective first pads 4d are made different from one another, the two semiconductor memory devices can be simultaneously tested upon testing the semiconductor memory circuits.
  • the fifth embodiment can bring about an advantageous effect in that since each of the first pads 4d comprises the probe region 4d1 against which the probe is pressed upon testing the semiconductor memory circuit 1 and the wire region 4d2 to which the wire for connecting to the lead terminal is electrically connected upon packaging, the wire for connecting to the lead terminal can be electrically connected to the wire region 4d2 different from the probe region 4d1 provided with a probe contact trace produced by pressing the probe against the probe region 4d1, and the wire for connecting to the lead terminal is no longer hard to connect to the first pad 4d, in a manner similar to the third embodiment (see FIGS. 4A and 4B).
  • FIG. 7 is a plan view illustrating a configuration of a semiconductor memory device according to a sixth embodiment of the present invention.
  • FIG. 7 shows the manner in which semiconductor memory circuits are being tested while pressing probes against five first pads respectively provided at two of a plurality of semiconductor memory devices formed on a semiconductor wafer, viewed through a window hole defined substantially in the center of a probe card.
  • the plurality of semiconductor memory devices formed on the semiconductor wafer are divided into individual semiconductor memory devices in the subsequent dicing process.
  • reference numerals 4e respectively denote first pads (pads) against which probes are respectively pressed upon testing semiconductor memory circuits 1 and to which wires for connecting to lead terminals are respectively electrically connected upon packaging. Since the sixth embodiment is identical or similar in other configuration to the first embodiment, its detailed description will be omitted.
  • the semiconductor memory device is shaped in the form of a square.
  • the five first pads 4e are divided into groups of two pads and three pads and disposed in two rows parallel to one side of the outer periphery of the semiconductor memory device. Since the semiconductor memory device is square-shaped, the first pads 4e are placed in parallel with the opposed two sides of the outer periphery thereof as a result of the placement of the first pads 4e in parallel with one side of the outer periphery thereof. Further, each of the first pads 4e comprises a probe pad 4e1 electrically connected to a wire pad 4e2, against which a probe is pressed upon testing the semiconductor memory circuit 1, and the wire pad 4e2 to which a wire for connecting to the lead terminal is electrically connected upon packaging.
  • the probes 8 are respectively pressed against the probe pads 4e1 of the first pads 4e respectively disposed within the two semiconductor memory devices continuously located in the direction in which the first pads 4e are in a row. In this condition, the two semiconductor memory devices are simultaneously tested. Since the five first pads 4e are divided into the two and three and arranged in two rows so as to run parallel with one side of the outer periphery, the probes 8 are pressed against the respective semiconductor memory devices from two directions opposed to each other.
  • the sixth embodiment can obtain an advantageous effect in that since the five first pads 4e are divided into the groups of two pads and three pads and disposed in two rows so as to run parallel with one side of the outer periphery, the two semiconductor memory devices can be simultaneously tested upon testing the semiconductor memory circuits.
  • each of the first pads 4e comprises the probe pad 4e1 electrically connected to the wire pad 4e2, against which the probe is pressed upon testing the semiconductor memory circuit 1 and the wire pad 4e2 to which the wire for connecting to the lead terminal is electrically connected upon packaging, a wire 12a for connecting to the lead terminal can be electrically connected to the wire pad 4e2 different from the probe pad 4e1 provided with a probe contact trace 11a produced by pressing the probe against the probe pad 4e1, and the wire 12a for connecting to the corresponding lead terminal is no longer hard to connect to the first pad 4e, as shown in FIGS. 8A and 8B. Incidentally, FIG.
  • FIG. 8 is a schematic view showing the state of the first pad 4e and the wire 12a at the time that the wire 12a for connecting to the lead terminal is electrically connected to the first pad 4e, in which FIG. 8A is a side view and FIG. 8B is a plan view.
  • FIG. 9 is a plan view showing a configuration of a semiconductor memory device according to a seventh embodiment of the present invention.
  • FIG. 9 shows the manner in which semiconductor memory circuits are being tested while pressing probes against five first pads respectively provided at two of a plurality of semiconductor memory devices formed on a semiconductor wafer, is viewed through a window hole defined substantially in the center of a probe card.
  • the plurality of semiconductor memory devices formed on the semiconductor wafer are divided into individual semiconductor memory devices in the subsequent dicing process.
  • reference numerals 4f respectively denote first pads (pads) against which probes are respectively pressed upon testing semiconductor memory circuits 1 and to which wires for connecting to lead terminals are respectively electrically connected upon packaging. Since the seventh embodiment is identical or similar in other configuration to the second embodiment, its detailed description will be omitted.
  • the semiconductor memory device is shaped in the form of a square.
  • the five first pads 4f are divided into groups of two pads and three pads and disposed in two rows parallel to one side of the outer periphery of the semiconductor memory device. Since the semiconductor memory device is square-shaped, the first pads 4f are placed in parallel with the opposed two sides of the outer periphery thereof as a result of the placement of the first pads 4f in parallel with one side of the outer periphery thereof. Further, the five first pads 4f are disposed so that row coordinates (corresponding to coordinates in the direction indicated by X in FIG. 9) of the respective first pads 4f are different from each other.
  • each of the first pads 4f comprises a probe pad 4f1 electrically connected to a wire pad 4f2, against which a probe is pressed upon testing the semiconductor memory circuit 1, and the wire pad 4f2 to which a corresponding wire for connecting to the lead terminal is electrically connected upon packaging.
  • the probes 8a are respectively pressed against the first pads 4f respectively disposed within the two semiconductor devices continuously located in the direction normal to the direction in which the first pads 4f are in a line. In this condition, the two semiconductor memory devices are simultaneously tested. Since the five first pads 4f are divided into the groups of two pads and three pads arranged in two rows parallel to one side of the outer periphery and the five first pads 4f are placed therein so that the row coordinates of the respective first pads 4f differ from each other, the probes 8a are pressed against one semiconductor memory device from one of two directions opposed to each other, whereas the probes 8a are pressed against the other semiconductor memory device from the other of the opposed two directions.
  • the seventh embodiment can obtain an advantageous effect in that since the five first pads 4f are divided into the groups of two pads and three pads and disposed in two rows parallel to one side of the outer periphery and the five first pads 4f are placed so that the row coordinates of the respective first pads 4f differ from one another, the two semiconductor memory devices can be simultaneously tested upon testing the semiconductor memory circuits.
  • the seventh embodiment can bring about an advantageous effect in that since each of the first pads 4f comprises the probe pad 4f1 electrically connected to the wire pad 4f2, against which the probe is pressed upon testing the semiconductor memory circuit 1, and the wire pad 4f2 to which the wire for connecting to the lead terminal is electrically connected upon packaging, the wire for connecting to the lead terminal can be electrically connected to the wire pad 4f2 different from the probe pad 4f1 provided with a probe contact trace produced by pressing the probe against the probe pad 4f1, and the wire for connecting to the lead terminal is no longer hard to connect to the first pad 4f, in a manner similar to the sixth embodiment (see FIGS. 8A and 8B).
  • the above-described first, fourth and sixth embodiments have described the case in which the first pads are arranged in two rows so as to run parallel with one side of the outer periphery.
  • the same advantageous effect as described above can be obtained even if the first pads are aligned in a row in parallel with one side of the outer periphery.
  • the aforementioned second, fifth and seventh embodiments have described the case in which the first pads are placed in two rows in parallel with one side of the outer periphery.
  • the same advantageous effect as described above can be brought about.
  • semiconductor memory circuits each having a bus width of 32 bits or more may be used as the semiconductor memory circuits employed in the aforementioned respective embodiments.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Memories (AREA)
  • Measuring Leads Or Probes (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
US09/018,055 1997-09-09 1998-02-03 Semiconductor memory device Expired - Lifetime US6025733A (en)

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JP9244370A JPH1187441A (ja) 1997-09-09 1997-09-09 半導体記憶装置
JP9-244370 1997-09-09

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KR (1) KR19990029192A (ko)
DE (1) DE19819252A1 (ko)
TW (1) TW392267B (ko)

Cited By (4)

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US6373143B1 (en) 1998-09-24 2002-04-16 International Business Machines Corporation Integrated circuit having wirebond pads suitable for probing
US6516430B1 (en) * 1999-06-29 2003-02-04 Fujitsu Limited Test circuit for semiconductor device with multiple memory circuits
US20110156736A1 (en) * 2009-12-28 2011-06-30 Hynix Semiconductor Inc. Semiconductor apparatus and probe test method thereof
US20120193622A1 (en) * 2011-01-27 2012-08-02 Elpida Memory, Inc. Device

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JP2005136246A (ja) * 2003-10-31 2005-05-26 Renesas Technology Corp 半導体集積回路装置の製造方法
JP4611067B2 (ja) * 2004-03-16 2011-01-12 パナソニック株式会社 半導体装置
JP2007096216A (ja) * 2005-09-30 2007-04-12 Fujitsu Ltd 半導体集積回路装置
JP6149503B2 (ja) * 2013-05-17 2017-06-21 住友電気工業株式会社 半導体装置

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US5514975A (en) * 1992-06-09 1996-05-07 International Business Machines Corporation Data output impedance control
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US5514975A (en) * 1992-06-09 1996-05-07 International Business Machines Corporation Data output impedance control
US5670890A (en) * 1993-04-22 1997-09-23 Lsi Logic Corporation Switchable pull-ups and pull-downs for IDDQ testing of integrated circuits
JPH07221147A (ja) * 1994-02-03 1995-08-18 Hitachi Ltd 半導体装置およびそのプロービング検査方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6373143B1 (en) 1998-09-24 2002-04-16 International Business Machines Corporation Integrated circuit having wirebond pads suitable for probing
US6429675B2 (en) * 1998-09-24 2002-08-06 International Business Machines Corporation Structure and method for probing wiring bond pads
US6516430B1 (en) * 1999-06-29 2003-02-04 Fujitsu Limited Test circuit for semiconductor device with multiple memory circuits
US20110156736A1 (en) * 2009-12-28 2011-06-30 Hynix Semiconductor Inc. Semiconductor apparatus and probe test method thereof
US8829933B2 (en) * 2009-12-28 2014-09-09 SK Hynix Inc. Semiconductor apparatus and probe test method thereof
US20120193622A1 (en) * 2011-01-27 2012-08-02 Elpida Memory, Inc. Device
US8816342B2 (en) * 2011-01-27 2014-08-26 Ps4 Luxco S.A.R.L. Semiconductor device
US20140332813A1 (en) * 2011-01-27 2014-11-13 PS4 Luxco S.A.R.L Semiconductor device
US9142469B2 (en) * 2011-01-27 2015-09-22 Ps4 Luxco S.A.R.L. Semiconductor device

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TW392267B (en) 2000-06-01
KR19990029192A (ko) 1999-04-26
JPH1187441A (ja) 1999-03-30
DE19819252A1 (de) 1999-03-11

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