US20190207055A1 - Method of manufacturing semiconductor optical device and semiconductor optical device - Google Patents

Method of manufacturing semiconductor optical device and semiconductor optical device Download PDF

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US20190207055A1
US20190207055A1 US16/311,816 US201716311816A US2019207055A1 US 20190207055 A1 US20190207055 A1 US 20190207055A1 US 201716311816 A US201716311816 A US 201716311816A US 2019207055 A1 US2019207055 A1 US 2019207055A1
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layer
semiconductor
optical device
substrate
thickness
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Jumpei Yamamoto
Tetsuya Ikuta
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Dowa Electronics Materials Co Ltd
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Dowa Electronics Materials Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004—Devices characterised by their operation
    • H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0079—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes

Definitions

  • This disclosure relates to a method of manufacturing a semiconductor optical device and a semiconductor optical device
  • semiconductor optical devices which emit or receive light in the infrared region are known, such as infrared emission semiconductor light-emitting diodes which emit light with a wavelength of 750 nm or more in the infrared region, and infrared range semiconductor light receiving devices which detect light with wavelengths in the infrared region.
  • infrared emission semiconductor light-emitting diodes are widely used in the applications such as sensors, gas analysis, and surveillance cameras.
  • a p-n junction area formed from an InGaAsP-based III-V semiconductor containing In and P is usually formed.
  • an InGaAsP-based III-V semiconductor layer such as an InP layer
  • an InP substrate is used as a growth substrate so that the growth substrate and the InGaAsP-based III-V semiconductor layer containing In and P are lattice matched.
  • JP H07-147454 A discloses a semiconductor laser diode emitting at wavelengths in the 1.3 ⁇ m range.
  • This semiconductor laser has a strained multiple quantum well active layer formed on an n-type InP substrate, and the strained multiple quantum well active layer has a structure in which InGaAsP strained quantum wells and InGaAsP barrier layers are alternately stacked.
  • JP H06-237042 A (PTL 2) describes that InGaAsP barrier layers having the same lattice constant as an InP substrate, and quantum well layers including strained quantum well layers each formed from an In 0.3 Ga 0.7 As layer having a smaller lattice constant than the InP substrate and lattice strain compensation layers each formed of InAs having a larger lattice constant than the InP substrate are provided on the InP substrate.
  • JP 2001-156324 A discloses a near infrared range semiconductor light receiving device in which an InAsP buffer layer is formed on an InP substrate, an InGaAs light absorption layer having the same lattice constant as the InP substrate is formed on the buffer layer, and an InAsP window layer is formed on the light absorption layer.
  • the InP substrate as the growth substrate is used directly as a support substrate of the semiconductor optical device. This does not affect transparency to infrared light, since the InP substrate is transparent to light in the near infrared region.
  • the thickness of a commercially available InP substrate is typically 350 ⁇ m or more for a 2 in substrate.
  • the thickness of an InGaAsP-based III-V semiconductor layer, an electrode, etc. provided other than the InP substrate in a semiconductor optical device is several micrometers at most. Accordingly, a substrate dominates a semiconductor optical device in thickness.
  • the inventors of this disclosure contemplated epitaxially growing an InGaAsP-based III-V semiconductor layer on an InP substrate and then grinding the InP substrate by 1 ⁇ 3 or more of the original thickness.
  • an InP substrate is brittle, the InP substrate would be broken if the InP substrate is excessively ground to less than 200 ⁇ m, for example 150 ⁇ m or less. Therefore, the thickness of a near infrared range semiconductor optical device could not be reduced sufficiently.
  • the inventors of this disclosure diligently studied ways to address the above problems, and conceived a bonding process method. Then they contemplated removing an InP growth substrate using an Si substrate which can be made thin to serve as a support substrate. This idea led to disclosure.
  • a method of manufacturing a semiconductor optical device comprising:
  • a method of manufacturing a semiconductor optical device comprising:
  • the support substrate is a conductive Si substrate.
  • the n-type cladding layer, the active layer, and the p-type cladding layer are layers formed of an InGaAsP-based III-V compound semiconductor containing at least In and P.
  • a semiconductor optical device comprising:
  • a conductive support substrate formed from a Si substrate
  • a semiconductor laminate in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are stacked, the semiconductor laminate being provided on the metal bonding layer.
  • a semiconductor optical device comprising:
  • a metal bonding layer provided on a surface of the conductive support substrate
  • a semiconductor laminate in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are stacked, the semiconductor laminate being provided on the reflective metal layer;
  • the reflective metal layer mainly contains Au
  • the conductive support substrate is formed from a conductive Si substrate.
  • a thickness of the conductive support substrate is in a range of 80 ⁇ m or more and less than 200 ⁇ m.
  • the semiconductor laminate includes an n-type cladding layer, an active layer, and a p-type cladding layer in this order, and
  • the n-type cladding layer, the active layer, and the p-type cladding layer are layers formed of an InGaAsP-based III-V compound semiconductor containing at least In and P.
  • This disclosure can provide a method of manufacturing a semiconductor optical device, which makes it possible to reduce the thickness of a semiconductor optical device including InGaAsP-based III-V compound semiconductor layers containing at least In and P to a thickness smaller than that of conventional devices, and provide a semiconductor optical device.
  • FIG. 1 presents schematic cross-sectional views illustrating Steps 1 A to 1 C of a manufacturing process of a semiconductor light-emitting diode according to a first embodiment of this disclosure
  • FIG. 2 presents schematic cross-sectional views illustrating Steps 2 A to 2 C of the manufacturing process of a semiconductor light-emitting diode according to the first embodiment of this disclosure
  • FIG. 3 presents schematic cross-sectional views illustrating Steps 3 A and 3 B of the manufacturing process of a semiconductor light-emitting diode according to the first embodiment of this disclosure
  • FIG. 4 presents schematic cross-sectional views illustrating Steps 4 A and 4 B of the manufacturing process of a semiconductor light-emitting diode according to the first embodiment of this disclosure
  • FIG. 5 is a schematic view illustrating the periphery of a dielectric layer and a contact portion of a semiconductor light-emitting diode according to a preferred aspect of the first embodiment of this disclosure
  • FIG. 6 presents schematic cross-sectional views illustrating Steps 6 A to 6 E of a manufacturing process of a semiconductor optical device according to a third embodiment of this disclosure
  • FIG. 7A is a schematic top view illustrating a pattern of an ohmic electrode portion of Examples
  • FIG. 7B is a schematic top view illustrating a pattern of a top electrode of Examples
  • FIG. 8A is a graph depicting a light distribution pattern of Example 1
  • FIG. 8B is a graph depicting a light distribution pattern of Conventional Example 1.
  • the expression “InGaAsP” alone for which the composition ratio is not specified means a given compound having a chemical composition ratio of group III elements (In and Ga in total) with respect to group V elements (As and P) of 1:1, in which the ratio between In and Ga that are group III elements and the ratio between As and P that are group V elements are undefined.
  • group III elements In and Ga in total
  • group V elements As and P
  • InGaAsP specified as “containing at least In and P” means that more than 0% and 100% or less of In is contained in the group III elements, and 0% and 100% or less of P is contained in the group V elements.
  • the expression “InGaP” means that As is not contained in “InGaAsP” above, and the expression “InGaAs” means that P is not contained in “InGaAsP” above.
  • the expression “InAsP” means that Ga is not contained in “InGaAsP” above, and the expression “GaAsP” means that In is not contained in “InGaAsP” above.
  • the expression “InP” means that Ga and As are not contained in “InGaAsP” above. Note that the ratio between the components of InGaAsP can be measured for example by a photoluminescence measurement or an X-ray diffraction measurement.
  • a layer serving as an electrically p-type layer is referred to as a p-type layer
  • a layer serving as an electrically n-type layer is referred to as an n-type layer
  • a layer that is not intentionally doped with certain impurities such as Zn, S, and Sn and does not serve as an electrically p-type or n-type layer is referred to as an “i-type” or “undoped” layer.
  • An undoped InGaAsP layer may contain impurities that are inevitably mixed in the production process. Specifically, when the carrier density is low (for example, less than 4 ⁇ 10 16 /cm 3 ), the layer is handled as being “undoped” in this specification. Further, the values of the impurity concentrations of Zn, Sn, etc. are determined by SIMS analysis.
  • the total thickness of the layers formed can be measured using a thickness measurement system using optical interferometry. Moreover, the thickness of each layer can be calculated by observing a cross section of the growth layer using a thickness measurement system using optical interferometry and a transmission electron microscope. When the thickness of each layer is small as in a superlattice structure, the thickness can be measured using TEM-EDS. Note that when a certain layer has an inclined surface in a cross-sectional view, the thickness of the layer is defined by the maximum height of the layer from a flat surface of the underlying layer.
  • a semiconductor optical device of this disclosure may take two forms: a semiconductor light-emitting diode and a semiconductor light receiving device.
  • a semiconductor light-emitting diode of the first embodiment will be described with reference to the drawings.
  • FIG. 1 to FIG. 4 present schematic cross-sectional views illustrating steps of a method of manufacturing a semiconductor light-emitting diode according to the first embodiment of this disclosure.
  • This semiconductor light-emitting diode can be manufactured in the order of Steps 1 A to 1 C in FIG. 1 , Steps 2 A to 2 C in FIG.
  • FIG. 5 is an enlarged view of the periphery of a dielectric layer 50 and a contact portion 40 of a preferred aspect which are preferably formed in Step 2 C of FIG. 2 .
  • components that are identical or corresponding to each other are herein denoted by the same reference numerals, and thus a description thereof will not be repeated also in the embodiment to be described with reference to FIG. 6 .
  • a substrate and layers in each diagram are exaggerated in width and thickness for convenience of description, so that the ratio between the vertical and horizontal dimensions of each illustrated component does not conform to the actual ratio.
  • a method of manufacturing a semiconductor light-emitting diode 100 has a first step, a second step, a third step, a fourth step, a fifth step, a sixth step, a seventh step, and an eighth step to be described in detail below.
  • a semiconductor laminate 30 in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are stacked is formed on an InP growth substrate 10 (Steps 1 A and 1 B in FIG. 1 ).
  • a contact layer 41 formed of a III-V compound semiconductor is formed on the semiconductor laminate 30 (Step 1 C in FIG. 1 ).
  • an ohmic metal portion 43 is formed on part of the contact layer 41 leaving an exposed area E 1 on a surface of the contact layer 41 (Step 2 A in FIG. 2 ).
  • the contact layer 41 of the exposed area E 1 is removed so that a surface of the semiconductor laminate 30 is exposed, thereby forming a contact portion 40 composed of the ohmic metal portion 43 and the contact layer 41 a and forming an exposed surface E 2 of the semiconductor laminate 30 (Step 2 B in FIG. 2 ).
  • a dielectric layer 50 is formed on at least part of the exposed surface E 2 of the semiconductor laminate 30 (Step 2 C in FIG. 2 ).
  • a reflective metal layer 60 mainly containing Au is formed on the dielectric layer 50 and the contact portion 40 (Step 3 A in FIG. 3 ).
  • a conductive support substrate 80 having a surface provided with a metal bonding layer 70 is bonded to the reflective metal layer 60 with the metal bonding layer 70 therebetween (Step 3 B in FIG. 3 ).
  • the InP growth substrate 10 is removed (Step 4 A in FIG. 4 ).
  • the support substrate 80 is a conductive Si substrate.
  • the first step is a step where the semiconductor laminate 30 in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are stacked is formed on the InP growth substrate 10 (Steps 1 A and 1 B in FIG. 1 ).
  • the InP growth substrate 10 is first prepared.
  • the InP growth substrate 10 may use any one of n-type InP substrate, an undoped InP substrate, and a p-type InP substrate, which are commercially available.
  • An embodiment using an n-type InP substrate as the InP growth substrate 10 for convenience of description will be described below.
  • the semiconductor laminate 30 in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are stacked is formed on the InP growth substrate 10 .
  • the semiconductor laminate 30 includes an n-type cladding layer 31 , an active layer 35 , and a p-type cladding layer 37 in this order, and the n-type cladding layer 31 , the active layer 35 , and the p-type cladding layer 37 are layers formed of an InGaAsP-based III-V compound semiconductor containing at least In and P.
  • the semiconductor laminate 30 may have a double hetero (DH) structure in which the active layer 35 is sandwiched between the n-type cladding layer 31 and the p-type cladding layer 37 or may have a multiple quantum well (MQW) structure. With a view to improving the light output power by reducing crystal defects, the semiconductor laminate 30 more preferably has a multiple quantum-well structure.
  • a multiple quantum-well structure can be formed by alternately repeating well layers 35 W and barrier layers 35 B.
  • the well layers 35 W may be of InGaAsP, and the barrier layers 35 B are preferably of InGaAsP having a larger band gap than the well layers 35 W.
  • the semiconductor laminate 30 as described above allows the semiconductor light-emitting diode 100 to emit light having a wavelength in a desired near-infrared region.
  • an emission peak wavelength of 1000 nm to 1650 nm can be achieved by changing the composition of the InGaAsP-based III-V compound.
  • an emission peak wavelength of 1000 nm to 1900 nm can be achieved by in addition to changing the composition of the InGaAsP-based III-V compound, applying strain to the well layers by controlling the composition difference between the well layers and the barrier layers.
  • n-type cladding layer 31 an n-type InP cladding layer is preferably used, and as the p-type cladding layer 37 , a p-type InP cladding layer is preferably used.
  • chemical composition of the well layers 35 W is expressed as In xw Ga 1-xw As yw P 1-yw , 0.5 ⁇ xw ⁇ 1 and 0.5 ⁇ yw ⁇ 1 can be satisfied, and 0.6 ⁇ xw ⁇ 0.8 and 0.3 ⁇ yw ⁇ 1 are preferably satisfied.
  • the chemical composition of the barrier layers 35 B is expressed as In xb Ga 1-xb As yb P 1-yb , 0.5 ⁇ xb ⁇ 1 and 0 ⁇ yb ⁇ 0.5 can be satisfied, and 0.8 ⁇ xb ⁇ 1 and 0 ⁇ yb ⁇ 0.2 are preferably satisfied.
  • the total thickness of the semiconductor laminate 30 may be for example, but not limited to, 2 ⁇ m to 8 ⁇ m.
  • the thickness of the n-type cladding layer 31 may be for example, but not limited to, 1 ⁇ m to 5 ⁇ m.
  • the thickness of the active layer 35 may be for example, but not limited to, 100 nm to 1000 nm.
  • the thickness of the p-type cladding layer 37 may be for example, but not limited to, 0.8 ⁇ m to 3 ⁇ m.
  • the thickness of the well layers 35 W may be 3 nm to 15 nm
  • the thickness of the barrier layers 35 B may be 5 nm to 15 nm.
  • the number of pairs of both layers may be 3 to 50.
  • the semiconductor laminate 30 preferably has a p-type cap layer 39 formed of InGaAsP containing at least In and P on the p-type cladding layer 37 .
  • the lattice mismatch can be reduced by providing the p-type cap layer 39 .
  • the thickness of the cap layer 39 may be for example, but not limited to, 50 nm to 200 nm. In the following embodiment, for convenience of description, description is made assuming that the outermost surface layer of the semiconductor laminate 30 is the p-type cap layer 39 ; however, since the p-type cap layer 39 is an optional component, the outermost surface layer of the semiconductor laminate 30 may be for example, the p-type cladding layer 37 .
  • the semiconductor laminate 30 preferably has an i-type InP spacer layer each between the n-type cladding layer 31 and the active layer 35 and between the active layer 35 and the p-type cladding layer.
  • the provision of the i-type InP spacer layers can hinder dopant diffusion.
  • the thickness of the i-type InP spacer layers may be for example, but not limited to, 50 nm to 400 nm.
  • the layers in the semiconductor laminate 30 can be formed by epitaxial growth, for example by a known thin film deposition technique such as metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or sputtering.
  • MOCVD metalorganic chemical vapor deposition
  • MBE molecular beam epitaxy
  • TMIn trimethylindium
  • TMGa trimethylgallium
  • arsine (AsH 3 ) as a an As source
  • phosphine (PH 3 ) as a P source at a predetermined mixing ratio
  • these source gases may be subjected to vapor phase epitaxy using a carrier gas to form an InGaAsP layer having a desired thickness by controlling the growth time.
  • a dopant source gas can be used in addition as desired.
  • an etch stop layer 20 is preferably formed on the InP growth substrate 10 .
  • the etch stop layer 20 can be used when the InP growth substrate 10 is removed by etching in the eighth step.
  • the etch stop layer may use an n-type InGaAs layer, in which case the content of In as a group III element in InGaAs is preferably 0.3 to 0.7, more preferably 0.5 to 0.6 so that the etch stop layer can be lattice matched with the InP growth substrate 10 .
  • the second step is a step where the contact layer 41 formed of a III-V compound semiconductor is formed on the semiconductor laminate 30 (Step 1 C in FIG. 1 ).
  • the p-type contact layer 41 can be formed on the p-type cap layer 39 .
  • the p-type contact layer 41 is a layer which is in contact with the ohmic metal portion 43 , is interposed between the ohmic metal portion 43 and the semiconductor laminate 30 , and has a composition allowing for lower contact resistance with the ohmic metal portion 43 than with the semiconductor laminate 30 .
  • a p-type InGaAs layer can be used as the p-type contact layer 41 .
  • the thickness of the contact layer 41 may be for example, but not limited to, 50 nm to 200 nm.
  • the third step is a step where the ohmic metal portion 43 is formed on part of the contact layer 41 leaving the exposed area E 1 on a surface of the contact layer 41 (Step 2 A in FIG. 2 ).
  • the ohmic metal portion 43 can be formed into islands distributed in a predetermined pattern.
  • a p-type InGaAs layer is used as the p-type contact layer 41 , for example, Au, AuZn, AuBe, AuTi, etc. can be used as the ohmic metal portion 43 , and a structure in which those materials are stacked can preferably be used as the ohmic metal portion 43 .
  • Au/AuZn/Au (a stack of Au, AuZn, and Au in this order) may be used as the ohmic metal portion 43 .
  • the thickness (or the total thickness) of the ohmic meal portion 43 may be for example, but not limited to 300 nm to 1300 nm, preferably 350 nm to 800 nm.
  • the third step can be performed by forming a resist pattern on a surface of the contact layer 41 , vapor depositing the ohmic metal portion 43 , and removing the resist pattern by lift-off to obtain the ohmic metal portion 43 .
  • the third step can be performed by forming a predetermined metal layer on the entire surface of the contact layer 41 , forming a mask on the metal layer, and performing for example etching to form the ohmic metal portion 43 .
  • the ohmic metal portion 43 is formed on part of the contact layer 41 , the surface of the contact layer 41 which is not in contact with the ohmic metal portion 43 , that is, the exposed area E 1 is formed.
  • the shape of the ohmic metal portion 43 may be a trapezoidal shape in a cross-sectional view in some cases as illustrated in Step 2 A of FIG. 2 by way of schematic illustration only.
  • the ohmic metal portion 43 may be formed into a rectangular shape or may have rounded corners in a cross-sectional view.
  • the fourth step is a step where the contact layer 41 of the exposed area E 1 is removed so that a surface of the semiconductor laminate 30 is exposed, thereby forming the contact portion 40 composed of the ohmic metal portion 43 and the contact layer 41 a and forming the exposed surface E 2 of the semiconductor laminate 30 (Step 2 B in FIG. 2 ).
  • the contact layer 41 of an area other than the areas of the ohmic metal portion 43 formed in the previous third step is etched to expose a surface of the p-type cap layer 39 which is the outermost surface layer of the semiconductor laminate 30 , thereby obtaining the contact layer 41 a .
  • a resist mask may be formed on and around (approximately 2 ⁇ m to 5 ⁇ m) the ohmic metal portion 43 , and the exposed area E 1 of the contact layer 41 may be wet etched using tartaric acid-hydrogen peroxide mixture.
  • wet etching may be performed using inorganic acid-hydrogen peroxide mixture, organic acid-hydrogen peroxide mixture, etc.
  • the etching of the fourth step can be performed in continuity with the etching in the third step.
  • the thickness of the contact portion 40 corresponds to the total thickness of the contact layer 41 ( 41 a ) and the ohmic metal portion 43 and may be 350 nm to 1500 nm, more preferably 400 nm to 1000 nm.
  • the fifth step is a step where the dielectric layer 50 is formed on at least part of the exposed surface E 2 of the semiconductor laminate 30 (Step 2 C in FIG. 2 ).
  • a dielectric layer 50 may be formed for example as follows.
  • a dielectric layer is deposited on the entire surface of the semiconductor laminate 30 so as to cover the semiconductor laminate 30 and the contact portion 40 .
  • a known technique such as plasma CVD or sputtering can be used.
  • a mask may be formed as desired and the dielectric on the contact portion may be removed by etching etc.
  • the dielectric on the contact portion may be wet etched using buffered hydrofluoric acid (BHF) or the like.
  • the dielectric layer 50 is formed on part of the exposed surface E 2 of the semiconductor laminate 30 leaving an exposed portion E 3 around the contact portion 40 .
  • the dielectric layer 50 and the exposed portion E 3 described above may be formed for example as follows. First, a dielectric layer is deposited on the entire surface of the semiconductor laminate 30 , and a window pattern completely surrounding the contact portion is formed using resist above the contact portion 40 in the surface of the deposited dielectric layer. In this case, the window pattern is preferably 1 ⁇ m to 5 ⁇ m larger than the contact portion both in the width direction and the length direction. Using the thus formed resist pattern to remove the dielectric around the contact portion by etching, the dielectric layer 50 can be formed, and the exposed portion E 3 is formed around the contact portion 40 .
  • Such an exposed portion E 3 is preferably provided, since a heat dissipation path of the semiconductor light-emitting diode 100 is formed.
  • the width W of the exposed portion E 3 is preferably 0.5 ⁇ m or more and 5 ⁇ m or less, more preferably 1 ⁇ m or more and 3.5 ⁇ m or less (see FIG. 5 ).
  • the ratio of the area of the dielectric layer 50 in contact with the semiconductor laminate 30 is preferably 80% or more 95% or less.
  • the contact area ratio can be measured on a wafer, and when the contact area ratio is calculated backwards from the state of singulated semiconductor light-emitting diodes, the calculation can be performed assuming that the width of the semiconductor layer at each end (a region where the electric layer has been present) removed by singulation is 20 ⁇ m to 30 ⁇ m (40 ⁇ m to 60 ⁇ m for both ends in total).
  • the relationship between the thickness H 1 of the dielectric layer 50 and the thickness H 2 of the contact portion 40 is not limited in particular; however, as illustrated in FIG. 5 , when the thickness of the dielectric layer 50 is expressed as H 1 and the thickness of the contact portion is expressed as H 2 , H 1 ⁇ H 2 can be satisfied, and H 1 >H 2 is preferably satisfied. Under these conditions, the thickness of the dielectric layer 50 may be for example, but not limited to 360 nm to 1600 nm, more preferably 410 nm to 1100 nm. Further, the difference between the thickness H 1 of the dielectric layer and the thickness H 2 of the contact portion 40 : H 1 -H 2 is preferably 10 nm or more and 100 nm or less.
  • the dielectric layer 50 may use SiO 2 , SiN, ITO, AlN, etc., and the dielectric layer 50 is preferably formed of SiO 2 in particular. SiO 2 can easily be treated by etching using BHF etc.
  • the sixth step is a step where the reflective metal layer 60 mainly containing Au is formed on the dielectric layer 50 and the contact portion 40 (Step 3 A in FIG. 3 ).
  • the reflective metal layer 60 is formed also on the exposed portion E 3 .
  • the reflective metal layer 60 “mainly containing Au” means that Au composes more than 50% by mass in the composition of the reflective metal layer 60 , and preferably Au composes 80% by mass or more.
  • the reflective metal layer 60 may include a plurality of metal layers; however, when it includes a metal layer formed of Au (hereinafter “Au metal layer”), the thickness of the Au metal layer is preferably more than 50% of the total thickness of the reflective metal layer 60 .
  • the reflective metal layer 60 may be constituted by a single layer formed of Au only; alternatively, the reflective metal layer 60 may include two or more Au metal layers.
  • the outermost surface layer of the reflective metal layer 60 is preferably a Au metal layer.
  • metal layers of Al, Au, Pt, and Au may be formed in this order on the dielectric layer 50 , the exposed portion E 3 , and the contact portion 40 to obtain the reflective metal layer 60 .
  • the thickness of one Au metal layer in the reflective metal layer 60 may be for example 400 nm to 2000 nm, and the thickness of each metal layer formed of a metal other than Au may be for example 5 nm to 200 nm.
  • the reflective metal layer 60 can be formed on the dielectric layer 50 , the exposed portion E 3 , and the contact portion 40 by a typical technique such as a vapor deposition process.
  • the seventh step is a step where the conductive support substrate 80 having a surface provided with the metal bonding layer 70 is bonded to the reflective metal layer 60 with the metal bonding layer 70 therebetween (Step 3 B in FIG. 3 ).
  • the metal bonding layer 70 may previously be formed by sputtering, vapor deposition, etc.
  • the metal bonding layer 70 and the reflective metal layer 60 are placed to face each other and put together, followed by bonding of the layers by thermocompression bonding at a temperature of approximately 250° C. to 500° C.
  • the metal bonding layer 70 bonded to the reflective metal layer 60 may be of metals such as Ti, Pt, and Au, or metals forming a eutectic alloy with gold (e.g., Sn), and is preferably formed from a laminate of those materials.
  • metals such as Ti, Pt, and Au
  • metals forming a eutectic alloy with gold e.g., Sn
  • a laminate obtained by stacking Ti with a thickness of 400 nm to 800 nm, Pt with a thickness of 5 nm to 20 nm, and Au with a thickness of 700 nm to 1200 nm in this order on the surface of the conductive support substrate 80 can be used as the bonging layer 70 .
  • a Au metal layer is provided as the outermost surface layer of the metal bonding layer 70 , and Au is also provided as a metal layer of the reflective bonding layer 60 on the metal bonding layer 70 side to perform bonding between Au and Au by Au—Au diffusion bonding.
  • a conductive Si substrate transparent to near infrared wavelengths is used as the conductive support substrate 80 .
  • a Si substrate hardly breaks, since it has higher hardness than an InP substrate. Accordingly, as compared with the case of using an InP substrate, the thickness of the conductive support substrate 80 can be significantly reduced when a Si substrate is used. Further, a Si substrate is also more advantageous in terms of heat dissipation and cost as compared with an InP substrate.
  • the eighth step is a step where the InP growth substrate 10 is removed (Step A in FIG. 4 ).
  • the InP growth substrate 10 can be removed by wet etching for example using a hydrochloric acid diluent, and when the etch stop layer 20 is formed, etching can be stopped by this layer.
  • the etch stop layer being an n-type InGaAs layer may be removed by wet etching for example using sulfuric acid-hydrogen peroxide mixture.
  • the semiconductor light-emitting diode 100 can be fabricated.
  • This semiconductor light-emitting diode 100 uses a conductive Si substrate as the conductive support substrate 80 , so that the thickness of the support substrate can be made sufficiently smaller than the case of using an InP substrate as the support substrate. Accordingly, the total thickness of the semiconductor light-emitting diode 100 can be made small, thus the semiconductor light-emitting diode 100 can be made small. Further, since the reflective metal layer 60 is provided on the Si substrate of the semiconductor light-emitting diode 100 , light is emitted from the surface of the diode opposite to the Si substrate.
  • the semiconductor light-emitting diode 100 is also useful in that the directivity of the emitted light is higher than the case of conventional semiconductor light-emitting diodes.
  • the manufacturing method according to this embodiment preferably further includes a grinding step of grinding the conductive support substrate 80 to a thickness in a range of 80 ⁇ m or more and less than 200 ⁇ m.
  • the conductive support substrate 80 since a Si substrate is used as the conductive support substrate 80 , the conductive support substrate 80 would not be broken even if it is ground to a thickness of less than 200 ⁇ m.
  • the conductive support substrate 80 can be ground to a thickness of 150 ⁇ m or less, or may be ground to a thickness of 100 ⁇ m or less.
  • the lower limit of the thickness is preferably set to 80 ⁇ m.
  • the semiconductor light-emitting diode 100 is sufficiently handleable.
  • This grinding step may be performed prior to the above seventh step, may be performed between the seventh step and the eighth step, or may be performed after the eighth step. Preferably, the grinding step is performed after the eighth step. Use of a thinned wafer reduces the process step, which prevents the breakage of the wafer more reliably.
  • the grinding step is performed after the eighth step, the grinding step is performed before the formation of the back electrode to be described. Note that the grinding of the conductive support substrate 80 formed from a Si substrate may be performed by typical mechanical grinding, and etching may be performed in addition to the mechanical grinding.
  • the manufacturing method according to this embodiment may further have a step of forming, after the fabrication of the semiconductor light-emitting diode 100 , a back electrode 91 on the back surface of the conductive support substrate 80 and forming a top electrode 93 on the surface of the semiconductor laminate 30 as illustrated in Step 4 B of FIG. 4 .
  • the top electrode 93 may include a wiring portion 93 a and a pad portion 93 b .
  • a semiconductor light-emitting diode 100 ′ can be fabricated.
  • the back electrode 91 and the top electrode 93 can be formed by a known technique; for example, sputtering, electron-beam physical vapor deposition, resistance heating, etc. can be used.
  • the layers formed on the InP growth substrate 10 have n-type and p-type conductivity types as described above.
  • a p-type InP substrate is used as the InP growth substrate 10 , it can naturally be understood that those layers have n-type and p-type conductivity types in reverse order.
  • the conductivity type of those layers may be determined to correspond to the conductivity (p-type or n-type) of the semiconductor layers formed on the InP growth substrate 10 .
  • the semiconductor light-emitting diode 100 can be fabricated by the manufacturing method of the above embodiment.
  • the semiconductor light-emitting diode 100 is a vertical semiconductor light-emitting diode 100 which operates when electric current flows in a vertical direction. Specifically, as illustrated in Step 4 A of FIG.
  • this semiconductor light-emitting diode 100 has the conductive support substrate 80 ; the metal bonding layer 70 provided on the surface of the conductive support substrate 80 ; the reflective metal layer 60 provided on the metal bonding layer 70 ; the semiconductor laminate 30 in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are stacked, provided on the metal reflective layer 60 ; and the dielectric layer 50 and the contact portion 40 which are provided in parallel between the reflective metal layer 60 and the semiconductor laminate 30 .
  • the main component of the reflective metal layer 60 is Au
  • the conductive support substrate 80 is formed from a conductive Si substrate.
  • this semiconductor light-emitting diode 100 uses a conductive Si substrate as the conductive support substrate 80 , so that the thickness of the support substrate can be made sufficiently small. Moreover, the semiconductor light-emitting diode 100 is also useful in that the directivity of the emitted light is higher than in the case of conventional semiconductor light-emitting diodes, since the reflective metal layer 60 is provided on the Si substrate side.
  • the thickness of the conductive support substrate 80 can be 80 ⁇ m or more and less than 200 ⁇ m, and the thickness can be 150 ⁇ m or less, or 100 ⁇ m or less.
  • the semiconductor laminate 30 includes an n-type cladding layer 31 , an active layer 35 , and a p-type cladding layer 37 in this order, and the n-type cladding layer 31 , the active layer 35 , and the p-type cladding layer 37 are layers formed of an InGaAsP-based III-V compound semiconductor containing at least In and P.
  • the semiconductor laminate 30 may have a double hetero structure in which the active layer 35 is sandwiched between the n-type cladding layer 31 and the p-type cladding layer 37 or a multiple quantum well structure, and the active layer 35 preferably has multiple quantum well structure.
  • the dielectric layer is preferably formed of SiO 2 .
  • the semiconductor light-emitting diode 100 may have another optional structure. Further, as illustrated in Step 4 B of FIG. 4 , the back electrode 91 and the top electrode 93 may be provided on the semiconductor light-emitting diode 100 to obtain the semiconductor light-emitting diode 100 ′.
  • a method of manufacturing a semiconductor optical device and a semiconductor optical device according to this disclosure can be applied to an embodiment of a semiconductor light receiving device.
  • a semiconductor laminate including for example an InGaAs light absorption layer and an InP window layer is provided instead of the semiconductor laminate 30 in the semiconductor light-emitting diode 100
  • the semiconductor optical device can be used as a semiconductor light receiving device. Since a semiconductor light receiving device according to this disclosure uses a Si substrate as a conductive support substrate, as in the semiconductor light-emitting diode 100 , the thickness of the conductive support substrate can be made small, and hence the total thickness of the semiconductor light receiving device can be made small; thus, a small semiconductor light receiving device can be obtained.
  • a conductive support substrate formed from a Si substrate in a semiconductor optical device using a III-V compound semiconductor containing In and P, formed on an InP substrate can of course be applied to the following method of manufacturing a semiconductor optical device of the third embodiment.
  • a method of manufacturing a semiconductor optical device 1 includes a step of forming the semiconductor laminate 30 in which a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are stacked, on the InP growth substrate (Steps 6 A and 6 B of FIG. 6 ); a step of bonding the semiconductor laminate 30 to the conductive support substrate 80 formed from a Si substrate, with at least the metal bonding layer 70 therebetween (Step 6 C of FIG. 6 ); and a step of removing the InP growth substrate 10 (Step 6 D of FIG. 6 ).
  • the manufacturing method according to this embodiment preferably further includes a grinding step of grinding the conductive support substrate 80 to a thickness in a range of 80 ⁇ m or more and less than 200 ⁇ m (Step 6 E of FIG. 6 ).
  • the small semiconductor optical device 1 ′ can be manufactured, in which the thickness of the conductive support substrate 80 is in a range of 80 ⁇ m or more and less than 200 ⁇ m.
  • the semiconductor optical device 1 of this disclosure can be fabricated by the manufacturing method of the above embodiment. Specifically, as illustrated in Step 6 D of FIG. 6 , the semiconductor optical device 1 of this disclosure has the conductive support substrate 80 formed from a Si substrate; a metal bonding layer 70 provided on the surface of the conductive support substrate 80 ; and the semiconductor laminate 30 obtained by stacking a plurality of InGaAsP-based III-V compound semiconductor layers containing at least In and P are stacked, provided on the metal bonding layer 70 .
  • the thickness of the conductive support substrate 80 is preferably in a range of 80 ⁇ m or more and less than 200 ⁇ m.
  • the semiconductor optical device 1 ′ can be made small.
  • any given structure of the semiconductor light-emitting diode and the semiconductor light receiving device according to the first embodiment and the second embodiment can be applied to the semiconductor optical device 1 ( 1 ′).
  • a semiconductor light-emitting diode of Example 1 was fabricated in accordance with the process steps illustrated in FIGS. 1 to 4 . The steps are demonstrated as follows.
  • an n-type In 0.57 Ga 0.43 As etch stop layer an n-type InP cladding layer (thickness: 2 ⁇ m), an i-type InP spacer layer (thickness: 300 nm), an active layer having a quantum well structure with an emission wavelength of 1300 nm (130 nm in total), an i-type InP spacer layer (thickness: 300 nm), a p-type InP cladding layer (thickness: 1.2 ⁇ m), a p-type In 0.8 Ga 0.20 As 0.5 P 0.5 cap layer (thickness: 50 nm), and a p-type In 0.57 Ga 0.43 As contact layer (thickness: 130 nm) were sequentially formed by MOCVD.
  • a p-type ohmic electrode portion (Au/AuZn/Au, total thickness: 530 nm) was formed into islands distributed as illustrated in FIG. 7A .
  • the cross-sectional view of FIG. 7A taken along line I-I corresponds to the schematic cross-sectional view of Step 2 A in FIG. 2 .
  • a resist pattern was formed and an ohmic electrode was then vapor deposited, followed by lift-off of the resist pattern.
  • the contact area ratio of the p-type ohmic electrode portion with respect to the semiconductor layer was 4.5%. Note that the outer size of the object depicted in FIG. 7A is 380 ⁇ m square.
  • a resist mask was formed on and around the p-type ohmic electrode portion, and the p-type In 0.57 Ga 0.43 As contact layer was removed, except for areas where the ohmic electrode portion was formed, by wet etching using tartaric acid-hydrogen peroxide mixture.
  • a dielectric layer thinness: 700 nm
  • SiO 2 was formed on the entire surface of the p-type In 0.80 Ga 0.20 As 0.50 P 0.50 cap layer by plasma CVD.
  • a window pattern having a shape extending over 3 ⁇ m each in the width direction and the longitudinal direction in an area above the p-type ohmic electrode portion was formed using resist, and the dielectric layer on and around the p-type ohmic electrode portion was removed by wet etching using BHF to expose the p-type In 0.80 Ga 0.20 As 0.50 P 0.50 cap layer.
  • the height H 1 (700 nm) of the dielectric layer on the p-type In 0.80 Ga 0.20 As 0.50 P 0.50 cap layer is larger than the height H 2 (660 nm) of the contact portion composed of the p-type contact layer (thickness: 130 nm) and the p-type ohmic electrode portion (thickness: 530 nm) by 40 nm.
  • the contact area ratio of the dielectric layer (SiO 2 ) was 90%.
  • a reflective metal layer (Al/Au/Pt/Au) was formed on the entire surface of the p-type In 0.80 Ga 0.20 As 0.50 P 0.50 cap layer by vapor deposition.
  • the thickness of the metal layers in the reflective metal layer was 10 nm, 650 nm, 100 nm, and 900 nm in this order.
  • a metal bonding layer (Ti/Pt/Au) was formed on a conductive Si substrate serving as a support substrate (thickness: 300 ⁇ m).
  • the thickness of the metal layers in the metal bonding layer was 650 nm, 10 nm, and 900 nm in this order.
  • the reflective metal layer and the metal bonding layer were placed to face one another and were subjected to thermocompression bonding at 300° C. Further, the InP substrate was removed by wet etching using a hydrochloric acid diluent, and the n-type In 0.57 Ga 0.43 As etch stop layer was removed by wet etching using sulfuric acid-hydrogen peroxide mixture.
  • an n-type electrode (Au (thickness: 10 nm)/Ge (thickness: 33 nm)/Au (thickness: 57 nm)/Ni (thickness: 34 nm)/Au (thickness: 800 nm)/Ti (thickness: 100 nm)/Au (thickness: 1000 nm)) was formed as a wiring portion of a top electrode by resist pattern formation, vapor deposition of an n-type electrode, and lift-off of the resist pattern as illustrated in FIG. 7B .
  • a pad portion (Ti (thickness: 150 nm)/Pt (thickness: 100 nm)/Au (thickness: 2500 nm)) was formed on the n-type electrode to obtain the top electrode having a pattern as illustrated in FIG. 7B .
  • the cross-sectional view of FIG. 7B taken along line II-II corresponds to Step 4 B in FIG. 4 .
  • the outer size of the object depicted in FIG. 7B is 380 ⁇ m square as with FIG. 7A .
  • the semiconductor layers between devices were removed by mesa etching to form dicing lines.
  • a back electrode Ti (thickness: 10 nm)/Pt (thickness: 50 nm)/Au (thickness: 200 nm) was formed on the back surface of the Si substrate, and chip singulation was performed by dicing to obtain a semiconductor light-emitting diode of Example 1.
  • the chip size was 350 ⁇ m ⁇ 350 ⁇ m.
  • a semiconductor light-emitting diode according to Example 2 was fabricated in the same manner as in Example 1 except that the Si substrate was ground to a thickness of approximately 87 ⁇ m immediately before forming the back electrode on the Si substrate to obtain a semiconductor light-emitting diode having a total thickness of 120 ⁇ m.
  • a semiconductor light-emitting diode according to Conventional Example 1 was fabricated as follows. First, on the (100) plane of an n-type InP substrate, an n-type InP cladding layer (thickness: 2 ⁇ m), an i-type InP spacer layer (thickness: 300 nm), an active layer having a quantum well structure with an emission wavelength of 1300 nm (130 nm in total), an i-type InP spacer layer (thickness: 300 nm), a p-type InP cladding layer (thickness: 1.2 ⁇ m), a p-type In 0.80 Ga 0.20 As 0.50 P 0.50 cap layer (thickness: 50 nm), and a p-type In 0.57 Ga 0.43 As contact layer (thickness: 130 nm) were sequentially formed by MOCVD.
  • a back electrode Ti (thickness: 10 nm)/Pt (thickness: 50 nm)/Au (thickness: 200 nm) was formed on the back surface of the n-type InP substrate, a top electrode (AuGe/Ni/Au electrode) was formed on a center portion of the p-type In 0.57 Ga 0.43 As contact layer, and singulation was performed as in Example 1. Note that in forming the active layer having a quantum well structure, ten In 0.73 Ga 0.27 As 0.50 P 0.50 well layers (thickness: 5 nm) and ten InP barrier layers (thickness: 8 nm) were alternately stacked.
  • Example 1 a semiconductor light-emitting diode was fabricated in the same manner as in Conventional Example 1 except that a InP substrate was ground immediately before forming a back electrode on an InP substrate. However, the InP substrate was broken in the grinding before the thickness of the InP substrate reached 150 ⁇ m and the device was not completed in Comparative Example 1.
  • Example 1 As can be seen from the comparison between Example 1 and Example 2, when a Si substrate was used as the conductive support substrate, the semiconductor light-emitting diode having a total thickness of 120 ⁇ m was obtained by grinding the Si substrate, thus a small semiconductor light-emitting diode with a center emission wavelength of 1300 nm was obtained. On the other hand, as can be seen from the comparison between Conventional Example 1 and Comparative Example 1, since the InP substrate was broken while being ground, thus a small semiconductor light-emitting diode was not obtained.
  • Example 1 An electric current of 20 mA was flown to each semiconductor light-emitting diode obtained in Example 1 and Conventional Example 1, and a light distribution pattern was identified using a spectrophotometer. Note that the identification was performed while the semiconductor light-emitting diode was rotated 180° with a solid angle of 6 ⁇ 10 ⁇ 3 steradians and the distance between the semiconductor light-emitting diode and the spectrophotometer was 20 cm.
  • the light distribution patterns of Example 1 and Conventional Example 1 are presented in FIGS. 8A and 8B , respectively. As seen from FIGS. 8A and 8B , higher directivity was achieved in Example 1 than in Conventional Example 1.
  • the forward voltage Vf at a 20 mA current supplied to each of the semiconductor light-emitting diodes obtained in Example 1 and Conventional Example 1 by a constant current constant voltage power supply was measured and the light output power Po thereof was measured using an integrating sphere.
  • the measurement was performed on three samples for each example, and the average of the measurement results for each example was calculated.
  • the results are given in Table 1.
  • the peak emission wavelength was measured using a fiber optic spectrometer in Example 1 and Conventional Example 1 and was in a range of 1290 nm to 1310 nm in each example.
  • Example 1 a small semiconductor light-emitting diode can be embodied with the use of a Si substrate in accordance with Examples 1 and 2 meeting the conditions of this disclosure. Further, since the reflective metal layer is used, Examples 1 and 2 are more advantageous than Conventional Example 1 in terms of achieving high directivity. Further, comparison of Example 1 and Conventional Example 1 confirmed that the light output power was substantially increased while the forward voltage was slightly reduced in Example 1, as compared with Conventional Example 1.
  • This disclosure advantageously provides a method of manufacturing a semiconductor optical device, which makes it possible to reduce the thickness of a semiconductor optical device including InGaAsP-based III-V compound semiconductor layers containing at least In and P to a thickness smaller than that of conventional devices, and provides a semiconductor optical device.
  • a semiconductor light-emitting diode high directivity and substantially increased light output power can be achieved, thus, the diode can be used as a high-performance semiconductor light-emitting diode.

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US11996496B2 (en) 2017-12-22 2024-05-28 Dowa Electronics Materials Co., Ltd. Semiconductor light-emitting device
US11894502B2 (en) 2018-03-30 2024-02-06 Dowa Electronics Materials Co., Ltd. Method of manufacturing semiconductor optical device and intermediate article of semiconductor optical device
US11515448B2 (en) * 2018-04-19 2022-11-29 Dowa Electronics Materials Co., Ltd. Semiconductor light-emitting element and method of manufacturing the same
US11637220B1 (en) 2018-04-19 2023-04-25 Dowa Electronics Materials Co., Ltd. Semiconductor light-emitting element

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US11417793B2 (en) 2022-08-16
US20200227585A1 (en) 2020-07-16
KR20190009794A (ko) 2019-01-29
CN109314158B (zh) 2021-06-01
KR102209263B1 (ko) 2021-01-28
TWI662629B (zh) 2019-06-11
DE112017003307T5 (de) 2019-04-04
TW201802952A (zh) 2018-01-16
JP6452651B2 (ja) 2019-01-16

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