US20190141357A1 - Semiconductor apparatus for image transmission - Google Patents

Semiconductor apparatus for image transmission Download PDF

Info

Publication number
US20190141357A1
US20190141357A1 US16/233,299 US201816233299A US2019141357A1 US 20190141357 A1 US20190141357 A1 US 20190141357A1 US 201816233299 A US201816233299 A US 201816233299A US 2019141357 A1 US2019141357 A1 US 2019141357A1
Authority
US
United States
Prior art keywords
data
semiconductor apparatus
character
character data
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US16/233,299
Other languages
English (en)
Inventor
Hiroharu ENDO
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Assigned to ROHM CO., LTD. reassignment ROHM CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ENDO, HIROHARU
Publication of US20190141357A1 publication Critical patent/US20190141357A1/en
Priority to US17/196,521 priority Critical patent/US11659211B2/en
Priority to US18/299,448 priority patent/US12126842B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
    • H04N19/93—Run-length coding
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/026—Control of mixing and/or overlay of colours in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/12—Synchronisation between the display unit and other units, e.g. other display units, video-disc players
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/18—Timing circuits for raster scan displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/37—Details of the operation on graphic patterns
    • G09G5/377—Details of the operation on graphic patterns for mixing or overlaying two or more graphic patterns
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/02—Handling of images in compressed format, e.g. JPEG, MPEG

Definitions

  • the present invention relates to a semiconductor apparatus for image transmission such as a timing controller.
  • FIG. 1 is a block diagram of an image display system.
  • An image display system 100 R includes a display panel 102 such as a liquid crystal display panel and an organic electroluminescence (EL) panel, a gate driver 104 , source drivers 106 , a graphic controller 110 , and a timing controller 200 R.
  • the graphic controller 110 generates image data to be displayed on the display panel 102 .
  • Pixel (RGB) data contained in this image data is transmitted to the timing controller 200 R in a serial manner.
  • the timing controller 200 R receives the image data and generates various control/synchronous signals.
  • the gate driver 104 sequentially selects scanning lines Ls of the display panel 102 in synchronization with the signals from the timing controller 200 R.
  • the RGB data is supplied to the source drivers 106 .
  • the timing controller 200 R includes a reception circuit 202 , a transmission circuit 204 , and a logic circuit 210 .
  • the reception circuit 202 receives image data from the graphic controller 110 in a serial manner.
  • An external read-only memory (ROM) 111 has stored therein ID (identification information), resolution, refresh rate, and the like of the display panel 102 .
  • the logic circuit 210 generates control/synchronous signals based on the image data received by the reception circuit 202 .
  • the transmission circuit 204 outputs the control signals and the image data to the gate driver 104 and the source drivers 106 .
  • the timing controller 200 R is required to have an On Screen Display (OSD) function of displaying predetermined characters, graphics, icons, and the like (hereinbelow referred to simply as characters) in addition to the image data received by the reception circuit 202 .
  • OSD On Screen Display
  • the logic circuit 210 includes an OSD circuit 212 .
  • the ROM 111 has stored therein bitmap data for several characters and icons.
  • the timing controller 200 R reads from the ROM 111 bitmap data for characters corresponding to the control signals to be input separately from the image data and displays the characters on the display panel 102 .
  • the timing controller 200 R and the graphic controller 110 are connected by means of a differential serial interface.
  • a differential serial interface During a period from start of activation of the image display system 100 R to establishment of a link between the timing controller 200 R and the graphic controller 110 by means of the serial interface, no image data can be transmitted, and no image can thus be displayed on the display panel 102 .
  • the link is once established, and in which the link is then disconnected due to a noise or the like, no image can be displayed on the display panel 102 until the link is established again.
  • a similar problem occurs in a case in which the cable is pulled or disconnected, or in which the serial interface or the graphic controller 110 is partially failed. In the present description, such a state in which no image can be displayed as each of the above states is referred to as “an undisplayable state.”
  • One embodiment of the present invention is accomplished by taking Problem 1 into consideration thereof, and an illustrative general purpose thereof is to provide a semiconductor apparatus for image data transmission enabling a flexible OSD function to be provided.
  • Another embodiment of the present invention is accomplished by taking Problem 2 into consideration thereof, and an illustrative general purpose thereof is to provide a semiconductor apparatus for image data transmission enabling an abnormal state to be detected.
  • the semiconductor apparatus includes a video input interface structured to receive input video data in a normal state, a control input interface structured to receive character data for On Screen Display (OSD) in a setup state, an encoder structured to encode the character data and store encoded compressed data in a memory in the setup state, a decoder structured to receive an instruction signal designating the character data to be displayed, read and decode one piece of compressed data corresponding to the instruction signal from the memory, and reproduce the character data before encoding in the normal state, and a multiplexer structured to superimpose the character data on the image data and output the data.
  • OSD On Screen Display
  • the encoder and the decoder for the character data for the OSD are incorporated in the semiconductor apparatus, and the character data is given each time the semiconductor apparatus is in the setup state, various kinds of character data can be displayed.
  • the character data can contain graphics, icons, characters, or an arbitrary combination thereof.
  • the encoder may compress the character data by means of run-length compression.
  • the compressed data may contain at least one piece of segment data, and each piece of segment data may represent a same-color segment including consecutive pixels having a same color. Accordingly, the circuit scale of the encoder can be reduced, and the capacity of the memory can be reduced.
  • the segment data may contain color data representing a color and a run-length value representing the number of the consecutive pixels.
  • a format length of the run-length value may be variable. Accordingly, the compression ratio can further be improved.
  • the segment data may contain a color word and at least one run-length word.
  • the color word may contain a separator bit and the color data
  • the run-length word may contain the separator bit and the run-length value.
  • the segment data may contain a color word containing the color data, a word number designation bit representing the number of words of the run-length value, and as many run-length words as the number of words.
  • the control input interface may receive size data designating a pixel size of the character data and store the size data as well as the compressed data in the memory. Accordingly, the character data of various sizes can be displayed.
  • the instruction signal may contain positional information designating a position at which the character data is to be displayed.
  • the multiplexer may display the character data at a position corresponding to the positional information. Accordingly, the further flexible OSD function can be provided.
  • the control input interface may be a serial peripheral interface (SPI) or an inter-integrated circuit (I 2 C) interface. Since these interfaces are used widely and generally, implementation thereof is easy.
  • SPI serial peripheral interface
  • I 2 C inter-integrated circuit
  • the semiconductor apparatus may be integrated on one semiconductor substrate.
  • integrated is used in a case in which all components of a circuit are formed on a semiconductor substrate and in a case in which main components of a circuit are formed on a semiconductor substrate. Some resistors, capacitors, and the like may be provided outside the semiconductor substrate for adjustment of circuit constant.
  • the electronic device may include any of the above semiconductor apparatuses.
  • Another embodiment of the present invention relates to an in-vehicle display device or a medical display device.
  • Each of these display devices may include any of the above semiconductor apparatuses.
  • the semiconductor apparatus includes a video input interface structured to receive input video data, a memory structured to store reference character data describing a predetermined character that can be contained in the input video data, an image processing circuit structured to generate output video data to be displayed on a display panel based on the input video data, and an abnormality detector structured to determine whether or not there is an abnormality based on the input video data and the reference character data.
  • the character data can contain graphics, icons, characters, or an arbitrary combination thereof.
  • the semiconductor apparatus may further include a control input interface provided separately from the video input interface to enable communication with an outside processor.
  • a display position of the predetermined character may be variable.
  • a control signal that the control input interface receives from the processor may contain positional information indicating the display position of the predetermined character.
  • the predetermined character may be arranged in a fixed manner at a predetermined position in a user-unrecognizable state.
  • the abnormality detector may perform determination processing per frame.
  • the predetermined character may be arranged in a fixed manner at a predetermined position at the end portion on the display panel that cannot be seen by the user.
  • a control signal that the control input interface receives from the processor may contain information indicating whether or not the predetermined character is targeted for determination by the abnormality detector.
  • the control signal may contain information indicating whether or not a current frame is targeted for determination by the abnormality detector.
  • the semiconductor apparatus may support an OSD function.
  • the memory may have stored therein character data for the OSD, and the image processing circuit may superimpose the character data for the OSD on the input video data in an OSD mode.
  • the reference character data and the character data for the OSD may be used in common. Accordingly, the capacity of the memory can be saved.
  • the semiconductor apparatus may be able to select the OSD mode or a determination mode in which determination is given by the abnormality detector.
  • the memory may be a non-volatile memory.
  • the memory may be a volatile memory.
  • the control input interface may be able to receive character data indicating the predetermined character in a setup state.
  • the semiconductor apparatus may include an encoder structured to encode the character data to generate compressed data and store the compressed data in the memory as the reference character data in the setup state, and a decoder structured to decode the reference character data to reproduce the predetermined character before encoding in a normal state. Since the encoder and the decoder for the character are incorporated in the semiconductor apparatus, and the character data is given each time the semiconductor apparatus is in the setup state, various kinds of character data can be displayed.
  • the encoder may compress the reference character data by means of run-length compression.
  • the compressed data may contain at least one piece of segment data.
  • Each piece of segment data may represent a same-color segment including consecutive pixels having a same color. Accordingly, the circuit scale of the encoder can be reduced, and the capacity of the memory can be reduced.
  • the control input interface may be a serial peripheral interface (SPI) or an inter-integrated circuit (I 2 C) interface. Since these interfaces are used widely and generally; implementation thereof is easy.
  • SPI serial peripheral interface
  • I 2 C inter-integrated circuit
  • the semiconductor apparatus may interrupt the processor. This enables notification of generation of an undisplayable state to be given to the processor.
  • the processor may operate the semiconductor apparatus in the determination mode before generation of the undisplayable state, and when the processor is interrupted, the processor may operate the semiconductor apparatus in the OSD mode and compensate for a loss of the input video data by means of the OSD with use of the control input interface.
  • the semiconductor apparatus may be integrated on one semiconductor substrate.
  • integrated is used in a case in which all components of a circuit are formed on a semiconductor substrate and in a case in which main components of a circuit are formed on a semiconductor substrate. Some resistors, capacitors, and the like may be provided outside the semiconductor substrate for adjustment of circuit constant.
  • the electronic device may include any of the above semiconductor apparatuses.
  • Another embodiment of the present invention relates to an in-vehicle display device or a medical display device.
  • Each of these display devices may include any of the above semiconductor apparatuses.
  • FIG. 1 is a block diagram of an image display system:
  • FIG. 2 is a block diagram of a timing controller according to a first embodiment
  • FIG. 3 describes run-length compression of character data
  • FIG. 4 illustrates a state in which compressed data is stored in a memory
  • FIG. 5A to FIG. 5C illustrate data structures of same-color segments:
  • FIG. 6 illustrates compression ratios of the same-color segments when a second data structure in FIG. 5B is employed
  • FIG. 7 illustrates a display panel on which two pieces of character data are displayed:
  • FIG. 8A to FIG. 8C illustrate an in-vehicle display device using the timing controller
  • FIG. 9 is a perspective view illustrating an electronic device:
  • FIG. 10 is a block diagram of an image display system including a timing controller according to a second embodiment
  • FIG. 11 illustrates an example of a predetermined character
  • FIG. 12A and FIG. 12B illustrate abnormality detection by means of the timing controller
  • FIG. 13 is a block diagram of an image display system including a timing controller according to an embodiment:
  • FIG. 14 is a block diagram of the image display system including a timing controller according to an embodiment.
  • FIG. 15 illustrates the display panel on which two pieces of character data are displayed.
  • a state in which a member A is connected to a member B includes a case in which the member A and the member B are connected physically directly and a case in which the member A and the member B are connected indirectly via another member which has no substantial effect on the electric connection state between the members or which does not impair a function and an effect obtained by the connection between the members.
  • a state in which a member C is provided between a member A and a member B includes a case in which the member A and the member C, or the member B and the member C, are connected directly and a case in which the member A and the member C. or the member B and the member C, are connected indirectly via another member which has no substantial effect on the electric connection state between the members or which does not impair a function and an effect obtained by the connection between the members.
  • FIG. 2 is a block diagram of a timing controller 300 according to a first embodiment.
  • the timing controller 300 receives input video data S 1 from a graphic controller 110 , supplies output video data S 2 to one or a plurality of source driver(s) 106 , and outputs a control/synchronous signal S to a gate driver 104 and one or the plurality of source driver(s) 106 .
  • the timing controller 300 may be a functional integrated circuit (IC) integrated on one semiconductor substrate.
  • the timing controller 300 includes a video input interface 302 , a memory 304 , a main logic 306 , an output interface 308 , a control input interface 310 , and an OSD processor 320 .
  • the video input interface 302 , the main logic 306 , and the output interface 308 are circuit blocks related to display of image data from the graphic controller 110 and may be the same as those included in the conventional timing controller 200 R.
  • the video input interface 302 is connected to the graphic controller 110 via a first line 112 and receives the input video data S 1 .
  • a differential high-speed serial interface such as a low voltage differential signaling (LVDS) can be employed.
  • the input video data S 1 received by the video input interface 302 is stored as frame data S 4 in the memory 304 .
  • the memory 304 may be a static random access memory (SRAM) without limitation.
  • the main logic 306 performs various kinds of signal processing to the frame data S 4 .
  • the signal processing of the main logic 306 is not particularly limited, and a known technique may be used such as ⁇ (gamma) correction, frame rate control (FRC) processing, and RGB mapping.
  • the output interface 308 outputs the output video data S 2 processed by the main logic 306 to the source driver 106 .
  • the main logic 306 also generates the control/synchronous signal S 3 that is to be supplied to the gate driver 104 and the source driver 106 .
  • the control input interface 310 , the OSD processor 320 , and a multiplexer 330 are provided in relation to an OSD function.
  • the timing controller 300 is in a setup state immediately after turning on the power.
  • the timing controller 300 has a period for setting parameters and the like of the ⁇ correction and the RGB mapping (initializing period) at the time of the power-on as a previous stage to reception and output of the video input data to a panel.
  • a part of the initializing period may be regarded as the setup state.
  • giving a command from an outside to the timing controller 300 may enable the setup state to be set.
  • a register associated with the setup state may be provided inside a timing controller 300 a , and 1 may be written in the register from the outside (for example, a processor 114 ) to shift a state to the setup state.
  • the state can be shifted to the setup state not only immediately after turning on the timing controller 300 but also at an arbitrary time.
  • the control input interface 310 receives character data S 5 for On Screen Display (OSD) from the processor 114 in the setup state.
  • the character data S 5 is stored in a non-volatile memory 118 and is transmitted via the processor 114 to the control input interface 310 .
  • the character data S 5 may be monochrome or colored bitmap data without limitation.
  • the representation form of the character data S 5 is an arbitrary form such as icons, graphics, and characters.
  • a register-access-type interface can be used as the control input interface 310 .
  • Favorable examples thereof include, but are not limited to, a serial peripheral interface (SPI) and an inter-integrated circuit (I 2 C) interface.
  • FIG. 2 illustrates a configuration in which the processor 114 is provided separately from the graphic controller 110 , the function of the processor 114 may be incorporated into the graphic controller 110 .
  • the OSD processor 320 includes an encoder 322 and a decoder 324 .
  • the encoder 322 encodes the character data S 5 and stores encoded compressed data S 6 in the memory 304 . Also, address information S 7 representing an address at which the compressed data S 6 has been stored is stored to correspond to the character data S 5 .
  • a plurality of pieces of character data S 5 may be input.
  • an ID may be given to each piece of character data S 5 , correspond to the compressed data S 6 and the address information S 7 , and be stored in the memory 304 .
  • control input interface 310 receives an instruction signal S 8 containing an ID designating character data to be displayed.
  • the decoder 324 refers to the address information S 7 corresponding to the ID and reads from the memory 304 and decodes a piece of compressed data S 6 corresponding to the ID information to reproduce original character data Sq.
  • the multiplexer 330 superimposes the character data S 9 on frame data S 10 output from the main logic 306 and outputs the data to the output interface 308 .
  • a position at which the character data S 9 is to be displayed is preferably controllable.
  • the instruction signal S 8 may contain positional information POS designating the position at which the character data S 9 is to be displayed.
  • the multiplexer 330 displays the character data S 9 at the position corresponding to the positional information POS.
  • FIG. 3 describes run-length compression of the character data S 5 .
  • the character data of 7 ⁇ 6 pixels is illustrated in FIG. 3 to simplify the description, actual character data may contain 50 ⁇ 50 pixels, 100 ⁇ 100 pixels, or as many pixels as another number. Also, the number of pixels in the vertical direction and the number of pixels in the horizontal direction may differ.
  • consecutive pixels having the same color are converted into color data CD and a run-length value RL representing a value for the consecutive number.
  • a run-length value RL representing a value for the consecutive number.
  • pixels are processed from the upper line to the lower line, and in each line, from the left end to the right end.
  • Each of the arrows in FIG. 3 represents a same-color segment SEG
  • the color data CD can be represented by 24 bits consisting of 8 bits of each of R. G and B.
  • the character data S 5 in FIG. 3 is divided into five same-color segments SEG 1 to SEG 5 .
  • the run-length values RL of the respective same-color segments SEG 1 to SEG 5 are 17, 2, 5, 2, and 16.
  • the same-color segments SEG 1 , SEG 3 , and SEG 5 have a first color while the same-color segments SEG 2 and SEG 4 have a second color. Accordingly, the compressed data S 6 corresponding to one piece of character data S 5 can be represented by one piece of segment data SEG or a combination of a plurality of pieces of segment data SEG.
  • FIG. 4 illustrates a state in which compressed data COMP (S 6 ) is stored in the memory 304 .
  • First compressed data COMP 1 contains M pieces of segment data representing M same-color segments
  • second compressed data COMP 2 contains N pieces of segment data
  • third compressed data COMP 3 contains K pieces of segment data.
  • An initial address of each piece of compressed data COMP is stored as address information ADR in the memory 304 .
  • a size (the number of pixels) of the character data S 5 may be fixed to 50 pixels ⁇ 50 pixels, for example. However, to provide additional flexibility, the size may be selectable from a plurality of options by a user.
  • the timing controller 300 may be configured to support two sizes of 50 ⁇ 50 pixels and 100 ⁇ 100 pixels.
  • size data SIZE designating the size may be input as well as the character data S 5 .
  • the size data SIZE is stored in the memory 304 to correspond to the ID of the character data S 5 .
  • the user may be able to designate the size of the character data S 5 freely.
  • the size data SIZE may be input to designate the number of vertical pixels and the number of horizontal pixels, as well as the character data S 5 .
  • the size data is stored in the memory 304 to correspond to the ID of the character data S 5 .
  • FIG. 5A to FIG. 5C illustrate data structures of the same-color segments SEG
  • FIG. 5A illustrates a first data structure.
  • Data of each same-color segment SEG contains one or a plurality of set(s) SET of a color word CW and a run-length word RLW.
  • run-length words RLW ⁇ 000> to ⁇ 111> can represent run-length values 1 to 8.
  • the compressed data thereof is represented by one set SET 1 containing one color word CW and one run-length word RLW as illustrated in FIG. 5A .
  • the same-color segment SEG contains a plurality of sets each having the same color data CD.
  • the consecutive number is divided into 16 and 1. That is, the same-color segment SEG 1 is represented by two sets SET 1 and SET 2 .
  • the color words CW are the same, and the run-length word RLW of the first set is ⁇ 111> while the run-length word RLW of the second set is ⁇ 011>.
  • the consecutive number can be divided into 8+8+a (where 1 ⁇ a ⁇ 8), and the same-color segment SEG can contain three sets SET.
  • the number of bits for each word is 3 here to facilitate understanding, the number is not limited to this and may be 4 to 6 bits or so.
  • the optimal number of bits for each word may be determined to have a high compression ratio in consideration of the shape and the size of the character data.
  • FIG. 5B illustrates a second data structure.
  • the format length of the run-length value RL is variable.
  • a separator bit representing a boundary of the same-color segment SEG is provided.
  • the separator bit is a termination bit TB representing a termination of the same-color segment, and the value 1 represents the termination.
  • the separator bit may represent a start point instead of the termination.
  • the same-color segment whose run-length value RL is 1 may contain only the color word CW whose termination bit TB is 1 and no run-length word RLW. This enables the compression ratio to be further raised.
  • the 4-bit run-length words RLW ⁇ 0000> to ⁇ 1111> can represent run-length values 2 to 17.
  • anti-aliasing may be provided to display a smooth font, and the same-color segment whose run-length value RL is 1 tends to be generated.
  • the compression ratio especially in the case of the characters can be raised.
  • the run-length value is represented by 2 words and 8 bits.
  • the first run-length word RLW may be allocated to the low 4 bits while the second run-length word RLW may be allocated to the high 4 bits, and vice versa.
  • the 8-bit run-length values RL ⁇ 00000000> to ⁇ 11111111> obtained by combining the two run-length words RLW represent run-length values 2 to 257.
  • a pixel group corresponding to the run-length value RL represented by the precedent run-length word RLW can be marked (or rasterized) before the subsequent run-length word RLW is read out.
  • the run-length value RL is represented by 3 words and 12 bits.
  • each set SET contains the color word CW of the same value, this is redundant, and the compression ratio may be lowered. Conversely, in the second data structure, since there is no redundancy of the color word CW, the compression ratio can be raised.
  • FIG. 5C illustrates a third data structure.
  • the format length of the run-length value RL is variable.
  • the segment data does not contain the termination bit TB for each word but contains a bit WB designating the number of words of the run-length value RL (word number designation bit).
  • word number designation bit designating the number of words of the run-length value RL
  • the number of bits of the word number designation bit WB is not particularly limited, the number of bits is 2 in this example. In a case in which the run-length value RL is 2 to 17, the word number designation bit WB is 1 ( ⁇ 01> in a case of a binary number), and the segment data contains one run-length word RLW.
  • the word number designation bit WB is 2 ( ⁇ 10> in a case of a binary number)
  • the segment data contains two run-length words RLW.
  • the initial run-length word RLW may represent the low 4 bits of the run-length value RL while the second run-length word RLW may represent the high 4 bits of the run-length value RL.
  • the second data structure or the third data structure may be selected to have a high compression ratio in consideration of the shape and the size of the character data.
  • the sum of the plurality of run-length words RLW may be the run-length value RL in a similar manner to that of the first data structure.
  • timing controller 300 The configuration of the timing controller 300 has been described above. Next, an operation thereof will be described.
  • the timing controller 300 When a device or a system including the timing controller 300 is activated, the timing controller 300 is in a setup state.
  • the processor 114 transmits the character data S 5 as well as the size data SIZE to the control input interface 310 .
  • the encoder 322 compresses the received character data S 5 and stores the compressed data S 6 in the memory 304 . In a case in which there are a plurality of pieces of character data S 5 , the plurality of pieces of character data are compressed sequentially.
  • the graphic controller 110 transmits the input video data S 1 via the first line 112 to the video input interface 302 .
  • the timing controller 300 processes the input video data S 1 and controls the gate driver 104 and the source drivers 106 to display an image on the display panel.
  • the processor 114 transmits the instruction signal S 8 separately from the input video data S 1 .
  • the instruction signal S 8 contains the ID information designating one of the plurality of pieces of character data S 5 transmitted to the timing controller 300 in the setup state and the positional information POS designating a display position.
  • the decoder 324 refers to the address information S 7 corresponding to the ID information and accesses the corresponding compressed data S 6 .
  • the decoder 324 then decodes the compressed data S 6 based on the size data SIZE to extract the character data S 9 in a bitmap format.
  • the multiplexer 330 displays the character data S 9 at a position designated by the positional information POS.
  • FIG. 7 illustrates the display panel 102 on which two pieces of character data S 91 and S 92 are displayed.
  • the multiplexer 330 may substitute the luminance value of the frame data S 10 at a region at which the character data S 9 is arranged with the luminance value of the character data S 9 .
  • timing controller 300 The operation of the timing controller 300 has been described above. Next, advantages thereof will be described.
  • FIG. 6 illustrates the compression ratios of the same-color segments when the second data structure in FIG. 5B is employed.
  • the bit wide of the run-length word RLW is 4 bits.
  • the run-length value RL is higher, the higher compression ratio is obtained.
  • the run-length value is 1 or 2
  • the segment data is larger than the data volume of the original pixel data.
  • the run-length value is 1 or 2 only in a case of anti-aliasing or the like, and the probability of occurrence thereof is extremely low. Accordingly, the compression ratio of the entire character data can sufficiently be raised.
  • the ROM 111 storing the character data for the OSD is required to be provided on the side of the timing controller 200 R in FIG. 1
  • the character data is not required to be stored in the ROM in the timing controller 300 in FIG. 2 . Since the memory 304 such as an SRAM is more reasonable than the ROM, the cost can be reduced.
  • an OTP (one time programmable) ROM is used for the ROM 111 .
  • the ROM 111 is required to be replaced.
  • the processor 114 is connected not the one time ROM but the rewritable non-volatile memory 118 such as a hard disk, a solid state drive (SSD), an electrically erasable programmable read-only memory (EEPROM), and a flash memory. Accordingly, in the timing controller 300 in FIG. 2 , the character for the OSD can be changed or added by changing or adding the character data stored in the non-volatile memory 118 .
  • SSD solid state drive
  • EEPROM electrically erasable programmable read-only memory
  • FIG. 8A illustrates an in-vehicle display device 600 using the timing controller 300 .
  • the in-vehicle display device 600 is buried in a console 602 on the cockpit front face.
  • the in-vehicle display device 600 receives from the vehicle processor and displays the input video data S including a speed meter 604 , a tachometer 606 indicating the number of revolutions of the engine, a fuel remaining amount 608 , and, in a case of a hybrid car or an electric car, a remaining amount of a battery ( FIG. 8A ).
  • an indicator lamp or a warning lamp (hereinbelow referred to simply as a warning lamp) indicating a certain abnormality or a dead battery as illustrated in FIG. 8B is displayed outside the display panel with use of an independent LED.
  • the reason for not displaying the warning lamp on the display panel is as follows. That is, the timing controller 300 and the graphic controller 110 are connected by means of a differential serial interface. During a period from start of activation of the system to establishment of a link between the timing controller 300 and the graphic controller 110 by means of the serial interface, no image data can be transmitted, and no image can thus be displayed on the display panel 102 .
  • the warning lamp Since the warning lamp has important information that should be given to the driver, the warning lamp is required to be lit even in the undisplayable state. Under such circumstances, the warning lamp is required to be provided outside the display panel.
  • the warning lamp can be displayed on the display panel as the character data S 5 for the OSD.
  • the reason for this is that communication by means of the differential serial interface is not required for the OSD display. Since this can dispense with the LED and the driving circuit thereof, the cost can be reduced. Also, since a standard function of the ECU such as I 2 C can be used, the cost can further be reduced.
  • the display panel 102 will black out, which poses a problem for driving.
  • numbers, alphabets, and the like may be prepared as the character data S 5 for the OSD.
  • car speed information 610 and information 612 about the number of revolutions of the engine can be displayed in real time with use of the OSD function, and the safety can be improved.
  • a character string such as “PLEASE WAIT . . . ” and current time can be displayed with use of the OSD function.
  • the timing controller 300 can be used for a medical display device.
  • the medical display device displays information required for doctors and nurses during an examination, treatment, or operation.
  • important information (such as a heart rate and blood pressure of a patient) can be displayed with use of the OSD function even in a state in which no input video data S 1 can be displayed.
  • FIG. 9 is a perspective view illustrating an electronic device 500 .
  • the electronic device 500 in FIG. 9 can be a laptop computer, a tablet terminal, a smartphone, a portable game machine, an audio player, or the like.
  • the electronic device 500 includes the graphic controller 110 , the display panel 102 , the gate driver 104 , and the source drivers 106 incorporated in a chassis 502 .
  • a transmission device 120 including a differential transmitter, a transmission path, and a differential receiver may be provided.
  • the character data S 9 for the OSD is displayed to be superimposed on the frame data S 10 in the embodiment, the present invention is not limited to this, and the character for the OSD may be displayed to be transparent or translucent by means of alpha blending.
  • the color data CD may be an a value representing the transparency. Consequently, the character data S 9 can be transparent or translucent and be displayed to be superimposed on the frame data S 10 .
  • the encoder 322 may further compress the 24-bit color data CD with use of a color palette.
  • a color palette For example, when the compressed data S 6 is constituted by sixteen or less colors, a 4-bit color palette is generated. Each time a segment of a new color appears, the encoder 322 adds the color to the palette and holds an identifier thereof in the color palette as the color data CD. In a case in which a same-color segment of a color included in the color palette appears, the encoder 322 holds an identifier of the color as the color data CD. Accordingly, the segment data can further be compressed.
  • control input interface 310 is not limited to the register access type.
  • differential serial transmission may be used in a similar manner to that in the first line 112 , or the control input interface 310 can be designed as an arbitrary interface.
  • the character data S 5 in the setup state and the instruction signal S 8 in the normal state are received by the common control input interface 310 in the embodiment, these may be received by separate interfaces.
  • run-length compression which is easily implemented, has been described in the embodiment, other image compression may be used.
  • error detection such as cyclic redundancy check (CRC) may be added to the character data S 5 , the instruction signal S 8 , and the like.
  • CRC cyclic redundancy check
  • error detection such as parity and checksum may be added.
  • FIG. 10 is a block diagram of an image display system 100 including a timing controller 400 according to a second embodiment.
  • the timing controller 400 receives the input video data S 1 from the graphic controller 110 , supplies the output video data S 2 to one or the plurality of source driver(s) 106 , and outputs the control/synchronous signal S 3 to the gate driver 104 and one or the plurality of source driver(s) 106 .
  • the timing controller 400 may be a functional integrated circuit (IC) integrated on one semiconductor substrate.
  • the timing controller 400 includes the video input interface 302 , a frame memory 303 , an image processing circuit 306 , the output interface 308 , the control input interface 310 , an abnormality detector 340 , and a memory 342 .
  • the video input interface 302 , the frame memory 303 , the image processing circuit 306 , and the output interface 308 are circuit blocks related to display of image data from the graphic controller 110 and may be the same as those included in the conventional timing controller 200 R.
  • the video input interface 302 is connected to the graphic controller 110 via a signal line 112 and receives the input video data S 1 .
  • a differential high-speed serial interface such as a low voltage differential signaling (LVDS) can be employed.
  • the input video data S 1 received by the video input interface 302 is stored as the frame data S 4 in the frame memory 303 .
  • the frame memory 303 may be a static random access memory (SRAM) without limitation. Meanwhile, the frame memory 303 may be a frame buffer holding one-frame image data or a line buffer holding data for one or a plurality of line(s), and the frame data S 4 may referred to as line data.
  • the image processing circuit 306 performs various kinds of signal processing to the frame data S 4 .
  • the signal processing of the image processing circuit 306 is not particularly limited, and a known technique may be used such as ⁇ (gamma) correction, frame rate control (FRC) processing, and RGB mapping.
  • the output interface 308 outputs the output video data S 2 processed by the image processing circuit 306 to the source driver 106 .
  • the image processing circuit 306 also generates the control/synchronous signal S 3 that is to be supplied to the gate driver 104 and the source driver 106 .
  • the abnormality detector 340 and the memory 342 are provided in relation to a function of detecting an abnormal state, especially the undisplayable state.
  • the memory 342 stores reference character data S REF describing predetermined characters that can be contained in the input video data S 1 .
  • the memory 342 may be a read-only memory (ROM) or a rewritable non-volatile memory such as a flash memory. Alternatively, the memory 342 may be a volatile memory as described in relation to an embodiment in FIG. 13 .
  • the abnormality detector 340 determines whether or not an abnormality (or the undisplayable state) exists based on the input video data S 1 and the reference character data S REF when a predetermined character should be contained in a frame represented by the input video data S 1 . Specifically, the abnormality detector 340 determines whether or not a predetermined character represented by the reference character data Su F is correctly contained in the input video data S 1 . The abnormality detector 340 determines that the state is normal in a case in which the predetermined character is contained and that the state is abnormal in a case in which the predetermined character is not contained.
  • the processor 114 is a central processing unit (CPU) or a microcomputer comprehensively controlling the image display system 100 .
  • FIG. 10 illustrates a configuration in which the processor 114 is provided separately from the graphic controller 110 , the function of the processor 114 may be incorporated into the graphic controller 110 .
  • the control input interface 310 is provided separately from the video input interface 302 , and the timing controller 400 is configured to enable communication with the processor 114 and can receive various control signals S 11 from the processor 114 .
  • a register-access-type interface can be used as the control input interface 310 .
  • Favorable examples thereof include, but are not limited to, a serial peripheral interface (SPI) and an inter-integrated circuit (I 2 C) interface.
  • the timing controller 400 may interrupt the processor 114 . This enables notification of generation of the abnormality (generation of the undisplayable state) to be given to the processor 114 .
  • the way to interrupt the processor 114 is not particularly limited, and an interrupt request (IRQ) may be used, for example.
  • timing controller 400 The configuration of the timing controller 400 has been described above. Next, an operation thereof will be described.
  • FIG. 11 illustrates an example of the predetermined character.
  • the example of the predetermined character is, but is not limited to, an icon representing the battery.
  • the memory 342 has stored therein the reference character data S REF representing such a predetermined character.
  • FIG. 12A and FIG. 12B illustrate abnormality detection by means of the timing controller 400 .
  • Each of FIG. 12A and FIG. 12B illustrates the frame data S 4 based on the input video data S 1 received by the video input interface 302 .
  • predetermined characters are contained at predetermined positions in all frames.
  • FIG. 12A illustrates frame data S 4 a in a case in which the video input interface 302 has received the input video data S 1 normally.
  • the frame data S 4 a can contain various characters such as a speed meter and a tachometer. Since the frame data S 4 a in FIG. 12A contains the predetermined character in FIG. 11 correctly at a predetermined position, the abnormality detector 340 determines that the state is normal.
  • FIG. 12B illustrates frame data S 4b in a case in which the video input interface 302 has not received the input video data S 1 correctly.
  • the abnormality detector 340 determines that the state is abnormal.
  • timing controller 400 Additional functions and characteristics of the timing controller 400 will be described below:
  • control signal S 11 that the control input interface 310 receives from the processor 114 may contain information S 11A indicating whether or not a current frame is targeted for determination by the abnormality detector 340 . Accordingly, in a case in which the predetermined character is contained in all frames, the frequency of abnormality determination (for example, once per sixty frames and once per second) can be controlled.
  • a character(s) to be displayed only when a predetermined condition is satisfied can be the predetermined character.
  • each of various warning lamps to be displayed on the cluster panel corresponds to such a character.
  • the display position of the predetermined character can be variable.
  • the control signal S 11 that the control input interface 310 receives from the processor 114 may contain positional information Sun indicating a display position of the predetermined character. Accordingly, the abnormality detector 340 may determine if the predetermined character is correctly displayed at a position indicated by the positional information S 11B of the frame data S 4 .
  • the predetermined character may be arranged in a fixed manner at a predetermined position at the end portion on the display panel that cannot be seen by the user. Accordingly, all frames can be targeted for determination by the abnormality detector 340 .
  • the number of the predetermined characters is not limited to one but may be plural.
  • the reference character data S REF may be prepared for each predetermined character.
  • the configuration of the present invention is comprehended as the block diagram or the circuit diagram in FIG. 10 , is applied to various devices and circuits led from the above description, and is not limited to a specific configuration.
  • more specific configuration examples and modification examples will be described to facilitate understanding of the nature of the invention and the circuit operation and clarify these, not to narrow the scope of the present invention.
  • FIG. 13 is a block diagram of an image display system 100 A including a timing controller 400 A according to an embodiment.
  • the timing controller 400 A is in a setup state immediately after turning on the power.
  • the timing controller 400 A has a period for setting parameters and the like of the ⁇ correction and the RGB mapping (initializing period) at the time of the power-on as a previous stage to reception and output of the video input data to a panel.
  • a part of the initializing period may be regarded as the setup state.
  • giving a command from an outside to the timing controller 400 A may enable the setup state to be set.
  • a register associated with the setup state may be provided inside the timing controller 400 A, and 1 may be written in the register from the outside (for example, the processor 114 ) to shift a state to the setup state.
  • the state can be shifted to the setup state not only immediately after turning on the timing controller 400 A but also at an arbitrary time.
  • the memory 342 may be a static random access memory (SRAM).
  • the control input interface 310 can receive the character data S 5 representing the predetermined character from the processor 114 in the setup state.
  • the character data S 5 is stored in the non-volatile memory 118 and is transmitted via the processor 114 to the control input interface 310 .
  • the character data S 5 may be monochrome or colored bitmap data without limitation.
  • the representation form of the character data S 5 is an arbitrary form such as icons, graphics, and characters. There may be the plurality of pieces of the character data S 5 .
  • the timing controller 400 A further includes the encoder 322 and the decoder 324 .
  • the encoder 322 encodes the character data S 5 received by the control input interface 310 , generates the reference character data S REF , and stores the data in the memory 342 .
  • the decoder 324 decodes the reference character data S REF read from the memory 342 and reproduces an original predetermined character.
  • timing controller 400 A The configuration of the timing controller 400 A has been described above. Next, an operation thereof will be described.
  • the timing controller 400 A When a device or a system including the timing controller 400 A is activated, the timing controller 400 A is in a setup state.
  • the processor 114 transmits the character data S 5 as well as the size data SIZE to the control input interface 310 .
  • the encoder 322 compresses the received character data S 5 and stores the compressed data S 6 in the memory 342 as the reference character data S REF . In a case in which there are a plurality of pieces of character data S 5 , the plurality of pieces of character data are compressed sequentially.
  • the graphic controller 110 transmits the input video data S 1 via the signal line 112 to the video input interface 302 .
  • the timing controller 400 A processes the input video data S 1 and controls the gate driver 104 and the source drivers 106 to display an image on the display panel.
  • the abnormality detector 340 determines whether or not the predetermined character reproduced by the decoder 324 is correctly contained in the frame data S 4 .
  • timing controller 400 A The operation of the timing controller 400 A has been described above. Next, advantages thereof will be described.
  • the abnormality determination can be performed with use of various kinds of character data.
  • FIG. 6 illustrates the compression ratios of the same-color segments when the second data structure in FIG. 5B is employed.
  • the bit wide of the run-length word RLW is 4 bits.
  • the run-length value RL is higher, the higher compression ratio is obtained.
  • the run-length value is 1 or 2
  • the segment data is larger than the data volume of the original pixel data.
  • the run-length value is 1 or 2 only in a case of anti-aliasing or the like, and the probability of occurrence thereof is extremely low. Accordingly, the compression ratio of the entire character data can sufficiently be raised.
  • the cost is raised.
  • a volatile memory such as an SRAM can be used as the memory 342 , the cost can be reduced.
  • the non-volatile memory 118 to be connected to the processor 114 not the one time ROM but the rewritable non-volatile memory 118 such as a hard disk, a solid state drive (SSD), an electrically erasable programmable read-only memory (EEPROM), and a flash memory is used, the following advantages can be obtained. That is, in a case in which the one time ROM is used as the memory 342 , and in which the reference character data S REF is stored in the one time ROM, the predetermined character cannot be added or changed.
  • the character data stored in the non-volatile memory 118 can be changed or added. Accordingly, the character for the abnormality detection can easily be changed or added.
  • FIG. 14 is a block diagram of the image display system 100 A including a timing controller 400 B according to an embodiment.
  • the timing controller 400 B includes the OSD function.
  • the memory 342 has stored therein the character data for the OSD.
  • the reference character data S REF for the abnormality detection and the character data for the OSD are used in common. This enables the capacity of the memory 342 to be saved.
  • an OSD mode and an abnormality detection mode are switchable.
  • the OSD mode and the abnormality detection mode may be selectable in accordance with the control signal S 11 from the processor 114 .
  • the OSD mode and the determination mode in which determination is given by the abnormality detector may be selectable.
  • the determination mode the abnormality detector 340 is activated and gives abnormality determination based on the character data reproduced by the decoder 324 .
  • the abnormality determination has been described above.
  • the abnormality detector 340 is deactivated, and the OSD processor 320 of the image processing circuit 306 is activated.
  • the OSD processor 320 superimposes the character data reproduced by the decoder 324 on the frame data S 4 to generate the output video data S 2 .
  • the processor 114 sets the timing controller 400 B to the OSD mode by means of the control signal S 11 .
  • the processor 114 transmits the instruction signal S 8 separately from the input video data S 1 .
  • the instruction signal S 8 contains the ID information designating one of the plurality of pieces of character data S 5 transmitted to the timing controller 400 B in the setup state and the positional information POS designating a display position.
  • the decoder 324 refers to the address information S 7 corresponding to the ID information and accesses the corresponding compressed data S 6 .
  • the decoder 324 then decodes the compressed data St based on the size data SIZE to extract the character data S 9 in a bitmap format.
  • the OSD processor 320 displays the character data S 9 at a position designated by the positional information POS.
  • FIG. 15 illustrates the display panel 102 on which two pieces of character data S 91 and S 92 are displayed.
  • both the OSD function and the abnormality detection function can be provided.
  • the capacity of the memory 342 can be reduced.
  • the abnormality detection function can be provided on another platform.
  • the abnormality detection function may be active by default, and in a case in which an abnormality is detected by the abnormality detector 340 , the OSD function may be used.
  • the processor 114 is interrupted by the timing controller 400 B. The interruption triggers the processor 114 to set the timing controller 400 B to the OSD mode.
  • the processor 114 can display an image on the display.
  • the instruction signal S 8 for the OSD and the control signal S 11 for the abnormality detection may be used in common.
  • the register for control of the OSD and the register for the abnormality detection may be used in common. For example, an address at which the positional information POS for the OSD is written and an address at which the positional information S 11B of the predetermined character is written in the abnormality detection mode may be equal. Accordingly, the capacity of the register can be reduced.
  • the timing controller 400 can be used in the in-vehicle display device 600 in FIG. 8A .
  • the in-vehicle display device 600 is buried in the console 602 on the cockpit front face.
  • the in-vehicle display device 600 receives from the vehicle processor and displays the input video data S 1 including the speed meter 604 , the tachometer 606 indicating the number of revolutions of the engine, the fuel remaining amount 608 , and, in a case of a hybrid car or an electric car, the remaining amount of a battery ( FIG. 8A ).
  • an indicator lamp or a warning lamp (hereinbelow referred to simply as a warning lamp) indicating a certain abnormality or a dead battery as illustrated in FIG. 8B is displayed outside the display panel with use of an independent LED.
  • the reason for not displaying the warning lamp on the display panel is as follows. That is, the timing controller 400 and the graphic controller 110 are connected by means of a differential serial interface. During a period from start of activation of the system to establishment of a link between the timing controller 400 and the graphic controller 110 by means of the serial interface, no image data can be transmitted, and no image can thus be displayed on the display panel 102 .
  • the warning lamp Since the warning lamp has important information that should be given to the driver, the warning lamp is required to be lit even in the undisplayable state. Under such circumstances, the warning lamp is required to be provided outside the display panel.
  • the warning lamp can be displayed on the display panel as the character data S 5 for the OSD.
  • the reason for this is that communication by means of the differential serial interface is not required for the OSD display. Since this can dispense with the LED and the driving circuit thereof, the cost can be reduced. Also, since a standard function of the ECU such as I 2 C can be used, the cost can further be reduced.
  • the display panel 102 will black out, which poses a problem for driving.
  • numbers, alphabets, and the like may be prepared as the character data S 5 for the OSD.
  • the car speed information 610 and the information 612 about the number of revolutions of the engine can be displayed in real time with use of the OSD function, and the safety can be improved.
  • a character string such as “PLEASE WAIT . . . ” and current time can be displayed with use of the OSD function.
  • the timing controller 400 can be used for a medical display device.
  • the medical display device displays information required for doctors and nurses during an examination, treatment, or operation.
  • important information (such as a heart rate and blood pressure of a patient) can be displayed with use of the OSD function even in a state in which no input video data S 1 can be displayed.
  • FIG. 9 is a perspective view illustrating the electronic device 500 .
  • the electronic device 500 in FIG. 9 can be a laptop computer, a tablet terminal, a smartphone, a portable game machine, an audio player, or the like.
  • the electronic device 500 includes the graphic controller 110 , the display panel 102 , the gate driver 104 , and the source drivers 106 incorporated in the chassis 502 .
  • the transmission device 120 including a differential transmitter, a transmission path, and a differential receiver may be provided.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Graphics (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
US16/233,299 2016-06-27 2018-12-27 Semiconductor apparatus for image transmission Abandoned US20190141357A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US17/196,521 US11659211B2 (en) 2016-06-27 2021-03-09 Semiconductor apparatus for image transmission
US18/299,448 US12126842B2 (en) 2016-06-27 2023-04-12 Semiconductor apparatus for image transmission

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2016-126996 2016-06-27
JP2016126996 2016-06-27
JP2017035487 2017-02-27
JP2017-035487 2017-02-27
PCT/JP2017/023101 WO2018003669A1 (ja) 2016-06-27 2017-06-22 タイミングコントローラ、それを用いた電子機器、車載用ディスプレイ装置、医療用ディスプレイ装置

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/023101 Continuation WO2018003669A1 (ja) 2016-06-27 2017-06-22 タイミングコントローラ、それを用いた電子機器、車載用ディスプレイ装置、医療用ディスプレイ装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/196,521 Division US11659211B2 (en) 2016-06-27 2021-03-09 Semiconductor apparatus for image transmission

Publications (1)

Publication Number Publication Date
US20190141357A1 true US20190141357A1 (en) 2019-05-09

Family

ID=60787224

Family Applications (2)

Application Number Title Priority Date Filing Date
US16/233,299 Abandoned US20190141357A1 (en) 2016-06-27 2018-12-27 Semiconductor apparatus for image transmission
US17/196,521 Active 2037-10-15 US11659211B2 (en) 2016-06-27 2021-03-09 Semiconductor apparatus for image transmission

Family Applications After (1)

Application Number Title Priority Date Filing Date
US17/196,521 Active 2037-10-15 US11659211B2 (en) 2016-06-27 2021-03-09 Semiconductor apparatus for image transmission

Country Status (4)

Country Link
US (2) US20190141357A1 (ja)
JP (1) JP6754429B2 (ja)
CN (1) CN109416904B (ja)
WO (1) WO2018003669A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11222570B2 (en) * 2018-09-07 2022-01-11 HKC Corporation Limited Display panel and driving method
US11244646B1 (en) * 2020-09-16 2022-02-08 Himax Technologies Limited Display device and display control method
US11594186B2 (en) * 2020-12-08 2023-02-28 Lg Display Co., Ltd. Display device and driving circuit having improved stability
EP4375827A1 (en) * 2022-10-20 2024-05-29 Himax Technologies Limited Display system and panel driving circuit
TWI847538B (zh) * 2023-02-09 2024-07-01 大陸商北京集創北方科技股份有限公司 靜態隨機存取記憶體的使用方法、顯示驅動晶片、顯示裝置以及資訊處理裝置

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2019146567A1 (ja) * 2018-01-23 2021-01-14 ローム株式会社 半導体装置、それを用いた電子機器、ディスプレイ装置
WO2019146568A1 (ja) * 2018-01-26 2019-08-01 ローム株式会社 ブリッジ回路、それを用いた電子機器、ディスプレイ装置
JP6706371B2 (ja) * 2018-08-08 2020-06-03 シャープ株式会社 表示装置およびその制御方法
CN113330508B (zh) * 2019-01-21 2024-04-30 罗姆股份有限公司 半导体装置、使用了它的车载用显示系统、电子设备
JP7317442B2 (ja) * 2019-04-16 2023-07-31 アルパイン株式会社 表示装置およびアイコンの故障判定方法
JP7229646B2 (ja) * 2019-09-25 2023-02-28 アルパイン株式会社 画像表示装置
JP7058253B2 (ja) * 2019-10-09 2022-04-21 本田技研工業株式会社 表示制御装置および情報処理装置
EP4167576A4 (en) * 2020-06-30 2023-11-29 Huawei Technologies Co., Ltd. IMAGE PROCESSING METHOD AND DEVICE
JP7556234B2 (ja) 2020-08-26 2024-09-26 セイコーエプソン株式会社 回路装置、電子機器及びエラー検出方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06317782A (ja) 1993-03-25 1994-11-15 Toshiba Corp 表示装置
JP2001184018A (ja) * 1999-12-24 2001-07-06 Matsushita Electric Ind Co Ltd 電子機器の表示機能の自動判定システムおよび自動判定方法
KR100370248B1 (ko) * 2000-08-08 2003-01-30 엘지전자 주식회사 디지털 텔레비젼
JP2002169524A (ja) 2000-12-01 2002-06-14 Sony Corp 通信方法および装置、ならびに、表示方法および装置
JP2002369092A (ja) * 2001-06-11 2002-12-20 Sony Corp 表示制御装置および映像表示装置
JP2003200757A (ja) * 2002-01-07 2003-07-15 Denso Corp 車両用表示装置
JP4122456B2 (ja) * 2003-09-18 2008-07-23 船井電機株式会社 画像データ圧縮方法
JP4570025B2 (ja) * 2004-02-06 2010-10-27 ルネサスエレクトロニクス株式会社 コントローラドライバ及び表示パネル駆動方法
JP2006246247A (ja) * 2005-03-04 2006-09-14 Toshiba Corp 映像信号処理装置及び映像信号処理方法
WO2007083597A1 (ja) 2006-01-17 2007-07-26 Matsushita Electric Industrial Co., Ltd. 信号処理装置および光ディスク装置
CN101331536A (zh) * 2006-01-17 2008-12-24 松下电器产业株式会社 信号处理装置和光盘装置
JP2008181017A (ja) * 2007-01-25 2008-08-07 Fujifilm Corp オンスクリーン表示装置、オンスクリーン表示方法及び撮像装置
JP2009135684A (ja) * 2007-11-29 2009-06-18 Sony Corp 表示装置及び異常検出方法
US8301013B2 (en) 2008-11-18 2012-10-30 Panasonic Corporation Reproduction device, reproduction method, and program for stereoscopic reproduction
CN101707677B (zh) * 2009-12-11 2011-12-21 华亚微电子（上海）有限公司 Osd控制器
JP5670117B2 (ja) * 2010-08-04 2015-02-18 ルネサスエレクトロニクス株式会社 表示制御装置
WO2015097855A1 (ja) * 2013-12-27 2015-07-02 三菱電機株式会社 映像監視装置及び映像監視方法及び映像監視プログラム

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11222570B2 (en) * 2018-09-07 2022-01-11 HKC Corporation Limited Display panel and driving method
US11244646B1 (en) * 2020-09-16 2022-02-08 Himax Technologies Limited Display device and display control method
US11594186B2 (en) * 2020-12-08 2023-02-28 Lg Display Co., Ltd. Display device and driving circuit having improved stability
EP4375827A1 (en) * 2022-10-20 2024-05-29 Himax Technologies Limited Display system and panel driving circuit
TWI847538B (zh) * 2023-02-09 2024-07-01 大陸商北京集創北方科技股份有限公司 靜態隨機存取記憶體的使用方法、顯示驅動晶片、顯示裝置以及資訊處理裝置

Also Published As

Publication number Publication date
CN109416904B (zh) 2022-06-14
US11659211B2 (en) 2023-05-23
CN109416904A (zh) 2019-03-01
JPWO2018003669A1 (ja) 2019-02-28
US20230254517A1 (en) 2023-08-10
JP6754429B2 (ja) 2020-09-09
WO2018003669A1 (ja) 2018-01-04
US20210195250A1 (en) 2021-06-24

Similar Documents

Publication Publication Date Title
US11659211B2 (en) Semiconductor apparatus for image transmission
KR101548337B1 (ko) 와이드 컬러 개멋 디스플레이 시스템
KR102642510B1 (ko) 표시 장치, 영상 데이터 및 커맨드 데이터를 수신하는 방법, 및 영상 데이터 및 커맨드 데이터를 전송하는 방법
US11367415B2 (en) Semiconductor apparatus
US12062309B2 (en) Device and method for detecting screen freeze error of display of vehicle
US11361737B2 (en) Bridge circuit
US12126842B2 (en) Semiconductor apparatus for image transmission
US10235931B2 (en) Timing controller
JP7097507B2 (ja) 半導体装置、それを用いた車載用ディスプレイシステム、電子機器
US20080043002A1 (en) Systems and methods for alternative to serial peripheral interface communication in dumb display driver integrated circuits
JP7336325B2 (ja) 半導体装置、それを用いた自動車、ディスプレイ装置
US11715442B2 (en) Semiconductor apparatus with OSD function
CN113646203B (zh) 半导体装置、使用了它的车载用显示器系统、电子设备
EP4345804A1 (en) Image processing device, operating method thereof, and display system including image processing device
CN115151971A (zh) 用于显示的动态伽玛曲线使用
CN117743019A (zh) 显示装置及用于检查其图像数据的方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: ROHM CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ENDO, HIROHARU;REEL/FRAME:047857/0361

Effective date: 20181212

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED

STPP Information on status: patent application and granting procedure in general

Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER

STPP Information on status: patent application and granting procedure in general

Free format text: FINAL REJECTION MAILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION