US20150084059A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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US20150084059A1
US20150084059A1 US14/452,877 US201414452877A US2015084059A1 US 20150084059 A1 US20150084059 A1 US 20150084059A1 US 201414452877 A US201414452877 A US 201414452877A US 2015084059 A1 US2015084059 A1 US 2015084059A1
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based semiconductor
semiconductor layer
gan based
gan
electrode
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Miki Yumoto
Masahiko Kuraguchi
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Toshiba Corp
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Toshiba Corp
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KURAGUCHI, MASAHIKO, YUMOTO, MIKI
Publication of US20150084059A1 publication Critical patent/US20150084059A1/en
Priority to US15/424,422 priority Critical patent/US10141439B2/en
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
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    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • GaN based semiconductor having high dielectric breakdown strength to a semiconductor device for power electronics or a high frequency power semiconductor device has been expected.
  • it has been requested to form a plurality of GaN based semiconductor elements, for example, transistors and diodes in one chip.
  • FIG. 1 is a schematic cross-sectional view illustrating a configuration of a semiconductor device according to a first embodiment
  • FIG. 2 is a circuit diagram of the semiconductor device according to the first embodiment
  • FIG. 3 is a schematic cross-sectional view illustrating a first manufacturing method of the semiconductor device according to the first embodiment
  • FIG. 4 is a schematic cross-sectional view illustrating the first manufacturing method of the semiconductor device according to the first embodiment
  • FIG. 5 is a schematic cross-sectional view illustrating the first manufacturing method of the semiconductor device according to the first embodiment
  • FIG. 6 is a schematic cross-sectional view illustrating the first manufacturing method of the semiconductor device according to the first embodiment
  • FIG. 7 is a schematic cross-sectional view illustrating the first manufacturing method of the semiconductor device according to the first embodiment
  • FIG. 8 is a schematic cross-sectional view illustrating the second manufacturing method of the semiconductor device according to the first embodiment
  • FIG. 9 is a schematic cross-sectional view illustrating the second manufacturing method of the semiconductor device according to the first embodiment.
  • FIG. 10 is a schematic cross-sectional view illustrating the second manufacturing method of the semiconductor device according to the first embodiment
  • FIG. 11 is a diagram illustrating a relation of an impurity concentration, thickness of a GaN layer, and an electric field.
  • FIG. 12 is a schematic cross-sectional view illustrating a configuration of a semiconductor device according to a second embodiment
  • FIG. 13 is a schematic cross-sectional view illustrating a first manufacturing method of the semiconductor device according to the second embodiment
  • FIG. 14 is a schematic cross-sectional view illustrating the first manufacturing method of the semiconductor device according to the second embodiment
  • FIG. 15 is a schematic cross-sectional view illustrating the first manufacturing method of the semiconductor device according to the second embodiment
  • FIG. 16 is a schematic cross-sectional view illustrating the first manufacturing method of the semiconductor device according to the second embodiment
  • FIG. 17 is a schematic cross-sectional view illustrating the first manufacturing method of the semiconductor device according to the second embodiment
  • FIG. 18 is a schematic cross-sectional view illustrating the first manufacturing method of the semiconductor device according to the second embodiment
  • FIG. 19 is a schematic cross-sectional view illustrating a second manufacturing method of the semiconductor device according to the second embodiment
  • FIG. 20 is a schematic cross-sectional view illustrating the second manufacturing method of the semiconductor device according to the second embodiment
  • FIG. 21 is a schematic cross-sectional view illustrating the second manufacturing method of the semiconductor device according to the second embodiment
  • FIG. 22 is a schematic cross-sectional view illustrating the second manufacturing method of the semiconductor device according to the second embodiment
  • FIG. 24 is a schematic cross-sectional view illustrating a configuration of a semiconductor device according to a third embodiment.
  • FIG. 25 is a schematic cross-sectional view illustrating a configuration of a semiconductor device according to a fourth embodiment.
  • GaN based semiconductor collectively means a semiconductor that contains gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and intermediate compositions thereof.
  • AlGaN means a semiconductor that is expressed by a compositional formula of Al x Ga 1-x N (0 ⁇ x ⁇ 1).
  • n + , n, n and p + , p, and p ⁇ illustrates the relative difference of the impurity concentration in each conductive type. That is, an n-type impurity concentration of n + is relatively higher than that of n and the n-type impurity concentration of n ⁇ is relatively lower than that of n. In addition, a p-type impurity concentration of p + is relatively higher than that of p and the p-type impurity concentration of p ⁇ is relatively lower than that of p. In addition, an n + type and an n ⁇ -type may be simply referred to as an n type and a p + type and a p ⁇ -type may be simply referred to as a p type.
  • a semiconductor device includes a first GaN based semiconductor layer of a first conductive type, a second GaN based semiconductor layer of the first conductive type that is provided on or above the first GaN based semiconductor layer and has an impurity concentration of the first conductive type lower than that of the first GaN based semiconductor layer, a third GaN based semiconductor layer of a second conductive type that is provided in a partial region on or above the second GaN based semiconductor layer, a fourth GaN based semiconductor layer of the first conductive type that is provided on or above the third GaN based semiconductor layer, is an epitaxial growth layer, and has the impurity concentration of the first conductive type higher than that of the second GaN based semiconductor layer, a gate insulating film that is provided on the second GaN based semiconductor layer, the third GaN based semiconductor layer, and the fourth GaN based semiconductor layer, a gate electrode that is provided on the gate insulating film, a first electrode that is provided on the fourth GaN based semiconductor layer, a second electrode
  • FIG. 1 is a schematic cross-sectional view illustrating a configuration of the semiconductor device according to this embodiment.
  • FIG. 2 is a circuit diagram of the semiconductor device according to this embodiment.
  • a transistor and a diode are formed in one chip. As illustrated in FIG. 2 , a source electrode of the transistor and an anode electrode of the diode are made to be common and a drain electrode of the transistor and a cathode electrode of the diode are made to be common.
  • the diode is useful for preventing an overcurrent to flow to the transistor.
  • the transistor is an n channel type transistor that uses electrons as carriers.
  • the transistor is a vertical transistor that moves carries between a source electrode of a surface side of a semiconductor substrate and a drain electrode of a back surface side.
  • the semiconductor device 100 includes an n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 provided on an n + -type GaN layer (first GaN based semiconductor layer) 12 .
  • the n + -type GaN layer 12 functions as a drain region of the transistor and a cathode region of the diode.
  • the n + -type GaN layer 12 contains Si (silicon) as n-type impurities.
  • An n-type impurity concentration of the n + -type GaN layer 12 is, for example, 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • n + -type GaN layer (fourth GaN based semiconductor layer) 18 is provided on the p-type GaN layer (third GaN based semiconductor layer) 16 .
  • the n + -type GaN layer 18 functions as a source region of the transistor.
  • the n + -type GaN layer 18 is an epitaxial growth layer.
  • the n-type impurity concentration of the n + -type GaN layer 18 is higher than that of the n ⁇ -type GaN layer 14 .
  • the n + -type GaN layer 18 contains Si (silicon) as the n-type impurities.
  • the n-type impurity concentration of the n + -type GaN layer 18 is, for example, 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 23 cm ⁇ 3 .
  • the p-type GaN layer 16 and the n + -type GaN layer 18 have a mesa structure. That is, the p-type GaN layer 16 and the n + -type GaN layer 18 protrude on the n ⁇ -type GaN layer 14 and have a cross-section of a trapezoidal shape.
  • a side of the mesa structure does not necessarily have a tapered shape and may be a vertical surface.
  • a gate insulating film 20 is provided continuously on the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 , the p-type GaN layer (third GaN based semiconductor layer) 16 , and the n + -type GaN layer (fourth GaN based semiconductor layer) 18 .
  • the gate insulating film 20 is, for example, a silicon oxide film or a silicon nitride film.
  • a gate electrode 22 is formed on the gate insulating film 20 .
  • the gate electrode 22 is provided in a region between two mesa structures.
  • the gate electrode 22 is a metal such as Ni (nickel) and Ti (titan).
  • metal silicide and polysilicon or the like can be applied to the gate electrode 22 .
  • a source electrode (first electrode) 24 is provided in the n + -type GaN layer (fourth GaN based semiconductor layer) 18 .
  • the source electrode 24 is a metal containing Ni (nickel).
  • the source electrode (first electrode) 24 is provided in a groove in which one end is positioned at the n + -type GaN layer (fourth GaN based semiconductor layer) 18 and the other end is positioned at the p-type GaN layer (third GaN based semiconductor layer) 16 .
  • the source electrode 24 contacts the p-type GaN layer 16 .
  • the source electrode 24 and the channel electrode (base electrode) may be individually provided.
  • the groove may not be provided and the source electrode 24 may be connected at a surface of the n + -type GaN layer (fourth GaN based semiconductor layer) 18 .
  • n + -type GaN layer (fourth GaN based semiconductor layer) 18 and the source electrode (first electrode) 24 are preferably ohmic-connected to each other, from the viewpoint of increasing an on-state current of the transistor.
  • a drain electrode (second electrode) 26 is provided at the side of the n + -type GaN layer (first GaN based semiconductor layer) 12 opposite to the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 .
  • the drain electrode 26 also functions as a cathode electrode of the diode.
  • the drain electrode 26 is a metal containing Ni.
  • the n + -type GaN layer (first GaN based semiconductor layer) 12 and the drain electrode (second electrode) 26 are preferably ohmic-connected to each other, from the viewpoint of increasing an on-state current of the transistor and increasing a forward current of the diode.
  • An anode electrode (third electrode) 28 is provided on the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 .
  • the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 and the anode electrode (third electrode) 28 are Schottky-connected to each other.
  • the anode electrode 28 includes a laminated structure of Ni (nickel)/Au (gold).
  • the source electrode (first electrode) 24 and the anode electrode (third electrode) 28 are preferably formed of different materials, from the viewpoint of optimizing individual contact characteristics.
  • the source electrode 24 and the anode electrode 28 may be configured to be made to be common by a wiring line not illustrated and apply the same potential or may be configured to be made not to be common and apply differential potentials.
  • the first manufacturing method of the semiconductor device includes forming a second GaN based semiconductor layer of a first conductive type having an impurity concentration of the first conductive type lower than that of a first GaN based semiconductor layer on the first GaN based semiconductor layer by an epitaxial growth method, forming a third GaN based semiconductor layer of a second conductive type on the second GaN based semiconductor layer by the epitaxial growth method, forming a fourth GaN based semiconductor layer of the first conductive type having the impurity concentration of the first conductive type higher than that of the second GaN based semiconductor layer on the third GaN based semiconductor layer by the epitaxial growth method, etching partial regions of the fourth GaN based semiconductor layer and the third GaN based semiconductor layer to expose a partial region of the second GaN based semiconductor layer and forming a plurality of first convex portions of a stacked structure of the third GaN based semiconductor layer and the fourth GaN based semiconductor layer, forming a gate insulating film on the second Ga
  • FIGS. 3 to 7 are schematic cross-sectional views illustrating the first manufacturing method of the semiconductor device according to this embodiment.
  • the n + -type GaN layer (first GaN based semiconductor layer) 12 that contains as the n-type impurities Si (silicon) with the impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 is prepared.
  • the n + -type GaN layer 12 becomes a substrate of the epitaxial growth.
  • the high-resistance n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 that contains as the n-type impurities Si with the impurity concentration of 5 ⁇ 10 15 cm ⁇ 3 to 5 ⁇ 10 17 cm 3 and has a film thickness of 0.5 ⁇ m to 30 ⁇ m is formed on the n + -type GaN layer 12 by the epitaxial growth method.
  • the epitaxial growth is performed by a metal organic chemical vapor deposition (MOCVD) method.
  • the p-type GaN layer (third GaN based semiconductor layer) 16 containing the p-type impurities is formed on the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 by the epitaxial growth method.
  • the p-type impurities are, for example, Mg (magnesium).
  • source gas is, for example, trimethyl gallium (TMG) or ammonia (NH 3 ) and a p-type dopant in the source gas is, for example, is cyclopentadienyl magnesium (Cp 2 Mg).
  • the n + -type GaN layer (fourth GaN based semiconductor layer) 18 is formed on the p-type GaN layer (third GaN based semiconductor layer) 16 by the epitaxial growth method.
  • the n + -type GaN layer 18 contains as the n-type impurities Si (silicon) with the impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • n + -type GaN layer (first GaN based semiconductor layer) 12 the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 , the p-type GaN layer (third GaN based semiconductor layer) 16 , and the n + -type GaN layer (fourth GaN based semiconductor layer) 18 is formed (refer to FIG. 3 ).
  • the partial regions of the n + -type GaN layer (fourth GaN based semiconductor layer) 18 and the p-type GaN layer (third GaN based semiconductor layer) 16 are etched to expose the n ⁇ -type GaN layer (second GaN based semiconductor layer) and the first convex portion of the stacked structure of the p-type GaN layer (third GaN based semiconductor layer) 16 and the n + -type GaN layer (fourth GaN based semiconductor layer) 18 is formed.
  • a mask material 30 is formed on the n + -type GaN layer (fourth GaN based semiconductor layer) 18 using a lithographic technique (refer to FIG. 4 ).
  • the mask material 30 is a resist.
  • the n + -type GaN layer (fourth GaN based semiconductor layer) 18 and the p-type GaN layer (third GaN based semiconductor layer) 16 are etched using the mask material 30 as a mask and a mesa structure (first convex portion) is formed (refer to FIG. 5 ).
  • the etching is performed by reactive ion etching (RIE).
  • RIE reactive ion etching
  • the mask material 30 is peeled (refer to FIG. 6 ).
  • the gate insulating film 20 is formed on the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 , the p-type GaN layer (third GaN based semiconductor layer) 16 , and the n + -type GaN layer (fourth GaN based semiconductor layer) 18 between the two mesa structures (first convex portions) (refer to FIG. 7 ).
  • the gate insulating film 20 is formed by depositing a silicon nitride film by a low pressure chemical vapor deposition (LPCVD) method and a plasma enhanced chemical vapor deposition (PECVD) method.
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the gate electrode 22 is formed on the gate insulating film 20 .
  • a resist mask is formed on the gate insulating film 20 using a photolithographic technique.
  • the gate electrode 22 is formed in only a patterned place using a deposition method and a lift-off method.
  • the source electrode (first electrode) 24 , the drain electrode (second electrode) 26 , and the anode electrode (third electrode) 28 are formed using a known process.
  • the semiconductor device according to this embodiment illustrated in FIG. 1 is manufactured.
  • a second manufacturing method of the semiconductor device includes forming a second GaN based semiconductor layer of a first conductive type having an impurity concentration of the first conductive type lower than that of a first GaN based semiconductor layer on the first GaN based semiconductor layer by an epitaxial growth method, covering a partial region on the second GaN based semiconductor layer by a first mask material and forming a third GaN based semiconductor layer of a second conductive type by a selective epitaxial growth method, forming a fourth GaN based semiconductor layer of the first conductive type having the impurity concentration of the first conductive type higher than that of the second GaN based semiconductor layer in at least a partial region on the third GaN based semiconductor layer by the selective epitaxial growth method, forming a gate insulating film on the second GaN based semiconductor layer, the third GaN based semiconductor layer, and the fourth GaN based semiconductor layer, forming a gate electrode on the gate insulating film, forming a first electrode on the fourth GaN based semiconductor layer
  • FIGS. 8 to 10 are schematic cross-sectional views illustrating the second manufacturing method of the semiconductor device according to this embodiment. A description of content overlapped to that of the first manufacturing method will be omitted.
  • the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 is formed on the n + -type GaN layer 12 by the epitaxial growth method.
  • the partial region on the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 is covered by a mask material 32 (first mask material) (refer to FIG. 8 ).
  • the mask material 32 is formed by patterning using a known film deposition method, photolithography, and etching.
  • the mask material 32 is, for example, a silicon oxide film.
  • the p-type GaN layer (third GaN based semiconductor layer) 16 containing the p-type impurities is formed on the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 by a selective epitaxial growth method.
  • the p-type impurities are, for example, Mg (magnesium).
  • source gas is, for example, trimethyl gallium (TMG) or ammonia (NH 3 ) and a p-type dopant in the source gas is, for example, is cyclopentadienyl magnesium (Cp 2 Mg).
  • the n + -type GaN layer (fourth GaN based semiconductor layer) 18 is formed on the p-type GaN layer (third GaN based semiconductor layer) 16 by the selective epitaxial growth method.
  • the n + -type GaN layer (fourth GaN based semiconductor layer) 18 contains as the n-type impurities Si (silicon) with the impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • a mesa structure is formed by the selective epitaxial growth method of the p-type GaN layer 16 and the n + -type GaN layer 18 (refer to FIG. 9 ).
  • the mask material 32 is peeled (refer to FIG. 10 ).
  • the mask material 32 is peeled by wet etching.
  • the gate insulating film 20 , the gate electrode 22 , the source electrode (first electrode) 24 , the drain electrode (second electrode) 26 , and the anode electrode (third electrode) 28 are formed.
  • the semiconductor device according to this embodiment illustrated in FIG. 1 is manufactured.
  • the transistor and the diode are formed in one chip, which results in improving an integration degree. Therefore, a semiconductor device in which miniaturization and low consumption power are enabled is realized.
  • a semiconductor layer formed by ion implantation in an impurity layer is not used. For this reason, an impurity layer having a high activation rate is realized. Therefore, contact resistance of the semiconductor layer and the electrode can be decreased and resistance of the semiconductor layer is also decreased. As a result, a semiconductor device having high performance in which an-on state current is large can be realized.
  • the transistor and the diode different in the layer structures can be formed in one chip by the simple structure and manufacturing method.
  • FIG. 11 is a diagram illustrating a relation of an impurity concentration, thickness of a GaN layer, and an electric field.
  • a horizontal axis illustrates an impurity concentration (doping concentration) of a GaN layer and a vertical axis illustrates a thickness of the GaN layer.
  • the case in which an electric field to be realized is 1.5 MV/cm and the case in which an electric field to be realized is 3.3 MV/cm are illustrated.
  • the electric field is preferably set to 1.5 MV/cm.
  • the breakdown voltage of the semiconductor device is determined under a condition of the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 . Therefore, the thickness and the n-type impurity concentration of the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 are preferably 1 ⁇ m to 20 ⁇ m and 1 ⁇ 10 16 cm ⁇ 3 to 2 ⁇ 10 17 cm ⁇ 3 , respectively, from the viewpoint of realizing the electric field of 1.5 MV/cm.
  • a semiconductor device is different from the semiconductor device according to the first embodiment in that the semiconductor device further includes a plurality of fifth GaN based semiconductor layers of a second conductive type, which surround a first electrode or a third electrode, are provided to be separated from each other, and have substantially the same impurity concentration of a second conductive type as a third GaN based semiconductor layer, provided in a partial region on or above a second GaN based semiconductor layer.
  • the semiconductor device according to this embodiment is different from the semiconductor device according to the first embodiment in that the semiconductor device further includes a sixth GaN based semiconductor layer of the second conductive type, which contacts the third electrode and has substantially the same impurity concentration of the second conductive type as the third GaN based semiconductor layer and the fifth GaN based semiconductor layer, provided in a partial region on or above the second GaN based semiconductor layer.
  • a part of a description of content overlapped to the content of the first embodiment will be omitted.
  • FIG. 12 is a schematic cross-sectional view illustrating a configuration of the semiconductor device according to this embodiment.
  • a semiconductor device 200 according to this embodiment includes p-type termination structures (fifth GaN based semiconductor layers) 40 and a p-type termination portion (sixth GaN based semiconductor layer) 42 , in addition to the structure according to the first embodiment.
  • the plurality of p-type termination structures (fifth GaN based semiconductor layers) 40 are provided in a partial region on an n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 to surround a source electrode (first electrode) 24 or an anode electrode (third electrode) 28 .
  • the p-type termination structures 40 are separated from each other.
  • the p-type termination structures 40 are so-called guard rings. By providing the p-type termination structures 40 , an electric field applied to a drain side of a transistor or a cathode side of a diode is alleviated and a breakdown voltage of the transistor or the diode is improved.
  • the p-type termination portion (sixth GaN based semiconductor layer) 42 is provided in a partial region on the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 to contact the anode electrode (third electrode) 28 .
  • an electric field of the anode electrode (third electrode) 28 is alleviated and the breakdown voltage of the diode is improved.
  • the p-type termination structures (fifth GaN based semiconductor layers) 40 and the p-type termination portion (sixth GaN based semiconductor layer) 42 are formed in substantially the same semiconductor layer as a p-type GaN layer (third GaN based semiconductor layer) 16 . Therefore, the p-type termination structures (fifth GaN based semiconductor layers) 40 and the p-type termination portion (sixth GaN based semiconductor layer) 42 have substantially the same p-type impurity concentration as the p-type GaN layer (third GaN based semiconductor layer) 16 .
  • the first manufacturing method of the semiconductor device according to this embodiment is different from the first manufacturing method of the semiconductor device according to the first embodiment in that partial regions of the fourth GaN based semiconductor layer and the third GaN based semiconductor layer are etched to form a plurality of second convex portions of the third GaN based semiconductor layer to be separated from each other and the partial region of the third GaN based semiconductor layer of the second convex portions is etched to exposure the second GaN based semiconductor layer and the third electrode is formed.
  • partial regions of the fourth GaN based semiconductor layer and the third GaN based semiconductor layer are etched to form a plurality of second convex portions of the third GaN based semiconductor layer to be separated from each other and the partial region of the third GaN based semiconductor layer of the second convex portions is etched to exposure the second GaN based semiconductor layer and the third electrode is formed.
  • FIGS. 13 to 18 are schematic cross-sectional views illustrating the first manufacturing method of the semiconductor device according to this embodiment.
  • Formation of an n + -type GaN layer (first GaN based semiconductor layer) 12 , an n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 , a p-type GaN layer (third GaN based semiconductor layer) 16 , and an n + -type GaN layer (fourth GaN based semiconductor layer) 18 is the same as that of the first embodiment.
  • a mask material 44 is formed on the n + -type GaN layer (fourth GaN based semiconductor layer) 18 (refer to FIG. 13 ).
  • the mask material 44 is formed by a known lithographic technique.
  • the mask material 44 is a resist.
  • the n + -type GaN layer (fourth GaN based semiconductor layer) 18 and the p-type GaN layer (third GaN based semiconductor layer) 16 are etched using the mask material 44 as a mask (refer to FIG. 14 ).
  • the etching is performed by reactive ion etching (RIE).
  • the mask material 44 is peeled.
  • the mask material 45 is formed such that the partial region of the n + -type GaN layer (fourth GaN based semiconductor layer) 18 is exposed (refer to FIG. 15 ).
  • the mask material 45 is formed by the known photolithographic technique.
  • the mask material 45 is a resist.
  • the partial region of the n + -type GaN layer (fourth GaN based semiconductor layer) 18 is etched using the mask material 45 as a mask (refer to FIG. 16 ).
  • the etching is performed by reactive ion etching (RIE).
  • the mask material 45 is peeled (refer to FIG. 17 ).
  • a mesa structure of the transistor, the p-type termination structure (fifth GaN based semiconductor layer) 40 of the transistor or the diode, and the p-type termination portion (sixth GaN based semiconductor layer) 42 of the diode are formed.
  • the mesa structure of the transistor corresponds to the first convex portion and the p-type termination structure 40 of the diode and the p-type termination portion (sixth GaN based semiconductor layer) 42 of the diode correspond to the second convex portion.
  • the gate insulating film 20 is formed on the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 , the p-type GaN layer (third GaN based semiconductor layer) 16 , the n + -type GaN layer (fourth GaN based semiconductor layer) 18 , the p-type termination structure (fifth GaN based semiconductor layer) 40 , and the p-type termination portion (sixth GaN based semiconductor layer) 42 (refer to FIG. 18 ).
  • the gate insulating film 20 is formed by depositing a silicon nitride film by a low pressure chemical vapor deposition (LPCVD) method and a plasma enhanced chemical vapor deposition (PECVD) method.
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the gate electrode 22 is formed on the gate insulating film 20 .
  • a resist mask is formed on the gate insulating film 20 using a photolithographic technique.
  • the gate electrode 22 is formed in only a patterned place using a deposition method and a lift-off method.
  • the source electrode (first electrode) 24 , the drain electrode (second electrode) 26 , and the anode electrode (third electrode) 28 are formed using a known process.
  • the anode electrode (third electrode) 28 is formed by etching the partial region of the p-type GaN layer (third GaN based semiconductor layer) 16 of the p-type termination portion (sixth GaN based semiconductor layer) 42 to expose the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 .
  • the semiconductor device according to this embodiment illustrated in FIG. 12 is manufactured.
  • the second manufacturing method of the semiconductor device according to this embodiment is different from the second manufacturing method of the semiconductor device according to the first embodiment in that the partial region on the third GaN based semiconductor layer is covered by the second mask material, when the fourth GaN based semiconductor layer is formed.
  • the partial region on the third GaN based semiconductor layer is covered by the second mask material, when the fourth GaN based semiconductor layer is formed.
  • FIGS. 19 to 23 are schematic cross-sectional views illustrating the second manufacturing method of the semiconductor device according to this embodiment. A description of content overlapped to that of the first manufacturing method will be omitted.
  • the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 is formed on the n + -type GaN layer (first GaN based semiconductor layer) 12 by the epitaxial growth method.
  • the partial region on the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 is covered by a mask material (first mask material) 46 (refer to FIG. 19 ).
  • the mask material 46 is formed by patterning using a known film deposition method, photolithography, and etching.
  • the mask material 46 is, for example, a silicon oxide film.
  • the p-type GaN layer (third GaN based semiconductor layer) 16 containing the p-type impurities is formed on the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 by the selective epitaxial growth method (refer to FIG. 20 ).
  • the p-type impurities are, for example, Mg (magnesium).
  • source gas is, for example, trimethyl gallium (TMG) or ammonia (NH 3 ) and a p-type dopant in the source gas is, for example, is cyclopentadienyl magnesium (Cp 2 Mg).
  • the partial region on the p-type GaN layer (third GaN based semiconductor layer) 16 is covered by a mask material (second mask material) 48 (refer to FIG. 21 ).
  • the mask material 48 is formed by patterning using a known film deposition method, photolithography, and etching.
  • the mask material 46 is, for example, a silicon oxide film.
  • the n + -type GaN layer (fourth GaN based semiconductor layer) 18 is formed on the p-type GaN layer (third GaN based semiconductor layer) 16 by the selective epitaxial growth method (refer to FIG. 22 ).
  • the n + -type GaN layer (fourth GaN based semiconductor layer) 18 contains as the n-type impurities Si (silicon) with the impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
  • the mask materials 46 and 48 are peeled (refer to FIG. 23 ).
  • the mask materials 46 and 48 are peeled by wet etching.
  • the gate insulating film 20 , the gate electrode 22 , the source electrode (first electrode) 24 , the drain electrode (second electrode) 26 , and the anode electrode (third electrode) 28 are formed.
  • the breakdown voltages of the transistor and the diode are improved. Therefore, a semiconductor device having a higher breakdown voltage is realized.
  • the p-type impurity concentrations of the p-type GaN layer (third GaN based semiconductor layer) 16 , the p-type termination structure (fifth GaN based semiconductor layer) 40 , and the p-type termination portion (sixth GaN based semiconductor layer) 42 are preferably higher than the n-type impurity concentration of the n ⁇ -type GaN layer (second GaN based semiconductor layer) 14 by one digit or more and three digit or less, from the viewpoint of improving the breakdown voltage of the semiconductor device 200 .
  • a semiconductor device is the same as the semiconductor device according to the second embodiment, except that the semiconductor device includes a Si (silicon) substrate of a first conductive type provided between a first GaN based semiconductor layer of the first conductive type and a second electrode. Therefore, a description of the same content as that of the second embodiment will be omitted.
  • FIG. 24 is a schematic cross-sectional view illustrating a configuration of the semiconductor device according to this embodiment.
  • a semiconductor device 300 according to this embodiment includes an n-type Si (silicon) substrate 52 provided between an n + -type GaN layer (first GaN based semiconductor layer) 12 and a drain electrode (second electrode) 26 , in addition to the structure according to the first embodiment.
  • a GaN based semiconductor layer is formed on the n-type Si (silicon) substrate 52 by a heteroepitaxial growth.
  • the n + -type GaN layer (first GaN based semiconductor layer) 12 functions as a buffer layer.
  • the n-type Si (silicon) substrate 52 can be used as the substrate of the epitaxial growth, a cost of the semiconductor device 400 can be decreased, and a diameter of a wafer can be easily increased.
  • a semiconductor device is the same as the semiconductor device according to the third embodiment, except that a concave portion reaching an n + -type GaN layer (first GaN based semiconductor layer) is provided in an n-type Si (silicon) substrate. Therefore, a description of the same content as that of the third embodiment will be omitted.
  • the concave portion is provided in the n-type Si (silicon) substrate 52 and the drain electrode 26 is formed in the concave portion, which results in decreasing on-resistance.
  • n-type Si (silicon) substrate 52 can be removed by etching or polishing.
  • an element structure is the same as that of the second embodiment.
  • the example of the case in which the first conductive type is the n type and the second conductive type is the p type has been described.
  • the first conductive type may be the p type and the second conductive type may be the n type.
  • one transistor and one diode are formed in one chip.
  • one transistor and a plurality of diodes, a plurality of transistors and one diode, or a plurality of transistors and a plurality of diodes can be formed in one chip.

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