US20140256147A1 - Plasma processing apparatus and plasma processing method - Google Patents

Plasma processing apparatus and plasma processing method Download PDF

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US20140256147A1
US20140256147A1 US14/347,033 US201214347033A US2014256147A1 US 20140256147 A1 US20140256147 A1 US 20140256147A1 US 201214347033 A US201214347033 A US 201214347033A US 2014256147 A1 US2014256147 A1 US 2014256147A1
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electrode
power
plasma
upper electrode
frequency
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Hikaru Watanabe
Masanobu Honda
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
    • H01J37/32155—Frequency modulation
    • H01J37/32165—Plural frequencies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/3244—Gas supply means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32532—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching

Definitions

  • the embodiments described herein pertain generally to a plasma process performed in microprocessing a target substrate such as a semiconductor wafer or the like, and particularly, to a capacitively coupled plasma processing apparatus and a plasma processing method.
  • plasma has been widely used to carry out a sufficient reaction to a processing gas at a relatively low temperature.
  • a high frequency power (RF) or a microwave power has been used to electrically discharge or ionize a processing gas within a vacuum processing chamber.
  • an upper electrode and a lower electrode are arranged to be parallel with each other within a processing chamber, a target substrate (a semiconductor wafer, a glass substrate, or the like) is typically mounted on the lower electrode, and a high frequency power having a frequency (typically, about 13.56 MHz or more) suitable for plasma generation is applied to the upper electrode or the lower electrode.
  • a high frequency electric field generated between the two electrodes facing each other by applying the high frequency power electrons are accelerated, and due to ionization by collision between the electrons and a processing gas, plasma is generated.
  • a gas phase reaction or a surface reaction of radicals or ions in the plasma a thin film is deposited on the substrate, or a material of the substrate or a thin film on a surface of the substrate is etched.
  • Patent Document 1 a technology of applying a negative DC (Direct Current) voltage to a facing electrode (typically, an upper electrode) that faces a substrate with a processing space therebetween has attracted attention.
  • a negative DC (Direct Current) voltage typically, an upper electrode
  • This upper electrode DC power applying manner has at least one of the following effects: (1) the effect of enhancing sputtering at the upper electrode by increasing an absolute value of a self-bias voltage of the upper electrode; (2) the effect of reducing generated plasma by expanding a plasma sheath at the upper electrode; (3) the effect of irradiating electrons generated near the upper electrode to the target substrate; (4) the effect of controlling a plasma potential; (5) the effect of increasing an electron density (plasma density); and (6) the effect of increasing a plasma density at a central portion thereof.
  • the upper electrode DC power applying manner as described above has often been used in a HARC (High Aspect Ratio Contact) process.
  • the HARC process is to form a narrow and deep contact hole or via hole in an oxide film (typically, a silicon oxide film) of an insulating layer by the plasma etching during a wiring forming process for manufacturing a LSI.
  • an anisotropic profile of high precision and high selectivity with respect to a mask and an underlying film may be required, a fluorocarbon-based gas may be used as an etching gas, and a silicon-containing material such as silicon or SiC may be used as a base material of an upper electrode.
  • anisotropy and selectivity can be greatly improved.
  • deposits mainly, fluorocarbon polymerized film
  • silicon sputtered from the base material of the upper electrode reacts with fluorine radicals, so that a highly volatile reaction product (SiF 4 ) is produced and then exhausted. Therefore, it is possible to reduce fluorine that lowers anisotropy and selectivity (fluorine scavenging effect).
  • electrons of high energy are introduced to the resist mask on the surface of the substrate, so that a composition of a surface layer of the resist mask is modified and etching resistance (plasma resistance) is enhanced.
  • a plasma potential is controlled to be reduced. That is, as an absolute value of a negative DC voltage to be applied to the upper electrode is increased in order to obtain any one of the other effects (1) to (3), (5), and (6) as desired, a plasma potential near a sidewall of the chamber is decreased. Accordingly, the effect of removing deposits attached to the sidewall of the chamber by the sputtering through the ion irradiation is reduced. This is also a problem.
  • example embodiments provide a plasma processing apparatus and a plasma processing method capable of maintaining advantages of an upper electrode DC power applying manner and removing disadvantages of the upper electrode DC power applying manner.
  • a plasma processing apparatus includes a processing chamber allowed to be vacuum exhausted; a first electrode that is provided within the processing chamber and configured to mount and support thereon a target substrate; a second electrode that is provided to be parallel with the first electrode with a preset gap within the processing chamber; a processing gas supply unit configured to supply a predetermined processing gas into a processing space between the first electrode and the second electrode within the processing chamber; a first high frequency power supply configured to apply a first high frequency power having a frequency for electrically discharging the processing gas and generating plasma to the first electrode; an AC power supply configured to apply a low frequency or a high frequency AC power having a frequency, which an ion in the plasma is allowed to follow, to the second electrode; and a blocking capacitor connected between the AC power supply and the second electrode.
  • a negative DC voltage i.e. a self-bias voltage
  • the self-bias voltage is overlapped with an AC voltage (instantaneous value). That is, an electric potential of the second electrode is cyclically changed since the self-bias voltage is overlapped with the AC voltage level (instantaneous value).
  • ion energy of ions which follows a frequency of the AC power and incident to the upper electrode from the plasma, is proportional to a depth (absolute value) in a direction of a negative electric potential of the second electrode and is cyclically changed.
  • the frequency of the AC power applied to the second electrode is higher than an ion plasma frequency, a follow-up property of the ions is decreased. Further, as the frequency of the AC power is increased, a width of an energy band in the ion energy distribution is narrowed. That is, a deviation of the ion energy is decreased and the ion energy is distributed almost near a central value corresponding to the self-bias voltage. Thus, the maximum value of the ion energy is decreased.
  • the sputtering yield largely depends on the magnitude (maximum value) of the ion energy rather than the number of incident ions.
  • the AC power applying manner of the example embodiment can improve the sputtering yield at the second electrode with more efficiency.
  • an electric potential of the second electrode is higher than the self-bias voltage, so that the plasma potential is increased accordingly. Therefore, the plasma potential near the sidewall of the chamber is increased in a time-average manner.
  • the sputtering effect of removing deposits attached to the sidewall of the chamber can be improved, and the deposits on the sidewall of the chamber can be efficiently removed.
  • a plasma etching method of forming a hole of a high aspect ratio in a silicon oxide film on a target substrate includes mounting and supporting the target substrate on a first electrode within a processing chamber in which the first electrode is provided to be parallel with a second electrode with a preset gap; vacuum exhausting an inside of the processing chamber to a preset pressure; generating plasma of a fluorocarbon-based etching gas in a processing space between the first electrode and the second electrode by supplying the etching gas into the processing space and applying a first high frequency power to the first electrode; and applying a low frequency AC power or a high frequency AC power having a frequency, which an ion in the plasma is allowed to follow, to the second electrode via a blocking capacitor.
  • the plasma etching method of the example embodiment since the above-described upper electrode AC power applying manner is used, it is possible to improve in-plane uniformity in etching rates while obtaining mask selectivity equivalent to that of the conventional upper electrode DC power applying manner.
  • FIG. 1 is a longitudinal cross sectional view showing a configuration of a capacitively coupled plasma etching apparatus in accordance with an example embodiment.
  • FIG. 2 shows a potential distribution between both electrodes and an ion energy distribution of ions incident to an upper electrode in an upper electrode AC power applying manner in accordance of the example embodiment.
  • FIG. 3 shows a potential distribution between both electrodes and an ion energy distribution of ions incident to an upper electrode in an upper electrode DC power applying manner in accordance of a comparative example.
  • FIG. 4 shows a correlation between ion energy and a sputtering yield.
  • FIG. 5A shows a wafer in-plane distribution of etching rates of a silicon oxide film obtained from a HARC process experiment to which the upper electrode AC power applying manner is applied.
  • FIG. 5B shows a wafer in-plane distribution of etching rates of a photoresist obtained from the HARC process experiment to which the upper electrode AC power applying manner is applied.
  • FIG. 6A shows a wafer in-plane distribution of etching rates of a silicon oxide film obtained from a HARC process experiment to which the upper electrode DC power applying manner is applied.
  • FIG. 6B shows a wafer in-plane distribution of etching rates of a photoresist obtained from the HARC process experiment to which the upper electrode DC power applying manner is applied.
  • FIG. 7 is a plot diagram showing correlations between mask selectivity and etching rate in-plane uniformity in the upper electrode AC power applying manner and the upper electrode DC power applying manner.
  • FIG. 8 shows etching profiles (SEM images) obtained from a HARC process experiment in accordance with an experimental example.
  • FIG. 9 shows correlations between mask selectivity and a bowing amount in the upper electrode AC power applying manner and the upper electrode DC power applying manner.
  • FIG. 10A and FIG. 10B are diagrams for explaining a BEOL process in accordance with an experimental example.
  • FIG. 11 shows cross sectional views (SEM images) of patterns obtained from a first experiment of the BEOL process in accordance with the experimental example and measurement values of measurement items.
  • FIG. 12 shows cross sectional views (SEM images) of patterns obtained from a second experiment of the BEOL process in accordance with the experimental example and measurement values of measurement items.
  • FIG. 13 is a plot diagram showing correlations between a top CD and a low-k damage amount obtained from a result of the first experiment.
  • FIG. 14 is a plot diagram showing correlations between a top CD and a low-k damage amount obtained from a result of the second experiment.
  • FIG. 15 shows correlations (N e —lower electrode V L characteristics) between an electron density (N e ) within a processing space and a self-bias voltage (V L ) generated at a lower electrode in the upper electrode DC power applying manner.
  • FIG. 16 shows correlations (N e —lower electrode V L characteristics) between an electron density (N e ) within a processing space and a self-bias voltage (V L ) generated at a lower electrode in the upper electrode AC power applying manner.
  • FIG. 17 is a plot diagram showing correlations between an upper electrode applying voltage or power and a plasma potential obtained from an experiment in accordance with an experimental example.
  • FIG. 18 shows experimental results (SEM images) of an ArF resist modifying process in the upper electrode AC power applying manner and the upper electrode DC power applying manner.
  • FIG. 1 shows a configuration of a plasma processing apparatus in accordance with an example embodiment.
  • the plasma processing apparatus is configured as a capacitively coupled (parallel plate type) plasma etching apparatus, in which dual high frequency powers are applied to a lower electrode.
  • the plasma processing apparatus includes a cylindrical vacuum chamber (processing chamber) 10 made of, for example, aluminum of which a surface is alumite treated (anodically oxidized). The chamber 10 is grounded.
  • a cylindrical susceptor supporting member 14 is provided via an insulating plate 12 such as ceramic, and a susceptor 16 made of, for example, aluminum is provided on the susceptor supporting member 14 .
  • the susceptor 16 constitutes a lower electrode, and a target substrate such as a semiconductor wafer W is mounted thereon.
  • an electrostatic chuck 18 configured to hold the semiconductor wafer W.
  • This electrostatic chuck 18 includes an electrode 20 made of a conductive film to be interposed between a pair of insulating layers or insulating sheets.
  • the electrode 20 is electrically connected to a DC power supply 22 .
  • the semiconductor wafer W can be held on the electrostatic chuck 18 by an electrostatic attracting force caused by a DC voltage from the DC power supply 22 .
  • a focus ring 24 made of, for example, silicon and configured to improve etching uniformity.
  • a cylindrical inner wall member 25 made of, for example, quartz is provided.
  • a coolant path 26 extending, for example, along a circumference thereof.
  • a coolant such as cooling water having a certain temperature is circulated and supplied from an external chiller unit (not illustrated) through lines 27 a and 27 b .
  • a process temperature of the semiconductor wafer W on the susceptor 16 is controlled according to a temperature of the coolant.
  • a heat transfer gas such as a He gas is supplied between an upper surface of the electrostatic chuck 18 and a rear surface of the semiconductor wafer W from a heat transfer gas supply device (not illustrated) through a gas supply line 28 .
  • the susceptor 16 is electrically connected to first and second high frequency power supplies 30 and 32 via matching units 34 and 36 , blocking capacitors 38 and 40 , and power supply rods 42 and 44 , respectively. Further, although the power supply rods 42 and 44 are separately illustrated in FIG. 1 , the power supply rods 42 and 44 may be a common or same power supply rod.
  • the first high frequency power supply 30 is configured to output a high frequency power RF H for plasma generation having a constant frequency of, for example, about 40 MHz, which mainly contributes to plasma generation.
  • the second high frequency power supply 32 outputs a high frequency power RF L for ion attraction having a constant frequency of, for example, about 13 MHz, which mainly contributes to ion attraction to the semiconductor wafer W on the susceptor 16 .
  • an upper electrode 46 facing the susceptor 16 to be parallel with each other.
  • This upper electrode 46 includes an electrode plate 48 made of a silicon-containing material, such as Si, SiC, or the like, and an electrode supporting body 50 made of a conductive material, for example, aluminum of which a surface is alumite treated. Multiple gas discharge holes 48 a are formed in the electrode plate 48 , and the electrode supporting body 50 is configured to detachably support the electrode plate 48 . Further, the upper electrode 46 in an electrically floated state is provided at the chamber 10 via a ring-shaped insulator 52 . A plasma generation space or a processing space (PS) is formed between the upper electrode 46 and the susceptor 16 .
  • PS processing space
  • the ring-shaped insulator 52 is made of, for example, alumina (Al 2 O 3 ) and provided to airtightly seal a gap between an outer peripheral surface of the upper electrode 46 and a sidewall of the chamber 10 , and also physically supports the upper electrode 34 .
  • the electrode supporting body 50 includes a gas buffer room 54 therein, and includes multiple gas vent holes 50 a communicating with the gas discharge holes 48 a of the electrode plate 48 from a lower surface of the gas buffer room 54 .
  • the gas buffer room 54 is connected to a processing gas supply source 58 via a gas supply line 56 .
  • a mass flow controller (MFC) 60 and an opening/closing valve 62 are provided.
  • etching gas etching gas
  • the processing gas is discharged in a shower shape into the processing space PS through the gas discharge holes 48 a of the electrode plate 48 toward the semiconductor wafer W on the susceptor 16 .
  • the upper electrode 34 serves as a shower head configured to supply the processing gas into the processing space PS.
  • a path (not illustrated) through which a coolant such as cooling water flows.
  • the entire upper electrode 46 , particularly, the electrode plate 48 are controlled to have a certain temperature by the coolant supplied from the external chiller unit.
  • a heater (not illustrated) made of, for example, a resistance heating element may be provided within the electrode supporting body 50 or on an upper surface of the electrode supporting body 50 .
  • This capacitively coupled plasma processing apparatus further includes an AC power supply 64 at an outside of the chamber 10 .
  • An output terminal of the AC power supply 64 is electrically connected to the upper electrode 46 via a matching unit 66 , a blocking capacitor 68 , and a DC power supply line or power supply rod 70 .
  • the AC power supply 64 is configured to output an AC power, and a power, a voltage peak value, or an effective value thereof is variable.
  • the AC power has a frequency f, which ions in the plasma can follow, i.e., the AC power has a low frequency or a high frequency, which is lower than an ion plasma frequency.
  • a ring-shaped DC ground part (not illustrated) made of a conductive member such as Si, SiC, or the like is provided.
  • This DC ground part is constantly grounded via a ground line (not illustrated).
  • An annular space between the susceptor 16 and the susceptor supporting member 14 and the sidewall of the chamber 10 is formed as an exhaust space, and at a bottom portion of the exhaust space, an exhaust opening 72 of the chamber 10 is formed.
  • This exhaust opening 72 is connected to an exhaust device 76 via an exhaust line 74 .
  • the exhaust device 76 includes a vacuum pump such as a turbo molecular pump or the like, and the inside of the chamber 10 , particularly, the processing space PS can be depressurized to a desired vacuum level.
  • a gate valve 80 configured to open and close a loading/unloading opening 78 for the semiconductor wafer W.
  • a control unit 82 includes a microcomputer, and is configured to control an operation of each component in the apparatus and particularly, the high frequency power supplies 30 and 32 , the AC power supply 64 , the matching units 34 , 36 , and 66 , the MFC 60 , the opening/closing valve 62 , the exhaust device 76 , and the like, and also the whole operation (sequence) of the apparatus according to software (program) and recipe information stored in an external memory or an internal memory.
  • the gate valve 80 is opened first, and the semiconductor wafer W as a target to be processed is loaded into the chamber 10 and mounted on the electrostatic chuck 18 . Then, a processing gas, i.e. an etching gas (typically, a mixed gas) is introduced from the processing gas supply source 58 into the chamber 10 at a certain flow rate with a flow rate ratio, and the chamber 10 is evacuated to have a preset pressure value by the exhaust device 76 .
  • an etching gas typically, a mixed gas
  • a first high frequency power of a certain frequency (about 40 MHz) and a second high frequency power of a certain frequency (about 13 MHz) from the first and second high frequency power supplies 30 and 32 , respectively, are overlapped with each other and applied to the susceptor 16 with preset powers.
  • a DC voltage is applied to the electrode 20 of the electrostatic chuck 18 from the DC power supply 22 to hold the semiconductor wafer W on the electrostatic chuck 18 .
  • the etching gas discharged from the shower head of the upper electrode 46 is electrically discharged under a high-frequency electric field between the both electrodes 46 and 16 , so that plasma is generated within the processing space PS.
  • a target film on a main surface of the semiconductor wafer W is etched with radicals or ions in the plasma.
  • the capacitively coupled plasma etching apparatus applies the first high frequency power having a relatively high frequency suitable for plasma generation to the susceptor 12 , the plasma can be in a desirable dissociation state with high density, so that high-density plasma can be generated under a lower pressure.
  • the second high frequency power having a relatively low frequency suitable for ion attraction is applied to the susceptor 12 , so that an anisotropic etching process can be performed on the target film on the semiconductor wafer W.
  • the capacitively coupled plasma etching apparatus employs a lower electrode dual high frequency power applying structure in which dual high frequency powers RF H and RF L for plasma generation and ion attraction, respectively, are applied to the lower electrode (susceptor) 16 .
  • the capacitively coupled plasma etching apparatus has a configuration and a function for an upper electrode AC power applying manner in which the AC power is applied to the upper electrode 46 via the blocking capacitor 68 from the AC power supply 64 .
  • the AC power has a frequency, which ions in the plasma can follow, i.e., the AC power has a frequency f lower than an ion plasma frequency.
  • the AC power supply 64 can vary a power, a voltage peak value, or an effective value thereof.
  • the ion plasma frequency f pi is determined by the following Equation (1).
  • e denotes the electric charge of the electron
  • n o denotes a plasma density
  • ⁇ 0 denotes a dielectric constant in a vacuum
  • m i denotes an ion mass
  • n o 1 ⁇ 10 9 cm ⁇ 3
  • f pi 2 MHz
  • n o 1 ⁇ 10 10 cm ⁇ 3
  • f pi 3 MHz.
  • FIG. 2 shows a potential distribution between the upper electrode 46 and the lower electrode (susceptor) 16 , and an ion energy distribution of ions incident to the upper electrode 46 in the capacitively coupled plasma etching apparatus.
  • a negative DC voltage i.e. a self-bias voltage V B is generated at the upper electrode 46 , and the self-bias voltage V B is overlapped with an AC voltage (instantaneous value).
  • the self-bias voltage V B since the frequency f of the AC power is lower than the ion plasma frequency f pi and an electron temperature near the upper electrode 46 is low, the self-bias voltage V B has a value close to the AC voltage peak value. As such, an electric potential of the upper electrode 46 is cyclically changed since the self-bias voltage V B is overlapped with the voltage level (instantaneous value).
  • ions of positive electric charges in the plasma are accelerated by an electric field within a sheath according to the electric potential of the upper electrode 46 and incident to the upper electrode 46 .
  • Energy of the ions incident to the upper electrode 46 is proportional to a depth (absolute value) in a direction of a negative electric potential of the upper electrode 46 and is cyclically changed. Therefore, during each cycle, when the AC voltage level has the minimum value, the ion energy has the maximum value, whereas when the AC voltage level has the maximum value, the ion energy has the minimum value.
  • an ion energy distribution IED since a lot of ions are incident to the electrode in a time range (near the maximum or minimum level) in which a voltage change over time is small, a lot of ions are distributed near the maximum ion energy level or the minimum ion energy level.
  • the upper electrode AC power applying manner of the example embodiment whenever the AC voltage level has the minimum value during each cycle, a lot of ions having the maximum ion energy corresponding to the maximum negative electric potential as the sum of the self-bias voltage V B and the AC voltage peak value are incident to the upper electrode 46 .
  • the frequency f of the AC power is higher than the ion plasma frequency f pi , a follow-up property of the ions is decreased. Further, as the frequency f of the AC power is increased, a width of an energy band in the ion energy distribution IED is narrowed as shown in FIG. 2 . That is, a deviation of the ion energy is decreased and the ion energy is distributed almost near a central value corresponding to the self-bias voltage V B . Thus, the maximum value of the ion energy is decreased.
  • FIG. 3 shows a potential distribution when a negative DC voltage V dc is applied to the upper electrode 46 by a DC power supply 84 and an ion energy distribution of ions incident to the upper electrode 46 according to the conventional upper electrode DC power applying manner as a comparative example of the upper electrode AC power applying manner.
  • an ion energy distribution IED has a profile in which energy of all incident ions are included in an energy band of a very narrow width corresponding to the DC voltage V dc . Therefore, during a plasma process, ions that are normally included in a uniform narrow energy band are incident to the upper electrode 46 at a substantially uniform rate.
  • the sputtering yield largely depends on the magnitude (maximum value) of the ion energy rather than the number of incident ions.
  • the upper electrode AC power applying manner of the example embodiment can improve a sputtering yield at the upper electrode 46 with more efficiency.
  • the upper electrode DC power applying manner since an electric potential of the upper electrode 46 is maintained to the negative DC voltage V dc , a plasma potential is decrease to be low.
  • the potential of the upper electrode 46 in a half cycle where an AC voltage level has a positive value, the potential of the upper electrode 46 is higher than the self-bias voltage V B , so that a plasma potential is increased accordingly.
  • a plasma potential near the sidewall of the chamber is increased to a considerably high value.
  • a plasma potential near the sidewall of the chamber 10 is considerably high in a time-average manner and ion energy of ions incident to the sidewall of the chamber 10 from the plasma is remarkably increased.
  • the sputtering effect of removing deposits attached to the chamber sidewall can be improved, and the deposits on the chamber sidewall can be efficiently removed. Therefore, reproducibility of the process and mass productivity of the apparatus can be improved.
  • the present inventors conducts an experiment for comparing the upper electrode AC power applying manner of the example embodiment and the conventional upper electrode DC power applying manner in a HARC process by using a plasma etching apparatus ( FIG. 1 ) of the present example embodiment.
  • a plasma etching apparatus FIG. 1
  • FIG. 5A and FIG. 5B wafer in-plane distributions of etching rates (E/R) of a silicon oxide film (etching target film) and a photoresist (mask) are shown as experimental results of the upper electrode AC power applying manner, respectively.
  • FIG. 6A and FIG. 6B wafer in-plane distributions of etching rates (E/R) of a silicon oxide film and a photoresist are shown as experimental results of the upper electrode DC power applying manner, respectively.
  • Principal process conditions of the HARC process experiment are as follows.
  • Resist ArF resist for acrylate base
  • Upper electrode/chamber sidewall/lower electrode about 60/about 60/about 40° C.
  • AC power frequency about 380 kHz
  • AC power about 0 W, about 250 W, about 500 W, about 1000 W
  • V dc about 0 V, about ⁇ 150 V, about ⁇ 300 V, about ⁇ 450 V, about ⁇ 600 V
  • the upper electrode AC power applying manner and the upper electrode DC power applying manner are not much different in etching rate distribution of the photoresist (PR), and each has a low and flat profile. That is, to enhance plasma resistance of the photoresist (PR), in the HARC process, the upper electrode AC power applying manner sufficiently has the above-described effects (1) and (3), and the upper electrode DC power applying manner also has the above-described effects (1) and (3) to be equivalent to those of the upper electrode AC power applying manner.
  • the profiles of the both manners are clearly different in etching rate distribution of the silicon oxide film (SiO 2 ). That is, in the profile of the upper electrode DC power applying manner, as an absolute value of a DC voltage V dc is increased, a difference between an etching rate at a central portion of the wafer and an etching rate at an edge portion of the wafer is increased, and an etching rate at the central portion of the wafer becomes remarkably increased. In short, as an application voltage (absolute value) is increased in the upper electrode DC power applying manner, in-plane uniformity in etching rates of SiO 2 is deteriorated.
  • a difference in in-plane uniformity in etching rates of SiO 2 in the HARC process of the upper electrode DC power applying manner and the upper electrode AC power applying manner may be caused by a difference in the effect (6). That is, it is deemed that in the upper electrode DC power applying manner, by increasing an absolute value of the DC voltage V dc , the effect (6) is unwillingly strengthened, whereas in the upper electrode AC power applying manner, even if the AC power is increased, the effect (6) is not as strong as that of the upper electrode DC power applying manner.
  • a correlation F AC between mask selectivity and in-plane uniformity in etching rates of SiO 2 in the upper electrode AC power applying manner is obtained from etching characteristics of an oxide film as shown in FIG. 5A and etching characteristics of a resist as shown in FIG. 5B by using the AC power as a parameter.
  • a correlation F DC between mask selectivity and in-plane uniformity in etching rates of SiO 2 in the upper electrode DC power applying manner is obtained from etching characteristics of an oxide film as shown in FIG. 6A and etching characteristics of a resist as shown in FIG. 6B by using the voltage value (absolute value) of the DC voltage V dc as a parameter.
  • FIG. 7 provides a plot diagram comparatively showing the correlations F AC and F DC .
  • the high frequency powers RF H and RF L serve as a principal control knob (first control knob), so that etching rate characteristics can be controlled.
  • first control knob a voltage value (absolute value) of the DC voltage V dc in the upper electrode DC power applying manner and the AC power (or a voltage peak value, an effective value of the AC power or the like) in the upper electrode AC power applying manner
  • second control knob a control knob
  • the first control knob may be as independent as possible of the second control knob. Therefore, when mask selectivity is changed by using the second control knob, even if the etching rate characteristic (for example, in-plane uniformity) is affected and changed by such a change, desirably, a variation may be as small as possible.
  • the upper electrode AC power applying manner is better than the upper electrode DC power applying manner as shown in FIG. 7 .
  • FIG. 8 shows SEM images used for measuring etching profiles.
  • FIG. 9 shows correlations between mask selectivity and a bowing amount by comparing the upper electrode AC power applying manner with the upper electrode DC power applying manner.
  • the bowing amount refers to a difference between the maximum diameter (bowing CD) and the uppermost diameter (top CD) within a fine hole formed in a silicon oxide film. As the bowing amount is decreased, a vertical process profile is improved.
  • the upper electrode AC power applying manner As shown in FIG. 8 , in the upper electrode DC power applying manner, as the absolute value of the DC voltage V dc is increased, both the mask selectivity and the bowing amount are improved. Further, in the upper electrode AC power applying manner, as the AC power is increased, both the mask selectivity and the bowing amount are improved. However, as shown in FIG. 9 , when the bowing amounts are the same, the upper electrode AC power applying manner obtains higher mask selectivity than the upper electrode DC power applying manner. That is, to obtain both of an etching profile and mask selectivity, the upper electrode AC power applying manner is better than the upper electrode DC power applying manner.
  • the present inventors conducts two experiments for comparing the upper electrode AC power applying manner of the example embodiments and the conventional upper electrode DC power applying manner in a BEOL process by using a plasma etching apparatus ( FIG. 1 ) of the present example embodiment.
  • the BEOL process is a technology of forming a relatively shallow via hole in an interlayer insulating film by plasma etching in a wiring forming process for manufacturing a LSI.
  • an organic low-k film has been widely used as an interlayer insulating film of a target object.
  • a semiconductor wafer W formed by stacking a SiC film 90 as an underlying layer or an etching stop layer, two organic low-k films 92 and 94 as an etching target material, a TEOS film 96 as a hard mask, and a photoresist 98 as an uppermost pattern mask in sequence from the bottom is used as a target substrate.
  • a SiOC-based organic film containing Si, O, C, and H is used as shown in FIG.
  • a hole 100 is formed in advance to a depth in the middle of the TEOS film 96 by plasma etching in a pre-process. Further, as shown in FIG. 10B , the etching hole 100 is formed to be close to the bottom of the underlying low-k film 92 by the first and second experiments.
  • the first and second high frequency powers RF H and RF L to be applied to the lower electrode (susceptor) 16 are set to be about 630 W and about 160 W, respectively.
  • the electron density (Ne) and the self-bias voltage (V L ) (lower electrode V L ) of the lower electrode (susceptor) 16 are set to be about 4 ⁇ 10 10 cm ⁇ 3 and about 300 V, respectively.
  • the other process conditions are the same in the first and second experiments as follows.
  • Upper electrode/chamber sidewall/lower electrode about 60/about 60/a bout 60° C.
  • AC power frequency about 380 kHz
  • AC power about 0 W, about 250 W, about 500 W
  • V dc about 0 V, about ⁇ 300 V, about ⁇ 700 V
  • FIG. 11 shows cross sectional views (SEM images) of patterns obtained from the first experiment of the BEOL process and measurement values of measurement items.
  • a top CD is decreased and a low-k damage amount is increased as the absolute value of the DC voltage V dc is increased in the upper electrode DC power applying manner and as the AC power is increased in the upper electrode AC power applying manner.
  • this tendency is stronger in the upper electrode AC power applying manner than in the upper electrode DC power applying manner.
  • the low-k damage amount allowable in this kind of BEOL process is about 5 nm or less. Therefore, the both manners use a low voltage (low power) range.
  • the low-k damage amount is about 4 nm.
  • the etching depth is about 160 nm
  • the top CD is about 47 nm
  • the bowing CD is about 49 nm.
  • the low-k damage amount is about 5 nm.
  • the etching depth is about 150 nm
  • the top CD is about 46 nm
  • the bowing CD is about 46 nm.
  • FIG. 12 shows cross sectional views (SEM images) of patterns obtained from the second experiment of the BEOL process and measurement values of measurement items. Even in the second experiment, as shown in FIG. 12 , the top CD is decreased and the low-k damage amount is increased as the absolute value of the DC voltage V dc is increased in the upper electrode DC power applying manner and as the AC power is increased in the upper electrode AC power applying manner.
  • the upper electrode DC power applying manner if the V dc is about ⁇ 300 V at which the low-k damage amount is about 2 nm, the etching depth is about 155 nm, the top CD is about 51 nm, and the bowing CD is about 51 nm. Meanwhile, in the upper electrode AC power applying manner, if the AC power is about 250 W at which the low-k damage amount is about 5 nm, the etching depth is about 150 nm, the top CD is about 46 nm, and the bowing CD is about 46 nm. As such, it can be seen that even in the second experiment, there is no substantial difference between the upper electrode AC power applying manner of the example embodiment and the conventional upper electrode DC power applying manner.
  • N e electron density
  • V L self-bias voltage
  • the upper electrode AC power applying manner can expand a process margin to a lower electrode N e —lower electrode V L range.
  • the lower electrode N e —lower electrode V L range is suitable for, for example, a process of etching an insulating thin film of a MRAM (Magnetroresistive Random Access Memory) at a low speed.
  • the present inventors conduct other plasma etching experiments under the same process conditions as those of first experiment of the BEOL process except that the AC power is variable from about 0 W to about 100 W, about 125 W, about 250 W, and about 500 W in the upper electrode AC power applying manner and the absolute value of the DC voltage V dc is variable from about 0 V to about 150 V and about 300 V in the upper electrode DC power applying manner.
  • the AC power is variable from about 0 W to about 100 W, about 125 W, about 250 W, and about 500 W in the upper electrode AC power applying manner and the absolute value of the DC voltage V dc is variable from about 0 V to about 150 V and about 300 V in the upper electrode DC power applying manner.
  • V dc is variable from about 0 V to about 150 V and about 300 V in the upper electrode DC power applying manner.
  • FIG. 17 shows experimental results thereof.
  • the upper electrode DC power applying manner As shown in FIG. 17 , it is found that according to the upper electrode DC power applying manner, as the absolute value of the DC voltage V dc is increased, the plasma potential near the chamber sidewall is decreased, whereas according to the upper electrode AC power applying manner, as the AC power is increased, the plasma potential near the chamber sidewall is increased.
  • the electric potential of the upper electrode 46 is set to be the negative DC voltage V dc and a plasma potential is decreased, as described above.
  • the upper electrode AC power applying manner in a half cycle where the AC voltage level has a positive value, the electric potential of the upper electrode 46 is higher than the self-bias voltage V B , so that the plasma potential is increased accordingly. Therefore, the plasma potential near the chamber sidewall is increased in a time-average manner.
  • the present inventors conduct an experiment for comparing the upper electrode AC power applying manner of the example embodiment and the conventional upper electrode DC power applying manner in terms of the effect of modifying (reforming) an ArF resist as an etching mask under plasma. Principal process conditions of the experiment are as follows.
  • Upper electrode/chamber sidewall/lower electrode about 60/about 60/about 30° C.
  • AC power frequency about 380 kHz
  • AC power about 0 W, about 250 W, about 500 W
  • V dc about 0 V, about ⁇ 300 V, about ⁇ 700 V
  • Processing time about 30 seconds
  • FIG. 18 provides SEM images showing experimental results of the ArF resist modifying process.
  • a thickness of a modification layer is about 16.7 nm, about 21.4 nm, and about 40.8 nm when V dc is about 0 V, about ⁇ 300 V, and about ⁇ 700 V, respectively.
  • a thickness of a modification layer is about 16.7 nm, about 26.6 nm, and about 50.6 nm when the AC power is about 0 W, about 250 W, and about 500 W, respectively.
  • the thickness of the modification layer is increased as the absolute value of the DC voltage V dc is increased in the upper electrode DC power applying manner and as the AC power is increased in the upper electrode AC power applying manner, and the both manners are not much different in the increasing rate thereof.
  • the upper electrode AC power applying manner of the example embodiment can maintain advantages of the conventional upper electrode DC power applying manner in terms of, for example, a BEOL process or the effect of modifying a ArF resist and can also remove disadvantages of the upper electrode DC power applying manner in terms of, for example, a HARC process.
  • a value (about 380 kHz) of the frequency f of the AC power in the experimental example is an example, and a certain value of the frequency f which ions can follow may be used for the frequency of the AC power. Therefore, as the frequency f of the AC power may be higher than about 380 kHz in the above-described example embodiment or may use a frequency band to about 13 MHz which is considered as a limit to a frequency which ions can typically follow (a frequency which can apply energy to ions in a different view).
  • the matching unit 66 is used in order to apply the AC power outputted from the AC power supply 64 to the upper electrode 46 at the maximum power transmission efficiency, but the matching unit 66 may be omitted. Furthermore, the second high frequency power RF L may not be applied to the lower electrode (susceptor) 16 , i.e. the high frequency power supply 32 , the matching unit 40 , and the blocking capacitor 40 may be omitted. Besides, the shower head configuration in the upper electrode 46 may be randomly changed.
  • the example embodiment is not limited to the capacitively coupled plasma etching apparatus and can be applied to a capacitively coupled plasma processing apparatus that performs a certain plasma process such as plasma CVD, plasma ALD, plasma oxidation, plasma nitrification, sputtering, and the like.
  • the target substrate in the example embodiment is not limited to the semiconductor wafer, and a flat panel display, organic EL, various substrates for solar cell, or a photo mask, a CD substrate, a print substrate, and the like may be used.

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