US20130299895A1 - Iii-v compound semiconductor device having dopant layer and method of making the same - Google Patents

Iii-v compound semiconductor device having dopant layer and method of making the same Download PDF

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US20130299895A1
US20130299895A1 US13/467,133 US201213467133A US2013299895A1 US 20130299895 A1 US20130299895 A1 US 20130299895A1 US 201213467133 A US201213467133 A US 201213467133A US 2013299895 A1 US2013299895 A1 US 2013299895A1
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Prior art keywords
layer
dopant
channel layer
semiconductor
iii
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US13/467,133
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Richard Kenneth Oxland
Mark Van Dal
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to US13/467,133 priority Critical patent/US20130299895A1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. reassignment TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OXLAND, RICHARD KENNETH, VAN DAL, MARK
Priority to US13/604,510 priority patent/US9252237B2/en
Priority to KR1020120143404A priority patent/KR101452064B1/ko
Priority to TW102113897A priority patent/TWI559533B/zh
Publication of US20130299895A1 publication Critical patent/US20130299895A1/en
Priority to US14/926,077 priority patent/US9685514B2/en
Priority to US14/977,112 priority patent/US9406791B2/en
Abandoned legal-status Critical Current

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Definitions

  • the disclosure relates to III-V compound semiconductor device, and methods of manufacturing the same.
  • CMOS complementary metal oxide semiconductor
  • CMOS technology includes N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS).
  • NMOS N-type metal oxide semiconductor
  • PMOS P-type metal oxide semiconductor
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • One aspect of high performance in NMOS and PMOS and various other devices is device switching frequency. For devices to operate at high frequencies, it is necessary to have a low resistance, including a low contact resistance between metal interconnect structures and the channel of the NMOS and PMOS transistors. Contact is made to the gate electrodes, as well as to both the source and drain regions, of the associated transistors.
  • III-V compound semiconductors are potential channel materials for future CMOS devices because of their high mobility and low carrier effective mass.
  • One challenge is to reduce resistance in the source/drain (S/D) extensions to maximize the performance of the associated transistors in III-V semiconductor CMOS technology.
  • FIG. 1A illustrates a cross-sectional view of an exemplary III-V semiconductor MOSFET device according to the disclosure.
  • FIG. 1B is an enlarged detail of FIG. 1A , showing components of the MOSFET device resistance.
  • FIG. 2 illustrates a cross-sectional view of an exemplary CMOS device without recess of the source/drain (S/D) region in accordance with one embodiment.
  • FIG. 3 illustrates a cross-sectional view of an exemplary CMOS device with recess of the source/drain (S/D) region in accordance with one embodiment.
  • FIG. 4 illustrates a cross-sectional view of an exemplary CMOS device without epitaxial growth of the source/drain (S/D) region in accordance with one embodiment.
  • FIGS. 5A-5C are flow chart diagrams illustrating methods of fabricating the exemplary CMOS devices without recess of the source/drain (S/D) region.
  • FIGS. 6A-6C are flow chart diagrams illustrating methods of fabricating the exemplary CMOS devices with recess of the source/drain (S/D) region.
  • FIGS. 7A-7B are flow chart diagrams illustrating methods of fabricating the exemplary CMOS device without epitaxial growth of the source/drain (S/D) region in accordance with one embodiment.
  • FIGS. 8A-8B illustrate a method of recessing the channel layer through etching in accordance with one embodiment.
  • FIGS. 9A-9C are schematic diagrams illustrating steps of forming a dopant layer through a method of monolayer doping in accordance with one embodiment.
  • FIGS. 10A-10B illustrate a method of selective epitaxial growth of the source and the drain (S/D) region in accordance with one embodiment.
  • FIGS. 11A-11B illustrate steps of a method of forming a metallic metal-semiconductor compound material, comprising coating a layer of metal followed by annealing at a raised temperature in accordance with one embodiment.
  • III-V compound semiconductors are potential channel materials for future CMOS devices because of their high electron mobility.
  • undoped source/drain (S/D) regions are used.
  • Two challenges include reducing resistance in the source/drain extension regions and reducing source/drain contact resistance.
  • a III-V compound semiconductor device and a method of making the same are provided to reduce external/extrinsic resistance in the S/D extension region.
  • the semiconductor device comprises a semiconductor substrate; active layers of at least one III-V semiconductor compound comprising a channel above the semiconductor substrate; a gate stack region above a first portion of the channel layer; a source region and a drain region on either side of the gate region in a second portion of the channel layer in some embodiments extending above the position of the surface of the channel layer; and a dopant layer comprising at least one dopant between the source and drain regions and the channel layer.
  • the dopant layer comprising at least one dopant contacting at least one portion of the channel layer provides low the external resistance in either a PMOS or NMOS device.
  • the S/D region in a PMOS or NMOS device comprises a metal-III-V-semiconductor ternary, quaternary or quinary compound with low resistivity.
  • the metal-III-V-semiconductor compound is thermodynamically stable when contacting semiconductor materials.
  • a method for forming such a semiconductor device comprises:
  • the step of providing the dopant layer includes forming a separate dopant layer above a portion of the channel layer and below the source or the drain (S/D) region.
  • the dopant layer is formed through a process selected from the group consisting of a monolayer doping process, an in-situ doping process, an implantation process or any combination thereof, as described in detail below.
  • a dopant is introduced into the channel in the S/D regions first.
  • a metal is then introduced onto the channel or in the S/D regions, followed by thermal annealing.
  • the metal reacts with the III-V semiconductor material in the S/D regions to form a metal-III-V-semiconductor compound in the S/D regions.
  • the dopant has low solid solubility in the metal-III-V semiconductor compound.
  • thermal annealing a dopant layer is formed between the channel and the S/D regions.
  • a localized highly doped channel layer is in the periphery of the S/D regions having the metal-III-V semiconductor compound.
  • the dopant diffuses into the channel at the interface.
  • FIGS. 1A-1B illustrate a cross-sectional view of an exemplary III-V semiconductor MOSFET device according to one embodiment.
  • the device is either a NMOS or a PMOS device.
  • FIG. 1B is an expanded view of the source/drain regions.
  • a transistor structure 100 is formed over substrate 102 , which, in some embodiments, is a semiconductor substrate such as silicon or silicon germanium or any other suitable semiconductor material. As in typical CMOS integrated circuits (ICs), the transistor comprises a shallow trench isolation region or a field oxide isolation region 104 above substrate 102 . Trench region 104 is made of oxides or other suitable insulating materials.
  • Buffer layer 106 is disposed over substrate 102 .
  • Buffer layer 106 is a III-V compound semiconductor in one embodiment, while other suitable buffer layers can be used in other embodiments.
  • a buffer layer of III-V semiconductor compounds is made of a combination of materials including a material from groups IIIA (B, Al, Ga, In, Tl) and a material from group VA (N, P, As, Sb, Bi) on the periodic table of elements.
  • Examples of a material for buffer layer 106 include GaAs, InP, InAs and other III-V materials, and are not limited to binary compound semiconductors.
  • Isolator layer 108 is disposed over buffer layer 106 .
  • isolator layer 108 is a III-V compound semiconductor material as described above.
  • Various suitable isolator materials include but not limited to CdTeSe, ZnSeTe, MgSeTe, InAlAs and AlAsSb, which are used as isolator layer 108 in various embodiments.
  • isolator layer 108 has a larger semiconductor bandgap than the channel material 110 .
  • isolator layer 108 is a buried dielectric material.
  • isolator layer 108 and buffer layer 106 have a lattice match for a high quality of epitaxial growth of channel layer 110 .
  • Channel layer 110 is disposed above isolator layer 108 .
  • Channel layer 110 and isolator layer 108 are referred as “active layers.”
  • channel layer 110 is a III-V semiconductor compound or other suitable materials. It is at least a binary material and may be a ternary material in various embodiments.
  • channel layer 110 shares a lattice structure matching with those of isolator layer 108 and buffer layer 106 , but they have different energy band gaps.
  • the material type of channel layer 110 determines the lattice structure, and the materials of isolator layer 108 and buffer layer 106 are selected based on such latter structure. For example, in one embodiment channel layer 110 is InAs, while isolator layer 108 is AlAsSb and buffer layer 106 is InAs.
  • channel layer 110 for NMOS is In x Ga (1-x) As, with x>0.7 although other suitable binary or ternary NMOS channel materials may be used in other embodiments.
  • NMOS channel material 108 is InAs.
  • channel layer 110 for PMOS is In y Ga (1-y) Sb, with 0 ⁇ y ⁇ 1 in some embodiments but various other suitable binary or ternary materials may be used in other embodiments.
  • channel layer 110 for PMOS is InSb or GaSb.
  • a CMOS transistor gate stack structure 120 is disposed above a first portion of channel layer 110 .
  • Gate stack structure 120 includes gate electrode and an insulating gate dielectric layer formed over channel material 110 and defines the gate region.
  • Gate dielectric layer is a high-k dielectric material but other suitable dielectric materials may be used in other embodiments.
  • Gate electrode is formed of various suitable gate materials such as polysilicon, titanium nitride or other suitable semiconductor or metal materials.
  • gate electrode is also used in this disclosure to encompass the gate stack structure 120 .
  • Gate stack is also used to refer to structure comprising a gate electrode and gate dielectric layer. In some drawings, the detailed structure of “gate stack” is not shown.
  • Spacer 118 is disposed along a side wall of gate stack 120 . In some embodiments, spacers are not used. Spacers 118 may be formed of oxides, nitrides, oxynitrides, combinations thereof and other suitable insulating materials.
  • Source/drain regions 114 are disposed above a second portion of the channel layer.
  • source/drain regions 114 are made of a III-V semiconductor compound or a derivatives thereof.
  • a material for source/drain regions 114 is a metallic ternary compound, such as nickelide compound, of a III-V semiconductor compound such as NiInP, NiInAs, and NiInSb Such are examples only and in other embodiments, other suitable ternary nickelide materials or other suitable metal semiconductor ternary, quaternary or quinary materials may be used in source/drain region 114 .
  • a material for source/drain region 114 is a low-resistance material as described above, and may include a resistance ranging from about 40 to 200 Ohms/sq.
  • Compositions and method of making a ternary (or other combination) compound of a III-V semiconductor material and a metal or metals are disclosed in U.S. application Ser. No. 13/414,437 in the name of the same inventors.
  • Metal contact structure 116 is coupled to source/drain regions 114 , and in various embodiments, suitable low resistivity conductive metals such as tungsten, copper, aluminum or their alloys or various other metals, are used as metal contact structure 116 .
  • semiconductor device 100 also comprises a separate dopant layer 112 comprising at least one dopant contacting the second portion of channel layer 110 .
  • dopant layer 112 directly contacts the second portion of channel layer 110 .
  • Dopant layer 112 is between the second portion of channel layer 110 and source/drain region 114 in some embodiments, but other suitable configurations and structures are suitable.
  • dopant layer 112 is formed at the interface of channel layer and source/drain. In some other embodiment, dopant layer 112 extends partially into the channel layer.
  • semiconductor device 100 is an NMOS transistor, and channel layer 110 is In x Ga (1-x) As, with x>0.7.
  • the dopant in dopant layer 112 is selected from the group consisting of sulfur and silicon or any other suitable material which shows limited solid solubility in the S/D metal-semiconductor compound.
  • semiconductor device 100 is a PMOS transistor, and channel layer 110 is In y Ga (1-y) As, with 0 ⁇ y ⁇ 1.
  • the dopant is beryllium, germanium, tin, carbon, or any other suitable material which shows limited solid solubility in the S/D metal-semiconductor compound.
  • Dopant layer is formed through a process selected from the group consisting of a monolayer doping process, an in-situ doping process, an implantation process, and any combinations thereof. These processes of forming a dopant layer are described in details hereafter in related steps shown in FIGS. 5A-5C .
  • R extension The resistance of source/drain extensions (R extension ) is reduced with introduction of dopant layer 112 .
  • R extension is further reduced with a combination of dopant layer 112 and source/drain (S/D) regions 114 comprising a metal-semiconductor compound such as nickelide, of III-V semiconductor compound. Reduction in total resistance of device 110 can be demonstrated in the following equation:
  • R total R channel +2*( R S/D +R extension +R c,1 +R c,2 )
  • R total is total resistance of device 110 ;
  • R S/D is resistance of source/drain regions 114 ;
  • R channel is resistance of channel layer 110 ;
  • R extension is resistance of the region under the spacer
  • R c,1 is contact resistance between metal contact structure 116 and source/drain regions 114 ;
  • R c,2 is contact resistance between source/drain regions 114 and channel layer 110 .
  • dopant layer 112 provides higher conductivity by doping the channel layer 110 or providing a high conductivity intermediate layer and decreases resistance between source drain 114 and channel layer 110 (R c,2 ).
  • source/drain (S/D) regions 114 comprising a metal-semiconductor compound such as nickelide, of III-V semiconductor compound, further decrease R S/D and contact resistance R c,1 and R c,2 .
  • both dopant layer 112 and source/drain (S/D) regions 114 comprising a metallic ternary compound decrease R extension .
  • source/drain regions 114 are recessed in some embodiments as shown in FIG. 1A-1B . In some embodiments, source/drain regions 114 are not recessed. In the “recessed” source/drain regions, the channel layer 110 are etched before formation of source/drain regions 114 so that a portion of the source region or the drain region or both is below a bottom height of the spacer. In some embodiments, regrowth of source/drain regions 114 are performed through a selective epitaxial growth technique. In some other embodiments, source/drain regions 114 are disposed after recess without using an epitaxial growth technique.
  • FIG. 2 illustrates a cross-sectional view of an exemplary CMOS device 200 without recess of the source/drain (S/D) region in accordance with one embodiment.
  • S/D source/drain
  • the exemplary device 200 in FIG. 2 is similar to that in FIG. 1A-1B , except that the source/drain regions 114 - 1 are not recessed.
  • FIG. 3 illustrates a cross-sectional view of an exemplary CMOS device with recess of the source/drain (S/D) region in accordance with one embodiment.
  • FIG. 3 is similar to that in FIG. 1A .
  • FIG. 1A is a cross-sectional view of a device in this disclosure.
  • the source/drain regions are recessed in some embodiments, and are not recessed in some other embodiments.
  • source/drain regions 114 - 2 are recessed so that a portion of the source region or the drain region or both is below a bottom height of the spacer.
  • FIG. 4 illustrates a cross-sectional view of an exemplary CMOS device 400 without recess or epitaxial growth of the source/drain (S/D) region in accordance with one embodiment.
  • compound semiconductor devices which include a dopant layer or locally doped channel region comprising at least one dopant contacting a second portion of the channel layer, can be fabricated based on different combination of the described structures.
  • the device can be either a PMOS or NMOS device.
  • the source/drain (S/D) regions can be recessed or not recessed. When the S/D regions are recessed, additional semiconductor material can be added to the S/D regions.
  • the variations in the structure are further combined with different processing steps of forming the dopant layer and the source/drain regions, as described below.
  • FIGS. 5A-5C , 6 A- 6 C, and 7 A- 7 B are flow chart diagrams to illustrate certain process steps and their combinations used to make the disclosed devices. The steps of forming a trench, a buffer layer, an isolator layer, a channel layer, a gate electrode including the dielectric layer, a spacer, and a metal contact structure above the substrate are not shown in the related diagrams.
  • FIGS. 8A-8B , 9 A- 9 C, 10 A- 10 B, and 11 A- 11 B are schematic cross-sectional diagrams to illustrate some of the key process steps including recessing the source/drain regions; forming the dopant layer through monolayer doping; regrowing the source/drain regions through selective epitaxial growth; forming a metallic ternary phases of III-V semiconductor compound in the source/drain regions, including forming the dopant layer (or doped region) at the periphery of the metal-semiconductor S/D region. Steps of FIGS. 5A-5C , 6 A- 6 C, and 7 A- 7 B, corresponding to FIGS. 8A-11B are individually described below.
  • dopant layer 112 is formed by introducing a dopant into the S/D regions through a process selected from the group consisting of a monolayer doping process, an in-situ doping process, an ion implantation process and any combination thereof.
  • a metallic ternary material is formed through a method comprising coating a layer of metal above source/drain regions 114 , followed by annealing at a raised temperature in accordance with some embodiments. Through this process, the dopant is driven out of the S/D region to the channel 110 at the periphery of the S/D regions 114 .
  • a dopant layer 112 is formed between the S/D regions 114 and the channel 110 .
  • source/drain regions 114 are recessed through an etching step. In some embodiments, the recessed source/drain regions are regrown through selective an epitaxial growth technique. As described as follows, various combinations of these steps of different techniques are combined to form the disclosed semiconductor devices.
  • FIGS. 5A-5C are flow chart diagrams illustrating methods of fabricating the exemplary CMOS devices without recess of the source/drain (S/D) region but with deposition, for example, by selective epitaxial growth, of raised S/D material.
  • MLD monolayer doping
  • a III-V semiconductor surface is coated with a dopant using a precursor in the form of a liquid, solid or gas.
  • the coating can be achieved through dipping coating, spraying coating, spin coating, or atomic layer deposition (ALD) or a plasma based technique, or any other suitable coating method.
  • ALD atomic layer deposition
  • the dopant is coated at monolayer or at nanometer-level in thickness.
  • the coated surface is then capped with dielectric materials, followed by annealing at a raised temperature.
  • the dopant diffuses into the III-V semiconductor surfaces.
  • such dopants have low or no solubility in a metallic metal-semiconductor compound formed in steps 505 and 508 .
  • a dopant precursor is coated onto the surface of channel 110 .
  • the MLD technique comprises at least two steps which are illustrated in FIGS. 9A-9C .
  • FIG. 9A shows a device structure in the fabrication process in the beginning of step 502 of FIG. 5A . Similar to that described in FIG. 1A , the device at this stage comprises channel layer 110 above substrate 102 . The gate stack above channel layer 110 are illustrated in details in FIG. 9A .
  • the gate stack or “gate electrode” includes gate dielectric layer 200 , gate electrode 202 , and another layer gate electrode 204 .
  • the gate stack of these three parts ( 200 , 202 , and 204 ) constitutes gate stack 120 in FIG. 1A .
  • the channel has not been recessed in the S/D regions prior to mono-layer doping.
  • a dopant layer 206 is disposed above and directly contacting with channel layer 110 .
  • the device is as illustrated in FIG. 9B .
  • the coated surface is then capped with dielectric materials 208 .
  • the device is as illustrated in FIG. 9C . After annealed at a raised temperature, a separate dopant layer 112 as illustrated in FIG. 1A is formed.
  • this MLD technique comprises one, two or multiple steps.
  • a monolayer sulfur dopant can be formed on a III-V semiconductor compound surface as follows: a MLD reactive solution as the dopant precursor comprises 20 wt % of (NH 4 ) 2 S and about 1.3 wt % of sulfur in water at 35° C. InGaAs surface is thoroughly cleaned by using HF solution followed by isopropanol. InGaAs surface is then immersed into the MLD reactive solution for 15 minutes, then rinsed in deionized water, the channel surface in the S/D region is thus covered with a thin layer of sulfur and then can be capped with dielectrics such as SiN and thermally annealed through rapid thermal anneal (RTA).
  • RTA rapid thermal anneal
  • the annealing is conducted at a high temperature, for example, at 700° C. for 30 seconds.
  • the dielectric capping layer can then be removed. This doping method is described by Barnett, et. al. for doping a NMOS junction. See 2010 Workshop on Junction Technology, 2010 IEEE, 978-4244-5869-1.
  • the S/D regions are grown using a selective epitaxial growth technique.
  • this step follows the standard procedures used for III-V semiconductor compounds.
  • FIGS. 10A-10B schematically illustrate a method of selective epitaxial growth of the source/drain (S/D) regions 212 in accordance with one embodiment.
  • the S/D regions through epitaxial growth include a thickness of about 5-200 nm according to some embodiments and is InAs in one embodiment.
  • the S/D regions are formed of InGaAs, InP, InSb or other suitable semiconductor materials.
  • dopants are optionally introduced in the grown layer as part of the epitaxial process.
  • a metal layer is deposited on the S/D regions, which comprise a III-V semiconductor compound.
  • the metal layered coated structure from step 506 is annealed at a raised temperature to form a metallic metal-semiconductor compound material of a III-V semiconductor compound.
  • FIGS. 11A-11B illustrate steps of the method of forming a metallic ternary, quaternary or quinary material in S/D regions 114 , comprising coating a layer of metal 214 followed by annealing at a raised temperature in accordance with one embodiment.
  • a metal material is nickel in some embodiments and any other suitable metal in some other embodiments.
  • Various conventional deposition methods such as sputtering, evaporation or other deposition (e.g. chemical vapor deposition CVD) methods may be used to form metal layer 214 such as nickel layer.
  • metal layer 214 such as nickel may include a thickness ranging from about 5 nm to about 200 nm. According to some embodiments, metal layer 214 will be formed to include sufficient thickness to react with all of the S/D regions.
  • a metal-semiconductor compound such as nickelide of a III-V semiconductor material is formed through annealing at high temperature.
  • the thermal annealing causes reaction to form a ternary, quaternary or quinary nickelide material.
  • the annealing operation can be a one-step operation or a multi-step operation. According to one embodiment, a two-step annealing process is used with the first step being a lower temperature step causing diffusion of the nickel metal into the underlying semiconductor material. After the first annealing step, a selective etching operation may optionally be used to remove unreacted nickel.
  • a second annealing operation of the two-step annealing operation is carried out at higher temperature and, in some embodiments, forms a thermodynamically stable ternary material that includes low resistance as described above.
  • the first step of the annealing operation may be carried out within a temperature range of 275-325° C. and the second step of the two-step annealing operation may include a temperature in the range of 325-450° C.
  • the thermal annealing technique in some embodiments described herein also provides additional benefits to cause dopant segregation in the source/drain (S/D) regions, and drives formation of a dopant layer 112 at the periphery of the S/D region 114 .
  • the dopant layer 112 may not be a distinct region of dopants but instead be a region of channel material 110 which is doped with the dopants.
  • Dopant layer (or doped region of the channel layer) 112 is above channel layer 110 .
  • dopant layer 112 directly contacts channel layer 110 .
  • Such dopant segregation effect during thermal annealing is also referred to as “snow plow effect.”
  • “snow plow effect” or dopant segregation technique in III-V semiconductors is obtained.
  • a dopant segregation technique is provided to form a dopant rich layer near the nickelide/III-V semiconductor interface to achieve a low resistance extension region and to reduce the resistance between nickelide and channel material.
  • the dopant segregation is achieved through nickel coating on a dopant-containing III-V semiconductor compound, followed by thermal annealing, in which a metallic ternary, quaternary or quinary nickelide material is also formed.
  • Examples of a metallic metal-semiconductor ternary, quaternary or quinary material include but are not limited to nickelide.
  • examples of a ternary nickelide include NiInP, NiInAs and NiInSb.
  • FIG. 5B illustrates a method of forming a device as described above in some embodiments, in which at least one dopant is introduced during growth of the S/D regions.
  • the processes steps are similar to that illustrated in FIG. 5A , except at step 504 .
  • a dopant is introduced simultaneously at the step of growing the source/drain regions through selective epitaxial growth of a III-V semiconductor compound. This doping process is referred as an in-situ doping technique.
  • such dopants have low or no solubility in a metallic ternary, quaternary or quinary phase formed after steps 506 and 508 .
  • Dopant concentration can be non-uniform in the epitaxial S/D. For example, in some embodiments, higher concentration of dopants is nearer to the channel than to the surface.
  • the dopants can be fully or partially driven close to or into the channel layer by the epitaxial growth process of step 504 and the thermal annealing of step 508 .
  • FIG. 5C illustrates a method of forming the device in some other embodiments, in which at least one dopant is introduced into the S/D regions through an ion implantation process.
  • Step 510 of ion implantation is performed after growth of the S/D regions at step 504 , and before metal coating and thermal annealing at steps 506 and 508 .
  • An ion implantation process suitable for III-V semiconductor compound can be used. Typical ion implant beam energies would be 20-100 KeV with beam fluence 1E14-1E16 cm 2 .
  • FIGS. 6A-6C are flow chart diagrams illustrating methods of fabricating the exemplary CMOS devices with recess of the source/drain (S/D) region.
  • FIGS. 6A-6C are similar to those in FIGS. 5A-5C , respectively, except that a process of recessing the channel layer, step 610 , is added in each method.
  • FIGS. 8A-8B schematically illustrate such a method of recessing the channel layer 110 through etching in accordance with one embodiment.
  • a gate stack structure including dielectric layer 200 , gate electrode 202 and another gate layer 204 is disposed over a first portion of channel layer 110 .
  • a spacer is disposed along a side-wall of the gate stack structure.
  • the “recessing” process comprises at least one step as illustrated in FIG. 8A-8B .
  • the device in the fabrication process is as shown in FIG. 8A .
  • step 610 a second portion of channel layer 110 are so etched using standard processing techniques that a portion of the source/drain regions is below a bottom height of the spacer 118 .
  • the configuration is as shown in FIG. 8B .
  • FIGS. 7A-7B are flow chart diagrams illustrating methods of fabricating an exemplary CMOS device without epitaxial growth of the source/drain (S/D) region in accordance with some embodiments.
  • the S/D regions are disposed above the channel layer 110 , which comprise a III-V semiconductor compound.
  • At least one dopant is introduced into the S/D regions through a technique of monolayer doping (step 502 ) or ion implantation (step 510 ).
  • the channel layer for NMOS is In x Ga (1-x) As with x>0.7 although other suitable binary or ternary NMOS channel materials may be used in other embodiments.
  • NMOS channel material is InAs.
  • metal in step 506 is nickel.
  • the ternary material at step 508 is NiInAs. Dopant layer is driven toward the channel layer so that it will be close to or directly contact with the channel layer thorough snow plow effect described above.
  • a III-V compound semiconductor device and a method of making the same are provided to reduce external/extrinsic resistance and resistance in the S/D extension region.
  • a semiconductor device comprises a semiconductor substrate; a channel layer of at least one III-V semiconductor compound above the semiconductor substrate; a gate electrode above a first portion of the channel layer; a source region and a drain region above a second portion of the channel layer; and a dopant layer comprising at least one dopant contacting the second portion of the channel layer.
  • the dopant layer comprising at least one dopant directly contacting at least one portion of the channel layer provides low contact resistance in either a PMOS or NMOS device.
  • the S/D region in a PMOS or NMOS device comprises a metal-III-V semiconductor ternary material with low resistivity and which is thermodynamically stable when contacting semiconductor materials.
  • the metallic ternary material is a nickelide of a III-V semiconductor compound.
  • a semiconductor device comprises a spacer which is disposed along a side wall of the gate electrode. In some embodiments, a portion of the dopant layer is underneath the spacer. In some other embodiments, the channel layer or the source/drain regions are recessed so that a portion of the S/D regions is below a bottom height of the spacer.
  • the disclosed semiconductor device is an NMOS transistor, and the channel layer is InxGa(1-x)As, with x>0.7.
  • the dopant is selected from the group consisting of sulfur and silicon.
  • the semiconductor device is a PMOS transistor, and the channel layer is InyGa(1-y)As, with 0 ⁇ y ⁇ 1.
  • the dopant is carbon or other suitable materials.
  • a method for forming such a semiconductor device comprises: providing a channel layer of at least one III-V semiconductor compound above a semiconductor substrate; forming a gate electrode above a first portion of the channel layer; providing a dopant layer comprising at least one dopant contacting the channel layer; and forming a source region and a drain region above a second portion of the channel layer.
  • the step of providing the dopant layer includes forming the dopant layer above the channel layer and below the source or the drain (S/D) region.
  • the dopant layer is formed through a process selected from the group consisting of a monolayer doping process, an in-situ doping process and an ion implantation process as described in this disclosure.
  • a monolayer doping process or an ion implantation process at least one dopant can be introduced into the S/D regions.
  • an in-situ doping process at least one dopant is introduced during the step of forming the S/D regions.
  • a method of forming the disclosed semiconductor further comprises forming a metallic ternary material with a III-V semiconductor compound in the source region and the drain region.
  • the step of forming a metallic ternary material comprises a step of depositing a metal layer on the semiconductor compound in the source region and the drain region, followed by a step of annealing at a raised temperature.
  • the metal is nickel, which forms a ternary nickelide of III-V semiconductor compound.
  • the disclosed method comprises disposing a spacer along a side wall of the gate electrode. In some embodiments, the method further comprises a step of recessing the channel layer before providing the dopant layer comprising at least one dopant contacting the channel layer.
  • the disclosed method comprises a step of forming the source region and the drain region above the second portion of the channel layer comprises disposing a portion of the source region and the drain region below a bottom height of the spacer.
  • the dopant is driven toward the channel layer to form a dopant-rich layer through dopant segregation effect or “snow plow effect,” as described above.
  • the dopant-rich layer is close to or directly contact with the channel layer.
  • the S/D regions are grown or regrown thorough a selective epitaxial growth technique. In some other embodiments, the S/D regions are grown without using a selective epitaxial growth technique.
  • a method for forming a NMOS semiconductor device in which no selective epitaxial growth of the S/D regions is used.

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130234205A1 (en) * 2012-03-07 2013-09-12 Taiwan Semiconductor Manufacturing Co. Ltd. Nickelide source/drain structures for cmos transistors
US20140361378A1 (en) * 2013-06-07 2014-12-11 Dong-Kyu Lee Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same
US20150054031A1 (en) * 2011-12-20 2015-02-26 Intel Corporation Tin doped iii-v material contacts
US9054186B2 (en) 2012-07-06 2015-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having metal contacts and method of making the same
WO2015099688A1 (en) * 2013-12-23 2015-07-02 Intel Corporation Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof
US9252237B2 (en) 2012-05-09 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors, semiconductor devices, and methods of manufacture thereof
US9627410B2 (en) 2015-05-21 2017-04-18 International Business Machines Corporation Metallized junction FinFET structures
US9647091B2 (en) 2015-05-01 2017-05-09 International Business Machines Corporation Annealed metal source drain overlapping the gate
US9705000B2 (en) 2011-12-20 2017-07-11 Intel Corporation III-V layers for n-type and p-type MOS source-drain contacts
US20170236936A1 (en) * 2013-12-23 2017-08-17 Intel Corporation Wide band gap transistor on non-native semiconductor substrates and methods of manufacture thereof
US20190189515A1 (en) * 2017-12-15 2019-06-20 Micron Technology, Inc. Methods Of Forming A Transistor And Methods Of Forming An Array Of Memory Cells

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160137977A (ko) * 2014-03-28 2016-12-02 인텔 코포레이션 선택적 에피택셜 성장된 iii-v족 재료 기반 디바이스
US9812323B2 (en) 2014-09-08 2017-11-07 Internaitonal Business Machines Corporation Low external resistance channels in III-V semiconductor devices
US9972711B2 (en) 2015-06-03 2018-05-15 International Business Machines Corporation Reduced resistance short-channel InGaAs planar MOSFET
US9355914B1 (en) 2015-06-22 2016-05-31 International Business Machines Corporation Integrated circuit having dual material CMOS integration and method to fabricate same
US9437614B1 (en) 2015-09-18 2016-09-06 International Business Machines Corporation Dual-semiconductor complementary metal-oxide-semiconductor device
CN108346697A (zh) * 2017-01-23 2018-07-31 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157208A1 (en) * 2006-12-29 2008-07-03 Fischer Kevin J Stressed barrier plug slot contact structure for transistor performance enhancement
US20100301392A1 (en) * 2009-06-01 2010-12-02 Chih-Hsin Ko Source/Drain Re-Growth for Manufacturing III-V Based Transistors
US20120012903A1 (en) * 2010-07-14 2012-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making a disilicide
US20120187505A1 (en) * 2011-01-25 2012-07-26 International Business Machines Corporation Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation
US20120256238A1 (en) * 2011-04-06 2012-10-11 International Business Machines Corporation Junction Field Effect Transistor With An Epitaxially Grown Gate Structure
US20130200443A1 (en) * 2012-02-08 2013-08-08 International Business Machines Corporation Interface Engineering to Optimize Metal-III-V Contacts

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5606184A (en) 1995-05-04 1997-02-25 Motorola, Inc. Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making
JPH09172165A (ja) * 1995-12-20 1997-06-30 Nec Corp 電界効果トランジスタおよびその製造方法
US5942773A (en) 1996-06-04 1999-08-24 Fujitsu Limited Field effect transistor with reduced delay variation
JP3290900B2 (ja) * 1996-06-04 2002-06-10 富士通株式会社 電界効果型トランジスタ、半導体集積回路装置および電界効果型トランジスタの製造方法
JP2000277533A (ja) * 1999-03-23 2000-10-06 Sanyo Electric Co Ltd 化合物半導体装置及びその製造方法
JP2001308319A (ja) 2000-04-20 2001-11-02 Fujitsu Ltd 絶縁ゲート型化合物半導体装置
US7045404B2 (en) 2004-01-16 2006-05-16 Cree, Inc. Nitride-based transistors with a protective layer and a low-damage recess and methods of fabrication thereof
JP2006054423A (ja) 2004-07-13 2006-02-23 Toshiba Corp 半導体装置及びその製造方法
US7320921B2 (en) * 2005-03-22 2008-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Smart grading implant with diffusion retarding implant for making integrated circuit chips
WO2007011789A1 (en) 2005-07-15 2007-01-25 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions and associated methods
KR20070114463A (ko) 2006-05-29 2007-12-04 주식회사 하이닉스반도체 자기 정렬 콘택 플러그를 구비한 반도체 소자 및 그제조방법
KR101026479B1 (ko) 2006-12-28 2011-04-01 주식회사 하이닉스반도체 반도체 소자 및 그의 제조 방법
US7569869B2 (en) 2007-03-29 2009-08-04 Intel Corporation Transistor having tensile strained channel and system including same
US7776698B2 (en) * 2007-10-05 2010-08-17 Applied Materials, Inc. Selective formation of silicon carbon epitaxial layer
US20110068348A1 (en) 2009-09-18 2011-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thin body mosfet with conducting surface channel extensions and gate-controlled channel sidewalls
JP5499319B2 (ja) 2009-11-10 2014-05-21 国立大学法人 東京大学 半導体デバイス及びその製造方法
US8936976B2 (en) 2009-12-23 2015-01-20 Intel Corporation Conductivity improvements for III-V semiconductor devices
US8461664B2 (en) 2010-06-02 2013-06-11 The United States Of America, As Represented By The Secretary Of The Navy N- and p-channel field-effect transistors with single quantum well for complementary circuits
US8697467B2 (en) * 2010-07-26 2014-04-15 The Regents Of The University Of California Surface and gas phase doping of III-V semiconductors
JP5559639B2 (ja) 2010-08-25 2014-07-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8053344B1 (en) * 2010-09-21 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuits
WO2013095377A1 (en) 2011-12-20 2013-06-27 Intel Corporation Self-aligned contact metallization for reduced contact resistance
US8765586B2 (en) 2011-12-20 2014-07-01 Globalfoundries Inc. Methods of forming metal silicide regions on semiconductor devices
US9680027B2 (en) 2012-03-07 2017-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Nickelide source/drain structures for CMOS transistors
US8866195B2 (en) 2012-07-06 2014-10-21 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having metal contacts and method of making the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080157208A1 (en) * 2006-12-29 2008-07-03 Fischer Kevin J Stressed barrier plug slot contact structure for transistor performance enhancement
US20100301392A1 (en) * 2009-06-01 2010-12-02 Chih-Hsin Ko Source/Drain Re-Growth for Manufacturing III-V Based Transistors
US20120012903A1 (en) * 2010-07-14 2012-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method for making a disilicide
US20120187505A1 (en) * 2011-01-25 2012-07-26 International Business Machines Corporation Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation
US20120256238A1 (en) * 2011-04-06 2012-10-11 International Business Machines Corporation Junction Field Effect Transistor With An Epitaxially Grown Gate Structure
US20130200443A1 (en) * 2012-02-08 2013-08-08 International Business Machines Corporation Interface Engineering to Optimize Metal-III-V Contacts

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9966440B2 (en) * 2011-12-20 2018-05-08 Intel Corporation Tin doped III-V material contacts
US20150054031A1 (en) * 2011-12-20 2015-02-26 Intel Corporation Tin doped iii-v material contacts
US9705000B2 (en) 2011-12-20 2017-07-11 Intel Corporation III-V layers for n-type and p-type MOS source-drain contacts
US9680027B2 (en) * 2012-03-07 2017-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Nickelide source/drain structures for CMOS transistors
US20130234205A1 (en) * 2012-03-07 2013-09-12 Taiwan Semiconductor Manufacturing Co. Ltd. Nickelide source/drain structures for cmos transistors
US9406791B2 (en) 2012-05-09 2016-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors, semiconductor devices, and methods of manufacture thereof
US9252237B2 (en) 2012-05-09 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors, semiconductor devices, and methods of manufacture thereof
US9391153B2 (en) 2012-07-06 2016-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having metal contacts and method of making the same
US9054186B2 (en) 2012-07-06 2015-06-09 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having metal contacts and method of making the same
US20140361378A1 (en) * 2013-06-07 2014-12-11 Dong-Kyu Lee Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same
US9425198B2 (en) * 2013-06-07 2016-08-23 Samsung Electronics Co., Ltd. Semiconductor device having strain-relaxed buffer layer and method of manufacturing the same
KR20160100925A (ko) * 2013-12-23 2016-08-24 인텔 코포레이션 비고유 반도체 기판들 상의 넓은 밴드 갭 트랜지스터들 및 그 제조 방법들
KR102167518B1 (ko) * 2013-12-23 2020-10-19 인텔 코포레이션 비고유 반도체 기판들 상의 넓은 밴드 갭 트랜지스터들 및 그 제조 방법들
US10580895B2 (en) 2013-12-23 2020-03-03 Intel Corporation Wide band gap transistors on non-native semiconductor substrates
US9660085B2 (en) 2013-12-23 2017-05-23 Intel Coporation Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof
WO2015099688A1 (en) * 2013-12-23 2015-07-02 Intel Corporation Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof
US20170236936A1 (en) * 2013-12-23 2017-08-17 Intel Corporation Wide band gap transistor on non-native semiconductor substrates and methods of manufacture thereof
US10032911B2 (en) * 2013-12-23 2018-07-24 Intel Corporation Wide band gap transistor on non-native semiconductor substrate
US9647091B2 (en) 2015-05-01 2017-05-09 International Business Machines Corporation Annealed metal source drain overlapping the gate
US9935200B2 (en) 2015-05-01 2018-04-03 International Business Machines Corporation Annealed metal source drain overlapping the gate of a fin field effect transistor
US10192888B2 (en) 2015-05-21 2019-01-29 International Business Machines Corporation Metallized junction FinFET structures
US9634028B2 (en) 2015-05-21 2017-04-25 International Business Machines Corporation Metallized junction FinFET structures
US9627410B2 (en) 2015-05-21 2017-04-18 International Business Machines Corporation Metallized junction FinFET structures
US20190189515A1 (en) * 2017-12-15 2019-06-20 Micron Technology, Inc. Methods Of Forming A Transistor And Methods Of Forming An Array Of Memory Cells
US10643906B2 (en) * 2017-12-15 2020-05-05 Micron Technology, Inc. Methods of forming a transistor and methods of forming an array of memory cells

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