US20130075268A1 - Methods of Forming Through-Substrate Vias - Google Patents

Methods of Forming Through-Substrate Vias Download PDF

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Publication number
US20130075268A1
US20130075268A1 US13/247,769 US201113247769A US2013075268A1 US 20130075268 A1 US20130075268 A1 US 20130075268A1 US 201113247769 A US201113247769 A US 201113247769A US 2013075268 A1 US2013075268 A1 US 2013075268A1
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copper
substrate
substrate via
via openings
alloy
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US13/247,769
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English (en)
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Luke G. England
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US Bank NA
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Micron Technology Inc
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Assigned to MICRON TECHNOLOGY, INC reassignment MICRON TECHNOLOGY, INC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ENGLAND, LUKE G.
Priority to US13/247,769 priority Critical patent/US20130075268A1/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to JP2014533547A priority patent/JP5921696B2/ja
Priority to KR1020147010132A priority patent/KR101611108B1/ko
Priority to CN201280045165.XA priority patent/CN103797566B/zh
Priority to PCT/US2012/053792 priority patent/WO2013048685A1/en
Priority to EP12836871.9A priority patent/EP2761646B1/de
Priority to TW101134975A priority patent/TWI469258B/zh
Publication of US20130075268A1 publication Critical patent/US20130075268A1/en
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
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Assigned to JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT reassignment JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON SEMICONDUCTOR PRODUCTS, INC., MICRON TECHNOLOGY, INC.
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Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Assigned to MICRON TECHNOLOGY, INC., MICRON SEMICONDUCTOR PRODUCTS, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • C25D5/50—After-treatment of electroplated surfaces by heat-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1194—Thermal treatment leading to a different chemical state of a material, e.g. annealing for stress-relief, aging

Definitions

  • Embodiments disclosed herein pertain to methods of forming through-substrate vias.
  • a through-substrate via is a vertical electrical connection passing completely through a substrate comprising integrated circuitry.
  • Through-substrate vias may be used to create 3D packages in 3D integrated circuits and are an improvement over other techniques such as package-on-package because the density of through-substrate vias may be substantially higher.
  • Through-substrate vias provide interconnection of vertically aligned electronic devices through internal wiring that significantly reduces complexity and overall dimensions of a multi-chip electronic circuit.
  • Common through-substrate via processes include formation of through-substrate via openings through most, but not all, of the thickness of the substrate.
  • a thin dielectric liner is then deposited to electrically insulate sidewalls of the through-substrate via openings.
  • Adhesion and/or diffusion barrier material(s) may be deposited to line over the dielectric.
  • the through-substrate via openings are then filled with conductive material. Substrate material is removed from the opposite side of the substrate from which the via openings were formed to expose the conductive material within the via openings.
  • One highly desirable conductive through-substrate via material is elemental copper that is deposited by electrodeposition. Copper may be formed by initially depositing a seed layer within the through-substrate via openings followed by electrodepositing elemental copper from an electroplating solution.
  • An example copper electroplating solution includes copper sulfate as a source of copper ions, sulfuric acid for controlling conductivity, and copper chloride for nucleation of suppressor molecules.
  • FIG. 1 is a diagrammatic sectional view of a substrate fragment in process in accordance with an embodiment of the invention.
  • FIG. 2 is view of the FIG. 1 substrate fragment at a processing stage subsequent to that of FIG. 1 .
  • FIG. 3 is view of the FIG. 2 substrate fragment at a processing stage subsequent to that of FIG. 2 .
  • FIG. 4 is view of the FIG. 3 substrate fragment at a processing stage subsequent to that of FIG. 3 .
  • FIG. 5 is view of the FIG. 4 substrate fragment at a processing stage subsequent to that of FIG. 4 .
  • FIG. 6 is view of the FIG. 5 substrate fragment at a processing stage subsequent to that of FIG. 5 .
  • FIG. 7 is a diagrammatic sectional view of a substrate fragment in process in accordance with an embodiment of the invention.
  • FIG. 8 is a diagrammatic sectional view of a substrate fragment in process in accordance with an embodiment of the invention.
  • FIG. 9 is view of the FIG. 8 substrate fragment at a processing stage subsequent to that of FIG. 8 .
  • FIG. 10 is view of the FIG. 9 substrate fragment at a processing stage subsequent to that of FIG. 9 .
  • FIG. 11 is view of the FIG. 10 substrate fragment at a processing stage subsequent to that of FIG. 10 .
  • FIG. 12 is view of the FIG. 11 substrate fragment at a processing stage subsequent to that of FIG. 11 .
  • Embodiments of the invention encompass methods of forming through-substrate vias and include separately electrodepositing copper and at least one element other than copper to fill remaining volume of through-substrate via openings that are formed within a substrate.
  • the electrodeposited copper and the at least one other element are annealed to form an alloy of the copper and the at least one other element which is used in forming conductive through-substrate via structures comprising the alloy.
  • Initial example embodiments are described with reference to FIGS. 1-6 .
  • a substrate fragment 10 comprises substrate material 12 having opposing sides 16 and 18 .
  • Material 12 would likely be non-homogenous having multiple materials, regions, layers and structures constituting part of integrated circuitry that has been fabricated or is in the process of being fabricated.
  • substrate side 16 is referred to herein as a first side of substrate 12 and substrate side 18 is referred to as a second side of substrate 12 .
  • Through-substrate via openings 20 have been formed into substrate 12 .
  • openings 20 extend partially through substrate 12 and are formed from first substrate side 16 .
  • through-substrate via openings 20 may extend completely through substrate material 12 and/or may be formed from second substrate side 16 .
  • through-substrate via openings 20 may be formed by chemical and/or physical means, with chemical etching, drilling, and laser ablation being a few examples.
  • Substrate material 12 may comprise silicon.
  • Through-substrate vias have also been referred to in the art as through silicon vias (TSVs).
  • TSVs through silicon vias
  • through-substrate vias encompass or are generic to through-silicon vias, and through-substrate vias include conductive vias extending through substrate material regardless of whether any of that material is silicon.
  • dielectric 22 Such may be homogenous or non-homogenous, with silicon dioxide and/or silicon nitride being examples.
  • a conductive seed material lining 24 has been formed laterally over dielectric 22 within through-substrate via openings 20 .
  • Such may be homogenous or non-homogenous, with copper being an example.
  • Copper diffusion barrier material(s) (not shown) may be provided between conductive seed material 24 and dielectric 22 .
  • Such may be homogenous or non-homogenous, with tantalum, tantalum/tungsten, tantalum nitride, or other materials capable of functioning as a barrier to copper migration.
  • the diffusion barrier material may be dielectric or conductive, and if conductive may function as or constitute part of seed material 24 .
  • a metal lining 26 has been formed within respective through-substrate via openings 20 by electrodepositing one of copper or an element other than copper.
  • the electrodepositing technique used can be any existing or yet-to-be-developed electrodepositing technique(s).
  • Substrate 10 might have previously been masked (not shown) such that metal lining 26 is electrodeposited as isolated metal linings within through-substrate via openings 20 (i.e., not being continuous between any separate openings 20 ).
  • Metal lining 26 may be homogenous or non-homogenous comprising more than one element other than copper, and may be in elemental and/or alloy forms. Example elements other than copper include zinc, tin, and nickel. Regardless, in one embodiment, metal lining 26 may be considered as forming an outwardly open void 27 within the respective through-substrate via openings 20 .
  • the other 28 of the copper or other element has been electrodeposited to fill voids 27 .
  • the electrodeposited copper and at least one other element have been annealed to form an alloy 30 of the copper and the at least one other element.
  • Seed material 24 (not shown) may inherently form part of alloy 30 (as shown).
  • Alloy 30 may be homogenous or non-homogenous.
  • the alloy may have more or less copper than other element(s).
  • zinc is another element, the alloy has more copper than zinc.
  • zinc may be present at from about 0.5% to 25% by weight which targets the alpha phase range in the copper-zinc phase diagram so the metals are in solid solution with one another.
  • the quantity of copper and other element in an alloy may be determined by the quantity of electrodeposited material 26 and 28 within through-substrate via openings 20 .
  • the starting pre-anneal thickness of the metal(s) other than copper may be varied with via opening diameter to achieve a targeted final alloy composition.
  • a large diameter via opening with more copper may use a thicker other element(s) layer prior to the annealing to achieve the targeted alloy composition in comparison to a via opening of smaller diameter.
  • the annealing is conducted in an inert atmosphere. In one embodiment the annealing is conducted at a temperature of from about 150° C. to 450° C. for from about 0.5 hour to about 3 hours, although sufficient annealing may occur in much less time. Atmospheric, subatmospheric, or pressures higher than atmospheric may be used. The annealing may be a dedicated anneal for purposes of forming the alloy or may occur in conjunction with other thermal processing of the substrate.
  • substrate material 12 has been removed from second substrate side 18 to expose and project conductive through-substrate via structures 32 comprising alloy 30 from second substrate side 18 .
  • Such removal may be conducted by any suitable technique and is not material to embodiments of the invention.
  • Materials 30 , 24 , and 22 may be removed from substrate side 16 as shown.
  • Subsequent processing (not shown) may occur to complete a desired structure and circuit, for example where at least some of dielectric material 22 projecting from substrate side 18 is removed.
  • the copper may be electrodeposited first and the one other element or elements electrodeposited to fill the voids.
  • the one other element or elements may be electrodeposited first and the copper electrodeposited to fill the voids.
  • the outwardly opening voids and the filled voids may be centered radially within through-substrate via openings 20 .
  • all conductive material within through-substrate via openings 20 consists essentially of alloy 30 , but for any conductive copper diffusion barrier material (not shown) that might be present radially outward of said alloy, and independent of whether the filled voids are centered radially within the through-substrate via openings.
  • the first electrodeposited material 26 and the second electrodeposited material 28 may be of the same lateral thickness (not shown) or of different lateral thicknesses (as shown). If of different thicknesses, either may be thicker than the other.
  • the embodiments of FIG. 4 shows first electrodeposited material 26 to be thinner than second electrodeposited material 28 . Where in an ideal embodiment greater quantity of copper is desired, the electrodeposited copper will be laterally thicker than the electrodeposited other element(s).
  • FIG. 7 depicts an alternate embodiment substrate fragment 10 a wherein a first electrodeposited material 26 a has been deposited to a greater lateral thickness than second electrodeposited material 28 a . Like numerals from the first described embodiment have been used where appropriate, with some construction differences being indicated with the suffix “a”.
  • the separate electrodepositings may be of copper and only one other element or of copper and multiple elements other than copper.
  • the alloy consists essentially of copper and zinc, copper and tin, or copper and nickel.
  • the total number of electrodepositings may be two or more than two.
  • FIGS. 4 and 7 embodiments depict only two electrodepositings which fill the remaining volume of through-substrate via openings 20 prior to conducting the annealing.
  • An alternate embodiment comprising a total of more than two electrodepositing is next described with reference to FIGS. 8-12 with respect to a substrate fragment 10 b .
  • Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “b” or with different numerals.
  • a first metal lining 26 b has been formed by electrodepositing one of copper or an element other than copper within respective through-substrate via openings 20 .
  • First metal lining 26 b is formed laterally inward of and may be formed directly against a conductive seed material 24 formed over sidewalls of the respective through-substrate via openings 20 .
  • a material or structure is “directly against” another when there is at least some physical touching contact of the stated materials or structures relative one another.
  • “over” encompasses “directly against” as well as constructions where intervening material(s) or structure(s) result(s) in no physical touching contact of the stated materials or structures relative one another.
  • First metal lining 26 b forms an outwardly open first void 40 within the respective through-substrate via openings 20 (e.g., which may be the same as a void 27 / 27 a in the first-described embodiments).
  • a second metal lining 28 b has been formed within the respective through-substrate via openings 20 by electrodepositing the other of the copper or other element.
  • Second metal lining 28 b is formed laterally inward of and may be directly against first metal lining 26 b , and forms an outwardly open second void 42 within the respective through-substrate via openings 20 .
  • Second metal lining 28 b and first metal lining 26 b may be of the same thickness (not shown) or of different thicknesses (as shown), with either being capable of being processed to be thicker than the other.
  • second voids 42 are ultimately filled with electrodeposited metal.
  • the substrate is then annealed to form an alloy containing at least copper and the other metal which is ultimately used in forming conductive through-substrate via structures comprising the alloy. Such may occur by conducting one more electrodeposition or more than one more electrodeposition.
  • the one of the copper or other element of first metal lining 26 b has been electrodeposited to form a third metal lining 44 within the respective through-substrate via openings 20 .
  • Third metal lining 44 is formed laterally inward of and may be directly against second metal lining 28 b , and forms an outwardly open third void 46 within the respective through-substrate via openings 20 .
  • Third metal lining 44 may comprise a metal other than those of first metal lining 26 b and second metal lining 28 b .
  • third metal lining 44 may comprise the same metal as one or more of those of first metal lining 26 b and/or second metal lining 28 b .
  • Third metal lining 44 and second metal lining 28 b may be of the same thickness (not shown) or of different thicknesses (as shown), and lining 44 may be of the same thickness (as shown) or of different thickness (not shown) as first metal lining 26 . Regardless, third voids 46 are ultimately filled with electrodeposited metal. Such may occur by conducting one more electrodeposition or more than one more electrodeposition.
  • fourth metal lining 48 is formed laterally inward of and may be directly against third metal lining 44 , and forms an outwardly open fourth void 50 within the respective through-substrate via openings 20 .
  • Fourth metal lining 48 may comprise a metal other than those of first metal lining 26 b , second metal lining 28 b , and third metal lining 44 .
  • fourth metal lining 48 may comprise the same metal as one or more of those of first metal lining 26 b , second metal lining 28 b , and/or third metal lining 44 .
  • Fourth metal lining 48 and third metal lining 44 may be of the same thickness (not shown) or of different thicknesses (as shown), and lining 48 may be of the same thickness (as shown) or of different thickness (not shown) as first metal lining 26 .
  • fourth voids 50 are ultimately filled with electrodeposited metal. Such may occur by conducting one more electrodeposition or more than one more electrodeposition, for example as shown in FIG. 12 with one additional electrodepositing, for example of the one of the copper or an element other than copper. Alternate and/or additional attributes and subsequent processing may also occur as described above.
  • the alloy consists essentially of copper and such other element.
  • Each of the above embodiments are but examples of methods of forming through-substrate vias.
  • Such methods encompass separately electrodepositing copper and at least one element other than copper to fill remaining volume of through-substrate via openings that have been formed within a substrate.
  • the electrodeposited copper and the at least one other element are annealed to form an alloy of the copper and the at least one element which ultimately forms conductive through-substrate via structures which comprise the alloy.
  • Two or more electrodepositings may be conducted wherein a first of the separate electrodepositings is of copper or where the first of the separate electrodepositings is of an element other than copper.
  • embodiments of the invention also encompass the last of the separate electrodepositings being of copper, or the last of the separate electrodepositings being of an element other than copper.
  • methods of forming through-substrate vias comprise separately electrodepositing copper and at least one element other than copper to fill remaining volume of through-substrate via openings formed within a substrate.
  • the electrodeposited copper and the at least one other element are annealed to form an alloy of the copper and the at least one other element, and which is used in forming conductive through-substrate via structures comprising the alloy.
  • methods of forming through-substrate vias comprise forming through-substrate via openings partially through a substrate from a first side of the substrate. Sidewalls of the through-substrate via openings are lined with dielectric. Conductive seed material is lined laterally over the dielectric within the through-substrate via openings. Copper and at least one element other than copper are separately electrodeposited to fill remaining volume of the through-substrate via openings. The electrodeposited copper and the at least one other element are annealed to form an alloy of the copper and the at least one other element. After the annealing, substrate material is removed from a second side of the substrate opposite the first side to expose and project conductive through-substrate via structures comprising the alloy from the second side of the substrate.
  • methods of forming through-substrate vias comprise electrodepositing one of copper or one element other than copper to form a metal lining within respective through-substrate via openings formed within a substrate.
  • the metal lining forms an outwardly open void within the respective through-substrate via openings.
  • the other of the copper or one element is electrodeposited to fill the voids.
  • the electrodeposited copper and one element are annealed to form an alloy of the copper and one element, and which is used in forming conductive through-substrate via structures comprising the alloy.
  • methods of forming through-substrate vias comprise electrodepositing one of copper or an element other than copper to form a first metal lining within respective through-substrate via openings formed within a substrate.
  • the first metal lining is formed laterally inward of and directly against a conductive seed material formed over sidewalls of the respective through-substrate via openings.
  • the first metal lining forms an outwardly open first void within the respective through-substrate via openings.
  • the other of the copper or other element is electrodeposited to form a second metal lining within the respective through-substrate via openings.
  • the second metal lining is formed laterally inward of and directly against the first metal lining.
  • the second metal lining forms an outwardly open second void within the respective through-substrate via openings.
  • the second voids are filled with electrodeposited metal.
  • the substrate is annealed to form an alloy containing at least copper and the other element, and which is used in forming conductive through-substrate via structures comprising the alloy.

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  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
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  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Physical Vapour Deposition (AREA)
US13/247,769 2011-09-28 2011-09-28 Methods of Forming Through-Substrate Vias Abandoned US20130075268A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US13/247,769 US20130075268A1 (en) 2011-09-28 2011-09-28 Methods of Forming Through-Substrate Vias
JP2014533547A JP5921696B2 (ja) 2011-09-28 2012-09-05 スルー基板ビアの形成方法
KR1020147010132A KR101611108B1 (ko) 2011-09-28 2012-09-05 관통 기판 비아들을 형성하는 방법들
CN201280045165.XA CN103797566B (zh) 2011-09-28 2012-09-05 形成贯穿衬底的导通体的方法
PCT/US2012/053792 WO2013048685A1 (en) 2011-09-28 2012-09-05 Methods of forming through-substrate vias
EP12836871.9A EP2761646B1 (de) 2011-09-28 2012-09-05 Verfahren zur herstellung von substratdurchgängen
TW101134975A TWI469258B (zh) 2011-09-28 2012-09-24 形成貫穿基板之通道的方法

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US13/247,769 US20130075268A1 (en) 2011-09-28 2011-09-28 Methods of Forming Through-Substrate Vias

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EP (1) EP2761646B1 (de)
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TW (1) TWI469258B (de)
WO (1) WO2013048685A1 (de)

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CN106163104A (zh) * 2016-08-30 2016-11-23 江门全合精密电子有限公司 一种采用防漏锡过孔的印刷电路板及其制作方法
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CN111163582A (zh) * 2020-01-02 2020-05-15 上海航天电子通讯设备研究所 一种基于激光纳米加工技术的垂直互连基板及其制造方法
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EP2761646A4 (de) 2015-08-12
KR20140070604A (ko) 2014-06-10
CN103797566A (zh) 2014-05-14
JP2014528180A (ja) 2014-10-23
TW201320243A (zh) 2013-05-16
TWI469258B (zh) 2015-01-11
CN103797566B (zh) 2018-06-15
KR101611108B1 (ko) 2016-04-08
JP5921696B2 (ja) 2016-05-24
EP2761646B1 (de) 2018-02-28
WO2013048685A1 (en) 2013-04-04

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