US20120307097A1 - Solid-state image sensor - Google Patents

Solid-state image sensor Download PDF

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Publication number
US20120307097A1
US20120307097A1 US13/477,456 US201213477456A US2012307097A1 US 20120307097 A1 US20120307097 A1 US 20120307097A1 US 201213477456 A US201213477456 A US 201213477456A US 2012307097 A1 US2012307097 A1 US 2012307097A1
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US
United States
Prior art keywords
capacitance element
switch
terminal
image sensor
solid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/477,456
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English (en)
Inventor
Yukio Araoka
Satoru Shingai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Assigned to CANON KABUSHIKI KAISHA reassignment CANON KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ARAOKA, YUKIO, Shingai, Satoru
Publication of US20120307097A1 publication Critical patent/US20120307097A1/en
Priority to US14/217,919 priority Critical patent/US8902342B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/667—Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present invention relates to a solid-state image sensor.
  • the solid-state image sensor 1 comprises a pixel array 10 including a plurality of pixel units 11 , and a signal processing circuit 20 for amplifying a signal output from the pixel array 10 to a column signal line 2 .
  • a transfer transistor TX transfers, for example, charges generated by the energy of light received by a photodiode PD to the gate of a source follower transistor SF. Then, the source follower transistor SF outputs a signal corresponding to the transferred charges to the column signal line 2 via a selection transistor SEL.
  • Each pixel unit 11 can include a reset transistor RES for resetting the potential of the gate of the source follower transistor SF to a predetermined voltage.
  • the signal processing circuit 20 is used to amplify the signal output from each pixel unit 11 to the column signal line 2 .
  • the signal processing circuit 20 includes an operation amplifier 21 having an input terminal 22 and an output terminal 23 , an input capacitance C 0 inserted between the input terminal 22 and the column signal line 2 , and a feedback capacitor Cf connecting the input terminal 22 to the output terminal 23 .
  • the amplification factor of the signal processing circuit 20 is determined based on a capacitance ratio C 0 /Cf. To change the amplification factor, for example, to switch the sensitivity setting of a digital still camera, it is only necessary to change the ratio C 0 /Cf. To change the amplification factor from, for example, 32 to 128, it is only necessary to increase the value of C 0 by a factor of four or decrease the value of Cf to a quarter.
  • a high amplification factor is required for the signal processing circuit 20 . This especially applies to a case in which a signal output to the column signal line 2 becomes very weak due to the reduction in the size of a photoelectric conversion element such as the photodiode PD or a case in which the sensitivity of a camera having the solid-state image sensor 1 is set to be higher.
  • To increase the amplification factor of the signal processing circuit 20 it is generally necessary (1) to increase the value of C 0 , (2) to decrease the value of Cf, or (3) to increase the value of C 0 and decrease the value of Cf.
  • increasing the capacitance value may cause an increase in chip area, and decreasing the capacitance value may cause a production variation.
  • the present invention provides a technique which is advantageous in increasing an amplification factor while suppressing an increase in chip area and a production variation.
  • One of the aspects of the present invention provides a solid-state image sensor comprising a pixel array having a plurality of pixels, and a plurality of signal processing circuits each of the plurality of signal processing circuits amplifying a signal output from the pixel array to a plurality of column signal lines, wherein each of the plurality of signal processing circuits comprises an operation amplifier which has an input terminal and an output terminal, an input capacitance arranged between the input terminal and the column signal line, and a feedback circuit which connects the input terminal with the output terminal, wherein the feedback circuit is configured to form a feedback path in which a first capacitance element and a second capacitance element are arranged in series in a path connecting the input terminal to the output terminal, and a third capacitance element is arranged between a reference potential and a path connecting the first capacitance element to the second capacitance element.
  • FIG. 1 is a circuit diagram for explaining a solid-state image sensor according to the prior art
  • FIG. 2 is a circuit diagram showing an example of a solid-state image sensor for explaining the present invention
  • FIG. 3 is a graph showing an amplification variation for explaining the effects of the present invention.
  • FIG. 4 is a circuit diagram showing an example of a solid-state image sensor for explaining the present invention.
  • FIG. 5 is a circuit diagram showing an example of a solid-state image sensor for explaining the present invention.
  • FIG. 6 is a circuit diagram showing an example of a signal processing circuit to which the present invention is applied.
  • a signal processing circuit includes an operation amplifier having an input terminal and an output terminal, an input capacitance arranged between the input terminal and a column signal line, and a feedback circuit for connecting the input terminal with the output terminal.
  • the feedback circuit has an arrangement in which a first capacitance element Cf 1 and a second capacitance element Cf 2 are arranged in series in a path connecting the input terminal to the output terminal, and a third capacitance element Cf 3 is inserted between a reference potential and a path connecting the capacitance elements Cf 1 and Cf 2 .
  • the reference potential may be, for example, a ground potential in the feedback circuit.
  • the feedback circuit may be, for example, a feedback circuit 34 shown in FIG. 2 .
  • the first capacitance element Cf 1 and the second capacitance element Cf 2 are connected in series in a path connecting an input terminal 32 and output terminal 33 of an operation amplifier 21 .
  • the third capacitance element Cf 3 is also connected between the reference potential and a node connecting the capacitance elements Cf 1 and Cf 2 .
  • the combined capacitance value of the feedback capacitors of the feedback circuit 34 is given by:
  • the amplification factor of the signal processing circuit 30 in this embodiment is given by:
  • the chip area may widen by an amount corresponding to a difference of 9.6 pF which is obtained by changing the value of C 0 from 3.2 pF to 12.8 pF for the arrangement shown in FIG. 1 .
  • FIG. 3 is a graph plotting a production variation (a standardized value for the arrangement shown in FIG. 1 ) for the signal amplitude of an input when the amplification factor is 128, and showing a comparison between a case in which the arrangement shown in FIG.
  • FIG. 4 is a circuit diagram showing a solid-state image sensor 4 according to the second embodiment.
  • the solid-state image sensor 4 has a first mode and a second mode as operation modes.
  • the solid-state image sensor 4 is configured to have a pixel array 10 and a plurality of signal processing circuits 40 .
  • a feedback circuit 44 included in the signal processing circuit 40 has, in a path connecting an input terminal 42 and output terminal 43 of an operation amplifier 21 , the following paths in parallel:
  • the feedback circuit 44 can include a switch 120 between a path connecting the capacitance element Cf 1 to the switch 132 and a path connecting the capacitance element Cf 2 to the switch 231 .
  • the feedback circuit 44 can also include a switch 130 between a path connecting the capacitance element Cf 1 to the switch 132 and a path connecting the capacitance element Cf 3 to the switch 332 , and a switch 140 between a reference potential and a path connecting the capacitance element Cf 3 to the switch 331 .
  • a status in which each switch is ON or OFF as shown in FIG. 4 represents the first mode.
  • the second mode indicates a status in which each switch shown in FIG. 4 is set to the opposite state.
  • the states of the plurality of switches are controlled so that a feedback path in which the capacitance elements Cf 1 and Cf 2 are connected in series and the capacitance element Cf 3 is connected between the reference potential and a node between the capacitance elements Cf 1 and Cf 2 is formed in the first mode, and the feedback path is not formed in the second mode.
  • the solid-state image sensor 4 can be configured to include three or more operation modes and to control the states of the plurality of switches, thereby enabling to form the feedback path in the first mode and not to form the feedback path in other modes.
  • FIG. 5 is a circuit diagram showing a solid-state image sensor 5 according to the third embodiment.
  • the solid-state image sensor 5 includes a first mode and a second mode as operation modes.
  • the solid-state image sensor 5 is configured to have a pixel array 10 and a plurality of signal processing circuits 50 .
  • a feedback circuit 54 included in the signal processing circuit 50 has, in a path connecting an input terminal 52 and output terminal 53 of an operation amplifier 21 , a first feedback path and a second feedback path in parallel.
  • a switch 100 , a capacitance element Cf 11 , and a capacitance element Cf 12 are connected in series, and a capacitance element Cf 13 is inserted between a reference potential and a path connecting the capacitance elements Cf 11 and Cf 12 .
  • a switch 200 and a capacitance element Cf 2 are connected in series.
  • the feedback circuit 54 it is possible to form the first feedback path by turning on the switch 100 and turning off the switch 200 in response to a first control signal (not shown).
  • a second feedback path by turning off the switch 100 and turning on the switch 200 in response to a second control signal (not shown).
  • the solid-state image sensor 5 can be configured to include three or more operation modes and to control the states of the switches, thereby making amplification factors in feedback paths formed in the respective operation modes different from each other.
  • FIG. 6 is a circuit diagram showing a signal processing circuit 6 according to the fourth embodiment.
  • the signal processing circuit 6 includes a fully-differential amplifier 7 , input capacitances C 0 and C 1 , and feedback circuits 66 and 67 .
  • the fully-differential amplifier 7 has a common-mode voltage node VCOM, input terminals 62 and 63 , and output terminals 64 and 65 .
  • the input capacitance C 0 is arranged between the input terminal 62 and a column signal line 60
  • the input capacitance C 1 is arranged between the input terminal 63 and a column signal line 61 .
  • the feedback circuit 66 connects the input terminal 62 with the output terminal 64
  • the feedback circuit 67 connects the input terminal 63 with the output terminal 65 . Note that a pixel array is the same as that in the first to third embodiments of the present invention, and is therefore not shown.
  • the feedback circuit 66 has a first capacitance element Cf 311 , a second capacitance element Cf 312 , and a third capacitance element Cf 313 .
  • the first capacitance element Cf 311 and the second capacitance element Cf 312 are arranged in series in a path connecting the input terminal 62 to the output terminal 64 .
  • the third capacitance element Cf 313 is arranged between a reference potential and a path connecting the capacitance elements Cf 311 and Cf 312 .
  • the feedback circuit 67 has a first capacitance element Cf 321 , a second capacitance element Cf 322 , and a third capacitance element Cf 323 .
  • the first capacitance element Cf 321 and the second capacitance element Cf 322 are arranged in series in a path connecting the input terminal 63 to the output terminal 65 . Furthermore, in the feedback circuit 67 , the third capacitance element Cf 323 is arranged between the reference potential and a path connecting the capacitance elements Cf 321 and Cf 322 .
  • the capacitance elements Cf 313 and Cf 323 can be connected with the common-mode voltage node VCOM as the reference potential.
  • the present invention is applicable to other amplification circuits, as a matter of course.
  • the camera conceptually includes not only a device whose principal purpose is photographing but also a device (for example, a personal computer or portable terminal) additionally provided with a photographing function.
  • the camera includes the solid-state image sensor according to the present invention, which has been exemplified in the above embodiments, and a processing unit for processing a signal output from the solid-state image sensor.
  • the processing unit can include, for example, an A/D converter, and a processor for processing digital data output from the A/D converter.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Amplifiers (AREA)
US13/477,456 2011-06-03 2012-05-22 Solid-state image sensor Abandoned US20120307097A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/217,919 US8902342B2 (en) 2011-06-03 2014-03-18 Solid-state image sensor with feedback circuits

Applications Claiming Priority (2)

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JP2011-125711 2011-06-03
JP2011125711A JP5804780B2 (ja) 2011-06-03 2011-06-03 固体撮像装置

Related Child Applications (1)

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US14/217,919 Division US8902342B2 (en) 2011-06-03 2014-03-18 Solid-state image sensor with feedback circuits

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US14/217,919 Expired - Fee Related US8902342B2 (en) 2011-06-03 2014-03-18 Solid-state image sensor with feedback circuits

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US (2) US20120307097A1 (enrdf_load_stackoverflow)
EP (1) EP2530928A3 (enrdf_load_stackoverflow)
JP (1) JP5804780B2 (enrdf_load_stackoverflow)
CN (1) CN102811316B (enrdf_load_stackoverflow)
BR (1) BR102012013323A2 (enrdf_load_stackoverflow)
RU (1) RU2510148C2 (enrdf_load_stackoverflow)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150181143A1 (en) * 2013-12-20 2015-06-25 SK Hynix Inc. Image sensing device
US20150215556A1 (en) * 2012-04-12 2015-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Readout device with readout circuit
US12003864B2 (en) 2012-09-04 2024-06-04 Duelight Llc Image sensor apparatus and method for obtaining multiple exposures with zero interframe time
US12401912B2 (en) 2014-11-17 2025-08-26 Duelight Llc System and method for generating a digital image
US12401911B2 (en) 2014-11-07 2025-08-26 Duelight Llc Systems and methods for generating a high-dynamic range (HDR) pixel stream

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5923061B2 (ja) 2013-06-20 2016-05-24 キヤノン株式会社 固体撮像装置
JP2015015596A (ja) 2013-07-04 2015-01-22 キヤノン株式会社 撮像装置及びその駆動方法
JP6362328B2 (ja) 2013-12-26 2018-07-25 キヤノン株式会社 固体撮像装置及びその駆動方法
JP6274904B2 (ja) 2014-02-25 2018-02-07 キヤノン株式会社 固体撮像装置及び撮像システム
CN111263088B (zh) * 2020-02-25 2022-03-22 西安微电子技术研究所 一种用于8t像元的高速采样电路及其控制方法
CN120074410A (zh) * 2025-04-28 2025-05-30 安徽创谱仪器科技有限公司 电荷放大装置及电子设备

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US20100259661A1 (en) * 2009-02-06 2010-10-14 Texas Instruments Incorporated Amplifying circuit and imaging device imaging device

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Cited By (7)

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Publication number Priority date Publication date Assignee Title
US20150215556A1 (en) * 2012-04-12 2015-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Readout device with readout circuit
US9369652B2 (en) * 2012-04-12 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Readout device with readout circuit
US12003864B2 (en) 2012-09-04 2024-06-04 Duelight Llc Image sensor apparatus and method for obtaining multiple exposures with zero interframe time
US20150181143A1 (en) * 2013-12-20 2015-06-25 SK Hynix Inc. Image sensing device
US9479719B2 (en) * 2013-12-20 2016-10-25 SK Hynix Inc. Image sensing device having input/output lines
US12401911B2 (en) 2014-11-07 2025-08-26 Duelight Llc Systems and methods for generating a high-dynamic range (HDR) pixel stream
US12401912B2 (en) 2014-11-17 2025-08-26 Duelight Llc System and method for generating a digital image

Also Published As

Publication number Publication date
CN102811316B (zh) 2015-10-28
JP5804780B2 (ja) 2015-11-04
EP2530928A3 (en) 2015-10-07
CN102811316A (zh) 2012-12-05
EP2530928A2 (en) 2012-12-05
RU2510148C2 (ru) 2014-03-20
RU2012122739A (ru) 2013-12-10
US20140197302A1 (en) 2014-07-17
US8902342B2 (en) 2014-12-02
JP2012253625A (ja) 2012-12-20
BR102012013323A2 (pt) 2013-06-25

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Owner name: CANON KABUSHIKI KAISHA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ARAOKA, YUKIO;SHINGAI, SATORU;REEL/FRAME:028960/0011

Effective date: 20120515

STCB Information on status: application discontinuation

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