US20120217591A1 - Semiconductor device and method of manufacturing the same, and power supply apparatus - Google Patents

Semiconductor device and method of manufacturing the same, and power supply apparatus Download PDF

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US20120217591A1
US20120217591A1 US13/326,253 US201113326253A US2012217591A1 US 20120217591 A1 US20120217591 A1 US 20120217591A1 US 201113326253 A US201113326253 A US 201113326253A US 2012217591 A1 US2012217591 A1 US 2012217591A1
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layer
tan
electrode material
diffusion suppression
material diffusion
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Yoichi Kamada
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Fujitsu Ltd
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Fujitsu Ltd
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    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
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Definitions

  • the embodiments discussed herein are related to a semiconductor device and a method of manufacturing the same, and a power supply apparatus.
  • field-effect transistors using a nitride semiconductor are expected to be applied to devices with a higher withstanding voltage and a higher output, also known as power devices, employed in server systems, for example, in view of their physical characteristics. They are also expected to be applied to high-output amplifiers employed in base stations, such as wireless base stations, for their lower power consumptions.
  • An MIS structure includes a gate insulation film between agate electrode and a semiconductor layer, for the purpose of suppressing leak currents, from the gate electrode, which adversely affect the characteristics of the GaN-based transistor.
  • GaN-based transistors capable of operating under higher currents or in a high-temperature environment are needed to be developed.
  • a GaN-based transistor includes electrodes including an Al layer, as ohmic electrodes, and further includes interconnections made of gold (Au) which is a low-resistance interconnection material, as interconnections.
  • Au gold
  • a GaN-based transistor in such a structure is operated with a direct contact of the Au interconnection and the Al layer, an Au—Al compound is readily formed, which causes an increase in the resistance.
  • provision of a single Pt layer, Ta layer, TaN layer, TiWN layer and so forth, as a barrier metal layer has been proposed, between the Au interconnection and the Al layer.
  • a semiconductor device and a power supply apparatus include a gate electrode; a gate insulation film; and an electrode material diffusion suppression layer, provided between the gate electrode and the gate insulation film, including a first TaN layer, a Ta layer, and a second TaN layer stacked in sequence.
  • a semiconductor device and a power supply apparatus include an ohmic electrode including an Al layer; an Au interconnection; and an electrode material diffusion suppression layer, provided between the Al layer and the Au interconnection, including a first TaN layer, a Ta layer, and a second TaN layer stacked in sequence.
  • a semiconductor device and a power supply apparatus include a first electrode material diffusion suppression layer, provided under a gate electrode, including a TaN layer, a Ta layer, and a TaN layer stacked in sequence; and a second electrode material diffusion suppression layer, provided over an ohmic electrode, including a TaN layer, a Ta layer, and a TaN layer stacked in sequence.
  • a method of manufacturing a semiconductor device includes forming a gate insulation film; forming an electrode material diffusion suppression layer over the gate insulation film by stacking a first TaN layer, a Ta layer, and a second TaN layer, in sequence; and forming a gate electrode over the electrode material diffusion suppression layer.
  • a method of manufacturing a semiconductor device includes forming an ohmic electrode including an Al layer; forming an electrode material diffusion suppression layer by stacking a first TaN layer, a Ta layer, and a second TaN layer, in sequence, over the Al layer; and forming an Au interconnection over the electrode material diffusion suppression layer.
  • a method of manufacturing a semiconductor device includes forming a first electrode material diffusion suppression layer by stacking a TaN layer, a Ta layer, and a TaN layer, in sequence; forming a gate electrode over the first electrode material diffusion suppression layer; forming an ohmic electrode; and forming a second electrode material diffusion suppression layer by stacking a TaN layer, a Ta layer, and a TaN layer, in sequence, over the ohmic electrode.
  • FIG. 1 is a schematic cross-sectional view illustrating the structure of the semiconductor device according to a first embodiment
  • FIG. 2 is a schematic cross-sectional view illustrating a GaN-based semiconductor stacked structure included in the semiconductor device according to the first embodiment
  • FIG. 3 is a schematic cross-sectional view illustrating the issues of the semiconductor device according to the first embodiment
  • FIGS. 4A and 4B are schematic cross-sectional views illustrating the issues of the semiconductor device according to the first embodiment
  • FIGS. 5A to 5G are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to the first embodiment
  • FIGS. 6A to 6E are schematic cross-sectional views illustrating the method of manufacturing a semiconductor device according to the first embodiment
  • FIG. 7 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a second embodiment
  • FIG. 8 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a third embodiment
  • FIG. 9 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a fourth embodiment.
  • FIG. 10 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a fifth embodiment
  • FIG. 11 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a sixth embodiment.
  • FIGS. 12A to 12D are diagrams illustrating the issues of the semiconductor device according to the sixth embodiment, wherein: FIG. 12A is a micrograph before a thermal degradation accelerated test; FIG. 12B is a micrograph illustrating an Au—Al compound formed when an electrode material diffusion suppression layer degrades during the thermal degradation accelerated test; FIGS. 12C and 12D are graphs illustrating the time durations until the electrode material diffusion suppression layer degrades and an Au—Al compound is formed (time durations from the state in FIG. 12A to the state in FIG. 12B ; reaction times) for each candidate of the electrode material diffusion suppression layer;
  • FIG. 13 is a graph illustrating the issues of the semiconductor device according to the sixth embodiment.
  • FIG. 14 is a graph illustrating the issues of the semiconductor device according to the sixth embodiment.
  • FIGS. 15A to 15F are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to the sixth embodiment
  • FIGS. 16A to 16E are schematic cross-sectional views illustrating the method of manufacturing a semiconductor device according to the sixth embodiment
  • FIG. 17 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a seventh embodiment
  • FIG. 18 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to an eighth embodiment.
  • FIG. 19 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a ninth embodiment.
  • FIG. 20 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a tenth embodiment
  • FIG. 21 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to an eleventh embodiment
  • FIGS. 22A to 22G are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to the eleventh embodiment
  • FIG. 23 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a twelfth embodiment
  • FIG. 24 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a thirteenth embodiment
  • FIG. 25 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a fourteenth embodiment
  • FIG. 26 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to a fifteenth embodiment
  • FIG. 27 is a schematic plan view illustrating the structure of a semiconductor device (semiconductor package) according to a sixteenth embodiment.
  • FIG. 28 is a schematic view illustrating the structure of a PFC circuit included in a power supply apparatus according to the sixteenth embodiment.
  • the material of the gate electrode diffuses into the gate insulation film due to a thermal treatment (an annealing process) performed during the manufacturing process or heat generation during a transistor operation, for example, which causes deterioration of the characteristics.
  • FIGS. 1-6E A semiconductor device and a method of manufacturing the same according to a first embodiment will be described with reference to FIGS. 1-6E .
  • the semiconductor device is a field-effect transistor using a nitride semiconductor, i.e., a high electron mobility transistor (HEMT) including a GaN-based semiconductor stacked structure (GaN-HEMT) on a semiconductor substrate, in this embodiment.
  • a nitride semiconductor i.e., a high electron mobility transistor (HEMT) including a GaN-based semiconductor stacked structure (GaN-HEMT) on a semiconductor substrate, in this embodiment.
  • This semiconductor device is also a MIS-type transistor including a gate insulation film. Note that such a semiconductor device is also referred to as a compound semiconductor device.
  • a GaN-based semiconductor stacked structure is also referred to as a nitride semiconductor stacked structure.
  • this MIS-type GaN-HEMT includes a GaN-based semiconductor stacked structure 1 wherein an i-GaN electron transit layer 41 , an i-AlGaN layer (not illustrated), an n-AlGaN electron supply layer 42 , and an n-GaN layer 43 are stacked in sequence on an SiC substrate (semiconductor substrate) 40 .
  • the electron transit layer 41 is also referred to as a carrier transit layer.
  • the electron supply layer 42 is also referred to as a carrier supply layer.
  • this MIS-type GaN-HEMT also includes a gate insulation film 2 on the GaN-based semiconductor stacked structure 1 , and a gate electrode 3 is provided over the gate insulation film 2 .
  • an electrode material diffusion suppression layer 6 is provided on the gate insulation film 2
  • the gate electrode 3 is provided on the electrode material diffusion suppression layer 6 .
  • the electrode material diffusion suppression layer 6 is provided between the gate electrode 3 and the gate insulation film 2 .
  • the electrode material diffusion suppression layer 6 will be described in detail later.
  • the surfaces of the gate electrode 3 , the electrode material diffusion suppression layer 6 , and the gate insulation film 2 are covered with an insulation film 7 .
  • the gate insulation film 2 is also referred to as a first insulation film.
  • the insulation film 7 is also referred to as a second insulation film.
  • the gate electrode 3 is provided between a source electrode 4 and a drain electrode 5 , which will be described later.
  • the gate insulation film 2 and the insulation film 7 are AlO (e.g., Al 2 O 3 films), for example.
  • the gate electrode 3 is made from an Al layer, for example.
  • the gate electrode material is aluminum which is a low-resistance material.
  • this MIS-type GaN-HEMT may include a gate recess.
  • this MIS-type GaN-HEMI may include a gate recess which is defined by removing portions of the n-GaN layer 43 and the n-AlGaN electron supply layer 42 constituting the GaN-based semiconductor stacked structure 1 .
  • this MIS-type GaN-HEMI includes a source electrode 4 and a drain electrode 5 provided on the GaN-based semiconductor stacked structure 1 .
  • the n-GaN layer 43 constituting the GaN-based semiconductor stacked structure 1 is removed, and the source and drain electrodes 4 and 5 are provided on the n-AlGaN electron supply layer 42 .
  • the source and drain electrodes 4 and 5 are electrodes including an Al layer, e.g., electrodes wherein a Ti layer and an Al layer are stacked together.
  • the source and drain electrodes 4 and 5 are also referred to as ohmic electrodes, ohmic electrodes including an Al layer, or Al-containing ohmic electrodes. Note that the ohmic electrodes including an Al layer or Al-containing ohmic electrodes may have any structure, as long as they include the Al layer on the top.
  • an Au interconnection 9 which is a low-resistance interconnection material, is provided on the Al-containing ohmic electrodes 4 and 5 , i.e., the Al layer included in the Al-containing ohmic electrodes 4 and 5 , via a barrier metal layer 8 .
  • the barrier metal layer 8 has a structure wherein a Ti layer and a Pt layer are stacked together. Note that the barrier metal layer 8 may be made of a Pt layer. Furthermore, an Au interconnection 9 has a structure wherein a first Au layer 9 A and a second Au layer 9 B are stacked together.
  • the surface is covered with an insulation film, e.g., an SiN film, here.
  • an insulation film e.g., an SiN film, here.
  • the electrode material diffusion suppression layer 6 is provided between the gate electrode 3 and the gate insulation film 2 , wherein this electrode material diffusion suppression layer 6 has a structure wherein a TaN layer (first TaN layer) 6 A, a Ta layer 6 B, and a TaN layer (second TaN layer) 6 C are stacked in sequence.
  • the first TaN layer 6 A and the second TaN layer 6 C preferably have a nitrogen content of greater than about 48% but no more than 52%. More preferably, the nitrogen content may be about 49% or greater but no more than 51%. This range of nitrogen content can suppress diffusion of the Al gate electrode material in a reliable manner.
  • Such a electrode material diffusion suppression layer 6 is provided for the following reasons.
  • the material of the gate electrode 3 diffuses into the gate insulation film 2 during a thermal treatment (an annealing process) during the manufacturing process, e.g., an annealing process (at 600° C. or lower, for example) for establishing an ohmic characteristic, which causes deterioration of the characteristics.
  • a thermal treatment an annealing process
  • an annealing process at 600° C. or lower, for example
  • a TaN layer 6 A which is a high-melting-point metal and a highly-stable metal, is considered, between the gate insulation film 2 and the gate electrode 3 .
  • a threshold shift is induced during a device operation, i.e., a transistor operation, which causes deterioration of the characteristics, i.e., the transistor characteristics.
  • aluminum i.e., the gate electrode material
  • electrons from the 2DEG region are easily trapped in the interface between the insulation film and the semiconductor.
  • the single TaN layer 6 A has two grain sizes, namely, about 8 nm and about 5 nm, for example.
  • the TaN layer 6 A having such a structure is not capable of suppressing diffusion of the Al gate electrode material due to a thermal treatment or heat generation described above.
  • the TaN layer formed on the Ta layer has three grain sizes, namely, about 8 nm, about 5 nm, and about 3 nm, for example.
  • a structure wherein a TaN layer, a Ta layer, and a TaN layer are stacked in sequence could suppress diffusion of the Al gate electrode material into the gate insulation film 2 , due to a thermal treatment or heat generation described above.
  • the structure having a TaN layer formed on a Ta layer has more complex diffusion paths within an Al gate electrode material, as compared to a structure with a single TaN layer 6 A. Accordingly, such a structure can suppress diffusion of the Al gate electrode material into the gate insulation film 2 , due to a thermal treatment or heat generation described above.
  • the electrode material diffusion suppression layer 6 has a structure wherein the TaN layer 6 A, the Ta layer 6 B, and the TaN layer 6 C are stacked in sequence, as described above. This can suppress diffusion of the Al gate electrode material into the gate insulation film 2 , due to a thermal treatment or heat generation described above. This can prevent electrons from the 2DEG region from being trapped in the interface between the insulation film and the semiconductor. As a result, a threshold shift during a transistor operation is prevented, which enables a stable transistor operation, thereby preventing deterioration of the transistor characteristics.
  • the nitrogen content of the TaN layer 6 C is controlled to be greater than about 48% but no more than 52%.
  • the nitrogen content of the TaN layer 6 C is controlled during formation of the TaN layer 6 C on the Ta layer 6 B with sputtering, thereby adjusting the grain sizes.
  • the lower TaN layer 6 A also preferably has a nitrogen content of greater than about 48% but no more than 52%.
  • FIGS. 5A to 5G and 6 A to 6 E a method of manufacturing a semiconductor device (MIS-type GaN-HEMT) according to this embodiment will be explained with reference to FIGS. 5A to 5G and 6 A to 6 E.
  • a GaN-based semiconductor stacked structure 1 is formed on a semiconductor substrate 40 .
  • an i-GaN electron transit layer 41 , an i-AlGaN layer (not illustrated), an n-AlGaN electron supply layer 42 , and an n-GaN layer 43 are grown, in sequence, on an SiC substrate 40 , with a metal organic vapor phase epitaxy (MOVPE) technique, for example (see FIG. 2 ).
  • MOVPE metal organic vapor phase epitaxy
  • the i-GaN electron transit layer 41 has a thickness of about 3 ⁇ m, for example.
  • the i-AlGaN layer has a thickness of about 5 nm, for example.
  • the n-AlGaN electron supply layer 42 has a thickness of about 20 nm, and an Si dope concentration of about 5 ⁇ 10 18 cm ⁇ 3 , for example.
  • the n-GaN layer 43 has a thickness of about 10 nm, for example.
  • a resist having an opening at a region wherein a gate electrode is to be formed (hereinafter, gate electrode formation region) may be provided with photolithography, for example.
  • the n-GaN layer 43 and the n-AlGaN electron supply layer 42 at the gate electrode formation region may be removed, with a dry etching using a fluorine-based gas, for example.
  • all or a portion of the n-AlGaN electron supply layer 42 in the thickness direction may be removed. For example, about 1 nm of the n-AlGaN electron supply layer 42 may be remained. Only the n-GaN layer 43 may be removed, while keeping the n-AlGaN electron supply layer 42 remained.
  • a gate insulation film 2 is formed on the GaN-based semiconductor stacked structure 1 .
  • an AlO film 2 (e.g., Al 2 O 3 film), as a gate insulation film, is formed on the GaN-based semiconductor stacked structure 1 , with an atomic layer deposition (ALD) technique, for example.
  • ALD atomic layer deposition
  • a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C are stacked on the gate insulation film 2 to from an electrode material diffusion suppression layer 6 .
  • the TaN layer 6 A, the Ta layer 6 B, and the TaN layer 6 C are stacked in sequence over the AlO film 2 as a gate insulation film, with sputtering, for example, to form the electrode material diffusion suppression layer 6 .
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are as follows: a degree of vacuum (pressure) of about 1.0 Pa and a power of about 1 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the nitrogen contents of the TaN layers 6 A and 6 C are about 50%.
  • a gate electrode material i.e., a gate electrode material
  • sputtering for example.
  • an Al layer which is to constitute a gate electrode 3 , is formed on the electrode material diffusion suppression layer 6 .
  • sputtering parameters for forming the Al layer 3 are as follows: a degree of vacuum (pressure) of about 0.7 Pa and a power of about 0.5 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • a resist 15 is provided at the gate electrode formation region with photolithography, for example, and the TaN layer 6 A, the Ta layer 6 B, the TaN layer 6 C, and the Al layer 3 being formed at a region other than the gate electrode formation region are removed, with a dry etching using a fluorine-based gas, for example.
  • the gate electrode 3 made of an Al layer is formed on the electrode material diffusion suppression layer 6 .
  • an MIS structure is formed.
  • an AlO film 7 (e.g., Al 2 O 3 film), as an insulation film, is formed on the AlO film 2 as a gate insulation film and the Al layer 3 as the gate electrode, with an ALD technique, for example.
  • the insulation film 7 made of an AlO film is formed so as to cover the gate insulation film 2 and the gate electrode 3 .
  • the Al-containing ohmic electrodes 4 and 5 are formed on the n-GaN layer 43 .
  • a first Au layer 9 A that is to constitute an Au interconnection 9 is formed.
  • a semiconductor device (MIS-type GaN-HEMT) is manufactured.
  • this semiconductor device includes, between the gate electrode 3 and the gate insulation film 2 , an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C, and a Pt layer 6 D, in sequence, from the gate insulation film 2 side.
  • an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C, and a Pt layer 6 D, in sequence, from the gate insulation film 2 side.
  • the gate electrode 3 made of an Al layer is formed on the top Pt layer 6 D in the electrode material diffusion suppression layer 6 , the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment.
  • the semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
  • a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Pt layer 6 D may be stacked in sequence, on an A 10 film 2 as a gate insulation film, with sputtering, for example.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer
  • the Pt layer 6 D is referred to as a fourth metal layer.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are similar to those in the above-described first embodiment.
  • sputtering parameters for forming the Pt layer 6 D are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the first embodiment as described above.
  • the electrode material diffusion suppression layer 6 provided between the gate electrode 3 and the gate insulation film 2 further includes an Ag layer 6 E stacked on the TaN layer 6 C (second TaN layer).
  • the same elements as those in the above-described first embodiment are referenced by the like reference symbols.
  • this semiconductor device includes, between the gate electrode 3 and the gate insulation film 2 , an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C, and an Ag layer 6 E, in sequence, from the gate insulation film 2 side.
  • an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C, and an Ag layer 6 E, in sequence, from the gate insulation film 2 side.
  • the gate electrode 3 made of an Al layer is formed on the top Ag layer 6 E in the electrode material diffusion suppression layer 6 , the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described second embodiment, without reducing the level of the diffusion suppression against the Al gate electrode material.
  • the semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
  • a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and an Ag layer 6 E maybe stacked in sequence, over an A 10 film 2 as agate insulation film, with sputtering, for example.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer
  • the Ag layer 6 E is referred to as a fourth metal layer.
  • the electrode material diffusion suppression layer 6 provided between the gate electrode 3 and the gate insulation film 2 further includes a Cu layer 6 F stacked on the TaN layer 6 C (second TaN layer).
  • the same elements as those in the above-described first embodiment are referenced by the like reference symbols.
  • the gate electrode 3 made of an Al layer is formed on the top Cu layer 6 F in the electrode material diffusion suppression layer 6 , the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described first embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described second and third embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described third embodiment, without reducing the level of the diffusion suppression against the Al gate electrode material.
  • the semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
  • a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Cu layer 6 F may be stacked in sequence, over an AlO film 2 as a gate insulation film, with sputtering, for example.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer
  • the Cu layer 6 F is referred to as a fourth metal layer.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are similar to those in the above-described first embodiment.
  • sputtering parameters for forming the Cu layer 6 F are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the first embodiment as described above.
  • This embodiment has a different structure of the electrode material diffusion suppression layer 6 , from that in the above-described first embodiment (see FIG. 1 ).
  • the electrode material diffusion suppression layer 6 provided between the gate electrode 3 and the gate insulation film 2 further includes a Ti layer 6 G stacked on the TaN layer 6 C (second TaN layer).
  • the same elements as those in the above-described first embodiment are referenced by the like reference symbols.
  • this semiconductor device includes, between the gate electrode 3 and the gate insulation film 2 , an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C, and a Ti layer 6 G, in sequence, from the gate insulation film 2 side.
  • an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C, and a Ti layer 6 G, in sequence, from the gate insulation film 2 side.
  • the semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are similar to those in the above-described first embodiment.
  • sputtering parameters for forming the Ti layer 6 G are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the first embodiment as described above.
  • a semiconductor device and a method of manufacturing the same according to a sixth embodiment will be described with reference to FIGS. 11 to 16E .
  • the electrode material diffusion suppression layer 6 is provided between the gate electrode 3 and the gate insulation film 2 .
  • the present embodiment is different in that the electrode material diffusion suppression layer 6 is provided between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 , as depicted in FIG. 11 .
  • FIG. 11 the same elements as those in the above-described first embodiment (see FIG. 1 , for example) are referenced by the like reference symbols.
  • the electrode material diffusion suppression layer 6 not only suppresses diffusion of aluminum which is the material of the ohmic electrodes 4 and 5 , but also suppresses diffusion of gold (Au) which is the material of the interconnection 9 . Accordingly, the electrode material diffusion suppression layer 6 also functions as an interconnection material diffusion suppression layer.
  • the first TaN layer 6 A and the second TaN layer 6 C preferably have a nitrogen content of greater than about 48% but no more than 52%. More preferably, the nitrogen content may be about 49% or greater but no more than 51%. This range of nitrogen content can suppress diffusion of the electrode and interconnection materials in a reliable manner.
  • Such a electrode material diffusion suppression layer 6 is provided for the following reasons.
  • Thermal degradation accelerated tests were conducted on a Pt layer (with a thickness of about 200 nm); a Ta layer (TaN layer of a nitrogen content of about 0%, with a thickness of about 200 nm); a TaN layer of a nitrogen content of about 44% (with a thickness of about 200 nm); a TaN layer of a nitrogen content of about 50% (with a thickness of about 200 nm); and a TaN layer of a nitrogen content of about 50% (with a thickness of about 100 nm), as candidates for an electrode material diffusion suppression layer, to accelerate their degradation.
  • thermal characteristics of the candidate electrode material diffusion suppression layers were evaluated, considering higher temperatures exceeding about 300° C., which may be experienced in a die bonding step for bonding a semiconductor chip to a base with a die bonding material, such as Au—Sn, for example.
  • FIGS. 12A to12D time durations from the state in FIG. 12A to the state in FIG. 12B ; reaction times
  • the TaN layer of a nitrogen content of about 44% had a shorter reaction time, i.e., provided an inferior diffusion suppression against the electrode and interconnection materials, as compared to the Pt layer.
  • the TaN layer of a nitrogen content of about 50% had a longer reaction time, i.e., provided a superior diffusion suppression against the electrode and interconnection materials, as compared to the Pt layer and the Ta layer.
  • a higher resistivity means increased heat generation and power consumption during a transistor operation, meaning reduced transistor characteristics.
  • FIGS. 12A to12D time durations from the state in FIG. 12A to the state in FIG. 12B ; reaction times
  • the electrode material diffusion suppression layer with a Ta/TaN structure had the resistivity of about 60% of that of the electrode material diffusion suppression layer using a TaN (of a nitrogen content of about 50%; with a thickness of about 200 nm). More specifically, when assuming that the resistivity of TaN (of a nitrogen content of about 50%; with a thickness of about 200 nm) is 1.0, the resistivity of the electrode material diffusion suppression layer having a Ta/TaN structure could be reduced to about 0.6.
  • an electrode material diffusion suppression layer having a Ta/Ti/TaN structure had a longer reaction time, i.e., a superior diffusion suppression against the electrode and interconnection materials, as compared with an electrode material diffusion suppression layer having a Ta/TaN structure.
  • a Ti layer adheresion layer
  • the adhesion between the Ta layer and the TaN layer can be improved, thereby enhancing the diffusion suppression against the electrode and interconnection materials.
  • an electrode material diffusion suppression layer having a Ta/TaN structure degrades and forms an Au—Al compound in six minutes when heated at 450° C. This results in an increased resistance, and deteriorates the transistor characteristics.
  • a GaN-based transistor is required to be operated under a high current density, and accordingly an electrode material diffusion suppression layer with an even higher diffusion suppression against the electrode and interconnection materials is required.
  • an electrode material diffusion suppression layer 6 has a structure wherein a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C are stacked in sequence, by additionally including a TaN layer in the above-described Ta/TaN structure.
  • the electrode material diffusion suppression layer 6 is configured such that the thickness, i.e., the total thicknesses of the TaN layer 6 A, the Ta layer 6 B, and the TaN layer 6 C becomes about 200 nm in this embodiment, this is not limiting. With this structure, an electrode material diffusion suppression layer 6 exhibiting a higher diffusion suppression against the electrode and interconnection materials and having a lower resistivity can be achieved.
  • FIGS. 15A to 15F and 16 A to 16 E a method of manufacturing a semiconductor device (MIS-type GaN-HEMT) according to this embodiment will be explained with reference to FIGS. 15A to 15F and 16 A to 16 E.
  • a GaN-based semiconductor stacked structure 1 is formed on a semiconductor substrate 40 .
  • a resist having openings at the ohmic electrode formation regions is provided with photolithography, for example, and the GaN-based semiconductor stacked structure 1 , namely, the n-GaN layer 43 , in this example, at the ohmic electrode formation regions is removed with a dry etching using a chorine-based gas, for example.
  • Al-containing ohmic electrodes (source electrode and drain electrodes, in this embodiment) 4 and 5 made of Ti/Al, for example, are formed on the GaN-based semiconductor stacked structure 1 , namely, the n-AlGaN electron supply layer 42 , in this embodiment, with photolithography, and evaporation and lift-off techniques, for example. More specifically, a first resist film 20 and a second resist film 21 having openings at the ohmic electrode formation regions are formed over the n-AlGaN electron supply layer 42 with photolithography, for example.
  • a Ti layer and an Al layer are formed, in sequence, over the entire surface, i.e., on the surface of the second resist film 21 and in the openings with evaporation, for example.
  • the Ti layer and the Al layer are correctively denoted by the reference numeral 22 in FIG. 15B .
  • the Ti layer and the Al layer formed in the openings are remained after removing the first resist film 20 and second resist film 21 , and the Al-containing ohmic electrodes 4 and 5 made of Ti/Al, for example, are formed. Thereafter, the ohmic characteristic is established by an annealing process between about 400° C. to about 1000° C., such as at 550° C., for example, in nitrogen atmosphere, for example.
  • a resist having an opening at a region wherein a gate electrode is to be formed (hereinafter, gate electrode formation region) may be provided with photolithography, for example. Thereafter, the n-GaN layer 43 and the n-AlGaN electron supply layer 42 at the gate electrode formation region may be removed, with a dry etching using a fluorine-based gas, for example.
  • a gate electrode 3 made of an Al layer is formed on the AlO film 2 , as a gate insulation film, with photolithography, and evaporation and lift-off techniques, for example. More specifically, a first resist film 23 and a second resist film 24 having an opening at the gate electrode formation region are formed over the AlO film 2 with photolithography, for example. Next, aluminum, which is a gate electrode material, is deposited over the entire surface, i.e., on the surface of the second resist film 24 and in the opening with evaporation, for example, thereby an Al layer 3 is formed. Only the Al layer 3 formed in the opening is remained after removing the first resist film 23 and the second resist film 24 , and the gate electrode 3 made of an Al layer is formed. In the above processes, an MIS structure is formed.
  • an AlO film 7 (e.g., Al 2 O 3 film), as an insulation film, is formed on the AlO film 2 as a gate insulation film and the Al layer 3 as the gate electrode, with an ALD technique, for example.
  • a resist having openings at the ohmic electrode formation regions is provided with photolithography, for example, and the gate insulation film 2 and the insulation film 7 at the ohmic electrode formation regions are removed with an ion milling technique using Ar gas, for example.
  • a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C are stacked in sequence over the Al-containing ohmic electrodes 4 and 5 , namely, over the Al layer included in the Al-containing ohmic electrodes 4 and 5 , in this example, with sputtering, for example.
  • the electrode material diffusion suppression layer 6 structured by stacking the TaN layer 6 A, the Ta layer 6 B, and the TaN layer 6 C, in sequence, is formed.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as second TaN layer or a third metal layer.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are as follows: a degree of vacuum (pressure) of about 1.0 Pa and a power of about 1 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the nitrogen contents of the TaN layers 6 A and 6 C are about 50%.
  • a first Au layer 9 A that is to constitute an Au interconnection 9 is formed on the electrode material diffusion suppression layer 6 .
  • the first Au layer 9 A is formed on the TaN layer 6 C included in the electrode material diffusion suppression layer 6 with sputtering, for example.
  • sputtering parameters for forming the first Au layer 9 A are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • a resist 26 having openings above the ohmic electrodes 4 and 5 is formed with photolithography, for example, and a second Au layer 9 B is formed on the first Au layer 9 A with a plating technique, for example, as depicted in FIG. 16D .
  • the Au interconnection 9 made of the first Au layer 9 A and the second Au layer 9 B is formed on the electrode material diffusion suppression layer 6 .
  • the electrode material diffusion suppression layer 6 is formed on the Al-containing ohmic electrodes 4 and 5
  • the Au interconnection 9 is formed on the electrode material diffusion suppression layer 6 .
  • a SiN film (insulation film), which is not illustrated, is formed over the entire surface with a CVD technique, for example.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics.
  • This embodiment has a different structure of the electrode material diffusion suppression layer 6 , from that in the above-described sixth embodiment (see FIG. 11 ).
  • the electrode material diffusion suppression layer 6 provided between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 further includes a Pt layer 6 D stacked on the TaN layer 6 C (second TaN layer).
  • the same elements as those in the above-described sixth embodiment are referenced by the like reference symbols.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the sixth embodiment as described above.
  • a semiconductor device and a method of manufacturing the same according to an eighth embodiment will be described with reference to FIG. 18 .
  • This embodiment has a different structure of the electrode material diffusion suppression layer 6 , from that in the above-described sixth embodiment (see FIG. 11 ).
  • the electrode material diffusion suppression layer 6 provided between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 further includes an Ag layer 6 E stacked on the TaN layer 6 C (second TaN layer).
  • the same elements as those in the above-described sixth embodiment are referenced by the like reference symbols.
  • this semiconductor device includes, between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 , an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C, and an Ag layer 6 E, in sequence, from the side of ohmic electrodes 4 and 5 .
  • the Au interconnection 9 is formed on the top Ag layer 6 E in the electrode material diffusion suppression layer 6 , the adhesion between the electrode material diffusion suppression layer 6 and the Au interconnection 9 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment, thereby further improving the reliability.
  • diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment.
  • the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described seventh embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 .
  • the semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
  • a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Ag layer 6 E maybe stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5 , with sputtering, for example.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer
  • the Ag layer 6 E is referred to as a fourth metal layer.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are similar to those in the above-described sixth embodiment.
  • sputtering parameters for forming the Ag layer 6 E are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the sixth embodiment as described above.
  • a semiconductor device and a method of manufacturing the same according to a ninth embodiment will be described with reference to FIG. 19 .
  • This embodiment has a different structure of the electrode material diffusion suppression layer 6 , from that in the above-described sixth embodiment (see FIG. 11 ).
  • the electrode material diffusion suppression layer 6 provided between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 further includes a Cu layer 6 F stacked on the TaN layer 6 C (second TaN layer).
  • the same elements as those in the above-described sixth embodiment are referenced by the like reference symbols.
  • this semiconductor device includes, between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 , an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C, and a Cu layer 6 F, in sequence, from the side of the ohmic electrodes 4 and 5 .
  • the Au interconnection 9 is formed on the top Cu layer 6 F in the electrode material diffusion suppression layer 6 , the adhesion between the electrode material diffusion suppression layer 6 and the Au interconnection 9 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment, thereby further improving the reliability.
  • diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment.
  • the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described seventh and eighth embodiments, without reducing the adhesion.
  • the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described eighth embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 .
  • the semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
  • a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Cu layer 6 F maybe stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5 , with sputtering, for example.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer
  • the Cu layer 6 F is referred to as a fourth metal layer.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are similar to those in the above-described sixth embodiment.
  • sputtering parameters for forming the Cu layer 6 F are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the sixth embodiment as described above.
  • a semiconductor device and a method of manufacturing the same according to a tenth embodiment will be described with reference to FIG. 20 .
  • This embodiment has a different structure of the electrode material diffusion suppression layer 6 , from that in the above-described sixth embodiment (see FIG. 11 ).
  • the electrode material diffusion suppression layer 6 provided between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 further includes a Ti layer 6 G stacked on the TaN layer 6 C (second TaN layer).
  • the same elements as those in the above-described sixth embodiment are referenced by the like reference symbols.
  • this semiconductor device includes, between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 , an electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, and a TaN layer 6 C, and a Ti layer 6 G, in sequence, from the side of the ohmic electrodes 4 and 5 .
  • the adhesion between the electrode material diffusion suppression layer 6 and the Au interconnection 9 can be improved, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment, thereby further improving the reliability.
  • diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the electrode material diffusion suppression layer 6 in the above-described sixth embodiment.
  • the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described seventh, eighth, and ninth embodiments, without reducing the adhesion.
  • the manufacturing cost can be reduced, as compared to the electrode material diffusion suppression layer 6 in the above-described seventh embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 .
  • the semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
  • a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Ti layer 6 G maybe stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5 , with sputtering, for example.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer
  • the Ti layer 6 G is referred to as a fourth metal layer.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are similar to those in the above-described sixth embodiment.
  • sputtering parameters for forming the Ti layer 6 G are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the sixth embodiment as described above.
  • FIGS. 21 and 22A to 22 G A semiconductor device and a method of manufacturing the same according to an eleventh embodiment will be described with reference to FIGS. 21 and 22A to 22 G.
  • an electrode material diffusion suppression layer 6 X having the same stacked structure as that in the above-described first embodiment is provided between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 , as depicted in FIG. 21 .
  • FIG. 21 the same elements as those in the above-described first embodiment (see FIG. 1 , for example) are referenced by the like reference symbols.
  • this embodiment by combining the above-described first embodiment (see FIG. 1 ) and the above-described sixth embodiment (see FIG. 11 ), provides an electrode material diffusion suppression layer 6 (first electrode material diffusion suppression layer) under the gate electrode 3 , while providing an electrode material diffusion suppression layer 6 X (second electrode material diffusion suppression layer) over the ohmic electrodes 4 and 5 .
  • the first electrode material diffusion suppression layer 6 is provided between the gate electrode 3 and the gate insulation layer 2 , wherein the first electrode material diffusion suppression layer 6 has a structure wherein a TaN layer 6 A (first TaN layer), a Ta layer 6 B, and a TaN layer 6 C (second TaN layer) are stacked in sequence.
  • the second electrode material diffusion suppression layer 6 X is provided between the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 , wherein the second electrode material diffusion suppression layer 6 X has a structure wherein a TaN layer 6 A (first TaN layer), a Ta layer 6 B, and a TaN layer 6 C (second TaN layer) are stacked in sequence.
  • the TaN layers 6 A and 6 C included in the first and second electrode material diffusion suppression layers 6 and 6 X preferably have a nitrogen content of greater than about 48% but no more than 52%. More preferably, the nitrogen content may be about 49% or greater but no more than 51%. This range of nitrogen content can suppress diffusion of the electrode material in a reliable manner.
  • a GaN-based semiconductor stacked structure 1 is formed on a semiconductor substrate 40 .
  • a resist having openings at the ohmic electrode formation regions is provided with photolithography, for example, and the GaN-based semiconductor stacked structure 1 , namely, the n-GaN layer 43 , in this example, at the ohmic electrode formation regions is removed with a dry etching using a chorine-based gas, for example.
  • Al-containing ohmic electrodes (source electrode and drain electrodes, in this embodiment) 4 and 5 made of Ti/Al, for example, are formed on the GaN-based semiconductor stacked structure 1 , namely, the n-AlGaN electron supply layer 42 , in this embodiment, with photolithography, and evaporation and lift-off techniques, for example. More specifically, a first resist film 30 and a second resist film 31 having openings at the ohmic electrode formation regions are formed over the n-AlGaN electron supply layer 42 with photolithography, for example.
  • a Ti layer and an Al layer are formed, in sequence, over the entire surface, i.e., on the surface of the second resist film 31 and in the openings with evaporation, for example.
  • the Ti layer and the Al layer are correctively denoted by the reference numeral 32 in FIG. 22B .
  • the Ti layer and the Al layer formed in the openings are remained after removing the first resist film 30 and the second resist film 31 , and the Al-containing ohmic electrodes 4 and 5 made of Ti/Al, for example, are formed. Thereafter, the ohmic characteristic is established by an annealing process between about 400° C. to about 1000° C., such as at 550° C., for example, in nitrogen atmosphere, for example.
  • a resist having an opening at a region wherein a gate electrode is to be formed (hereinafter, gate electrode formation region) may be provided with photolithography, for example. Thereafter, the n-GaN layer 43 and the n-AlGaN electron supply layer 42 at the gate electrode formation region may be removed, with a dry etching using a fluorine-based gas, for example.
  • an AlO film (e.g., Al 2 O 3 film), as a gate insulation film, is formed on the GaN-based semiconductor stacked structure 1 with an ALD technique, for example.
  • a resist having openings above the ohmic electrodes 4 and 5 is provided with photolithography, for example, and the AlO film 2 as a gate insulation film above the ohmic electrodes 4 and 5 is removed with an ion milling technique using Ar gas, for example.
  • a TaN layer 33 , a Ta layer 34 , and a TaN layer 35 are stacked in sequence over the ohmic electrodes 4 and 5 (Al layer included in the Al-containing ohmic electrodes in this example) and the AlO film 2 , as a gate insulation film, with sputtering, for example.
  • Au which is an interconnection material
  • sputtering for example, to form an Au layer 36 .
  • a resist having an opening at the gate electrode formation region is provided with photolithography, for example, and the Au layer 36 being formed at the gate electrode formation region is removed with an ion milling technique using Ar gas, for example, as depicted in FIG. 22E .
  • Al which is a gate electrode material
  • sputtering for example, aluminum
  • a resist is provided above the gate electrode formation region and the ohmic electrodes 4 and 5 with photolithography, for example, and the TaN layer 6 A, the Ta layer 6 B, the TaN layer 6 C, the Au layer 36 , and the Al layer 37 , being formed at a region other than regions above the gate electrode formation region and the ohmic electrodes 4 and 5 , are removed with an ion milling technique using Ar gas, for example, as depicted in FIG. 22F .
  • the first electrode material diffusion suppression layer 6 structured by stacking the TaN layer 6 A, the Ta layer 6 B, and the TaN layer 6 C, in sequence, is formed over the gate insulation film 2 .
  • the second electrode material diffusion suppression layer 6 X structured by stacking the TaN layer 6 A, the Ta layer 6 B, and the TaN layer 6 C, in sequence, is formed over the ohmic electrodes 4 and 5 .
  • the first and second electrode material diffusion suppression layers 6 and 6 X are formed simultaneously.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer.
  • the first and second electrode material diffusion suppression layers 6 and 6 X are formed simultaneously, they may be formed in separate steps.
  • a gate electrode 3 made of an Al layer is formed on the first electrode material diffusion suppression layer 6 , namely, on the TaN layer 6 C included in the first electrode material diffusion suppression layer 6 , in this example.
  • the gate electrode 3 made of an Al layer is formed over the GaN-based semiconductor stacked structure 1 , having the AlO film 2 as a gate insulation film and the first electrode material diffusion suppression layer 6 interposed therebetween. In this manner, an MIS structure is formed.
  • a first Au layer 9 A to constitute an Au interconnection 9 is formed on the second electrode material diffusion suppression layer 6 X, namely, on the TaN layer 6 C included in the electrode material diffusion suppression layer 6 X, in this example.
  • an AlO film 7 (e.g., Al 2 O 3 film), as an insulation film, is formed on the Al layer 3 as a gate electrode and the first Au layer 9 A, with an ALD technique, for example.
  • a resist having openings at regions above the ohmic electrodes 4 and 5 is provided with photolithography, for example, and the insulating film 7 above the ohmic electrodes 4 and 5 is removed with an ion milling technique using Ar gas, for example.
  • a resist having openings at regions above the ohmic electrodes 4 and 5 is formed with photolithography, for example, and a second Au layer 9 B is formed on the first Au layer 9 A with a plating technique, for example, as depicted in FIG. 22G .
  • the Au interconnection 9 made of the first Au layer 9 A and the second Au layer 9 B is formed on the second electrode material diffusion suppression layer 6 X.
  • the second electrode material diffusion suppression layer 6 X is formed on the Al-containing ohmic electrodes 4 and 5
  • the Au interconnection 9 is formed on the second electrode material diffusion suppression layer 6 X.
  • a SiN film (insulation film), which is not illustrated, is formed over the entire surface with a CVD technique, for example.
  • a semiconductor device (MIS-type GaN-HEMT) is manufactured.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the first and sixth embodiments described above.
  • a semiconductor device and a method of manufacturing the same according to a twelfth embodiment will be described with reference to FIG. 23 .
  • This embodiment has different structures of the first and second electrode material diffusion suppression layers 6 and 6 X, from those in the above-described eleventh embodiment (see FIG. 21 ).
  • the first and second electrode material diffusion suppression layers 6 and 6 X further include a Pt layer 6 D stacked on the TaN layer (second TaN layer) 6 C.
  • the same elements as those in the above-described eleventh embodiment are referenced by the like reference symbols.
  • this semiconductor device includes a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Pt layer 6 D in sequence, and a second electrode material diffusion suppression layer 6 X structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Pt layer 6 D in sequence.
  • a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Pt layer 6 D in sequence
  • a second electrode material diffusion suppression layer 6 X structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Pt layer 6 D in sequence.
  • the gate electrode 3 made of an Al layer is formed on the top Pt layer 6 D in the first electrode material diffusion suppression layer 6 , the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment.
  • the Au interconnection 9 is formed on the top Pt layer 6 D in the second electrode material diffusion suppression layer 6 X, the adhesion between the second electrode material diffusion suppression layer 6 X and the Au interconnection 9 can be improved, as compared to the second electrode material diffusion suppression layer 6 X in the above-described eleventh embodiment, thereby further improving the reliability.
  • diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the second electrode material diffusion suppression layer 6 X in the above-described eleventh embodiment.
  • the semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
  • a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Pt layer 6 D may be stacked in sequence, on the Al layer included in the ohmic electrodes 4 and 5 and the AlO film 2 as a gate insulation film, with sputtering, for example.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer
  • the Pt layer 6 D is referred to as a fourth metal layer.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are similar to those in the above-described eleventh embodiment.
  • sputtering parameters for forming the Pt layer 6 D are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the eleventh embodiment as described above.
  • a semiconductor device and a method of manufacturing the same according to a thirteenth embodiment will be described with reference to FIG. 24 .
  • This embodiment has different structures of the first and second electrode material diffusion suppression layers 6 and 6 X, from those in the above-described eleventh embodiment (see FIG. 21 ).
  • the first and second electrode material diffusion suppression layers 6 and 6 X further include an Ag layer 6 E stacked on the TaN layer (second TaN layer) 6 C.
  • the same elements as those in the above-described eleventh embodiment are referenced by the like reference symbols.
  • this semiconductor device includes a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and an Ag layer 6 E in sequence, and a second electrode material diffusion suppression layer 6 X structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and an Ag layer 6 E in sequence.
  • a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and an Ag layer 6 E in sequence
  • a second electrode material diffusion suppression layer 6 X structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and an Ag layer 6 E in sequence.
  • the gate electrode 3 made of an Al layer is formed on the top Ag layer 6 E in the first electrode material diffusion suppression layer 6 , the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the first electrode material diffusion suppression layer 6 in the above-described twelfth embodiment, without reducing the level of the diffusion suppression against the Al gate electrode material.
  • the Au interconnection 9 is formed on the top Ag layer 6 E in the second electrode material diffusion suppression layer 6 X, the adhesion between the second electrode material diffusion suppression layer 6 X and the Au interconnection 9 can be improved, as compared to the second electrode material diffusion suppression layer 6 X in the above-described eleventh embodiment, thereby further improving the reliability.
  • diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the second electrode material diffusion suppression layer 6 X in the above-described eleventh embodiment.
  • the manufacturing cost can be reduced, as compared to the second electrode material diffusion suppression layer 6 X in the above-described twelfth embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 .
  • the semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
  • a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and an Ag layer 6 E may be stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5 and the AlO film 2 as a gate insulation film, with sputtering, for example.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer
  • the Ag layer 6 E is referred to as fourth metal layer.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are similar to those in the above-described eleventh embodiment.
  • sputtering parameters for forming the Ag layer 6 E are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the eleventh embodiment as described above.
  • a semiconductor device and a method of manufacturing the same according to a fourteenth embodiment will be described with reference to FIG. 25 .
  • This embodiment has different structures of the first and second electrode material diffusion suppression layers 6 and 6 X, from those in the above-described eleventh embodiment (see FIG. 21 ).
  • the first and second electrode material diffusion suppression layers 6 and 6 X further include a Cu layer 6 F stacked on the TaN layer (second TaN layer) 6 C.
  • the same elements as those in the above-described eleventh embodiment are referenced by the like reference symbols.
  • this semiconductor device includes a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Cu layer 6 F in sequence, and a second electrode material diffusion suppression layer 6 X structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Cu layer 6 F in sequence.
  • a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Cu layer 6 F in sequence
  • a second electrode material diffusion suppression layer 6 X structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Cu layer 6 F in sequence.
  • the gate electrode 3 made of an Al layer is formed on the top Cu layer 6 F in the first electrode material diffusion suppression layer 6 , the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the first electrode material diffusion suppression layer 6 in the above-described twelfth and thirteenth embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the first electrode material diffusion suppression layer 6 in the above-described thirteenth embodiment, without reducing the level of the diffusion suppression against the Al gate electrode material.
  • the Au interconnection 9 is formed on the top Cu layer 6 F in the second electrode material diffusion suppression layer 6 X, the adhesion between the second electrode material diffusion suppression layer 6 X and the Au interconnection 9 can be improved, as compared to the second electrode material diffusion suppression layer 6 X in the above-described eleventh embodiment, thereby further improving the reliability.
  • diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the second electrode material diffusion suppression layer 6 X in the above-described eleventh embodiment.
  • the manufacturing cost can be reduced, as compared to the second electrode material diffusion suppression layer 6 X in the above-described twelfth and thirteenth embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the second electrode material diffusion suppression layer 6 X in the above-described thirteenth embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 .
  • the semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
  • a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Cu layer 6 F may be stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5 and the AlO film 2 as a gate insulation film, with sputtering, for example.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer
  • a the Cu layer 6 F is referred to as fourth metal layer.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are similar to those in the above-described eleventh embodiment.
  • sputtering parameters for forming the Cu layer 6 F are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the eleventh embodiment as described above.
  • a semiconductor device and a method of manufacturing the same according to a fifteenth embodiment will be described with reference to FIG. 26 .
  • This embodiment has different structures of the first and second electrode material diffusion suppression layers 6 and 6 X, from those in the above-described eleventh embodiment (see FIG. 21 ).
  • the first and second electrode material diffusion suppression layers 6 and 6 X further include a Ti layer 6 G stacked on the TaN layer (second TaN layer) 6 C.
  • the same elements as those in the above-described eleventh embodiment are referenced by the like reference symbols.
  • this semiconductor device includes a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Ti layer 6 G in sequence, and a second electrode material diffusion suppression layer 6 X structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Ti layer 6 G in sequence.
  • a first electrode material diffusion suppression layer 6 structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Ti layer 6 G in sequence
  • a second electrode material diffusion suppression layer 6 X structured by stacking a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Ti layer 6 G in sequence.
  • the gate electrode 3 made of an Al layer is formed on the top Ti layer 6 G in the first electrode material diffusion suppression layer 6 , the adhesion between the electrode material diffusion suppression layer 6 and the gate electrode 3 can be improved, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment, thereby further improving the reliability. Furthermore, diffusion of the Al gate electrode material can be suppressed more effectively, as compared to the first electrode material diffusion suppression layer 6 in the above-described eleventh embodiment. Furthermore, the manufacturing cost can be reduced, as compared to the first electrode material diffusion suppression layer 6 in the above-described twelfth, thirteenth, and fourteenth embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the first electrode material diffusion suppression layer 6 in the above-described twelfth embodiment, without reducing the level of the diffusion suppression against the Al gate electrode material.
  • the Au interconnection 9 is formed on the top Ti layer 6 G in the second electrode material diffusion suppression layer 6 X, the adhesion between the second electrode material diffusion suppression layer 6 X and the Au interconnection 9 can be improved, as compared to the second electrode material diffusion suppression layer 6 X in the above-described eleventh embodiment, thereby further improving the reliability.
  • diffusion of the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 can be suppressed more effectively, as compared to the second electrode material diffusion suppression layer 6 X in the above-described eleventh embodiment.
  • the manufacturing cost can be reduced, as compared to the second electrode material diffusion suppression layer 6 X in the above-described twelfth, thirteenth, and fourteenth embodiments, without reducing the adhesion. Furthermore, the manufacturing cost can be reduced, as compared to the second electrode material diffusion suppression layer 6 X in the above-described twelfth embodiment, without reducing the level of the diffusion suppression against the materials of the Al layer included in the ohmic electrodes 4 and 5 and the Au interconnection 9 .
  • the semiconductor device (MIS-type GaN-HEMT) having the above structure can be manufactured as follows.
  • a TaN layer 6 A, a Ta layer 6 B, a TaN layer 6 C, and a Ti layer 6 G may be stacked in sequence, over the Al layer included in the ohmic electrodes 4 and 5 and the AlO film 2 as a gate insulation film, with sputtering, for example.
  • the TaN layer 6 A is referred to as a first TaN layer or a first metal layer
  • the Ta layer 6 B is referred to as a second metal layer
  • the TaN layer 6 C is referred to as a second TaN layer or a third metal layer
  • the Ti layer 6 G is referred to as a fourth metal layer.
  • sputtering parameters for forming the Ta layer 6 B and the TaN layers 6 A and 6 C are similar to those in the above-described eleventh embodiment.
  • sputtering parameters for forming the Ti layer 6 G are as follows: a degree of vacuum (pressure) of about 0.8 Pa and a power of about 0.8 kW, for example.
  • the target-substrate distance (T/S) is about 200 mm, for example.
  • the semiconductor device and the method of manufacturing the same according to this embodiment is advantageous in that diffusion of an electrode material can be suppressed, thereby achieving further improved characteristics, as in the eleventh embodiment as described above.
  • the semiconductor device according to the present embodiment is a semiconductor package including a semiconductor chip of a semiconductor device (GaN-HEMT) according to any one of the above-described embodiments and their variants. Note that such a semiconductor chip is also referred to as a HEMT chip.
  • GaN-HEMT semiconductor device
  • this semiconductor device includes a stage 50 mounting a semiconductor chip 56 according to any one of the above-described embodiments and their variants, a gate lead 51 , a source lead 52 , a drain lead 53 , bonding wires 54 A to 54 C (Al wires, in this embodiment), and an encapsulation resin 55 .
  • a semiconductor chip 56 is also referred to as a HEMT chip.
  • the encapsulation resin 55 is also referred to as a molding resin.
  • the gate pad 10 , the source pad 11 , and the drain pad 12 in the semiconductor chip 56 mounted on the stage 50 are connected to the gate lead 51 , the source lead 52 and the drain lead 53 through the Al wire 54 A to 54 C, respectively, which then undergoes resin encapsulation.
  • the stage 50 to which the back face of the substrate in the semiconductor chip 56 is secured with a die attach material 57 (solder, in this embodiment), is electrically connected to the drain lead 53 .
  • a die attach material 57 solder, in this embodiment
  • a semiconductor chip 56 (GaN-HEMT) according to any one of the above-described embodiments and their variants is secured on the stage 50 of a lead frame, with the die attach material 57 (solder, in this embodiment), for example.
  • the gate pad 10 , the drain pad 12 , and the source pad 11 in the semiconductor chip 56 are connected to the gate lead 51 , the drain lead 53 , and the source lead 52 , through bonding with the Al wire 54 A to 54 C, respectively, for example.
  • the lead frame After resin encapsulation using the transfer mold technique, for example, the lead frame is separated.
  • the semiconductor device according to the present embodiment may be fabricated in the steps set forth above.
  • this PFC circuit includes diode bridge 60 , a choke coil 61 , a first capacitor 62 , a GaN-HEMI 63 included in the above-described semiconductor package, a diode 64 , and a second capacitor 65 .
  • this PFC circuit is configured to include the diode bridge 60 , the choke coil 61 , the first capacitor 62 , GaN-HEMI 63 included in the above-described semiconductor package, the diode 64 , and the second capacitor 65 , mounted over a circuit substrate.
  • the drain lead 53 , the source lead 52 , and the gate lead 51 in the above-described semiconductor package are inserted into a drain lead slot, a source lead slot and a gate lead slot in the circuit substrate, respectively, and are then secured with solder, for example.
  • solder for example.
  • the GaN-HEMI 63 included in the above-described semiconductor package is connected to the PFC circuit formed on the circuit substrate.
  • one terminal of the choke coil 61 and the anode terminal of the diode 64 are connected to the drain electrode 5 in the GaN-HEMI 63 .
  • One terminal of the first capacitor 62 is connected to the other terminal of the choke coil 61
  • one terminal of the second capacitor 65 is connected to the cathode terminal of the diode 64 .
  • the other terminal of the first capacitor 62 , the source electrode 4 in the GaN-HEMT 63 and the other terminal of the second capacitor 65 are grounded.
  • a pair of terminals of the diode bridge 60 is connected to the two terminals of the first capacitor 62 , and the other pair of terminals of the diode bridge 60 is connected to input terminals for receiving an alternating current (AC) voltage.
  • AC alternating current
  • the two terminals of the second capacitor 65 are connected to output terminals for outputting a direct current (DC) voltage.
  • Agate driver which is not illustrated, is connected to the gate electrode 3 in the GaN-HEMT 63 .
  • an AC voltage received through the input terminals is converted into a DC voltage, which is output from the output terminals.
  • the power supply apparatus has an advantage of improving the reliability. More specifically, since this power supply apparatus has a semiconductor chip 56 according to any one of the above-described embodiments and their variants, a reliable power supply apparatus can be constructed.
  • the above-described semiconductor device semiconductor package including a GaN-HEMT or GaN-HEMT
  • the above-described semiconductor device may also be used in electronic appliances (electronic apparatuses), such as non-server computers.
  • the above-described semiconductor device may also be used for other circuits provided in a power supply apparatuses (e.g., DC-DC converters).
  • the present disclosure may be applied to field-effect transistors having other structures as semiconductor stacked structures.
  • a gate electrode includes an Al layer in the above-described embodiments, this is not limiting.
  • the gate electrode may have any structure, as long as the gate electrode includes at least one layer including a material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi (e.g., CoSi 2 ), WSi (e.g., WSi 2 ), NiSi, MoSi (e.g., MoSi 2 ), TiSi (e.g., TiSi 2 ), AlSi (e.g., an Al—Si compound), Al—Cu (e.g., an Al—Cu compound), and AlSiCu (e.g., an Al—Si—Cu compound).
  • a gate insulation film is an AlO film in the above-described embodiments, this is not limiting.
  • the gate insulation film may be any film, as long as the gate insulation film includes at least one layer including a material selected from AlO (e.g., Al 2 O 3 ), SiN, SiO (e.g., SiO 2 ), HfO (e.g., HfO 2 ), and AlN.
  • an insulation film covering the gate insulation film is an AlO film in the above-described embodiments, this is not limiting.
  • the insulation film covering the gate insulation film may be any film, as long as it includes at least one layer including a material selected from AlO (e.g., Al 2 O 3 ), SiN, SiO (e.g., SiO 2 ), HfO (e.g., HfO 2 ), and AlN.
  • AlO e.g., Al 2 O 3
  • SiN e.g., SiN
  • SiO e.g., SiO 2
  • HfO e.g., HfO 2
  • AlN AlN
  • a layer (adhesion layer), provided at least one of between the gate electrode 3 and the electrode material diffusion suppression layer 6 , and between gate insulation film 2 and the electrode material diffusion suppression layer 6 , including at least one layer including any material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi (e.g., CoSi 2 ), WSi (e.g., WSi 2 ), NiSi, MoSi (e.g., MoSi 2 ), TiSi (e.g., TiSi 2 ), AlSi (e.g., an Al—Si compound), AlCu (e.g., an Al—Cu compound), and AlSiCu (e.g., an Al—Si—Cu compound), may be included.
  • a layer (adhesion layer), provided at least one of between the Au interconnection 9 and the electrode material diffusion suppression layer 6 (the second electrode material diffusion suppression layer 6 X), and between the Al layer included in the ohmic electrodes 4 and 5 and the electrode material diffusion suppression layer 6 (the second electrode material diffusion suppression layer 6 X), including at least one layer including any material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi (e.g., CoSi 2 ), WSi (e.g., WSi 2 ), NiSi, MoSi (e.g., MoSi 2 ), TiSi (e.g., TiSi 2 ), AlSi (e.g., an Al—Si compound), AlCu (e.g., an Al—Cu compound), and AlSiCu (e.g., an Al—Cu compound), and AlSiCu (e.g., an
  • an Au interconnection may be made from other low-resistance interconnection materials.
  • a layer (adhesion layer), provided at least one of between the Au interconnection 9 and the barrier metal 8 , and between the Al layer included in the ohmic electrodes 4 and 5 and the barrier metal layer 8 including at least one layer including any material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi (e.g., CoSi 2 ), WSi (e.g., WSi 2 ), NiSi, MoSi (e.g., MoSi 2 ), TiSi (e.g., TiSi 2 ), AlSi (e.g., an Al—Si compound), AlCu (e.g., an Al—Cu compound
  • a layer (adhesion layer), provided between the gate electrode 3 and the gate insulation film 2 including at least one layer including any material selected from Pt, Ir, W, Ni, Ti, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, CoSi (e.g., CoSi 2 ), WSi (e.g., WSi 2 ), NiSi, MoSi (e.g., MoSi 2 ), TiSi (e.g., TiSi 2 ), AlSi (e.g., an Al—Si compound), AlCu (e.g., an Al—Cu compound), and AlSiCu (e.g., an Al—Si—Cu compound), may be included.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
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