US20110103391A1 - System and method for high-performance, low-power data center interconnect fabric - Google Patents

System and method for high-performance, low-power data center interconnect fabric Download PDF

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Publication number
US20110103391A1
US20110103391A1 US12/794,996 US79499610A US2011103391A1 US 20110103391 A1 US20110103391 A1 US 20110103391A1 US 79499610 A US79499610 A US 79499610A US 2011103391 A1 US2011103391 A1 US 2011103391A1
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United States
Prior art keywords
node
switch
nodes
data
mac
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US12/794,996
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English (en)
Inventor
Mark Bradley Davis
David James Borland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SMOOTH STONE Inc
Silicon Valley Bank Inc
III Holdings 2 LLC
Original Assignee
SMOOTH STONE Inc C/O BARRY EVANS
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Application filed by SMOOTH STONE Inc C/O BARRY EVANS filed Critical SMOOTH STONE Inc C/O BARRY EVANS
Priority to US12/794,996 priority Critical patent/US20110103391A1/en
Assigned to SMOOTH STONE, INC. reassignment SMOOTH STONE, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BORLAND, DAVID JAMES, DAVIS, MARK BRADLEY
Priority to CN201510827453.6A priority patent/CN105357152B/zh
Priority to KR1020127013870A priority patent/KR101516216B1/ko
Priority to CN201080060153.5A priority patent/CN102668473B/zh
Priority to EP10827330.1A priority patent/EP2494748B1/en
Priority to CN201510217826.8A priority patent/CN104836755B/zh
Priority to PCT/US2010/053227 priority patent/WO2011053488A1/en
Priority to EP16163413.4A priority patent/EP3070894B1/en
Priority to JP2012536877A priority patent/JP2013509808A/ja
Assigned to CALXEDA, INC. reassignment CALXEDA, INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: SMOOTH-STONE, INC.
Publication of US20110103391A1 publication Critical patent/US20110103391A1/en
Priority to US13/234,054 priority patent/US9876735B2/en
Priority to US13/453,086 priority patent/US8599863B2/en
Priority to US13/475,722 priority patent/US9077654B2/en
Priority to US13/475,713 priority patent/US9054990B2/en
Priority to US13/624,725 priority patent/US9405584B2/en
Priority to US13/624,731 priority patent/US9075655B2/en
Priority to US13/662,759 priority patent/US9465771B2/en
Priority to US13/692,741 priority patent/US9311269B2/en
Priority to US13/705,386 priority patent/US8745302B2/en
Priority to US13/705,340 priority patent/US9008079B2/en
Priority to US13/705,414 priority patent/US8737410B2/en
Priority to US13/705,428 priority patent/US20130097351A1/en
Priority to US13/728,308 priority patent/US9262225B2/en
Assigned to SILICON VALLEY BANK reassignment SILICON VALLEY BANK SECURITY AGREEMENT Assignors: CALXEDA, INC.
Priority to US14/052,723 priority patent/US9680770B2/en
Assigned to CALXEDA, INC. reassignment CALXEDA, INC. RELEASE OF SECURITY INTEREST Assignors: SILICON VALLEY BANK
Assigned to SILICON VALLEY BANK reassignment SILICON VALLEY BANK ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CALXEDA, INC.
Priority to US14/334,178 priority patent/US9479463B2/en
Priority to US14/334,931 priority patent/US9454403B2/en
Assigned to III HOLDINGS 2, LLC reassignment III HOLDINGS 2, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SILICON VALLEY BANK
Assigned to SILICON VALLEY BANK reassignment SILICON VALLEY BANK CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPL. NO. 13/708,340 PREVIOUSLY RECORDED AT REEL: 030292 FRAME: 0207. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Assignors: CALXEDA, INC.
Priority to US14/725,543 priority patent/US9509552B2/en
Priority to US15/042,489 priority patent/US10135731B2/en
Priority to US15/078,115 priority patent/US9977763B2/en
Priority to US15/254,111 priority patent/US9866477B2/en
Priority to US15/270,418 priority patent/US9929976B2/en
Priority to US15/281,462 priority patent/US20170115712A1/en
Priority to US15/357,332 priority patent/US10140245B2/en
Priority to US15/360,668 priority patent/US9749326B2/en
Priority to US15/672,418 priority patent/US10050970B2/en
Priority to US16/198,619 priority patent/US10877695B2/en
Priority to US17/089,207 priority patent/US11526304B2/en
Priority to US17/985,241 priority patent/US11720290B2/en
Priority to US18/209,801 priority patent/US20240012581A1/en
Abandoned legal-status Critical Current

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Definitions

  • the disclosure relates generally to a switching fabric for a computer-based system.
  • FIGS. 1A and 1B show a classic data center network aggregation as is currently well known.
  • FIG. 1A shows a diagrammatical view of a typical network data center architecture 100 wherein top level switches 101 a - n are at the tops of racks 102 a - n filled with blade servers 107 a - n interspersed with local routers 103 a - f . Additional storage routers and core switches. 105 a - b and additional rack units 108 a - n contain additional servers 104 e - k and routers 106 a - g FIG.
  • 1 b shows an exemplary physical view 110 of a system with peripheral servers 111 a - bn arranged around edge router systems 112 a - h , which are placed around centrally located core switching systems 113 .
  • a - bn arranged around edge router systems 112 a - h , which are placed around centrally located core switching systems 113 .
  • Typically such an aggregation 110 has 1-Gb Ethernet from the rack servers to their top of rack switches, and often 10 Gb Ethernet ports to the edge and core routers.
  • FIGS. 1A and 1B illustrate a typical data center system
  • FIG. 2 is an overview of a network aggregation system
  • FIG. 3 illustrates an overview of an exemplary data center in a rack system
  • FIG. 4 illustrates a high-level topology of a network aggregating system
  • FIG. 5A illustrates a block diagram of an exemplary switch of the network aggregation system
  • FIG. 5B illustrates the MAC address encoding
  • FIG. 6 illustrates a first embodiment of a broadcast mechanism of the network aggregation system
  • FIG. 7 illustrates an example of unicast routing of the network aggregation system
  • FIG. 8 illustrates an example of fault-resistant unicast routing of the network aggregation system
  • FIG. 9 illustrates a second embodiment of a broadcast mechanism of the network aggregation system.
  • the disclosure is particularly applicable to a network aggregation system and method as illustrated and described below and it is in this context that the disclosure will be described. It will be appreciated, however, that the system and method has greater utility since the system and method can be implemented using other elements and architectures that are within the scope of the disclosure and the disclosure is not limited to the illustrative embodiments described below.
  • the system and method also supports a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology.
  • each node in the system maybe be a combination computational/switch node, or just a switch node, and input/output (I/O) can reside on any node as described below in more detail.
  • the system may also provide a system with a segmented Ethernet Media Access Control (MAC) architecture which may have a method of re-purposing MAC IP addresses for inside MACs and outside MACs, and leveraging what would normally be the physical signaling for the MAC to feed into the switch.
  • MAC Seged Ethernet Media Access Control
  • the system may also provide a method of non-spoofing communication, as well as a method of fault-resilient broadcasting, which may have a method of unicast misrouting for fault resilience.
  • a spoofing attack is a situation in which one person or program successfully masquerades as another by falsifying data and thereby gaining an illegitimate advantage.
  • the system may also provide a rigorous security between the management processors, such that management processors can “trust” one another.
  • management processors can “trust” one another.
  • FIG. 5A which is described below in more detail
  • the software running on the management processor is trusted because a) the vendor (in this case Smooth-Stone) has developed and verified the code, b) non-vendor code is not allowed to run on the processor.
  • Maintaining a Trust relationship between the management processors allow them to communicate commands (e.g. reboot another node) or request sensitive information from another node without worrying that a user could spoof the request and gain access to information or control of the system.
  • the system may also provide a network proxy that has an integrated microcontroller in an always-on power domain within a system on a chip (SOC) that can take over network proxying for the larger onboard processor, and which may apply to a subtree.
  • SOC system on a chip
  • the system also provide a multi-domaining technique that can dramatically expand the size of a routable fat tree like structure with only trivial changes to the routing header and the routing table.
  • FIG. 2 illustrates a network aggregation system 300 .
  • the network aggregation supports one or more high speed links 301 (thick lines), such as a 10 -Gb/sec Ethernet communication, that connect an aggregation router 302 and one or more racks 303 , such as three racks 303 a - c as shown in FIG. 3 .
  • the network aggregation system provides multiple high-speed 10 Gb paths, represented by thick lines, between one or more Smooth-Stone computing unit 306 a - d , such as server computers, on shelves within a rack. Further details of each Smooth-Stone computing unit are described in more detail in U.S. Provisional Patent Application Ser. No.
  • An embedded switch 306 a - d in the Smooth-Stone computing units can replace a top-of-rack switch, thus saving a dramatic amount of power and cost, while still providing a 10 Gb Ethernet port to the aggregation router 302 .
  • the network aggregation system switching fabric can integrate traditional Ethernet (1 Gb or 10 Gb) into the XAUI fabric, and the Smooth-Stone computing units can act as a top of rack switch for third-party Ethernet connected servers.
  • a middle rack 303 b illustrates another configuration of a rack in the network aggregation system in which one or more Smooth-Stone computing units 306 e, f can integrate into existing data center racks that already contain a top-of-rack switch 308 a .
  • the IT group can continue to have their other computing units connected via 1 Gb Ethernet up to the existing top-of-rack switch and the internal Smooth-Stone computing units can be connected via 10 Gb XAUI fabric and they can integrate up to the existing top-of-rack switch with either a 1 Gb or 10 Gb Ethernet interconnects as shown in FIG. 2 .
  • a third rack 303 c illustrates a current way that data center racks are traditionally deployed.
  • the thin red lines in the third rack 303 c represent 1 Gb Ethernet.
  • the current deployments of data center racks is traditionally 1 Gb Ethernet up to the top-of-rack switch 308 b , and then 10 Gb (thick red line 301 ) out from the top of rack switch to the aggregation router.
  • all servers are present in an unknown quantity, while they are pictured here in finite quantities for purposes of clarity and simplicity.
  • no additional routers are needed, as they operate their own XAUI switching fabric, discussed below.
  • FIG. 3 shows an overview of an exemplary “data center in a rack” 400 according to one embodiment of the system.
  • the “data center in a rack” 400 may have 10-Gb Ethernet PHY 401 a - n and 1-Gb private Ethernet PHY 402 .
  • Large computers (power servers) 403 a - n support search; data mining; indexing; Apache Hadoop, a Java software framework; MapReduce, a software framework introduced by Google to support distributed computing on large data sets on clusters of computers; cloud applications; etc.
  • Computers (servers) 404 a - n with local flash and/or solid-state disk (SSD) support search, MySQL, CDN, software-as-a-service (SaaS), cloud applications, etc.
  • Data center 400 has an array 406 of hard disks, e.g., in a Just a Bunch of Disks (JBOD) configuration, and, optionally, Smooth-Stone computing units in a disk form factor (for example, the green boxes in arrays 406 and 407 ), optionally acting as disk controllers.
  • Hard disk servers or SS disk servers may be used for web servers, user applications, and cloud applications, etc.
  • an array 407 of storage servers and historic servers 408 a, b (any size, any vendor) with standard Ethernet interfaces for legacy applications.
  • the data center in a rack 400 uses a proprietary system interconnect approach that dramatically reduces power and wires and enables heterogeneous systems, integrating existing Ethernet-based servers and enabling legacy applications.
  • a complete server or storage server is put in a disk or SSD form factor, with 8-16 SATA interfaces with 4 ServerNodesTM and 8 PCIe x4 interfaces with 4 ServerNodesTM. It supports disk and/or SSD+ServerNodeTM, using a proprietary board paired with a disk(s) and supporting Web server, user applications, cloud applications, disk caching, etc.
  • the Smooth-Stone XAUI system interconnect reduces power, wires and the size of the rack. There is no need for high powered, expensive Ethernet switches and high-power Ethernet Phys on the individual servers. It dramatically reduces cables (cable complexity, costs, significant source of failures). It also enables a heterogeneous server mixture inside the rack, supporting any equipment that uses Ethernet or SATA or PCIe. It can be integrated into the system interconnect.
  • the herein presented aspects of a server-on-a-chip (SOC) with packet switch functionality are focused on network aggregation.
  • SOC server-on-a-chip
  • the SOC is not a fully functionally equivalent to an industry-standard network switch, such as, for example, a Cisco switch or router. But for certain applications discussed throughout this document, it offers a better price/performance ratio as well as a power/performance ratio.
  • It contains a layer 2 packet switch, with routing based on source/destination MAC addresses. It further supports virtual local area network (VLAN), with configurable VLAN filtering on domain incoming packets to minimize unnecessary traffic in a domain.
  • VLAN virtual local area network
  • the embedded MACs within the SOC do have complete VLAN support providing VLAN capability to the overall SOC without the embedded switch explicitly having VLAN support.
  • management processor can also wake up the system by management processor notifying the management processor on link state transitions to reprogram routing configurations to route around faults.
  • Such functionality does not require layer3 (or above) processing (i.e., it is not a router). It also does not offer complete VLAN support, support for QoS/CoS, address learning, filtering, spanning tree protocol (STP), etc.
  • FIG. 4 shows a high-level topology 800 of the network system that illustrates XAUI connected SoC nodes connected by the switching fabric.
  • the 10 Gb Ethernet ports Eth 0 801 a and Eth 1 801 b come from the top of the tree.
  • Ovals 802 a - n are Smooth-Stone nodes that comprise both computational processors as well as the embedded switch.
  • the nodes have five XAUI links connected to the internal switch.
  • the switching layers use all five XAUI links for switching.
  • the vast majority of trees and fat trees have active nodes only as leaf nodes, and the other nodes are pure switching nodes. This approach makes routing much more straightforward.
  • Topology 800 has the flexibility to permit every node to be a combination computational and switch node, or just a switch node. Most tree-type implementations have I/O on the leaf nodes, but topology 800 let the I/O be on any node. In general, placing the Ethernet at the top of the tree minimizes the average number of hops to the Ethernet.
  • FIG. 5A illustrates one example implementation of an individual node of the cluster.
  • the A9 Cores ( 905 ) may be optionally enabled, or could be just left powered-off. So the upper level switching nodes (N 10 -N 21 ) in FIG. 6 can be used as pure switching elements (like traditional implementations), or we can power on the A9 Cores module and use them as complete nodes within the computing cluster.
  • FIG. 5 a shows a block diagram of an exemplary switch 900 according to one aspect of the system and method disclosed herein. It has four areas of interest 910 a - d .
  • Area 910 a corresponds to Ethernet packets between the CPUs and the inside MACs.
  • Area 910 b corresponds to Ethernet frames at the Ethernet physical interface at the inside MACs, that contains the preamble, start of frame, and inter-frame gap fields.
  • Area 910 c corresponds to Ethernet frames at the Ethernet physical interface at the outside MAC, that contains the preamble, start of frame, and inter-frame gap fields.
  • Area 910 d corresponds to Ethernet packets between the processor of routing header 901 and outside MAC 904 .
  • This segmented MAC architecture is asymmetric.
  • the inside MACs have the Ethernet physical signaling interface into the routing header processor, and the outside MAC has an Ethernet packet interface into the routing header processor.
  • the MAC IP is re-purposed for inside MACs and outside MACs, and what would normally be the physical signaling for the MAC to feed into the switch is leveraged.
  • MAC configuration is such that the operating system device drivers of A9 cores 905 manage and control inside Eth 0 MAC 902 and inside ETH 1 MAC 903 .
  • the device driver of management processor 906 manages and controls Inside Eth 2 MAC 907 .
  • Outside Eth MAC 904 is not controlled by a device driver.
  • MAC 904 is configured in Promiscuous mode to pass all frames without any filtering for network monitoring. Initialization of this MAC is coordinated between the hardware instantiation of the MAC and any other necessary management processor initialization.
  • Outside Eth MAC 904 registers are visible to both A9 905 and management processor 906 address maps. Interrupts for Outside Eth MAC 904 are routable to either the A9 or management processor.
  • the XGMAC supports several interruptible events that the CPUs may want to monitor, including any change in XGMII link fault status, hot-plugging or removal of PHY, alive status or link status change, and any RMON counter reaching a value equal to the threshold register.
  • the routing frame header processor may standardize these fields.
  • the XAUI interface may need some or all of these fields.
  • the routing header processor at area 910 d needs to add these going into the switch, and to remove them leaving the switch.
  • these three fields may be removed (if the XAUI interface allows it).
  • the routing header processor at area 910 b will need to strip these going into the switch, and add them back leaving the switch.
  • the routing frame header processor receives an Ethernet frame from a MAC, sending a routing frame to the switch. It also standardizes the preamble, start of frame, and inter-frame gap fields, prepends a routing header, and receives a routing frame from the switch, sending the Ethernet frame into a MAC. This processor then strips the routing header and standardizes the preamble, start of frame, and inter-frame gap fields. Note that all frames that are flowing within the fabric are routing frames, not Ethernet frames. The Ethernet frame/routing frame conversion is done only as the packet is entering or leaving the fabric via a MAC. Note also that the routing logic within the switch may change fields within the routing frame. The Ethernet frame is never modified (except the adding/removing of the preamble, start of frame, and inter-frame gap fields).
  • the routing frame is composed of the routing frame header plus the core part of the Ethernet frame, and is structured as shown in Table 1, below:
  • bit sizing is 4096 nodes ⁇ 12 bit node IDs. These fields may be resized during implementation as needed.
  • the routing frame header consists of the fields shown in Table 2, below:
  • a switch If a switch receives a packet that fails the checksum, the packet is dropped, a statistic counter is incremented, and the management processor is notified.
  • the routing frame processor differentiates between several destination MAC address encodings.
  • MAC addresses are formatted as shown in FIG. 5 b .
  • the following table describes the usage of the 3 byte OUI and 3 byte NIC specific field within the MAC address.
  • One of the novel aspects of the system and method disclosed herein is the use of additional address bits to encode an internal to external MAC mapping, as shown also in the Table 3, below, in the second entry under “Fabric Internal Node local address Hits MAC Lookup CAM”.
  • Neighbor Multicast bit 12 bits: Packet sent Multicast set SS_NEIGHBOR_MCAST_MAGIC through all Locally 12 bits: Reserved XAUI links to administered neighboring OUI Switch nodes and not OUI rebroadcast to other nodes
  • SS_MAC_NODE_ENCODED_MAGIC and SS_MAC_LINK_ENCODED_MAGIC are constant identifiers used for uniquely identifying these MAC address types.
  • the term “magic number” is a standard industry term for a constant numerical or text value used to identify a file format or protocol. These magic numbers are configured in two registers (magicNodeEncodedMAC and magicLinkEncodedMAC that default to standard values during hardware initialization, but allow the management processor software to change them if necessary.
  • the header processor contains a MAC Lookup CAM (Content Addressable Memory), macAddrLookup, that maps from 6 byte MAC addresses to 12-bit Node IDs, as shown in Table 4, below.
  • MAC Lookup CAM Content Addressable Memory
  • macAddrLookup maps from 6 byte MAC addresses to 12-bit Node IDs, as shown in Table 4, below.
  • the number of rows in this CAM is implementation dependent, but would be expected to be on the order of 256-1024 rows.
  • the management processor initializes the CAM with Node ID mappings for all the nodes within the SS fabric. There are two types of rows, depending upon the setting of the Node Local bit for the row.
  • the Node Local field allows a 4:1 compression of MAC addresses in the CAM for default MAC addresses, mapping all four MACs into a single row in the CAM table, which is Table 5, below.
  • a Node Encoded Address refers to a Smooth Stone Taken from Local assigned MAC address for a node. It encodes the port # low 2 bits of (MAC0, MAC1, management processor, Rsvd) into a 2- MAC Address bit Port ID in the lowest two bits of the NIC address Input field. Ignores low 2 bits during match. Arbitrary 0 Matches against all 6 bytes Taken from CAM Output field
  • the arbitrary rows in the CAM allow mapping of the MAC address aliases to the nodes.
  • Linux and the MACs
  • the MAC addresses to be reassigned on a network interface (e.g., with ifconfig eth 0 hw ether 00:80:48:BA:d1:30). This is sometime used by virtualization/cloud computing to avoid needing to re-ARP after starting a session.
  • the switch architecture provides for a secondary MAC Lookup CAM that only stores the 3 bytes of the NIC Specific part of the MAC address for those addresses that match the Switch OUI.
  • the availability of this local OUI CAM is determined by the implementation. See Table 6, below.
  • the maximum number of nodes limitation for three types of MAC address encodings may be evaluated as follows:
  • Default MAC Addressees management processor sets Node Local mappings for each of the nodes in the fabric. There is one entry in the CAM for each node. Max # of nodes is controlled by maximum # of rows in the MAC Address Lookup CAM.
  • Node Encoded Addresses All the MACs are reprogrammed to use Node Encoded Addresses. In this way the Node IDs are directly encoded into the MAC addresses. No entries in the MAC Lookup CAM are used. Max # of nodes is controlled by maximum # of rows in the Unicast lookup table (easier to make big compared to the Lookup CAM). Note that this also gives us some risk mitigation in case the MAC Lookup CAM logic is busted. Provides use case for the node encoded addresses idea.
  • Arbitrary MAC Address Aliases Takes a row in the CAM. As an example, a 512-row CAM could hold 256 nodes (Node local addresses)+1 MAC address alias per node.
  • the management processor Since the Lookup CAM is only accessed during Routing Header creation, the management processor actually only needs to populate a row if the MAC address within the fabric is being used as a source or destination MAC address within a packet. In other words, if two nodes never will talk to each other, a mapping row does not need to be created. But usually the management processor won't have that knowledge, so it's expected that mappings for all nodes are created in all nodes. Also note that even if an entry is not created in the Lookup CAM, the routing will actually still succeed by routing the packet out the Ethernet gateway, through an external router, back into the Fabric, to the destination node.
  • Table 7 defines how to set fields within the Routing Header for all the fields except for destination node and port.
  • Table 8 defines how to set destination node and port for addresses within the fabric:
  • Table 9 defines how to set destination node and port for addresses outside the fabric:
  • management processor software architecture of the system and method disclosed here currently depends on the ability of management processor nodes to “trust” each other. This more rigorous security on management processor to management processor communication is desirable, as well a better security on private management LANs across the fabric.
  • This fabric issue may be mitigated by simply defining, for environments that require multiple “hard” security domains, that customers simply don't mix security domains within a fabric. In such cases, it may be possible to connect 14-node boards to the top of rack switch, allowing customers to have VLAN granularity control of each 14-node board.
  • the multi-domain fabric architecture addresses the lack of VLAN support by creating secure “tunnels” and domains across the fabric, and it can interoperate with VLAN protected router ports on a 1:1 basis.
  • the approach to domain management in the system and method disclosed here is as follows: Support multiple domain IDs within the fabric. Allow each of the MACs within a node (management processor, MAC0, MAC1, Gateway) to be assigned to a domain ID individually (and tagged with domain 0 if not set). Allow each of the MACs within a node to have a bit indicating access to the management domain.
  • the domain IDs associated with a MAC could only be assigned by the management processor, and could not be altered by the A9.
  • the routing frame processor would tag the routing frame with the domain ID and management domain state associated with that MAC.
  • Domains would provide the effect of tunnels or VLANs, in that they keep packets (both unicast and multicast) within that domain, allowing MACs outside that domain to be able to neither sniff or spoof those packets. Additionally, this approach would employ a five-bit domain ID. It would add options to control domain processing, such as, for example, a switch with a boolean per MAC that defines whether packets are delivered with non-defined (i.e., zero) domain ID, or a switch that has a boolean per MAC that defines whether packets are delivered with defined (non-zero) but non-matching domain IDs. A further option in the switch could turn off node encoded MAC addresses per MAC (eliminating another style of potential attack vector).
  • the management domain bit on all management processor MACs could be marked.
  • the management processor should route on domain 1 (by convention).
  • domain 1 by convention.
  • Such a technique allows all the management processor's to tunnel packets on the management domain so that they cannot be inspected or spoofed by any other devices (inside or outside the fabric), on other VLANs or domains.
  • a gateway MAC that has the management domain bit set could be assigned, keeping management packets private to the management processor domain.
  • the switch fabric could support “multi-tenant” within itself, by associating each gateway MAC with a separate domain.
  • each gateway MAC could connect to an individual port on an outside router, allowing that port to be optionally associated with a VLAN. As the packets come into the gateway, they are tagged with the domain ID, keeping that traffic private to the MACs associated with that domain across the fabric.
  • the switch supports a number of registers (aka CSRs, aka MMRs) to allow software or firmware to control the switch.
  • CSRs aka MMRs
  • MMRs magnetic resonance registers
  • the actual layout of these registers will be defined by the implementation.
  • the fields listed in Table 10 are software read/write. All these registers need to have a mechanism to secure them from writing from the A9 (could be secure mode or on a management processor private bus).
  • the use case here is where the management processor wants to see the gratuitous ARPs that are locally initiated so that it can communicate across the management processor fabric and add corresponding entries into the local unicast routing tables.
  • macAddrLookup Lookup CAM which is MAC address lookup CAM to convert MAC described elsewhere in addresses to Node IDs.
  • macAcceptOtherDomain[MAC] 1 bit[MAC] Defines that the MAC accepts packets that are tagged with a non-zero, non-matching domain ID.
  • macAcceptZeroDomain[MAC] 1 bit[MAC] Defines that the MAC accepts packets that are not tagged with a domain (i.e. 0 domain)
  • macDomainID[MAC] 5 bits[MAC] Defines the Domain ID for each of the 4 MACs. A value of 0 indicates that the domain ID for that MAC is not set.
  • macMgmtDomain[MAC] 1 bit[MAC] Defines that the MAC may access the management domain.
  • magicNodeEncodedMAC 10 bits Magic number for Node Encoded MAC addresses
  • magicLinkEncodedMAC 12 bits Magic number for Link Encoded MAC addresses maxTTL 6 bits Maximum TTL count allowed in a routing header. Exceeding this number of hops causes the switch to drop the packet, update a statistic counter, and inform the management processor.
  • myNodeID 12 bits Need not be contiguous. Subtree's should ideally be numbered within a range to facilitate subtree network proxying.
  • portRemap[INT_PORTS]; Array [INT_PORTS] x Allows remapping of incoming destination 2 bits port IDs to the internal port where it'll be delivered. This register defaults to an equivalence remapping. An example of where this will get remapped is during Network Proxy where the management processor will remap MAC0 packets to be sent to the management processor.
  • INT_PORTS 4. Array elements are the Ports enumeration (management processor, MAC0, MAC1, OUT). 2 bits contents is the Ports enumeration.
  • primaryEthGatewayNode[INT_PORTS] Array [INT_PORTS] Specifies Node ID of primary Ethernet of 12-bit gateway for this node.
  • promiscuousPortVec 4 bits Can be configured for Promiscuous Mode allowing traffic on one or more links to be snooped by the management processor or A9s in order to collect trace data or to implement an Intruder Detection System (IDS). This causes all traffic passing through the switch to be copied to the internal ports defined by this port vector.
  • IDMS Intruder Detection System
  • routeForeignMACsOut 1 bit When enabled, a MAC address that does not contain a myOUI address, will not check the MAC lookup CAM, and will get treated as a MAC lookup CAM miss, thus getting routed to the gateway port.
  • secondaryEthGatewayNode[INT_PORTS] Array [INT_PORTS] Specifies Node ID of secondary Ethernet of 12-bit gateway. Incoming (from OUT) packets routing through the fabric will be sent here.
  • unicastPortsFromOtherExt 1 bit An incoming unicast from an external Gateways gateway will get the gateway node put into the source node field of the routing header. Upon reaching the destination node, this bit will be checked. When the bit is clear, the external gateway node must match the destination gateway node for it to be delivered to internal ports.
  • the registers shown in Table 11 are contained within the Switch implementation, but need not be software accessible.
  • FIG. 6 shows an exemplary broadcast mechanism 1000 according to one aspect of the system and method disclosed herein.
  • the link between nodes N 101001 and N 21 1002 is down, as indicated by the dashed line 1003 .
  • the source node puts an incremented broadcast ID for that source node in the routing frame (rframe.bcastID).
  • N 04 1004 initiates a broadcast to all neighbors, i.e., N 11 1105 .
  • N 11 has not seen the packet, so it broadcasts to all non-incoming neighbors, which, in this example, are N 21 1002 , N 20 1006 , N 03 1007 , and N 05 1008 , and accepts the packet internally.
  • Nodes N 03 and N 05 haven't seen the packet, so they accept the broadcast internally and are done.
  • N 21 hasn't seen the packet, so it broadcasts the packet to all active, non-incoming links (e.g., N 10 , N 12 1009 ), and accepts the packet internally.
  • N 20 broadcasts the packet to all active, non-incoming links (i.e., N 12 ), and accepts the packet internally.
  • N 10 broadcasts down to N 00 1010 , N 01 1011 , and N 02 1012 .
  • N 12 rebroadcasts to N 06 1013 , N 07 1014 , N 08 1015 and to one of N 21 and N 20 (the one it didn't get the broadcast packet from). Note that one of N 20 and N 21 , and N 12 , see the packet twice. They take action only on their first instance, the secondary times it hits the broadcast CAM as a duplicate, and the packet is ignored.
  • Unicast routing (as shown in FIG. 7 ) is responsible for routing non-multicast (i.e. unicast) packets to the next node. This is done by utilizing a software computed unicastRoute[ ] next node routing table that provides a vector of available links to get to the destination node.
  • the packet will be routed upward until a common parent of (source, destination) is reached. This upward routing can be deterministic, oblivious, or adaptive. The packet is then routed downward to the destination using deterministic routing.
  • FIG. 7 illustrates a packet routing from node N 00 1010 to N 08 1015 .
  • the packet is routed in the upward phase to the common ancestor (N 21 ) through node N 10 1001 , and then a descent phase to the destination.
  • the first candidate link could be chosen deterministically, or an adaptive algorithm could dynamically select either of the links. But, once the node reaches the common ancestor and turns downward, there are no redundant paths (in general) for the node to reach the destination.
  • link weights should represent:
  • register enableMisrouting that allows software to control whether the switch will initiate the misrouting algorithm.
  • Multi-Domaining whose goal is to increase the addressability of nodes to a large number of nodes (e.g., 64K nodes), without having to increase the size of the unicast routing table to 64K nodes.
  • the unicast routing table is a single-dimension array indexed by node number (i.e. 0 to MAX_NODES ⁇ 1), where a typical implementation will be between 256 and 4K nodes.
  • network proxy is the ability of the main processors ( FIG. 5A , 905 ) to maintain network presence while in a low-power sleep/hibernation state, and intelligently wake when further processing is required.
  • the computer to be woken is shut down (sleeping, hibernating, or soft off; i.e., ACPI state G1 or G2), with power reserved for the network card, but not disconnected from its power source.
  • the network card listens for a specific packet containing its MAC address, called the magic packet, broadcast on the broadcast address for that particular subnet (or an entire LAN, though this requires special hardware or configuration).
  • the magic packet is sent on the data link or layer 2 in the OSI model and broadcast to all NICs within the network of the broadcast address; the IP-address (layer 3 in the OSI model) is not used.
  • the network card checks the packet for the correct information. If the magic packet is valid, the network card takes the computer out of hibernation or standby, or starts it up.
  • the magic packet is a broadcast frame containing anywhere within its payload: 6 bytes of ones (resulting in hexadecimal FF FF FF FF FF FF FF), followed by sixteen repetitions of the target computer's MAC address. Since the magic packet is only scanned for the string above, and not actually parsed by a full protocol stack, it may be sent as a broadcast packet of any network- and transport-layer protocol. It is typically sent as a UDP datagram to port 0, 7 or 9, or, in former times, as an IPX packet.
  • the management processor can support these Wake-On-LAN packets. It will get these broadcast packets, will know the MAC addresses for the other MACs on the node, and be able to wake up the main processor as appropriate. No further functionality is needed in the switch to support these Wake-on-LAN packets.

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US12/794,996 US20110103391A1 (en) 2009-10-30 2010-06-07 System and method for high-performance, low-power data center interconnect fabric
JP2012536877A JP2013509808A (ja) 2009-10-30 2010-10-19 高性能、低電力データセンター相互接続構造のためのシステム及び方法
CN201510217826.8A CN104836755B (zh) 2009-10-30 2010-10-19 用于高性能、低功率数据中心互连结构的系统和方法
EP16163413.4A EP3070894B1 (en) 2009-10-30 2010-10-19 Multiprocessor system with hibernation state
KR1020127013870A KR101516216B1 (ko) 2009-10-30 2010-10-19 고성능, 저전력 데이터 센터 상호접속 패브릭에 대한 시스템 및 방법
CN201080060153.5A CN102668473B (zh) 2009-10-30 2010-10-19 用于高性能、低功率数据中心互连结构的系统和方法
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CN201510827453.6A CN105357152B (zh) 2009-10-30 2010-10-19 用于高性能、低功率数据中心互连结构的系统和方法
PCT/US2010/053227 WO2011053488A1 (en) 2009-10-30 2010-10-19 System and method for high-performance, low-power data center interconnect fabric
US13/234,054 US9876735B2 (en) 2009-10-30 2011-09-15 Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect
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US13/475,713 US9054990B2 (en) 2009-10-30 2012-05-18 System and method for data center security enhancements leveraging server SOCs or server fabrics
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US13/624,725 US9405584B2 (en) 2009-10-30 2012-09-21 System and method for high-performance, low-power data center interconnect fabric with addressing and unicast routing
US13/624,731 US9075655B2 (en) 2009-10-30 2012-09-21 System and method for high-performance, low-power data center interconnect fabric with broadcast or multicast addressing
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US15/254,111 US9866477B2 (en) 2009-10-30 2016-09-01 System and method for high-performance, low-power data center interconnect fabric
US15/270,418 US9929976B2 (en) 2009-10-30 2016-09-20 System and method for data center security enhancements leveraging managed server SOCs
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US18/209,801 US20240012581A1 (en) 2009-10-30 2023-06-14 Memcached Server Functionality in a Cluster of Data Processing Nodes

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US12/889,721 Continuation-In-Part US20140359323A1 (en) 2009-09-24 2010-09-24 System and method for closed loop physical resource control in large, multiple-processor installations
US13/284,855 Continuation-In-Part US20130107444A1 (en) 2009-09-24 2011-10-28 System and method for flexible storage and networking provisioning in large scalable processor installations
US13/475,713 Continuation-In-Part US9054990B2 (en) 2009-09-24 2012-05-18 System and method for data center security enhancements leveraging server SOCs or server fabrics
US13/527,498 Continuation-In-Part US9069929B2 (en) 2009-09-24 2012-06-19 Arbitrating usage of serial port in node card of scalable and modular servers
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US13/234,054 Continuation-In-Part US9876735B2 (en) 2009-09-24 2011-09-15 Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect
US13/453,086 Continuation-In-Part US8599863B2 (en) 2009-09-24 2012-04-23 System and method for using a multi-protocol fabric module across a distributed server interconnect fabric
US13/475,713 Continuation-In-Part US9054990B2 (en) 2009-09-24 2012-05-18 System and method for data center security enhancements leveraging server SOCs or server fabrics
US13/475,722 Continuation-In-Part US9077654B2 (en) 2009-09-24 2012-05-18 System and method for data center security enhancements leveraging managed server SOCs
US13/624,731 Division US9075655B2 (en) 2009-10-30 2012-09-21 System and method for high-performance, low-power data center interconnect fabric with broadcast or multicast addressing
US13/624,725 Division US9405584B2 (en) 2009-10-30 2012-09-21 System and method for high-performance, low-power data center interconnect fabric with addressing and unicast routing
US13/662,759 Continuation-In-Part US9465771B2 (en) 2009-09-24 2012-10-29 Server on a chip and node cards comprising one or more of same
US13/692,741 Continuation-In-Part US9311269B2 (en) 2009-10-30 2012-12-03 Network proxy for high-performance, low-power data center interconnect fabric
US13/705,414 Continuation US8737410B2 (en) 2009-10-30 2012-12-05 System and method for high-performance, low-power data center interconnect fabric
US13/705,386 Continuation US8745302B2 (en) 2009-10-30 2012-12-05 System and method for high-performance, low-power data center interconnect fabric
US13/705,428 Continuation US20130097351A1 (en) 2009-10-30 2012-12-05 System and Method for High-Performance, Low-Power Data Center Interconnect Fabric
US13/705,340 Continuation US9008079B2 (en) 2009-10-30 2012-12-05 System and method for high-performance, low-power data center interconnect fabric
US13/728,308 Continuation US9262225B2 (en) 2009-10-30 2012-12-27 Remote memory access functionality in a cluster of data processing nodes
US14/334,931 Continuation US9454403B2 (en) 2009-10-30 2014-07-18 System and method for high-performance, low-power data center interconnect fabric

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US13/624,731 Active US9075655B2 (en) 2009-10-30 2012-09-21 System and method for high-performance, low-power data center interconnect fabric with broadcast or multicast addressing
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US9866477B2 (en) 2018-01-09
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US9008079B2 (en) 2015-04-14
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US20130097351A1 (en) 2013-04-18
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