US20100044237A1 - Method for manufacturing printed circuit boards - Google Patents

Method for manufacturing printed circuit boards Download PDF

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Publication number
US20100044237A1
US20100044237A1 US12/426,276 US42627609A US2010044237A1 US 20100044237 A1 US20100044237 A1 US 20100044237A1 US 42627609 A US42627609 A US 42627609A US 2010044237 A1 US2010044237 A1 US 2010044237A1
Authority
US
United States
Prior art keywords
electrically conductive
metal layer
layer
conductive metal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/426,276
Other languages
English (en)
Inventor
Chung-Jen Tsai
Yu-Cheng Huang
Hung-Yi Chang
Cheng-Hsien Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhen Ding Technology Co Ltd
Original Assignee
Foxconn Advanced Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Foxconn Advanced Technology Inc filed Critical Foxconn Advanced Technology Inc
Assigned to FOXCONN ADVANCED TECHNOLOGY INC. reassignment FOXCONN ADVANCED TECHNOLOGY INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHANG, HUNG-YI, HUANG, YU-CHENG, LIN, CHENG-HSIEN, TSAI, CHUNG-JEN
Publication of US20100044237A1 publication Critical patent/US20100044237A1/en
Assigned to Zhen Ding Technology Co., Ltd. reassignment Zhen Ding Technology Co., Ltd. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: FOXCONN ADVANCED TECHNOLOGY INC.
Abandoned legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025—Abrading, e.g. grinding or sand blasting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0346—Deburring, rounding, bevelling or smoothing conductor edges
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections

Definitions

  • the present disclosure generally relates to printed circuit boards, and particularly, relates to a method for manufacturing printed circuit boards (PCBs).
  • PCBs printed circuit boards
  • a through hole metalizing process is employed in a traditional method for manufacturing double-sided PCBs or multilayer PCBs to establish electrical connection between circuits of different layers.
  • the through hole metalizing process generally includes a step of filling electrically conductive material into a through hole of a PCB substrate having a base and two copper layers formed on opposite surfaces of the base. As such, the conductive material electrically connects the copper layers to each other.
  • the thermal expansion index of the electrically conductive material may be different from that of the copper layers.
  • interspaces are formed between the conductive material and the PCB substrate.
  • etchant may be lodged into the interspaces and corrode the PCB substrate.
  • FIG. 1 is a flow chart showing a method for manufacturing a PCB according to a first embodiment.
  • FIG. 2 is a cross-sectional view of a substrate defining a through hole according to the first embodiment.
  • FIG. 3 is similar to FIG. 2 , but showing a protecting layer is applied on an outer surface of the substrate with the through hole exposed.
  • FIG. 4 is similar to FIG. 3 , but showing a first electrically conductive metal layer formed on an inner surface of the substrate defined in the though hole.
  • FIG. 5 is similar to FIG. 4 , but showing a second electrically conductive metal layer formed on the first electrically conductive metal layer and the through hole completely filled by the second electrically conductive metal layer.
  • FIG. 6 is similar to FIG. 5 , but showing the protecting layer removed.
  • FIG. 7 is similar to FIG. 6 , but showing two ends of the second electrically conductive metal layer smoothened.
  • FIG. 8 is a cross-sectional view of a substrate defining a blind hole according to a second embodiment.
  • FIG. 9 is similar to FIG. 8 , but showing a first electrically conductive metal layer formed on an inner surface defined in the through hole and an outer surface of the substrate.
  • FIG. 10 is similar to FIG. 9 , but showing a protecting layer applied on an outer surface of the substrate.
  • FIG. 11 is similar to FIG. 10 , but showing a second electrically conductive metal layer formed in the blind hole and the blind hole is filled by the second electrically conductive metal layer.
  • FIG. 12 is similar to FIG. 11 , but showing the protecting material attached on the first electrically conductive metal layer removed.
  • FIG. 13 is similar to FIG. 12 , but showing a portion of the first electrically conductive metal layer formed on the outer surface removed.
  • a method for manufacturing a PCB provided in a first embodiment includes the following steps.
  • a double-sided substrate 10 is provided.
  • the substrate 10 includes a base 13 , a first electrically conductive layer 11 and a second electrically conductive layer 12 formed on two opposite surfaces of the base 13 .
  • the first conductive layer 11 has a first outer surface 111
  • the second conductive layer 12 has a second outer surface 121 .
  • the substrate 10 defines a through hole 101 therein passing through the first, second conductive layers 11 , 12 and the base 13 , and has an inner surface 1011 in the through hole 101 .
  • the base 13 is an insulating resin layer, and the first conductive layer 11 and the second conductive layer 12 are made of copper.
  • the thickness of the first conductive layer 11 and the second conductive layer 12 is less than or equal to 10 micrometers, and the diameter of the through hole 101 is in the range from 50 micrometers to 100 micrometers.
  • the base 13 can be an overlapping structure of a unit including an insulating resin layer and two conductive layers disposed on two opposite surfaces of the resin layer.
  • step 2 as shown in FIG. 4 , a first electrically conductive metal layer 20 is formed on the inner surface 1011 of the substrate 10 using an electro-less plating process.
  • a protecting layer 31 is applied onto and fully cover each of the first and second outer surfaces 111 , 121 of the substrate 10 except the through hole 101 .
  • the two protecting layers 31 are configured for protecting the first and second conductive layers 11 , 13 from being plated.
  • the two protecting layers 31 are dry photoresist films attached on the substrate 10 using a laminating process.
  • the two protecting layers 31 can be liquid photoresist layers applied using a coating process, or a known binder layer capable of being manually stripped from the substrate 10 .
  • the first and second outer surfaces 111 , 112 can be firstly cleared using a lye and secondly etched using a known etchant.
  • the substrate 10 is subsequently plated using an electro-less plating process.
  • the inner surface 1011 is cleared using a lye and etched to improve an adhesion force of metal layer contained in the electro-less plating process.
  • a first electrically conductive metal layer 20 is formed on the inner surface 1011 of the substrate 10 .
  • the first electrically conductive metal layer 20 is made of copper and the thickness thereof is general less than 6 micrometers.
  • a second electrically conductive metal layer 40 is directly formed on the first electrically conductive metal layer 20 using an electro-plating process until the through hole 101 is entirely filled with the second electrically conductive metal layer 40 .
  • a portion of the obtained second electrically conductive metal layer 40 adjacent to the first electrically conductive metal layer 20 is thicker than the central portion thereof.
  • the second electrically conductive metal layer 40 defines a first end 41 and an opposite second end 42 . Both the first and second ends 41 , 42 are arc-shaped in cross-section, and respectively extend beyond the first and second outer surfaces 111 , 112 .
  • the protecting layers 31 on the substrate 10 are removed using a typical etching process. Thereafter, as shown in FIG. 7 , the second electrically conductive metal layer 40 is smoothened using a roller 90 until both the first and second ends 41 , 42 have a flat end surface. Additionally, when being a binder layer, the protecting layer 31 can be manually stripped, and the second electrically conductive metal layer 40 can be polished.
  • both the first and second electrically conductive metal layers 20 , 40 are compact, and have approximate similar thermal expansion indexes to those of the two conductive layers 11 , 12 . Therefore, interspace is prevented from being formed between the two electrically conductive metal layers 20 , 40 and the two conductive layers 11 , 12 , the inner surface 1011 is protected from corrosion in wet process.
  • a method for manufacturing a PCB is provided in a second embodiment, differing from the first embodiment is that the substrate 50 defining a blind hole 501 passing through only the first conductive layer 51 and the base 53 , and exposing a portion of the second conductive layer 52 .
  • the substrate 50 defines an inner surface 5011 in the blind hole 501 and an outer surface 511 on the first conductive layer 51 .
  • the method includes a step of forming a first electrically conductive metal layer 60 on the substrate 50 using an electro-less plating process.
  • the first electrically conductive metal layer 60 includes a first portion 61 formed on the outer surface 511 and a second portion 63 formed on the inner surface 5011 defined in the blind hole 501 .
  • the method includes a step of applying protecting layers 71 onto the substrate 50 .
  • the first portion 61 of the first metal layer 60 and the second conductive layer 52 are covered by the protecting layers 71 while the second portion 63 is exposed.
  • the protecting layers 71 are dry photoresist films.
  • the protecting layers 71 can be liquid photoresist layers or binder layers.
  • the method includes a step of forming a second electrically conductive metal layer 80 on the second portion 63 using an electro-plating process until the blind hole 501 is filled with conductive metal layer 80 .
  • the method includes a step of removing a portion of the protecting layer 71 attached on the first portion 61 from the substrate 50 using a typical etching process or by manual stripping. Another portion of the protecting layer 71 attached on the second conductive layer 52 is kept for manufacturing electrical traces in subsequent process using a traditional exposing and developing method. Additionally, when the protecting layers 71 are binder layers, another portion of the protecting layers 71 attached on the second conductive layer 52 should be removed.
  • the first portion 61 of the first electrically conductive metal layer 60 is removed. Therefore, the thickness of the first conductive layer 51 remains unchanged.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
US12/426,276 2008-08-19 2009-04-19 Method for manufacturing printed circuit boards Abandoned US20100044237A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN200810304044.8 2008-08-19
CN2008103040448A CN101657072B (zh) 2008-08-19 2008-08-19 电路板制作方法

Publications (1)

Publication Number Publication Date
US20100044237A1 true US20100044237A1 (en) 2010-02-25

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ID=41695342

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/426,276 Abandoned US20100044237A1 (en) 2008-08-19 2009-04-19 Method for manufacturing printed circuit boards

Country Status (2)

Country Link
US (1) US20100044237A1 (zh)
CN (1) CN101657072B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI557544B (zh) * 2015-06-24 2016-11-11 碁鼎科技秦皇島有限公司 散熱片及其製作方法及電子設備
KR20190012075A (ko) * 2017-07-26 2019-02-08 삼성전기주식회사 인쇄회로기판

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104659017A (zh) * 2013-11-20 2015-05-27 宏启胜精密电子(秦皇岛)有限公司 中介板及其制作方法
CN105789938B (zh) * 2014-12-23 2020-08-04 南京中兴软件有限责任公司 机架内部供电方法、总线式供电板以及通信设备
CN107404804B (zh) * 2016-05-20 2020-05-22 鹏鼎控股(深圳)股份有限公司 电路板及其制作方法
CN112770518A (zh) * 2019-10-21 2021-05-07 深南电路股份有限公司 电路板及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6039889A (en) * 1999-01-12 2000-03-21 Fujitsu Limited Process flows for formation of fine structure layer pairs on flexible films
US20030178229A1 (en) * 2001-03-14 2003-09-25 Yukihiko Toyoda Multilayered printed wiring board
US20040078970A1 (en) * 2001-02-23 2004-04-29 Keiichi Naitoh Method of manufacturing flexible wiring board

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5891606A (en) * 1996-10-07 1999-04-06 Motorola, Inc. Method for forming a high-density circuit structure with interlayer electrical connections method for forming
JP2002076617A (ja) * 2000-08-28 2002-03-15 Matsushita Electric Works Ltd プリント配線板の製造方法及びプリント配線板
JP2006179822A (ja) * 2004-12-24 2006-07-06 Cmk Corp プリント配線板とその製造方法
CN101192542A (zh) * 2006-11-22 2008-06-04 全懋精密科技股份有限公司 电路板结构及其制造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6039889A (en) * 1999-01-12 2000-03-21 Fujitsu Limited Process flows for formation of fine structure layer pairs on flexible films
US20040078970A1 (en) * 2001-02-23 2004-04-29 Keiichi Naitoh Method of manufacturing flexible wiring board
US20030178229A1 (en) * 2001-03-14 2003-09-25 Yukihiko Toyoda Multilayered printed wiring board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI557544B (zh) * 2015-06-24 2016-11-11 碁鼎科技秦皇島有限公司 散熱片及其製作方法及電子設備
KR20190012075A (ko) * 2017-07-26 2019-02-08 삼성전기주식회사 인쇄회로기판
JP2019029636A (ja) * 2017-07-26 2019-02-21 サムソン エレクトロ−メカニックス カンパニーリミテッド． プリント回路基板
KR102421980B1 (ko) * 2017-07-26 2022-07-18 삼성전기주식회사 인쇄회로기판
JP7148052B2 (ja) 2017-07-26 2022-10-05 サムソン エレクトロ－メカニックス カンパニーリミテッド． プリント回路基板

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Publication number Publication date
CN101657072A (zh) 2010-02-24
CN101657072B (zh) 2011-12-21

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Legal Events

Date Code Title Description
AS Assignment

Owner name: FOXCONN ADVANCED TECHNOLOGY INC.,TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TSAI, CHUNG-JEN;HUANG, YU-CHENG;CHANG, HUNG-YI;AND OTHERS;REEL/FRAME:022564/0665

Effective date: 20090416

AS Assignment

Owner name: ZHEN DING TECHNOLOGY CO., LTD., TAIWAN

Free format text: CHANGE OF NAME;ASSIGNOR:FOXCONN ADVANCED TECHNOLOGY INC.;REEL/FRAME:026895/0332

Effective date: 20110613

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION