US20090218119A1 - Method of manufacturing multilayer printed wiring board - Google Patents

Method of manufacturing multilayer printed wiring board Download PDF

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Publication number
US20090218119A1
US20090218119A1 US12/327,444 US32744408A US2009218119A1 US 20090218119 A1 US20090218119 A1 US 20090218119A1 US 32744408 A US32744408 A US 32744408A US 2009218119 A1 US2009218119 A1 US 2009218119A1
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United States
Prior art keywords
insulating layer
resin insulating
plating film
interlaminar resin
conductor
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Abandoned
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US12/327,444
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English (en)
Inventor
Toru Nakai
Sho Akai
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Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
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Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to US12/327,444 priority Critical patent/US20090218119A1/en
Assigned to IBIDEN CO., LTD. reassignment IBIDEN CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AKAI, SHO, NAKAI, TORU
Publication of US20090218119A1 publication Critical patent/US20090218119A1/en
Priority to US13/187,060 priority patent/US8499446B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0341—Intermediate metal, e.g. before reinforcing of conductors by plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/073—Displacement plating, substitution plating or immersion plating, e.g. for finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49162—Manufacturing circuit on or in base by using wire as conductive path
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

  • the present invention relates to a method of manufacturing a multilayer printed wiring board.
  • Laid-Open Patent Publication No. 2003-31927 discloses a method of forming conductor circuits on an interlaminar resin insulating layer.
  • the method including forming an electroless nickel plating film on the entirety of the surface of a laminate board without a copper foil, forming a plating resist on this electroless nickel plating film, and forming a patterned copper plating film. Also included is subsequently stripping the plating resist, and undertaking a selective etching to remove the electroless nickel plating film, other than the conductor pattern, which has become unnecessary.
  • An exemplary embodiment of a method of manufacturing a multilayer printed wiring board includes forming a first interlaminar resin insulating layer, a first conductor circuit on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer, opening portions in the second interlaminar resin insulating layer to expose a face of the first conductor circuit, an electroless plating film on the second interlaminar resin insulating layer and the exposed face, and a plating resist on the electroless plating film.
  • the method further includes substituting the electroless plating film with a thin film conductor layer, having a lower ion tendency than the electroless plating film, and a metal of the exposed face, forming an electroplating film including the metal on a portion of the electroless plating film and the thin film conductor layer, stripping the plating resist, and removing the electroless plating film exposed by the stripping.
  • An exemplary embodiment of a multilayer printed wiring board includes a first interlaminar resin insulating layer, a first conductor circuit, a second interlaminar insulating layer, an electroless plating film, a thin film conductor layer, and an electroplating film.
  • the first conductor circuit is formed on the first interlaminar resin insulating layer.
  • the second interlaminar resin insulating layer is formed on the first conductor circuit and the first interlaminar resin insulating layer, and includes opening portions to expose a face of the first conductor circuit.
  • the electroless plating film is formed on a portion of the second interlaminar resin insulating layer.
  • the thin film conductor layer is formed on the exposed face and the electroless plating film, has a lower ion tendency than the electroless plating film, and includes a metal of the exposed face of the first conductor circuit.
  • the electroplating film includes the metal formed on the thin film conductor layer.
  • FIG. 1A through FIG. 1G are sectional views illustrating steps of a method of manufacturing a multilayer printed wiring board in accordance with an exemplary embodiment
  • FIG. 2A through FIG. 2E are sectional views illustrating steps of a method of manufacturing a multilayer printed wiring board in accordance with an exemplary embodiment
  • FIG. 3A through FIG. 3D are sectional views illustrating steps of a method of manufacturing a multilayer printed wiring board in accordance with an exemplary embodiment
  • FIG. 4A through FIG. 4D are sectional views illustrating steps of a method of manufacturing a multilayer printed wiring board in accordance with an exemplary embodiment.
  • an upper layer interlaminar resin insulating layer is laminated onto a lower layer interlaminar resin insulating layer on which conductor circuits are formed, and opening portions for forming via conductors are formed in this upper layer interlaminar resin insulating layer. Then, those opening portions are electroless-plated and electroplated to form via conductors.
  • via conductors were formed with the application of the method cited in Patent Document 1, these via conductors would be formed of an electroless nickel plating film and an electrolytic copper plating film formed on this electroless nickel plating film. Accordingly, it is believed that the conductor circuits formed of copper and formed on the lower layer interlaminar resin insulating layer and the via conductors are connected such that nickel of a different type of metal is present between copper and copper.
  • the present inventors found, as a result of their diligent research, a method of enhancing the connectivity between conductor circuits and via conductors while meeting the demands for finer conductor circuits, and completed a method of manufacturing a multilayer printed wiring board in accordance with the present invention.
  • a method of manufacturing a multilayer printed wiring board pertaining to an exemplary embodiment will be described in the order of steps.
  • the substrate is not limited to the insulating substrate, and a resin substrate such as, to give some examples, a glass epoxy substrate, a bismaleimide triazine (BT) resin substrate, a copper-clad laminate board, and an RCC substrate, a ceramic substrate such as an aluminum nitride substrate, a silicone substrate, etc., may be used.
  • the conductor circuits may be formed by etching after a plain conductor layer is formed on the surface of the insulating substrate with electroless plating, for example.
  • through-hole conductors to make a connection between the conductor circuits sandwiching the insulating substrate may be formed, and the surfaces of the conductor circuits may be roughened with etching, etc., as necessary, following the formation of the conductor circuits.
  • the interlaminar resin insulting layer may be formed by a thermosetting resin, a photosensitive resin, a resin in which a photosensitive group is added into a portion of a thermosetting resin, or a resin complex containing a combination thereof and a thermoplastic resin, etc.
  • a resin layer is formed by coating an unhardened resin with a roll coater, a curtain coater, etc., or a resin film being thermo-compression bonded. Then, the resin is hardened as necessary. At that juncture, the opening portions are formed with a laser treatment, exposure and development to form an interlaminar resin insulating layer having the opening portions. For example, it will suffice to form a resin layer including the thermoplastic resin by a resin molded material molded in a film shape that is thermo-compression-bonded.
  • an electroless nickel plating film On the surface of the interlaminar resin insulating layer (including the wall faces of the opening portions) and on the exposed faces of the conductor circuits on the insulating substrate exposed by the opening portions there is formed an electroless nickel plating film. Specifically, a palladium catalyst is adhered to the surface of the interlaminar resin insulating layer (including the wall faces of the opening portions) and to the exposed faces of the conductor circuits. Then, the electroless nickel plating film is formed by it being immersed in an electroless nickel plating aqueous solution. The electroless nickel plating film is preferably 0.1 to 2.0 ⁇ m in thickness. Further, the surface of the interlaminar resin insulating layer may be pre-roughened prior to the formation of the electroless nickel plating film.
  • the electroless nickel plating film is preferably formed such that it densely covers, with certainty, the entirety of the surface of the interlaminar resin insulating layer and that it coarsely covers, if at all possible, the exposed faces of the conductor circuits.
  • the electroless nickel plating film on the surface of the interlaminar resin insulating layer needs to, with certainty, cover the surface of the interlaminar resin insulating layer, as it functions as a seed layer during the subsequent step of forming an electroplating film.
  • the electroless nickel plating film on the exposed faces of the conductor circuits is an unnecessary element for via conductors that are completed, and, it is preferably formed coarsely, if at all possible, as the conductor circuits themselves exposed by the opening portions can function as a seed layer during the subsequent step of forming an electroplating film.
  • the amount of palladium catalyst to be adhered prior to the electroless plating it will suffice to set the amount of palladium catalyst to be adhered prior to the electroless plating to be large as to the surface of the interlaminar resin insulating layer and small as to the exposed faces of the conductor circuits. Accordingly, as for a method of adjusting the amount of palladium catalyst, with the polarity of the interlaminar resin insulating layer and the polarity of the palladium catalyst being set to be opposing polarities and the polarities of the exposed faces of the conductor circuits and of the palladium catalyst being like polarities (positive polarities or negative polarities), for example, a method of adhering palladium catalyst may be used.
  • a plating resist is formed on the electroless nickel plating film.
  • the plating resist is formed on the portions where conductor circuits and via conductors are not formed.
  • the plating resist may be formed by being exposed and developed after a photosensitive dry film has been bonded, for example.
  • a thin film conductor layer having copper is a thin film conductor layer having copper for a principal constituent of a thin film conductor layer. It is a thin film conductor layer having the atomic % of copper in the thin film conductor layer that is no less than 50%. Specifically, it is undertaken by a substrate having undergone up to the formation of the plating resist being immersed in a substitution copper plating solution.
  • the electroless plating film on the exposed faces of the first conductor circuits is substituted, the electroless plating film on the portion where no plating resist has been formed is also substituted.
  • the amount of a different type of metal in the conductor circuits formed on the second interlaminar resin insulating layer is reduced, resulting in the improved electrical property of the manufactured multilayer printed wiring board.
  • the adhesion strength between the conductor circuits e.g., the second conductor circuits 142 illustrated in FIG.
  • the conductor circuits include the thin film conductor layer and the electroplating film on the thin film conductor layer, as described in the following.
  • the thin film conductor layer on the first conductor circuits may be a thin film conductor layer including copper. In this case, it results in the connection reliability between the first conductor circuits and via conductors formed on the first conductor circuits being enhanced and the connectivity resistance becoming low. Further, the thin film conductor layer including copper is a thin film conductor layer in which all of the nickel in the electroless nickel plating film is substituted with copper. When it comes to the substitution plating, the electroless nickel plating film on the portion where a plating resist has not been formed on the interlaminar resin insulating layer can be substituted with a thin film conductor layer including copper. In this case, the resistance value of the conductor circuits declines.
  • the electroless nickel plating film tends to form more densely on the interlaminar resin insulating layer than on the exposed faces of the conductor circuits.
  • the substitution copper plating ends at the point in time when the electroless nickel plating film on the exposed faces of the conductor circuits is completely substituted, only a portion of the electroless nickel plating film on the interlaminar resin insulating layer is substituted.
  • the lower layer thereof is a conductor layer
  • the electroless nickel plating film on the interlaminar resin insulating layer the lower layer thereof is a non-conductor layer (a resin layer). Accordingly, it leads to the electroless nickel plating film on the conductor circuits being more easily substituted than the electroless nickel plating film on the interlaminar resin insulating layer.
  • the substitution copper plating ends at the point in time when the electroless nickel plating film on the exposed faces of the conductor circuits is completely substituted, only a portion of the electroless nickel plating film on the interlaminar resin insulating layer is substituted. Further, with the control over the treatment time of the substitution treatment, a portion of nickel of the electroless nickel plating film could be substituted with a thin film conductor layer having copper, or the entirety of nickel of the electroless nickel plating film could be substituted with copper to provide a thin film conductor layer having copper.
  • an electrolytic copper plating film is formed on the portions where the plating resist is not formed and on the thin film conductor layer formed on the exposed faces of the conductor circuits.
  • the electrolytic copper plating is undertaken with a method well known in the art. Further, the electrolytic copper plating film is preferably 5 to 20 ⁇ m in thickness.
  • the plating resist on the interlaminar resin insulating layer is stripped. For example, by stripping the plating resist with an alkali aqueous solution, etc.
  • the electroless nickel plating film (the electroless nickel plating film between electrolytic copper plating films) exposed by the stripped plating resist is removed.
  • the electroless nickel plating film may be removed, for example, with the use of an etchant, and, in particular, it is preferable to use an etchant capable of selectively etching nickel.
  • an etchant capable of selectively etching nickel MEC Remover NH-1865 made by MEC Corporation, for example, etc., may be used.
  • the removal with certainty of an electroless plating film is preferably undertaken with the use of an etchant. Further, the selection of an etchant allows an electroplating film to selectively be not etched and an electroless plating film to be removed with certainty. During the step of removing an electroless plating film, the use of such a selective etchant does not allow the electrolytic plating film to be etched. Therefore, in forming independent conductor circuits there is no need to have formed an electroplating film wider than the finished product on account of a projection that a portion of the electroplating film be removed. Accordingly, the etchant is suited to form fine conductor circuits having a low L/S (line/space).
  • steps (3) through (8) allows conductor circuits on the interlaminar resin insulating layer to be formed and, at the same time, via conductors for connecting conductor circuits to be formed on different interlaminar resin insulating layers.
  • the insulating substrate e.g., the insulating substrate 11 illustrated in FIG. 1
  • the catalyst on the interlaminar resin insulating layer may be removed with an acid or an oxidizer, as necessary, following the formation of the conductor circuits. Thus, preventing the electrical property from declining.
  • an interlaminar resin insulating layer and conductor circuits may be formed and, at the same time, via conductors may be formed with the steps of the above-described (2) through (8) being repeated as necessary.
  • the interlaminar resin insulating layer formed under the step of the above-described (2) corresponds to the first interlaminar resin insulating layer (e.g., the interlaminar resin insulating layer 121 illustrated in FIG. 4D )
  • the interlaminar resin insulating layer formed under the step of the above-described (9) corresponds to the second interlaminar resin insulating layer (e.g., the interlaminar resin insulating layer 122 illustrated in FIG. 4D ).
  • the conductor circuits 142 correspond to the first conductor circuits
  • the conductor circuits 143 correspond to the second conductor circuits, as illustrated, e.g., in FIG. 4D .
  • solder resist layer and solder bumps are formed to complete a multilayer printed wiring board.
  • a solder resist composition with a roll coater, etc. to which an opening treatment is carried out with laser treatment, exposure and development, etc., and a solder resist layer is formed by a hardening treatment, etc., being carried out.
  • solder bumps are formed in the opening portions of the solder resist layer to finish the manufacture of a printed wiring board.
  • all of the via conductors are formed of copper, and the via conductors and the exposed faces of the conductor circuits therebelow are formed of the identical metal (copper).
  • the electroless nickel plating film between electrolytic copper plating films can be removed with the use of an etchant selectively etching nickel when independent conductor circuits are formed.
  • via conductors connecting the lower layer conductor circuits including copper and the upper layer conductor circuits are formed on the lower layer conductor circuits and include a thin film conductor layer having copper and an electrolytic copper plating film formed on the thin film conductor layer. Accordingly, the formation of fine conductor circuits and the securing of the interlaminar connection reliability of via conductors can both be attainable together.
  • conductor circuits and a thin film conductor formed on those conductor circuits, as well as a thin film conductor and an electroplating film formed on that thin film conductor layer have the same type of metal (copper). Accordingly, as compared to the via conductors formed with the application of the method of forming conductor circuits as set forth in Patent Document 1, the crystal lattices between the two become more likely to match in the via conductors formed with the above-described manufacturing method. Thus, the connection strength between the first conductor circuits and the thin film conductor, and between the thin film conductor and the electroplating film on the thin film conductor, becomes elevated.
  • the via conductors formed with the above-described manufacturing method exhibit, as compared to the via conductors formed with the application of the method of forming conductor circuits as set forth in Patent Document 1, exhibited an excellent connection reliability following a temperature cycle test.
  • the via conductors formed with the above-described manufacturing method exhibit, as they are low in electrical resistance, an excellent electrical property as compared to the via conductors formed with the application of the method of forming conductor circuits set forth in Patent Document 1.
  • the electroless nickel plating film on the exposed faces of the conductor circuits is completely substituted and that the electroless nickel plating film on the interlaminar resin insulating layer (including the wall faces of the opening portions) is not completely substituted but only a portion thereof is substituted.
  • finer conductor circuits can be achieved.
  • the interlaminar connectivity of via conductors can be enhanced.
  • the adhesion between an interlaminar resin insulating layer and conductor circuits formed on that interlaminar resin insulating layer can be enhanced.
  • the adhesion between the interlaminar resin insulting layer and the conductor circuits formed on that interlaminar resin insulating layer can be enhanced.
  • the starting material was a copper-clad laminate board.
  • the copper-clad laminate board includes an insulating substrate 11 formed of a 0.8 mm-thick glass epoxy resin and a 18 ⁇ m copper foil 18 laminated on both surfaces of the insulating substrate 11 , as illustrated in FIG. 1A .
  • FIG. 1B holes were drilled in this copper-clad laminate board such that through holes 29 for through-hole conductors were formed.
  • the copper foils 18 and the surfaces of the through holes 29 were electroless-copper-plated and electrolytic-copper-plated to form conductor layers including through-hole conductors 19 including the electroless copper plating film and the electrolytic copper plating film.
  • the through-hole conductors 19 were filled in with the resin filler described under Section A, described above, with the method described below. Namely, after the resin filler had first been squeezed into the through-hole conductors with the use of a squeegee, it was dried under the conditions that are at 100° C. and for 20 minutes. Subsequently, one face of the substrate was sanded by belt-sander grinding using a #600 belt-sanding sandpaper (made by Sankyo Rikagaku Co., Ltd.) such that the resin filler 20 does not remain on the electrolytic copper plating film, which was, next, buffed to remove any marring due to the belt-sander grinding.
  • a #600 belt-sanding sandpaper made by Sankyo Rikagaku Co., Ltd.
  • a similar series of grinding was likewise performed on the other face of the substrate. Next, it was heated at 100° C. for one hour, at 120° C. for three hours, at 150° C. for one hour, and at 180° C. for seven hours to form resin filler layers 20 .
  • a conductor layer 21 including an electroless copper plating film and an electrolytic copper plating film was formed on the electrolytic copper plating film and the resin filler 20 .
  • conductor circuits 14 were formed on the insulating substrate 11 with a subtractive method. At that time, conductor circuits 114 concurrently covering the resin filler 20 were also formed.
  • the substrate was soft-etched, and, subsequently, the entirety of the surface (including the land surface of the through-hole conductors 19 ) of the conductor circuits 14 was roughened (not illustrated) by the surfaces of the conductor circuits 14 (including the conductor circuits 114 covering the resin filler 20 ) being etched with an etchant sprayed on both faces of the substrate with a sprayer.
  • an etchant containing 10 parts by weight of imidazole-copper (II) complex, 7 parts by weight of glycolic acid, and 5 parts by weight of potassium chloride (made by MEC Corporation, MEC Bond) was used.
  • an interlaminar resin insulating layer 12 was formed on the insulating substrate 11 and the conductor circuits 14 with the use of a film for interlaminar resin insulating layer formation (made by Ajinomoto Co., Inc., ABF). Namely, a film for interlaminar resin insulating layer formation was compression-bonded on the substrate under the conditions of a vacuum of 65 Pa, a pressure of 0.4 MPa, the temperature at 80° C., and the time for 60 seconds, which, then, was thermoset at 170° C. for 30 minutes to form an interlaminar resin insulating layer 12 .
  • a film for interlaminar resin insulating layer formation was compression-bonded on the substrate under the conditions of a vacuum of 65 Pa, a pressure of 0.4 MPa, the temperature at 80° C., and the time for 60 seconds, which, then, was thermoset at 170° C. for 30 minutes to form an interlaminar resin insulating layer 12 .
  • opening portions 16 having a diameter of 80 ⁇ m were formed in the interlaminar resin insulating layer 12 with a CO 2 gas laser. As a result, a portion (the exposed face 14 a ) of the conductor circuits 14 was exposed by the opening portion 16 .
  • the substrate in which the opening portions 16 were formed was immersed in an 80° C. solution containing 60 g/l of permanganic acid for 10 minutes such that the surface of the interlaminar resin insulating layer 12 including the inner wall faces of the opening portions 16 was roughened (not illustrated).
  • the substrate which had been subjected to the above-treatment was immersed in a neutralization solution (made by Shipray Co.) and then washed in water. Further, a palladium catalyst (not illustrated) was applied to the surface of the interlaminar resin insulating layer 12 (including the inner wall faces of the opening portions 16 ) and the exposed faces 14 a of the conductor circuits exposed by the opening portions 16 . Specifically, the substrate was immersed in Activator Neoganth 834 conc (made by Atotech Corp.), and the catalyst was applied by metal palladium being deposited.
  • Activator Neoganth 834 conc made by Atotech Corp.
  • the substrate to which a palladium catalyst had been applied was immersed in a nickel boron bath (made by Uemura Industries Co., Ltd., KLP VERI) such that an electroless nickel plating film 25 was formed on the surface of the interlaminar resin insulating layer 12 (including the inner wall faces of the opening portions 16 ) and the exposed faces 14 a of the conductor circuits exposed by the opening portions 16 .
  • the electroless nickel plating film 25 is 1 ⁇ m in thickness on the surface of the interlaminar resin insulating layer 12 and 0.5 ⁇ m in thickness on the exposed faces 14 a of the conductor circuits.
  • the substrate on which a plating resist 13 had been formed was immersed in a substitution copper plating solution (1M CuSO 4 .5H 2 O), which was subjected to substitution copper plating for 3 minutes whereby an electroless nickel plating film 25 is substituted with a copper plating film to form a thin film conductor layer 22 .
  • a substitution copper plating solution (1M CuSO 4 .5H 2 O)
  • the electroless nickel plating film 25 on the exposed faces 14 a of the conductor circuits may be completely substituted with the copper plating film, while only a portion of the remaining electroless nickel plating film 25 may be substituted from nickel to copper.
  • the substrate on which a thin film conductor layer 22 has been formed was washed in 50° C. water and degreased, and after having been washed in 25° C. water and further in sulfuric acid, it was electroplated under the following conditions to form an electrolytic copper plating film 23 on the portion where a plating resist 13 was not formed.
  • Electro current density 1 A/dm 2 Time: 90 minutes Temperature: 23° C.
  • the plating resist 13 was stripped and removed. Further, the electroless nickel plating film 25 between the adjacent electrolytic copper plating films was etched with a nickel selective etchant (made by MEC Corporation, NH-1865, or another etchant such as NH-1860), dissolved and removed, and conductor circuits 14 including the thin film conductor layer 22 and the electrolytic copper plating film 23 on the thin film conductor layer and via conductors 17 were formed.
  • a nickel selective etchant made by MEC Corporation, NH-1865, or another etchant such as NH-1860
  • the minimum value for the L/S (line/space) of the conductor circuits 14 in the example was set to be 8 ⁇ m/8 ⁇ m.
  • solder resist composition was coated in 30 ⁇ m in thickness on the outermost layer of the interlaminar resin insulating layer 12 and the conductor circuit 14 , which was dried under the conditions that are at 70° C. for 20 minutes and at 70° C. for 30 minutes such that a commercially available solder resist layer 24 ′ was formed.
  • solder resist composition layer 24 ′ became hardened to form a solder resist layer 24 (20 ⁇ m in thickness) having openings for solder bump formation 28 .
  • substrate was immersed in an electroless gold plating solution containing potassium gold cyanide (7.6 ⁇ 10 ⁇ 3 mol/l), ammonium chloride (1.9 ⁇ 10 ⁇ 1 mol/l), sodium citrate (1.2 ⁇ 10 ⁇ 1 mol/l), and sodium hypophosphite (1.7 ⁇ 10 ⁇ 1 mol/l) under the condition that is at 80° C. for 7.5 minutes such that a 0.03 ⁇ m-thick gold plating layer was formed on the nickel layer providing solder pads 26 .
  • potassium gold cyanide 7.6 ⁇ 10 ⁇ 3 mol/l
  • ammonium chloride 1.9 ⁇ 10 ⁇ 1 mol/l
  • sodium citrate 1.2 ⁇ 10 ⁇ 1 mol/l
  • sodium hypophosphite 1.7 ⁇ 10 ⁇ 1 mol/l
  • solder paste was printed over the openings for solder bump formation 28 formed in the solder resist layer 24 such that solder bumps 27 were formed by reflow at 200° C., completing a multilayer printed wiring board 10 .
  • electroless plating film is not limited to the electroless nickel plating film and, in other embodiments in accordance with the present invention, the electroless plating film may be an electroless tin plating film, an electroless zinc plating film, an electroless iron plating film, etc. These electroless plating films are also suitable, as their ionization tendencies are greater than copper, for the formation of a thin film conductor layer with substitution copper plating at a later step.
  • the material for the thin film conductor layer to be formed with substitution plating is not limited so long as it is a metal having a lower ionization tendency than the electroless plating film, and it will suffice to select a metal satisfying the above-described condition for ionization tendency of copper, etc.
  • the electroless nickel plating film on the exposed faces of the conductor circuits is completely substituted and only a portion of the electroless nickel plating film on the interlaminar resin insulating layer (including the wall faces of the opening portions) is substituted
  • the electroless nickel plating film on the interlaminar resin insulating layer may, alternatively, be completely substituted with a copper plating film or may not be substituted at all.
  • the number of the repetition thereof is not limited, and it may be twice or more.
  • the total number of interlaminar resin insulating layers is the same for both sides of the insulating substrate, the total numbers may, alternatively, vary from one side to the other of the insulating substrate.
  • this electroless plating film is substituted with a thin film conductor layer having the same metal as the metal constituting the exposed faces of the first conductor circuits.
  • via conductors are formed by an electroplating film including the same metal (the metal deposited by the substitution metal) as the thin film conductor layer being formed on this thin film conductor layer.
  • the via conductors formed since the first conductor circuits and the thin film conductor layer, as well as the thin film conductor layer and the electroplating on the thin film conductor layer, are connected via a same type of metal, it results in a high connection strength and an excellent connection reliability. Further, for the first conductor circuits and the electroplating film, copper is preferred on account of the electrical resistance and the ease of formation.
  • the electroless plating film is preferably an electroless nickel film
  • the thin film conductor layer preferably includes a thin film conductor layer having copper or a thin film conductor layer including copper
  • the electroplating film is preferred to be an electrolytic copper plating film.
  • An electroless plating film including nickel is easily formed, and a thin film conductor layer having copper or a thin film conductor layer including copper is easily formed with substitution plating.
  • a thin film conductor layer having copper and a thin film conductor layer including copper and an electrolytic copper film are suited as constituent materials for via conductors as they are low in electrical resistance.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
US12/327,444 2008-03-03 2008-12-03 Method of manufacturing multilayer printed wiring board Abandoned US20090218119A1 (en)

Priority Applications (2)

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US12/327,444 US20090218119A1 (en) 2008-03-03 2008-12-03 Method of manufacturing multilayer printed wiring board
US13/187,060 US8499446B2 (en) 2008-03-03 2011-07-20 Method of manufacturing multilayer printed wiring board

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US3320908P 2008-03-03 2008-03-03
US12/327,444 US20090218119A1 (en) 2008-03-03 2008-12-03 Method of manufacturing multilayer printed wiring board

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US13/187,060 Expired - Fee Related US8499446B2 (en) 2008-03-03 2011-07-20 Method of manufacturing multilayer printed wiring board

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JP (1) JP5216079B2 (ja)
KR (1) KR101229644B1 (ja)
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US20100059257A1 (en) * 2008-09-05 2010-03-11 Samsung Electro-Mechanics Co., Ltd. Method of nickel-gold plating and printed circuit board
US20110272286A1 (en) * 2008-03-03 2011-11-10 Ibiden Co., Ltd. Method of manufacturing multilayer printed wiring board
US8197659B2 (en) 2004-09-24 2012-06-12 Ibiden Co., Ltd. Plating apparatus, plating method and multilayer printed circuit board
US8661665B2 (en) 2008-09-30 2014-03-04 Ibiden Co., Ltd. Method for manufacturing multilayer printed wiring board
US8683685B2 (en) 2008-03-03 2014-04-01 Ibiden Co., Ltd. Method of manufacturing multilayer printed wiring board
US9038266B2 (en) 2008-09-30 2015-05-26 Ibiden Co., Ltd. Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

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CN111373849A (zh) * 2017-11-16 2020-07-03 三菱瓦斯化学株式会社 带经图案化的金属箔的层叠体的制造方法和带经图案化的金属箔的层叠体

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US20110272286A1 (en) * 2008-03-03 2011-11-10 Ibiden Co., Ltd. Method of manufacturing multilayer printed wiring board
US8499446B2 (en) * 2008-03-03 2013-08-06 Ibiden Co., Ltd. Method of manufacturing multilayer printed wiring board
US8683685B2 (en) 2008-03-03 2014-04-01 Ibiden Co., Ltd. Method of manufacturing multilayer printed wiring board
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US8661665B2 (en) 2008-09-30 2014-03-04 Ibiden Co., Ltd. Method for manufacturing multilayer printed wiring board
US9038266B2 (en) 2008-09-30 2015-05-26 Ibiden Co., Ltd. Multilayer printed wiring board and method for manufacturing multilayer printed wiring board

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US20110272286A1 (en) 2011-11-10
CN101911850B (zh) 2012-05-30
WO2009110259A1 (ja) 2009-09-11
CN101911850A (zh) 2010-12-08
KR101229644B1 (ko) 2013-02-04
JPWO2009110259A1 (ja) 2011-07-14
JP5216079B2 (ja) 2013-06-19
US8499446B2 (en) 2013-08-06
KR20100077061A (ko) 2010-07-06

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