US20080121883A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
US20080121883A1
US20080121883A1 US11/961,317 US96131707A US2008121883A1 US 20080121883 A1 US20080121883 A1 US 20080121883A1 US 96131707 A US96131707 A US 96131707A US 2008121883 A1 US2008121883 A1 US 2008121883A1
Authority
US
United States
Prior art keywords
side wall
gate electrode
dielectric film
oxide film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/961,317
Other languages
English (en)
Inventor
Young Suk Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Semiconductor Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, YOUNG SUK
Publication of US20080121883A1 publication Critical patent/US20080121883A1/en
Assigned to FUJITSU MICROELECTRONICS LIMITED reassignment FUJITSU MICROELECTRONICS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU LIMITED
Assigned to FUJITSU SEMICONDUCTOR LIMITED reassignment FUJITSU SEMICONDUCTOR LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU MICROELECTRONICS LIMITED
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • the present invention generally relates to semiconductor devices. More particularly, the present invention relates to an ultra-microscopic, ultra-high-speed semiconductor device having a gate length of less than 40 nm, and a manufacturing method thereof.
  • a low-resistance silicide layer made of CoSi 2 , NiSi, or the like is formed on the silicon surfaces of the source area, the drain area, the gate electrode, etc., by a salicide method or the like.
  • a metal film such as a Co film or a Ni film is deposited on the surfaces of the source area, a drain area, and a gate electrode, and the metal film is then heat-treated so that a desired silicide layer is formed on the silicon surfaces. Unreacted portions of the metal layer are removed by a wet etching process (see, for example, Patent Document 1).
  • Patent Document 1 Japanese Laid-Open Patent Application No. H7-202184
  • Non-patent Literature 1 Bin Yu et al., International Electronic Device Meeting Tech. Dig., 2001, pp. 937
  • Non-patent Literature 2 N. Yasutake, et al., 2004 Symposium on VLSI Technology Digest of Technical Papers, pp. 84
  • the gate length is also reduced to under 40 nm, for example, to 15 nm or 6 nm (see, Non-patent Literature 1 and 2).
  • FIGS. 1A through 1C are diagrams for describing the problem that arises when forming a silicide layer, by the conventional salicide method, in such an ultra-microscopic/ultra-high-speed semiconductor device.
  • a p-channel MOS transistor is taken as an example; the same description is applicable to an n-channel MOS transistor by inverting the conductivity type.
  • a device area 11 A including an n-type well is defined by device separation areas 11 I having an STI structure.
  • device area 11 A there is formed a p+ type polysilicon gate electrode 13 corresponding to a predetermined channel area on the silicon substrate 11 via a gate dielectric film 12 .
  • a p-type source extension area 11 a and a p-type drain extension area 11 b are formed on opposite sides of the polysilicon gate electrode 13 .
  • a side wall oxide film 130 W made of a CVD oxide film is formed in such a manner that each side wall oxide film 130 W continuously extends to cover part of the source extension area 11 a or the drain extension area 11 b of the silicon substrate 11 .
  • the side wall oxide film 130 W is provided for the purpose of blocking a current path of a gate leakage current along the side wall surface of the polysilicon gate electrode 13 .
  • a side wall dielectric film 13 SW made of a material having high HF resistance, such as SiN or SiON.
  • a p+ type source area 11 c and a p+ type drain area 11 d are formed in such a manner as to be on the outside of each of the side wall dielectric films 13 SW.
  • a metal film 14 made of Co, Ni, or the like is deposited on the structure shown in FIG. 1A by a sputtering method or the like.
  • heat-treatment is performed to cause the metal film 14 to react with the silicon surface underneath.
  • a low-resistance silicide layer 15 made of CoSi2, NiSi, or the like is formed on the surfaces of the source area 11 c , the drain area 11 d , and on the surface of the polysilicon gate electrode 13 .
  • unreacted portions of the metal film 14 are removed by a wet etching process. Consequently, a device structure as shown in FIG. 1C is formed.
  • the gate length of the gate electrode 13 is reduced to under 40 nm, for example, to 15 nm or 6 nm, the proportion of the silicide layer 15 formed on the polysilicon gate electrode 13 will become extremely small. Hence, even if the silicide layer 15 is formed, the sheet resistance will increase. Therefore, it will not be possible to reduce the gate resistance to a desired level. Accordingly, the semiconductor device will not be able to realize a desired operational speed.
  • Patent Document 1 proposes a configuration for reducing the sheet resistance of the polysilicon gate electrode by forming a wide gate electrode head at the tip of the polysilicon gate electrode having a short gate length, and forming a silicide layer on the gate electrode head.
  • FIGS. 2A and 2B are diagrams for describing the steps for manufacturing a semiconductor device disclosed in Patent Document 1.
  • a device area is defined by device separation areas 22 a , 22 b , 24 a , and 24 b .
  • a silicon layer 23 acting as a channel layer, in an epitaxial manner.
  • the silicon layer 23 is in a polycrystal state, i.e., polysilicon.
  • FIG. 2A further illustrates a polysilicon gate electrode 25 formed on the silicon layer 23 via a gate dielectric film 24 , corresponding to a channel area in the silicon layer 23 .
  • Side wall dielectric films are formed around the polysilicon gate electrode 25 in such a manner that the top of the polysilicon gate electrode 25 is exposed.
  • an SiGe layer is deposited, so that SiGe layers 27 a and 27 c are formed on the left and the right of the polysilicon gate electrode 25 and a SiGe polycrystal head 27 b is formed as a wide head on the exposed top part of the polysilicon gate electrode 25 .
  • a metal film made of Co, Ni, or the like is deposited on the structure shown in FIG. 2A , and a salicide process is performed so that the SiGe layers 27 a through 27 c are converted into silicide areas 28 a through 28 c .
  • the silicide area 28 b On the polysilicon gate electrode 25 is formed the silicide area 28 b , having a broad width and low resistance, as the gate electric head.
  • a wide polycrystal area is formed on a gate electrode having a short gate length, and the polycrystal area is converted into silicide. Accordingly, a wide head having sufficiently low sheet resistance can be formed on the top of the gate electrode in the form of a silicide layer.
  • the inventor of the present invention has found that in such a device stricture, if the gate length is reduced to under 40 nm, or further reduced to 15 nm or 6 nm, the gate leakage current will increase.
  • FIG. 3 is an SEM image of a structure in which a polycrystal head was actually formed on a polysilicon gate electrode. It can be observed that the polycrystal head is covering part of the surfaces of the side wall dielectric films on opposite sides of the gate electrode.
  • the distance between the wide gate electrode head 28 b and the silicide area 28 a or the silicide area 28 b will be reduced. Accordingly, as indicated by arrows in FIG. 2B , gate leakage current paths will be formed along the surfaces of the side wall dielectric films.
  • the side wall dielectric films are SiN or SiON films that generally have HF resistance. These films generally have high interface densities on their surfaces, and therefore, a leakage current path will be easily formed via the surfaces with high interface densities.
  • the present invention provides a semiconductor device and a manufacturing method thereof in which one or more of the above-described disadvantages are eliminated.
  • An embodiment of the present invention provides a semiconductor device including a substrate; a gate electrode arranged on the substrate via a gate dielectric film, wherein a first side of the gate electrode is defined by a first side wall and a second side of the gate electrode is defined by a second side wall, the second side wall being opposite to the first side wall; and the gate electrode comprises a first width; a first side wall dielectric film formed on the substrate on the same side as the first side of the gate electrode, the first side wall dielectric film including a first inner wall opposite to and spaced apart from the first side wall; a second side wall dielectric film formed on the substrate on the same side as the second side of the gate electrode, the second side wall dielectric film including a second inner wall opposite to and spaced apart from the second side wall; a gate electrode head formed on the gate electrode in such a manner as to extend from the first inner wall and the second inner wall, wherein the gate electrode head comprises a second width that is greater than the first width; and a first extension area formed in the substrate on the same side as
  • An embodiment of the present invention provides a method of manufacturing a semiconductor device, which method includes the steps of forming a polysilicon gate electrode defined by a first side wall and a second side wall on a substrate via a gate dielectric film; forming a first extension area in the substrate on the same side as the first side wall of the polysilicon gate electrode and a second extension area in the substrate on the same side as the second side wall of the polysilicon gate electrode; forming a first side wall oxide film on the first side wall on a first side of the polysilicon gate electrode and a second side wall oxide film on the second side wall on a second side of the polysilicon gate electrode; forming, on the first side wall oxide film, a first side wall dielectric film having a different etching resistance from that of the first side wall oxide film, and forming, on the second side wall oxide film, a second side wall dielectric film having a different etching resistance from that of the second side wall oxide film; etching the first side wall oxide film and the second side wall oxide film, starting
  • An embodiment of the present invention provides a method of manufacturing a semiconductor device, which method includes the steps of forming a polysilicon gate electrode defined by a first side wall and a second side wall on a substrate via a gate dielectric film; forming a first extension area in the substrate on the same side as the first side wall of the polysilicon gate electrode and a second extension area in the substrate on the same side as the second side wall of the polysilicon gate electrode; forming a first side wall oxide film on the first side wall on a first side of the polysilicon gate electrode and a second side wall oxide film on the second side wall on a second side of the polysilicon gate electrode; forming, on the first side wall oxide film, a first side wall dielectric film having a different etching resistance from that of the first side wall oxide film, and forming, on the second side wall oxide film, a second side wall dielectric film having a different etching resistance from that of the second side wall oxide film; etching the first side wall oxide film and the second side wall oxide film, starting
  • a gate electrode head with a broad width can be formed on a polysilicon gate electrode, which width corresponds to a length between a first side wall dielectric film and a second side wall dielectric film.
  • FIG. 1A illustrates a conventional salicide process
  • FIG. 1B illustrates a conventional salicide process
  • FIG. 1C illustrates a conventional salicide process
  • FIG. 2A illustrates a problem of the conventional technology
  • FIG. 2B illustrates a problem of the conventional technology
  • FIG. 3 illustrates a problem of the conventional technology
  • FIG. 4A illustrates a method of manufacturing a semiconductor device according to a first embodiment (part 1 );
  • FIG. 4B illustrates a method of manufacturing a semiconductor device according to the first embodiment (part 2 );
  • FIG. 4C illustrates a method of manufacturing a semiconductor device according to the first embodiment (part 3 );
  • FIG. 4D illustrates a method of manufacturing a semiconductor device according to the first embodiment (part 4 );
  • FIG. 4E illustrates a method of manufacturing a semiconductor device according to the first embodiment (part 5 );
  • FIG. 4F illustrates a method of manufacturing a semiconductor device according to the first embodiment (part 6 );
  • FIG. 4G illustrates a method of manufacturing a semiconductor device according to the first embodiment (part 7 );
  • FIG. 5A illustrates a method of manufacturing a semiconductor device according to a second embodiment (part 1 );
  • FIG. 5B illustrates a method of manufacturing a semiconductor device according to the second embodiment (part 2 );
  • FIG. 5C illustrates a method of manufacturing a semiconductor device according to the second embodiment (part 3 );
  • FIG. 5D illustrates a method of manufacturing a semiconductor device according to the second embodiment (part 4 );
  • FIG. 6A illustrates a method of manufacturing a semiconductor device according to a third embodiment (part 1 );
  • FIG. 6B illustrates a method of manufacturing a semiconductor device according to the third embodiment (part 2 );
  • FIG. 6C illustrates a method of manufacturing a semiconductor device according to the third embodiment (part 3 ).
  • FIG. 6D illustrates a method of manufacturing a semiconductor device according to the third embodiment (part 4 ).
  • FIGS. 4A through 4G illustrate a method of manufacturing a semiconductor device 40 according to a first embodiment of the present invention.
  • a p-channel MOS transistor is taken as an example of the semiconductor device 40 ; the same description is applicable to an n-channel MOS transistor by inverting the conductivity type.
  • a device area 41 A including an n-type well is defined by STI type device separation areas 41 I.
  • a polysilicon gate electrode 43 is formed on the silicon substrate 41 via a gate dielectric film 42 .
  • a p-type impurity element such as B + is injected into the silicon substrate 41 by ion implantation, with the polysilicon gate electrode 43 acting as a mask.
  • a p-type source extension area 41 a and a p-type drain extension area 41 b are formed.
  • step shown in FIG. 4B on opposite sides of the polysilicon gate electrode 43 , side wall oxide films 430 X 1 and 430 X 2 are formed by a CVD method, with each having a thickness of 5 nm through 10 nm.
  • step shown in FIG. 4C outer side wall oxide films 430 Y 1 and 430 Y 2 are respectively formed on the side wall oxide films 430 X 1 and 430 X 2 by a CVD method.
  • Each of the outer side wall oxide films 430 Y 1 and 430 Y 2 continuously extend to cover part of the surface of the silicon substrate 41 . Furthermore, in the step shown in FIG.
  • SiN side wall dielectric films 43 SN 1 and 43 SN 2 are respectively formed on the outer side wall oxide films 430 Y 1 and 430 Y 2 .
  • the SiN side wall dielectric films 43 SN 1 and 43 SN 2 formed in this manner have higher HF etching resistance than that of the side wall oxide films 430 X 1 , 430 X 2 , 430 Y 1 , and 430 Y 2 .
  • a large dose of a p-type impurity element such as B + is injected into the silicon substrate 41 by ion implantation, with the polysilicon gate electrode 43 , the side wall oxide films 430 X 1 , 430 X 2 , 430 Y 1 , and 430 Y 2 , and the side wall dielectric films 43 SN 1 and 43 SN 2 acting as a mask. Accordingly, a p+ type source extension area 41 c and a p+ type drain extension area 41 d are formed in the silicon substrate 41 at areas outside the side wall dielectric films 43 SN 1 and 43 SN 2 .
  • the structure shown in FIG. 4D is placed in HF, and wet etching is performed on the side wall dielectric films 43 SN 1 and 43 SN 2 and the gate electrode 43 , so that the side wall oxide films 430 X 1 , 430 X 2 , 430 Y 1 , and 430 Y 2 recede. Accordingly, a gap is formed around the gate electrode 43 in such a manner that the top part of the gate electrode 43 is exposed.
  • the side wall oxide films between the side wall dielectric film 43 SN 1 or 43 SN 2 and the silicon substrate 41 i.e., the side wall oxide films 430 Y 1 and 430 Y 2 are also subjected to wet etching.
  • the exposed area of the side wall oxide films 430 Y 1 and 430 Y 2 is extremely small as shown in FIG. 4D , and therefore, the etching speed is slow.
  • the wet etching of the oxide films primarily occurs along the side wall faces of the gate electrode 43 .
  • a polysilicon film is deposited on the structure shown in FIG. 4E , so that the above-described gap is filled. Accordingly, a polysilicon gate electrode head 43 A, formed on the gate electrode 43 , has a width equal to the distance between the inner wall face of the side wall dielectric film 43 SN 1 and the inner wall face of the side wall dielectric film 43 SN 2 .
  • the polysilicon gate electrode head 43 A is extending above the top ends of the side wall dielectric films 43 SN 1 and 43 SN 2 .
  • the width of the polysilicon gate electrode head 43 A is substantially the same at the portion between the side wall dielectric films 43 SN 1 and 43 SN 2 and at the portion extending above the top ends of the side wall dielectric films 43 SN 1 and 43 SN 2 .
  • the source/drain extension areas 41 c , 41 d are doped to a high impurity concentration. Therefore, if a process for depositing a silicon film is performed to form the above-described polysilicon gate electrode head 43 A, a polysilicon film may grow on the source extension area 41 c and the drain extension area 41 d , but a Si epitaxial layer will not grow on these areas. Furthermore, by optimizing the process of depositing a silicon film, it is possible to mitigate the growth of a polysilicon film. By employing such optimal conditions, it is possible to only form a polysilicon gate electrode head 43 A.
  • the salicide steps described with reference to FIGS. 1A through 1C are performed on the structure processed as above. Accordingly, as shown in FIG. 4G , a silicide layer 45 G with low sheet resistance is formed on the polysilicon gate electrode head 43 A, so that the gate resistance is significantly reduced. At the same time, silicide layers 45 S, 45 D similar to the silicide layer 45 G are formed on the source extension area 41 c and the drain extension area 41 d , respectively.
  • the width of the polysilicon gate electrode head 43 A is effectively increased.
  • a p-channel MOS transistor is taken as an example; an embodiment of the present invention is also applicable to an n-channel MOS transistor by replacing the p-type impurity with an n-type impurity in the above description.
  • the n-type impurity “As” and “P” are usually employed.
  • FIGS. 5A through 5D illustrate a method of manufacturing a semiconductor device 60 according to a second embodiment of the present invention.
  • elements corresponding to those described above are denoted by the same reference numbers, and are not further described.
  • the steps shown in FIGS. 4A through 4C are performed. Then, immediately after these steps, a HF wet etching process is performed on the structure shown in FIG. 4C , so that a structure shown in FIG. 5A is formed, which is similar to the structure shown in FIG. 4E . However, unlike the step shown in FIG. 4D performed after the step shown in FIG. 4C , as shown in FIG. 5A , the source/drain extension areas 41 c , 41 d , doped to a high concentration, are not yet formed.
  • a polysilicon film is deposited on the structure shown in FIG. 5A , similar to the step shown in FIG. 4F . Accordingly, the polysilicon gate electrode head 43 A is formed on the gate electrode 43 . Furthermore, because the source/drain extension areas 41 c , 41 d are not yet formed on the surface of the silicon substrate 41 , epitaxial growth of silicon layers 44 A, 44 B occur on the silicon substrate 41 at areas outside of the side wall dielectric films 43 SN 1 and 43 SN 2 .
  • a large dose of a p-type impurity element such as B + is injected into the structure shown in FIG. 5B formed as above by ion implantation. Accordingly, the p+ type source extension area 41 c and the p+ type drain extension area 41 d are formed in the silicon substrate 41 at areas outside of the side wall dielectric films 43 SN 1 , 43 SN 2 . At the same time, the polysilicon gate electrode head 43 A and the gate electrode 43 are doped to be p+ types.
  • the Si layers 44 A, 44 B are formed in an epitaxial manner on the silicon substrate 41 as part of the source/drain areas, and therefore, the depth of the extension areas 41 c , 41 d formed in the silicon substrate 41 as source/drain areas can be reduced by a corresponding amount. As a result, it is possible to reduce leakage currents occurring between the bottom edge of the source extension area and the bottom edge of the drain extension area in the silicon substrate.
  • the above-described salicide process is performed on the structure shown in FIG. 5C . Accordingly, a structure is obtained in which the silicide layer 45 G corresponding to the gate electrode head 43 A is formed, and silicide layers 45 S, 45 D are formed in such a manner as to lay upon the source/drain extension areas 41 c , 41 d , respectively.
  • FIGS. 6A through 6D illustrate a method of manufacturing a semiconductor device 80 according to a third embodiment of the present invention.
  • elements corresponding to those described above are denoted by the same reference numbers, and are not further described.
  • the step shown in FIG. 6A corresponds to the step shown in FIG. 4E .
  • a selective wet etching process is performed by using HF to make the side wall oxide films 430 X 1 , 430 Y 1 , 430 X 2 , and 430 Y 2 recede, and the top part of the polysilicon gate electrode 43 is exposed.
  • the exposed part of the polysilicon gate electrode 43 is made to recede by performing a dry etching process using, for example, HCl as the etchant.
  • the polysilicon gate electrode 43 is made to recede to form a gap defined by the inner wall faces of the side wall oxide films 430 X 1 and 430 X 2 , in such a manner as to be in communication with the gap formed between the inner wall faces of the side wall dielectric films 43 SN 1 and 43 SN 2 .
  • a gate electrode top part and head 43 is formed in such a manner as to continue from the polysilicon gate electrode 43 .
  • the silicon polycrystal material is deposited by performing a low pressure CVD method using silane (SiH 4 ) gas or silane gas and germane (GeH 4 ) gas as the raw material at a substrate temperature of approximately 500° C.
  • silane (SiH 4 ) gas or silane gas and germane (GeH 4 ) gas as the raw material at a substrate temperature of approximately 500° C.
  • SiH 4 silane
  • germaneH 4 germane
  • the silicon polycrystal material can be deposited without dopant gas added, and later on an impurity element can be injected by ion implantation; however, the silicon polycrystal material can be deposited with dopant gas added.
  • the thickness of the polysilicon gate electrode 43 in contact with the gate dielectric film 42 is sufficiently reduced without exposing the gate dielectric film 42 .
  • the entire gate electrode including the polysilicon gate electrode head 43 A can be substantially doped to the desired conductivity type.
  • the semiconductor device is preferably a p-channel MOS transistor.
  • the silicide layer 45 G corresponding to the polysilicon gate electrode head 43 A is formed, and the silicide layers 45 S, 45 D are formed in such a manner as to lay upon the source/drain extension areas 41 c , 41 d , respectively.
  • the silicon epitaxial layers 44 A, 44 B it is also possible to cause the silicon epitaxial layers 44 A, 44 B to grow on the source/drain extension areas 41 c , 41 d.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
US11/961,317 2005-07-07 2007-12-20 Semiconductor device and manufacturing method thereof Abandoned US20080121883A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/012595 WO2007007375A1 (ja) 2005-07-07 2005-07-07 半導体装置およびその製造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2005/012595 Continuation WO2007007375A1 (ja) 2005-07-07 2005-07-07 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
US20080121883A1 true US20080121883A1 (en) 2008-05-29

Family

ID=37636783

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/961,317 Abandoned US20080121883A1 (en) 2005-07-07 2007-12-20 Semiconductor device and manufacturing method thereof

Country Status (5)

Country Link
US (1) US20080121883A1 (ja)
JP (1) JPWO2007007375A1 (ja)
KR (1) KR100958607B1 (ja)
CN (1) CN101218667B (ja)
WO (1) WO2007007375A1 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104810404A (zh) * 2015-04-08 2015-07-29 中国电子科技集团公司第五十五研究所 一种精细多晶硅硅化物复合栅结构及其制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168072A (en) * 1990-10-12 1992-12-01 Texas Instruments Incorporated Method of fabricating an high-performance insulated-gate field-effect transistor
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US5869359A (en) * 1997-08-20 1999-02-09 Prabhakar; Venkatraman Process for forming silicon on insulator devices having elevated source and drain regions
US6214679B1 (en) * 1999-12-30 2001-04-10 Intel Corporation Cobalt salicidation method on a silicon germanium film
US6287924B1 (en) * 1998-09-21 2001-09-11 Texas Instruments Incorporated Integrated circuit and method
US6461951B1 (en) * 1999-03-29 2002-10-08 Advanced Micro Devices, Inc. Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers
US20050116360A1 (en) * 2003-12-01 2005-06-02 Chien-Chao Huang Complementary field-effect transistors and methods of manufacture

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996030946A1 (fr) * 1995-03-29 1996-10-03 Hitachi, Ltd. Dispositif semi-conducteur et son procede de fabrication
JPH08330582A (ja) * 1995-06-02 1996-12-13 Oki Electric Ind Co Ltd Ｍｏｓｆｅｔおよびその製造方法
JPH098292A (ja) * 1995-06-21 1997-01-10 Hitachi Ltd 半導体装置及びその製造方法
JP3234144B2 (ja) * 1996-01-16 2001-12-04 沖電気工業株式会社 シリサイドゲート電極の形成方法
JPH09213941A (ja) * 1996-02-07 1997-08-15 Sony Corp 半導体装置及び半導体装置の製造方法
JPH10335651A (ja) * 1997-05-28 1998-12-18 Oki Electric Ind Co Ltd Ｍｏｓｆｅｔ及びｍｏｓｆｅｔの製造方法
KR19990018279A (ko) * 1997-08-27 1999-03-15 윤종용 살리사이드에 의한 게이트-소스-드레인 쇼트를 방지하는 모스펫 소자 및 그 제조방법
JP2001068673A (ja) * 1999-07-21 2001-03-16 Motorola Inc 半導体装置の形成方法
JP2001085392A (ja) * 1999-09-10 2001-03-30 Toshiba Corp 半導体装置の製造方法
JP2002246593A (ja) * 2001-02-20 2002-08-30 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5168072A (en) * 1990-10-12 1992-12-01 Texas Instruments Incorporated Method of fabricating an high-performance insulated-gate field-effect transistor
US5397909A (en) * 1990-10-12 1995-03-14 Texas Instruments Incorporated High-performance insulated-gate field-effect transistor
US5710450A (en) * 1994-12-23 1998-01-20 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US6326664B1 (en) * 1994-12-23 2001-12-04 Intel Corporation Transistor with ultra shallow tip and method of fabrication
US5869359A (en) * 1997-08-20 1999-02-09 Prabhakar; Venkatraman Process for forming silicon on insulator devices having elevated source and drain regions
US6287924B1 (en) * 1998-09-21 2001-09-11 Texas Instruments Incorporated Integrated circuit and method
US6461951B1 (en) * 1999-03-29 2002-10-08 Advanced Micro Devices, Inc. Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers
US6214679B1 (en) * 1999-12-30 2001-04-10 Intel Corporation Cobalt salicidation method on a silicon germanium film
US20050116360A1 (en) * 2003-12-01 2005-06-02 Chien-Chao Huang Complementary field-effect transistors and methods of manufacture

Also Published As

Publication number Publication date
CN101218667A (zh) 2008-07-09
JPWO2007007375A1 (ja) 2009-01-29
KR100958607B1 (ko) 2010-05-18
CN101218667B (zh) 2010-12-29
WO2007007375A1 (ja) 2007-01-18
KR20080011465A (ko) 2008-02-04

Similar Documents

Publication Publication Date Title
US7315063B2 (en) CMOS transistor and method of manufacturing the same
US6858506B2 (en) Method for fabricating locally strained channel
US8502301B2 (en) Semiconductor device and method for fabricating the same
KR101605150B1 (ko) 스트레인 유도 합금 및 그레이드형 도펀트 프로파일을 포함하는 인 시츄 형성되는 드레인 및 소스 영역들
CN101777516B (zh) 半导体集成电路的制造方法
US7714394B2 (en) CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same
US10079279B2 (en) FET with local isolation layers on S/D trench sidewalls
US7432180B2 (en) Method of fabricating a nickel silicide layer by conducting a thermal annealing process in a silane gas
US20060220153A1 (en) Method of fabricating a field effect transistor structure with abrupt source/drain junctions
US6608354B2 (en) Semiconductor device and method of manufacturing the same
US20030203560A1 (en) CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof
US20100181599A1 (en) Semiconductor device and method for fabricating the same
US20090085123A1 (en) Semiconductor device and method for fabricating the same
US20080194070A1 (en) Metal-oxide-semiconductor transistor device, manufacturing method thereof, and method of improving drain current thereof
US7732289B2 (en) Method of forming a MOS device with an additional layer
US7429525B2 (en) Fabrication process of a semiconductor device
US20080093666A1 (en) Semiconductor Device and Manufacturing Method Thereof
JP5034332B2 (ja) 半導体装置の製造方法
US20080121883A1 (en) Semiconductor device and manufacturing method thereof
US9412869B2 (en) MOSFET with source side only stress
JP2008171999A (ja) 半導体装置およびその製造方法
US20080070360A1 (en) Method and structure for forming silicide contacts on embedded silicon germanium regions of cmos devices
US6720224B2 (en) Method for forming transistor of semiconductor device
JPH11243065A (ja) 半導体装置の製造方法および導電性シリコン膜の形成方法
JP3918218B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: FUJITSU LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KIM, YOUNG SUK;REEL/FRAME:020324/0365

Effective date: 20071026

AS Assignment

Owner name: FUJITSU MICROELECTRONICS LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021976/0089

Effective date: 20081104

Owner name: FUJITSU MICROELECTRONICS LIMITED,JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021976/0089

Effective date: 20081104

AS Assignment

Owner name: FUJITSU SEMICONDUCTOR LIMITED, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:024651/0744

Effective date: 20100401

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION