US20070256937A1 - Apparatus and method for electrochemical processing of thin films on resistive substrates - Google Patents

Apparatus and method for electrochemical processing of thin films on resistive substrates Download PDF

Info

Publication number
US20070256937A1
US20070256937A1 US11/417,146 US41714606A US2007256937A1 US 20070256937 A1 US20070256937 A1 US 20070256937A1 US 41714606 A US41714606 A US 41714606A US 2007256937 A1 US2007256937 A1 US 2007256937A1
Authority
US
United States
Prior art keywords
semiconductor wafer
electrochemical
electrode
electrolytic solution
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/417,146
Other languages
English (en)
Inventor
Veeraraghavan Basker
John Cotte
Hariklia Deligianni
Matteo Flotta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US11/417,146 priority Critical patent/US20070256937A1/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BASKER, VEERARAGHAVAN S., COTTE, JOHN M., DELIGIANNI, HARIKLIA, FLOTTA, MATTEO
Priority to CN2007100881273A priority patent/CN101070602B/zh
Priority to JP2007120448A priority patent/JP5102534B2/ja
Priority to KR1020070043658A priority patent/KR20070108087A/ko
Publication of US20070256937A1 publication Critical patent/US20070256937A1/en
Priority to US12/198,274 priority patent/US8303791B2/en
Priority to US13/596,593 priority patent/US20120322243A1/en
Priority to US13/596,641 priority patent/US20120318673A1/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Abandoned legal-status Critical Current

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/005—Apparatus specially adapted for electrolytic conversion coating
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D11/00—Electrolytic coating by surface reaction, i.e. forming conversion layers
    • C25D11/02—Anodisation
    • C25D11/024—Anodisation under pulsed or modulated current or potential
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/011—Electroplating using electromagnetic wave irradiation
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/02—Etching
    • C25F3/14—Etching locally
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition

Definitions

  • This invention relates to the electrochemical processing of thin films directly on semiconducting or insulating layers and an apparatus for implementing such processes.
  • the metal is typically electrodeposited on a metallic seed or plating base layer.
  • the seed layer is typically formed on a semiconductor wafer by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • the current flow driving the electrodeposition is passed laterally through the seed layer from the electrical contact established at the seed layer edges. Current through the semiconductor wafer itself and any dielectric layers contained within the semiconductor wafer is essentially negligible.
  • Electrochemical processing of semiconducting/insulating materials can occur where the semiconductor wafer, typically a thin oxide coating or semiconductor, can conduct small amounts of an electric current.
  • Conductance can be provided by transport of charges directly through the valence or conduction band of a semiconducting/insulating semiconductor wafer. The latter case becomes important when working with semiconducting oxides such as TiO 2 , ZnO and Ta 2 O 5 , as well as any n-type wide band-gap semiconductor.
  • electron tunneling or current leakage can also be a mechanism for conductivity.
  • Defects can also provide many electron states in the band gap of an insulator and for a high density of gap states these defects can provide a pathway for the electric current.
  • FIG. 1 This principle is illustrated schematically in FIG. 1 .
  • empty oxidant states in solution overlap with the electron states of a conduction band of a semiconductor ( FIG. 1A )
  • electroreduction of oxidants will be possible at an n-doped semiconductor wafer (conduction band electrons available) but not at a p-doped semiconductor wafer (no conduction band electrons available in the dark).
  • the Gaussian distribution of oxidant states corresponds with energies in the band gap of a semiconductor, no charge transport will be possible and the oxidant can be expected to be inactive at this particular semiconductor wafer ( FIG. 1B ).
  • An electrochemical method comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, and the semiconductor wafer functions as a first electrode; providing a second electrode in the electrolytic solution, wherein the first and second electrodes are connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes.
  • the electrochemical method is a cathodic electrodeposition process of a 125 mm or larger, p-type semiconductor wafer with an optional insulating layer.
  • the process comprises: positioning the p-type semiconductor wafer in an electrolytic solution; positioning a counter electrode in the electrolytic solution; illuminating a front side of the p-type semiconductor wafer or the insulating layer, if present, or illuminating a back side of the semiconductor wafer, with a light source; and applying an electric current to the semiconductor wafer and to the counter electrode.
  • the electrochemical method is as an anodic electrochemical process of a 125 mm or larger, n-type semiconductor wafer with a metal layer.
  • the anodic process comprises: positioning the p-type semiconductor wafer in an electrolytic solution; positioning a counter electrode in the electrolytic solution; illuminating a front side or the back side of the n-type semiconductor wafer with a light source; and applying an electric current to the semiconductor wafer and to the counter electrode.
  • the anodic electrochemical process is an electroetching process of the metal layer or an anodization process of the metal layer.
  • the invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical methods of the invention.
  • FIGS. 1A to 1 C show schematic illustrations of electronic configurations for conduction and valence bands in a semiconductor wafer and an oxidant containing solution, with a Gaussian distribution of density of electron states;
  • FIGS. 2A and 2B show, in cross sectional view, a schematic illustration of blanket electrodeposition using through-gate dielectric current flow
  • FIG. 3 shows current-voltage curves for n-type and p-type Si/SiO 2 (1 nm)/HfO 2 (3 nm) in a nickel sulfate solution in the dark and under white-light illumination;
  • FIGS. 4A and 4B show, in cross sectional view, a schematic illustration of the selective photo-electrodeposition of a metal pattern on a blanket gate dielectric by illumination of the semiconductor wafer through a mask while applying a potential or current;
  • FIG. 5 is a schematic representation of an apparatus of the invention.
  • FIG. 6 is a schematic representation of another apparatus of the invention.
  • FIG. 7 is a schematic representation of another apparatus of the invention.
  • FIG. 8 is a schematic representation of another apparatus of the invention.
  • FIG. 9 is a schematic representation of another apparatus of the invention.
  • FIG. 10 shows a 200 mm silicon wafer electroplated selectively with copper
  • FIG. 11 is a graphical representation of capacitance-voltage characteristics for Re gates measured with a 100 ⁇ m ⁇ 100 ⁇ m MOS test structure
  • FIG. 12 exhibits the XRD diffraction patterns for deposited ruthenium using conventional methods known in the art and using the photo-electrodeposition process of the invention.
  • FIG. 13 exhibits the XRD diffraction patterns for deposited rhenium using conventional methods known in the art and using the photo-electrodeposition process of the invention.
  • the present invention describes an electrochemical process for obtaining thin films directly on a 125 mm or larger semiconductor wafer with or without an insulating layer, and an apparatus to conduct the process.
  • the electrochemical process comprises a backside contact scheme for electrical connection to a semiconductor wafer with or without an insulating layer, wherein the top surface of the semiconductor wafer/layer acts as an electrode, e.g., a working electrode, in the electrochemical process.
  • the desired electrochemical reaction can occur on the surface of the semiconductor wafer.
  • the desired electrochemical reaction can occur on a thin metallic/semiconductor/insulating layer disposed on top of the semiconductor wafer.
  • the process does not require an underlying seed layer to carry the current.
  • FIGS. 2A and 2B illustrate a contact scheme of one embodiment of the invention.
  • a dielectric layer 2 also referred to as an insulating layer or insulator
  • a dielectric layer 2 such as a thin gate oxide is placed atop a 125 mm or larger semiconductor wafer 4 such as silicon.
  • Electrical contact 5 is made to the semiconductor wafer 4 as a backside contact.
  • the insulating layer 2 is a semiconductor (such as a wide band-gap semiconductor, for example, n-ZnO, n-TiO 2 or n-Ta 2 O 5 ) for which an ohmic contact scheme is known, an electrical contact can be made directly to the insulating layer.
  • An electrolyte solution 1 is placed in contact with dielectric layer with the semiconductor wafer front side fully submerged, or optionally, with the semiconductor wafer partially submerged in areas where processing is desired.
  • the semiconductor wafer acts as one electrode and a counter electrode 6 is positioned in the electrolyte solution. While semiconductor wafer 4 and insulating layer 2 of FIG. 2 are shown as planar, it is understood that semiconductor wafer 4 can also have some topography and insulating layer 2 can be a conformal layer.
  • FIG. 2B shows the formation of a plated metal film 9 at the structure/electrolyte on the dielectric or insulating layer 2 .
  • electrochemical processing can be expected to occur preferentially on regions that are the most conductive since the current will follow the path of least resistance.
  • electrochemical processing by current transport across such semiconductor wafers can be an extremely selective process.
  • factors or parameters may determine the selectivity and include: underlying semiconductor wafer, insulator thickness, type of insulator, electrolyte solution, physical blockage, light, and other external means.
  • Electrode kinetics are also determined by the makeup of the underlying semiconductor wafer. These characteristics may vary dramatically, for example, according to the type of semiconductor wafer materials used and the type of doping used. Thus, they can be expected to be different for metals, n-type semiconductors, p-type semiconductors and combinations thereof.
  • electrochemical reduction of metal ions from solution for metal electrodeposition on the semiconductor wafer can be achieved either via the conduction band (electron capture process) or the valence band (hole injection process) for n-type semiconductor wafers, whereas electroreduction is only possible via a hole-injection process at p-type semiconductor wafers (in the dark), or when driven into inversion.
  • the semiconductor material including its band-gap and energy of band edges
  • the dopant concentration including its flat band potential and depletion layer thickness
  • SIE semiconductor/insulator/electrolyte
  • valence-band electrons over the band gap is necessary. This can be achieved by illumination of the semiconductor wafer, for example, via illumination through the electrolyte solution or from the back-side of the semiconductor wafer. Selectivity can be obtained in several ways. For example, careful selection of the light wavelength will activate electrochemical processes only at those semiconductor wafers or oxides where either the complete band gap can be crossed or gap states can be activated to mediate the electrode reaction. Alternatively, a narrow laser beam can be used to directly write an etched or deposited pattern, or a mask can be used to illuminate only certain regions of the semiconductor wafer surface.
  • the electrochemical process involves the electrodeposition of a metal layer on a 125 mm or larger semiconductor wafer.
  • the semiconductor wafer acts as the negative electrode (cathode) and provides the electrons required for the electrodeposition of the metal.
  • the electrodeposition process also includes providing a light source in order to facilitate the electrodeposition of the metal layer on semiconductor wafers with low or no electrons such as p-type silicon.
  • the electrochemical process involves the electroetching and/or anodization of a metal layer from a 125 mm or larger semiconductor wafer.
  • the electrochemical process requires positive charges and the semiconductor wafer acts as the positive electrode (anode).
  • the electrochemical process also includes providing a light source in order to facilitate the electroetching and/or anodization of a metal layer from the semiconductor wafer.
  • the electroetch or anodizing process will include a metal layer comprising one or more metals selected from Al, Ti, Zr, Nb, Hf, Ta, W, Mo and Cd.
  • the semiconductor wafer can comprise Si, Ge, In, Ga, Sb, P and any combination thereof.
  • FIG. 3 depicts the current-voltage characteristics (scanning towards negative voltage) for n-type and p-type Si/SiO 2 /HfO 2 semiconductor wafers in a nickel sulfate bath (0.1M NiSO 4 +0.1M H 3 BO 3 ) in the dark and under white-light illumination (21V, 150 W halogen lamp) during a potentiodynamic scan towards negative potentials (forward scan).
  • the current density i is given in milliamps per square centimeter (mA/cm 2 ) and the electrode potential U is given in Volts versus the Normal Hydrogen Electrode (NHE).
  • the scan rate was 50 millivolts per second and the electrode rotation rate was 250 rpm.
  • an n-type semiconductor wafer shows an exponential increase of the current at negative voltages past ⁇ 2V in the dark and under illumination.
  • the p-type semiconductor wafer does not show any current flow in the dark, and shows a cathodic current for Ni 2+ reduction below ⁇ 1.5V only if the sample is illuminated with light.
  • This phenomenon allows for the selective plating of n-type and p-type regions simultaneously exposed through mask openings.
  • n-type regions can be selectively metallized by electrodeposition in the dark and the p-type regions can be metallized with another metal of choice by photo-electrodeposition. In the latter case, both the n-and p-type areas are plated (i.e. the metal already deposited on the n-type areas gets another metal coating on top), or by the correct choice of deposition potential, the p-type regions are metallized selectively (no additional plating in n-type regions).
  • the current becomes limited by the light intensity at sufficiently negative applied potentials.
  • the incident photon flux and thus the measured photo-current are lowered if light is absorbed by the solution and by the deposited metal.
  • the current density for plating at p-type semiconductor wafers can be controlled by the light-intensity.
  • pulse plating can be done at constant potential by strobing or chopping the light beam.
  • the current-voltage characteristics show the selectivity of metal deposition on n-type and p-type semiconductor wafers. According to the above given example, Ni could be deposited selectively in the dark on n-type regions at potentials more negative than ⁇ 2V (by applying constant voltage or constant current). After the metal has been deposited in the n-type regions, Ni could be deposited selectively at the p-type regions under illumination at potentials between ⁇ 0.9V and ⁇ 1.8V.
  • n-Si would require light for obtaining electrochemical currents and p-type would not need light for the electrochemical reactions.
  • electroetching/anodization reactions light would be required for n-type semiconductor wafers.
  • FIG. 4 depicts an arrangement as described for FIG. 2A , but where selective photo-electrodeposition of a metal pattern 9 on a blanket gate dielectric 2 is achieved by illumination of the semiconductor wafer with a light source 20 through several openings in a mask 13 while applying a current to the semiconductor wafer 4 with an electrical contact 5 and the counter electrode 6 .
  • FIG. 4A depicts an arrangement for photo-electrodeposition
  • FIG. 4B shows the patterned metal obtained in the illuminated regions which where not blocked by the mask.
  • any method of patterning that provides open areas can be used in order to obtain the desired reaction in the open regions.
  • the patterning can be obtained with the help of a photoresist on the wafer.
  • the electrochemical process can be used in conjunction with both metallic and doped or undoped semiconductor wafers of 125 mm or larger.
  • Exemplary doped or undoped semiconductor wafers can be selected from a Si semiconductor wafer, a Ge semiconductor wafer or a (Si—Ge) semiconductor wafer, or a doped or undoped binary, tertiary and quaternary semiconductor wafer comprising Ga, As, P, Sb, In, Se and Al.
  • exemplary semiconductor wafers include a doped or undoped II-VI semiconductor wafer comprising Cd, Zn, Te, Se, S and combination of each thereof, and a doped or undoped oxide semiconductor wafer comprising Ti or Zr oxides, a Cu or Sr based semiconductor wafer or a semiconductor-on-insulator semiconductor wafer selected from silicon-on-insulator or silicon germanium-on-insulator combinations.
  • Still other exemplary semiconductor wafers can comprise electroluminescent polymer selected from polyacetylene, poly(dialkoxy p-phenylene-vinylene, poly(dialkylfluorene) and the derivatives of each thereof.
  • the electrochemical process of the invention includes electrodeposition processes in which one or more metals selected from the group consisting of Ru, Re, Ni, Pd, Co, Pt, Rh, Cr and Mn and any combination of each metal thereof is deposited on the semiconductor wafer.
  • Other select metals and non-metals selected from the group consisting of Os, Ir, Sb, Bi, Sn, In, Ga, Ge, As, Fe, Zn, Cd, Se, Te, Cu, Ag, Au, W, Hg, Tl, Po, Pb, Mo, V, B, C, P, S and any combination of each metal thereof can also be deposited on the semiconductor wafer.
  • FIG. 5 depicts an electrochemical apparatus that can be used in the described electrochemical processes of the invention.
  • the design of the apparatus is aimed towards processing 125 mm or larger, particularly 200 mm or 300 mm semiconductor wafers.
  • the apparatus can be modified to handle wafers of any shape or size.
  • the apparatus primarily consists of an electrolyte container tank 101 .
  • the silicon semiconductor wafer 111 is held by a tool head 102 equipped with pneumatic sealing and a ring seal 103 .
  • the ring seal 103 pushes the semiconductor wafer, against the metal plate 104 , thereby preventing the liquid from reaching the back side of the semiconductor wafer.
  • the metal plate 104 provides electrical contact to the semiconductor wafer.
  • Electrical contact to a semiconductor wafer such as Si can be made by a backside contact arrangement.
  • electrical contact to the semiconductor wafer can be made through an opening in an oxide layer.
  • a conductive or electric pathway from the point of contact to the dielectric on the semiconductor wafer can pass one or more interfaces and provides the electrical current path for the electrochemical process.
  • the electrical contact can also include a dry solid-state contact.
  • a dry solid-state contact to a semiconductor wafer can include an ohmic contact, which is typically created by providing a highly doped surface (about 10 19 cm ⁇ 3 ) through implantation of dopant elements or creation of surface defects.
  • certain metals can also be applied to the surface of the semiconductor wafer in order to facilitate electrical connectivity. For example, metals with low work functions such as indium can provide an ohmic contact for n-type semiconductor wafers. Metals with high work functions can provide an ohmic contact to p-type semiconductor wafers.
  • the apparatus further consists of a counter electrode 105 .
  • the counter electrode in this configuration is a mesh-type electrode so that the semiconductor wafer can be illuminated through the solution.
  • the illumination is provided by a light source 107 , whose wavelength can be chosen depending on the required energy levels for the desired electrodeposition.
  • the light source can be monochromatic such as a laser or a composite light source such as a halogen lamp. Further, the light source can include an arrangement to vary the light intensity in order to control the reaction rates.
  • the electrochemical apparatus of FIG. 5 is particularly useful if the plating solution is transparent or semi-transparent to the light source so that sufficient amounts of light can penetrate to the semiconductor wafer to facilitate the electrochemical reaction.
  • the apparatus can also include a shutter 106 disposed between the semiconductor wafer and the light source.
  • the apparatus can be used for pulse and pulse-reversal modes of electrochemical processing of the semiconductor wafers.
  • the metal contact 104 for the semiconductor wafer 111 is connected to one end of a power source 108 so that the semiconductor wafer can act as the cathode or the anode depending on the nature of the electrochemical process being performed.
  • the semiconductor wafer e.g., p-type silicon
  • the negative electrode cathode
  • the semiconductor wafer e.g. n-type silicon
  • the positive electrode anode
  • the counter electrode is then connected to the opposite end of the power source 109 to complete the electrical circuitry for each electrochemical process.
  • FIG. 6 depicts a modification of the tool head of FIG. 5 .
  • metal contact 204 is a mesh-type metal contact for providing electrical contact to semiconductor wafer 201
  • the lamp assembly 207 is placed within the tool head 102 .
  • Such design is advantageous with electrochemical processing conditions in which the electrolyte is near-opaque or opaque to light.
  • the light source helps in generating the current carriers (electrons or holes) directly from the back of the semiconductor wafer without being absorbed by the electroplating solution.
  • the counter electrode 205 can be a metal sheet or a mesh-type electrode.
  • the apparatus can also include a shutter 106 disposed between the semiconductor wafer and the light source 207 .
  • FIG. 7 depicts a tool modification in which uniform electrical contact is provided to the semiconductor wafer with a spring-loaded metal plate 310 .
  • the spring loaded metal plate 310 is electrically connected to a back plate 304 . As the semiconductor wafer 301 pushes against the ring seal 103 , the springs provide uniform pressure distribution on the surface of the semiconductor wafer and provide uniform current distribution across the back of the semiconductor wafer.
  • a spongy or mesh contact 310 ′ can be used to distribute the current uniformly across the semiconductor wafer. Further, in order to enhance the uniform current distribution, another high-conducting mesh 311 is connected to the spring-loaded plate 310 .
  • FIG. 8 depicts a further modification of the tool head of FIG. 7 .
  • the apparatus combines the modification of FIG. 6 .
  • the spring loaded plate 310 along with a high-conductivity mesh 311 provides uniform current distribution to the back of the semiconductor wafer 301 when it is pushed against the ring-seal 103 .
  • the lamp assembly 207 is placed inside the tool head so as to enable electrochemical processing of semiconductor wafers in which the electrolyte used is translucent or opaque to the light source.
  • FIG. 9 shows the apparatus modification in which the single counter electrode 105 and the light source 207 are contained within assembly 501 .
  • the assembly can be positioned in the tank and used to illuminate the semiconductor wafer. This arrangement can be used in the case of transparent or semi-transparent solutions.
  • the glass (or other transparent material) case 502 housing the lamp assembly 207 (for e.g., LED or halogen lamp) is protected against electrolyte leaking or seeping with o-rings 503 .
  • the counter electrode 105 in the form of a mesh is held in place with the help of o-rings 503 .
  • the lamp assembly 207 can be designed for any number of lamps and orientation. Two such lamp designs are shown in FIGS. 9A and 9B , in which low-intensity lamps 507 and high-intensity lamps 508 , respectively, can be arranged for illuminating the semiconductor wafer.
  • a plating solution comprising from 1 g/liter to 300 g/liter of CuSO 4 , 1 ml/liter to about 250 ml/liter of H 2 SO 4 and 1 to 10000 ppm of Cl ⁇ can be used.
  • the plating solution can comprise about 240 g/liter of CuSO 4 and about 100 g/liter of H 2 SO 4 , having a pH from about 1 to about 2.
  • the source of the Cl ⁇ is sodium chloride.
  • other inorganic constituents such as bromides, iodides, fluorides, sulfides, sulfates, boric acid, borates and metal salts & organic additives such as surfactants, brighteners, accelerators, suppressors and levelers can be added.
  • one or more of several methods of applying a current or voltage can be used. These include, for example: application of a constant current from 1 mA/cm 2 to 50 mA/cm 2 or equivalent potentials (electrode potentials of ⁇ 2V to ⁇ 3V versus NHE); and pulse plating with a first current from 5 mA/cm 2 to 250 mA/cm 2 for about 20 milliseconds to about 5 seconds such as about 0.1 second, and a second current from 1.0 ⁇ A/cm 2 up to 2 mA/cm 2 for about 0.1 seconds to about 10 seconds, including pulse plating with potentials of ⁇ 2V to 3.5V versus NHE for about 1 cycle up to about 500 cycles such as 25 cycles.
  • the temperature during processing can, for example, range from 20° C. to 90° C.
  • FIG. 10 shows an example of a 200 mm semiconductor wafer electroplated selectively with copper using the above mentioned bath and operating conditions. Copper was electroplated into deep vias with aspect ratios greater than 10, i.e, vias ranging from 1 to 40 ⁇ m in height and 0.1 to 2 ⁇ m in width.
  • the semiconductor wafer used in this example is n-Si/TaN/Ta/Cu.
  • the TaN/Ta/Cu layers were deposited using physical vapor deposition. The layers were very thin in the order of 100-300 ⁇ .
  • the liner material, typically Ta/TaN, and seed, typically Cu or Ru, was removed from the top of the vias using Chemical Mechanical Planarization (CMP) method prior to plating.
  • CMP Chemical Mechanical Planarization
  • a plating solution comprising from 1 g/liter to 100 g/liter of NH 4 ReO 4 and about 1 ml/liter to about 250 ml/liter of HCl (38%) can be used.
  • the plating solution can comprise about 10 g/liter of NH 4 ReO 4 and about 10 ml/liter of HCl (38 wt. %), having a pH from about 1 to about 2.
  • NH 4 ReO 4 other perrhenate salts and inorganic Re salts can be used.
  • other chloride salts can be used.
  • inorganic constituents such as bromides, iodides, fluorides, sulfides, sulfates, boric acid, borates and metal salts
  • organic additives such as surfactants
  • Patterned MOS structures were prepared by the electrodeposition of rhenium (Re) with p-type semiconductor wafers using a thick SiO 2 mask with openings from 1 ⁇ m ⁇ 1 ⁇ m to 400 ⁇ m ⁇ 400 ⁇ m.
  • the Re was deposited selectively on top of a high-k/SiO 2 /Si stack.
  • the high-k material was HfO 2 and HfSiO, 3 nm and 4 nm, respectively, which was prepared by MOCVD.
  • SiON (1 nm) was prepared by rapid thermal oxidation and the SiO 2 (1 nm) was a chemical oxide.
  • FIG. 11 is a graphical representation of capacitance-voltage and current-voltage characteristics for Re gates measured with a 100 ⁇ m ⁇ 100 ⁇ m MOS test structure.
  • the Re gates were prepared on 200 mm, p-type Si semiconductor wafers. The figure shows the uniformity of the electrical characteristics across the wafer.
  • the Re was deposited potentiostatically under white light illumination ( ⁇ 3V vs. SCE; 120V/500 W halogen lamp, 100 rpm).
  • one or more of several methods of applying a current or voltage can be used. These include, for example: application of a constant current from 3 mA/cm 2 to 50 mA/cm 2 or equivalent potentials (electrode potentials of ⁇ 2V to ⁇ 3V versus NHE); and pulse plating with a first current from 5 mA/cm 2 to 250 mA/cm 2 for about 20 milliseconds to about 5 seconds such as about 0.1 second, and a second current from 1.0 ⁇ A/cm 2 up to 2 mA/cm 2 for about 0.1 seconds to about 10 seconds, including pulse plating with potentials of ⁇ 2V to 3.5V versus NHE for about 1 cycle up to about 500 cycles such as 25 cycles.
  • the temperature during processing can, for example, range from 20° C. to 90° C.
  • FIGS. 12 ad 13 show XRD characteristics of the metal layers obtained by electroplating as compared to other conventional techniques such as evaporation, chemical vapor deposition and sputtering. Ru and Re were deposited by the conventional techniques under standard conditions.
  • the crystal structure orientation (100/002/101) for both ruthenium and rhenium vary depending upon the deposition process used.
  • the CVD and PVD/annealed exhibit quite similar crystal structure orientation in that the 002 intensity dominates the XRD and there appears to be very little contribution of 100 (comparing the peak intensities of both 002 and 101).
  • the ruthenium that is photo-electrodeposited by the process of the invention exhibits a crystal structure orientation in which 101 dominates the XRD and 100 and 002 exhibit similar intensities.
  • the as deposited evaporated Re (spectrum b) and the PVD/annealed Re (spectrum e) exhibit quite similar crystal structure orientation in that all three crystal orientations exhibit similar intensities in the XRD.
  • the Re that is photo-electrodeposited by the process of the invention exhibits a crystal structure orientation in which 002 peak dominates and there is very little contribution from 100.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Electromagnetism (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Formation Of Insulating Films (AREA)
US11/417,146 2006-05-04 2006-05-04 Apparatus and method for electrochemical processing of thin films on resistive substrates Abandoned US20070256937A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US11/417,146 US20070256937A1 (en) 2006-05-04 2006-05-04 Apparatus and method for electrochemical processing of thin films on resistive substrates
CN2007100881273A CN101070602B (zh) 2006-05-04 2007-03-15 电化学方法和用于电化学方法的设备
JP2007120448A JP5102534B2 (ja) 2006-05-04 2007-05-01 抵抗性半導体ウェハ上に薄膜を電気化学処理するための装置及び方法
KR1020070043658A KR20070108087A (ko) 2006-05-04 2007-05-04 저항성 반도체 웨이퍼상에서 박막의 전기화학적 처리 장치및 방법
US12/198,274 US8303791B2 (en) 2006-05-04 2008-08-26 Apparatus and method for electrochemical processing of thin films on resistive substrates
US13/596,593 US20120322243A1 (en) 2006-05-04 2012-08-28 Apparatus and method for electrochemical processing of thin films on resistive substrates
US13/596,641 US20120318673A1 (en) 2006-05-04 2012-08-28 Apparatus and method for electrochemical processing of thin films on resistive substrates

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/417,146 US20070256937A1 (en) 2006-05-04 2006-05-04 Apparatus and method for electrochemical processing of thin films on resistive substrates

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/198,274 Continuation US8303791B2 (en) 2006-05-04 2008-08-26 Apparatus and method for electrochemical processing of thin films on resistive substrates

Publications (1)

Publication Number Publication Date
US20070256937A1 true US20070256937A1 (en) 2007-11-08

Family

ID=38660227

Family Applications (4)

Application Number Title Priority Date Filing Date
US11/417,146 Abandoned US20070256937A1 (en) 2006-05-04 2006-05-04 Apparatus and method for electrochemical processing of thin films on resistive substrates
US12/198,274 Expired - Fee Related US8303791B2 (en) 2006-05-04 2008-08-26 Apparatus and method for electrochemical processing of thin films on resistive substrates
US13/596,641 Abandoned US20120318673A1 (en) 2006-05-04 2012-08-28 Apparatus and method for electrochemical processing of thin films on resistive substrates
US13/596,593 Abandoned US20120322243A1 (en) 2006-05-04 2012-08-28 Apparatus and method for electrochemical processing of thin films on resistive substrates

Family Applications After (3)

Application Number Title Priority Date Filing Date
US12/198,274 Expired - Fee Related US8303791B2 (en) 2006-05-04 2008-08-26 Apparatus and method for electrochemical processing of thin films on resistive substrates
US13/596,641 Abandoned US20120318673A1 (en) 2006-05-04 2012-08-28 Apparatus and method for electrochemical processing of thin films on resistive substrates
US13/596,593 Abandoned US20120322243A1 (en) 2006-05-04 2012-08-28 Apparatus and method for electrochemical processing of thin films on resistive substrates

Country Status (4)

Country Link
US (4) US20070256937A1 (ja)
JP (1) JP5102534B2 (ja)
KR (1) KR20070108087A (ja)
CN (1) CN101070602B (ja)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100108525A1 (en) * 2008-11-06 2010-05-06 Andreas Krause Light-induced plating
WO2010108996A1 (en) * 2009-03-27 2010-09-30 Alchimer Device and method to conduct an electrochemical reaction on a surface of a semiconductor substrate
US20110011745A1 (en) * 2007-11-30 2011-01-20 Wuxi Suntech Power Co., Ltd. Method for electrochemically depositing a metal electrode of a solar cell
US20120097547A1 (en) * 2010-10-25 2012-04-26 Universiteit Gent Method for Copper Electrodeposition
US20120318666A1 (en) * 2007-11-15 2012-12-20 International Business Machines Corporation Method and apparatus for electroplating on soi and bulk semiconductor wafers
EP2500927A3 (de) * 2011-03-17 2014-07-30 SEMIKRON Elektronik GmbH & Co. KG Verfahren zur Abscheidung einer Metallschicht auf einem Halbleiterbauelement und Halbleiterbauelement
WO2014029667A3 (de) * 2012-08-22 2014-09-04 Fraunhofer-Gesellsch. Z. Förderung D. Angew. Forschung E.V. Verfahren und vorrichtung zum lichtinduzierten oder lichtunterstützten abscheiden von metall auf einer oberfläche eines halbleiterbauelements
EP3206236A4 (en) * 2014-10-20 2017-11-22 Sharesun Co., Ltd. Method for horizontally electrochemically depositing metal
US10985006B2 (en) * 2018-03-20 2021-04-20 Toshiba Memory Corporation Electrolytic plating apparatus
US20220263572A1 (en) * 2021-02-17 2022-08-18 Wistron Corporation Optical Network Optimizer and Optical Network Optimization Method Thereof
US12012667B2 (en) 2018-04-09 2024-06-18 Lam Research Corporation Copper electrofill on non-copper liner layers

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110253545A1 (en) * 2010-04-19 2011-10-20 International Business Machines Corporation Method of direct electrodeposition on semiconductors
EP2463410B1 (en) 2010-12-13 2018-07-04 Rohm and Haas Electronic Materials LLC Electrochemical etching of semiconductors
JP2012159448A (ja) * 2011-02-02 2012-08-23 Toshiba Corp 欠陥検査方法および半導体装置の製造方法
US8703572B2 (en) 2011-10-10 2014-04-22 International Business Machines Corporation Embeded DRAM cell structures with high conductance electrodes and methods of manufacture
CN102747397B (zh) * 2012-08-01 2015-05-20 云南大学 一种光诱导电镀制备太阳能电池表面栅状电极的方法及装置
CN102881732B (zh) * 2012-10-17 2015-06-03 云南大学 一种高光电转换率晶体硅太阳能电池及其制造方法
US10566638B2 (en) 2013-01-31 2020-02-18 The Curators Of The University Of Missouri Radiolytic electrochemical generator
US11932960B2 (en) * 2013-11-26 2024-03-19 Arizona Board Of Regents On Behalf Of Arizona State University Light-induced aluminum plating on silicon for solar cell metallization
US20170167042A1 (en) 2015-12-14 2017-06-15 International Business Machines Corporation Selective solder plating
WO2018044930A1 (en) * 2016-08-29 2018-03-08 Board Of Trustees Of The University Of Arkansas Light-directed electrochemical patterning of copper structures
CN106555219B (zh) * 2016-12-01 2019-05-17 福州大学 一种用于高通量材料制备的光定向电泳沉积方法
EP3413340B1 (en) * 2017-06-08 2021-11-17 Brooks Automation (Germany) GmbH Method for inspecting a container and inspection system
CN109518184B (zh) * 2018-11-23 2020-07-31 东南大学 一种Hf-BHfN-BHfNC复合涂层刀具及其制备方法
CN112813467B (zh) * 2019-11-15 2022-05-03 源秩科技（上海）有限公司 电化学加工装置及其方法
JP7279629B2 (ja) * 2019-12-24 2023-05-23 株式会社デンソー 光電気化学エッチング装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5209833A (en) * 1989-05-31 1993-05-11 Siemens Aktiengesellschaft Method and apparatus for large-area electrical contacting of a semiconductor crystal body with the assistance of electrolytes
US6010774A (en) * 1996-08-26 2000-01-04 Canon Kabushiki Kaisha Electrodeposition coated member
US6340544B1 (en) * 1996-09-19 2002-01-22 Fuji Xerox Co., Ltd. Process for recording image using photoelectrodeposition method and process for producing color filter using the same
US6797769B2 (en) * 2000-09-22 2004-09-28 Fuji Xerox Co., Ltd. Electrodepositing solution for low-potential electrodeposition and electrodeposition method using the same
US6974531B2 (en) * 2002-10-15 2005-12-13 International Business Machines Corporation Method for electroplating on resistive substrates
US20060163072A1 (en) * 2000-03-21 2006-07-27 Semitool, Inc. Electrolytic process using anion permeable barrier
US7449098B1 (en) * 1999-10-05 2008-11-11 Novellus Systems, Inc. Method for planar electroplating

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3345274A (en) * 1964-04-22 1967-10-03 Westinghouse Electric Corp Method of making oxide film patterns
US3890176A (en) * 1972-08-18 1975-06-17 Gen Electric Method for removing photoresist from substrate
JPS4972137A (ja) * 1972-11-11 1974-07-12
US4247373A (en) * 1978-06-20 1981-01-27 Matsushita Electric Industrial Co., Ltd. Method of making semiconductor device
US4283259A (en) * 1979-05-08 1981-08-11 International Business Machines Corporation Method for maskless chemical and electrochemical machining
JPS57141919A (en) 1981-02-26 1982-09-02 Fujitsu Ltd Manufacture of semiconductor device
JPS582024A (ja) * 1981-06-26 1983-01-07 Fujitsu Ltd 選択メツキ電極引き出し方法
US4473795A (en) * 1983-02-23 1984-09-25 International Business Machines Corporation System for resist defect measurement
US4507181A (en) * 1984-02-17 1985-03-26 Energy Conversion Devices, Inc. Method of electro-coating a semiconductor device
JPH072996B2 (ja) * 1984-09-21 1995-01-18 株式会社日立製作所 光誘起電極反応装置
US5086328A (en) * 1988-02-08 1992-02-04 Santa Barbara Research Center Photo-anodic oxide surface passivation for semiconductors
JPH01259532A (ja) * 1988-04-08 1989-10-17 Fujitsu Ltd 光照射めっき方法及び装置
DE4036895A1 (de) * 1990-11-20 1992-05-21 Messerschmitt Boelkow Blohm Elektrochemisches verfahren zum anisotropen aetzen von silizium
US5348627A (en) * 1993-05-12 1994-09-20 Georgia Tech Reserach Corporation Process and system for the photoelectrochemical etching of silicon in an anhydrous environment
US5581091A (en) * 1994-12-01 1996-12-03 Moskovits; Martin Nanoelectric devices
US6042712A (en) * 1995-05-26 2000-03-28 Formfactor, Inc. Apparatus for controlling plating over a face of a substrate
JP3193863B2 (ja) * 1996-01-31 2001-07-30 ホーヤ株式会社 転写マスクの製造方法
US6699667B2 (en) * 1997-05-14 2004-03-02 Keensense, Inc. Molecular wire injection sensors
US6074546A (en) * 1997-08-21 2000-06-13 Rodel Holdings, Inc. Method for photoelectrochemical polishing of silicon wafers
JP3125748B2 (ja) * 1998-05-27 2001-01-22 富士ゼロックス株式会社 画像記録方法
JP3187011B2 (ja) * 1998-08-31 2001-07-11 日本電気株式会社 半導体装置の製造方法
EP1132500A3 (en) 2000-03-08 2002-01-23 Applied Materials, Inc. Method for electrochemical deposition of metal using modulated waveforms
WO2001091170A1 (fr) * 2000-05-24 2001-11-29 Mitsubishi Denki Kabushiki Kaisha Procede et appareil d'attaque electrochimique par rayonnement et produit grave
KR100370171B1 (ko) 2001-03-15 2003-01-29 주식회사 하이닉스반도체 반도체 소자의 격리막 형성 방법
US6815959B2 (en) * 2001-04-09 2004-11-09 Kla-Tencor Technologies Corp. Systems and methods for measuring properties of conductive layers
JP4177567B2 (ja) * 2001-06-26 2008-11-05 松下電工株式会社 陽極酸化方法および陽極酸化装置および電界放射型電子源およびメモリ素子
US6709929B2 (en) * 2001-06-25 2004-03-23 North Carolina State University Methods of forming nano-scale electronic and optoelectronic devices using non-photolithographically defined nano-channel templates
US6998219B2 (en) * 2001-06-27 2006-02-14 University Of South Florida Maskless photolithography for etching and deposition
US6881318B2 (en) 2001-07-26 2005-04-19 Applied Materials, Inc. Dynamic pulse plating for high aspect ratio features
US20030181136A1 (en) * 2002-03-22 2003-09-25 Billett Bruce H. CMP pad platen with viewport
US6872645B2 (en) * 2002-04-02 2005-03-29 Nanosys, Inc. Methods of positioning and/or orienting nanostructures
JP2003347272A (ja) * 2002-05-24 2003-12-05 Fujikura Ltd 光励起電解研磨法による貫通孔形成方法
US6805786B2 (en) * 2002-09-24 2004-10-19 Northrop Grumman Corporation Precious alloyed metal solder plating process
US20040084320A1 (en) * 2002-10-30 2004-05-06 Xerox Corporation Copper interconnect by immersion/electroless plating in dual damascene process
US7025868B2 (en) * 2003-01-07 2006-04-11 The Boeing Company Methods and apparatus for simultaneous chlorine and alkaline-peroxide production
US7332062B1 (en) * 2003-06-02 2008-02-19 Lsi Logic Corporation Electroplating tool for semiconductor manufacture having electric field control
JP4314901B2 (ja) 2003-06-27 2009-08-19 富士ゼロックス株式会社 電着膜形成装置
US7250104B2 (en) * 2003-08-08 2007-07-31 Novellus Systems, Inc. Method and system for optically enhanced metal planarization
JP3802016B2 (ja) * 2003-08-27 2006-07-26 東京エレクトロン株式会社 陽極酸化装置、陽極酸化方法
US7476306B2 (en) * 2004-04-01 2009-01-13 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for electroplating
US7115959B2 (en) * 2004-06-22 2006-10-03 International Business Machines Corporation Method of forming metal/high-k gate stacks with high mobility
US7368045B2 (en) * 2005-01-27 2008-05-06 International Business Machines Corporation Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow
US7582556B2 (en) * 2005-06-24 2009-09-01 Megica Corporation Circuitry component and method for forming the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5209833A (en) * 1989-05-31 1993-05-11 Siemens Aktiengesellschaft Method and apparatus for large-area electrical contacting of a semiconductor crystal body with the assistance of electrolytes
US6010774A (en) * 1996-08-26 2000-01-04 Canon Kabushiki Kaisha Electrodeposition coated member
US6340544B1 (en) * 1996-09-19 2002-01-22 Fuji Xerox Co., Ltd. Process for recording image using photoelectrodeposition method and process for producing color filter using the same
US7449098B1 (en) * 1999-10-05 2008-11-11 Novellus Systems, Inc. Method for planar electroplating
US20060163072A1 (en) * 2000-03-21 2006-07-27 Semitool, Inc. Electrolytic process using anion permeable barrier
US6797769B2 (en) * 2000-09-22 2004-09-28 Fuji Xerox Co., Ltd. Electrodepositing solution for low-potential electrodeposition and electrodeposition method using the same
US6974531B2 (en) * 2002-10-15 2005-12-13 International Business Machines Corporation Method for electroplating on resistive substrates

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120318666A1 (en) * 2007-11-15 2012-12-20 International Business Machines Corporation Method and apparatus for electroplating on soi and bulk semiconductor wafers
US8926805B2 (en) * 2007-11-15 2015-01-06 International Business Machines Corporation Method and apparatus for electroplating on SOI and bulk semiconductor wafers
US20110011745A1 (en) * 2007-11-30 2011-01-20 Wuxi Suntech Power Co., Ltd. Method for electrochemically depositing a metal electrode of a solar cell
US20100108525A1 (en) * 2008-11-06 2010-05-06 Andreas Krause Light-induced plating
TWI512814B (zh) * 2009-03-27 2015-12-11 Alchimer 在半導體基材表面上實行電化學反應之裝置及方法
WO2010108996A1 (en) * 2009-03-27 2010-09-30 Alchimer Device and method to conduct an electrochemical reaction on a surface of a semiconductor substrate
FR2943688A1 (fr) * 2009-03-27 2010-10-01 Alchimer Dispositif et procede pour realiser une reaction electrochimique sur une surface d'un substrat semi-conducteur
US8795503B2 (en) 2009-03-27 2014-08-05 Alchimer Device and method to conduct an electrochemical reaction on a surface of a semi-conductor substrate
US20120097547A1 (en) * 2010-10-25 2012-04-26 Universiteit Gent Method for Copper Electrodeposition
EP2500927A3 (de) * 2011-03-17 2014-07-30 SEMIKRON Elektronik GmbH & Co. KG Verfahren zur Abscheidung einer Metallschicht auf einem Halbleiterbauelement und Halbleiterbauelement
WO2014029667A3 (de) * 2012-08-22 2014-09-04 Fraunhofer-Gesellsch. Z. Förderung D. Angew. Forschung E.V. Verfahren und vorrichtung zum lichtinduzierten oder lichtunterstützten abscheiden von metall auf einer oberfläche eines halbleiterbauelements
EP3206236A4 (en) * 2014-10-20 2017-11-22 Sharesun Co., Ltd. Method for horizontally electrochemically depositing metal
US10985006B2 (en) * 2018-03-20 2021-04-20 Toshiba Memory Corporation Electrolytic plating apparatus
US12012667B2 (en) 2018-04-09 2024-06-18 Lam Research Corporation Copper electrofill on non-copper liner layers
US20220263572A1 (en) * 2021-02-17 2022-08-18 Wistron Corporation Optical Network Optimizer and Optical Network Optimization Method Thereof
US11863231B2 (en) * 2021-02-17 2024-01-02 Wistron Corporation Optical network optimizer and optical network optimization method thereof

Also Published As

Publication number Publication date
KR20070108087A (ko) 2007-11-08
US20090057154A1 (en) 2009-03-05
US20120318673A1 (en) 2012-12-20
JP5102534B2 (ja) 2012-12-19
US8303791B2 (en) 2012-11-06
JP2007297714A (ja) 2007-11-15
US20120322243A1 (en) 2012-12-20
CN101070602A (zh) 2007-11-14
CN101070602B (zh) 2010-05-26

Similar Documents

Publication Publication Date Title
US8303791B2 (en) Apparatus and method for electrochemical processing of thin films on resistive substrates
US7868410B2 (en) Gate stack engineering by electrochemical processing utilizing through-gate-dielectric current flow
US8790956B2 (en) Structure and method of fabricating a CZTS photovoltaic device by electrodeposition
JP5123394B2 (ja) 太陽電池の金属電極の電気化学的堆積方法
CN101263246B (zh) 通过电镀使用金属涂布基底表面的方法
CN101263247B (zh) 用于使用金属涂布基底表面的电镀组合物
US8926805B2 (en) Method and apparatus for electroplating on SOI and bulk semiconductor wafers
US20080128013A1 (en) Electroplating on roll-to-roll flexible solar cell substrates
US7918984B2 (en) Method of electrodepositing germanium compound materials on a substrate
CN101681993A (zh) 溶液处理的固体电解层器件和制造
TW200834948A (en) Precision printing electroplating through plating mask on a solar cell substrate
US20130230933A1 (en) Methods for fabricating thin film solar cells
US8343327B2 (en) Apparatus and methods for fast chemical electrodeposition for fabrication of solar cells
TW200834951A (en) Apparatus and method for electroplating on a solar cell substrate
EP2009143B1 (en) Bipolar electroless deposition method
Philipsen et al. Nucleation and growth kinetics of electrodeposited Ni films on Si (100) surfaces
EIECTROCHEMICA et al. Vereecken et al.

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BASKER, VEERARAGHAVAN S.;COTTE, JOHN M.;DELIGIANNI, HARIKLIA;AND OTHERS;REEL/FRAME:018127/0170

Effective date: 20060424

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910