US20170167042A1 - Selective solder plating - Google Patents
Selective solder plating Download PDFInfo
- Publication number
- US20170167042A1 US20170167042A1 US14/967,861 US201514967861A US2017167042A1 US 20170167042 A1 US20170167042 A1 US 20170167042A1 US 201514967861 A US201514967861 A US 201514967861A US 2017167042 A1 US2017167042 A1 US 2017167042A1
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- Prior art keywords
- comprised
- indium
- tin
- plating bath
- metal layer
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- Abandoned
Links
- 238000007747 plating Methods 0.000 title claims abstract description 54
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 57
- 239000000463 material Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000009713 electroplating Methods 0.000 claims abstract description 14
- 229910052738 indium Inorganic materials 0.000 claims description 31
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 31
- 239000010949 copper Substances 0.000 claims description 27
- 239000010936 titanium Substances 0.000 claims description 21
- 229910021607 Silver chloride Inorganic materials 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- HKZLPVFGJNLROG-UHFFFAOYSA-M silver monochloride Chemical compound [Cl-].[Ag+] HKZLPVFGJNLROG-UHFFFAOYSA-M 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- AFVFQIVMOAPDHO-UHFFFAOYSA-N Methanesulfonic acid Chemical compound CS(O)(=O)=O AFVFQIVMOAPDHO-UHFFFAOYSA-N 0.000 claims description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 claims description 3
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 claims description 3
- 239000002253 acid Substances 0.000 claims description 3
- VUAQKPWIIMBHEK-UHFFFAOYSA-K bis(methylsulfonyloxy)indiganyl methanesulfonate Chemical compound [In+3].CS([O-])(=O)=O.CS([O-])(=O)=O.CS([O-])(=O)=O VUAQKPWIIMBHEK-UHFFFAOYSA-K 0.000 claims description 3
- JWVAUCBYEDDGAD-UHFFFAOYSA-N bismuth tin Chemical compound [Sn].[Bi] JWVAUCBYEDDGAD-UHFFFAOYSA-N 0.000 claims description 3
- VBXWCGWXDOBUQZ-UHFFFAOYSA-K diacetyloxyindiganyl acetate Chemical compound [In+3].CC([O-])=O.CC([O-])=O.CC([O-])=O VBXWCGWXDOBUQZ-UHFFFAOYSA-K 0.000 claims description 3
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims description 3
- 229910003437 indium oxide Inorganic materials 0.000 claims description 3
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 claims description 3
- 229910000337 indium(III) sulfate Inorganic materials 0.000 claims description 3
- PSCMQHVBLHHWTO-UHFFFAOYSA-K indium(iii) chloride Chemical compound Cl[In](Cl)Cl PSCMQHVBLHHWTO-UHFFFAOYSA-K 0.000 claims description 3
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 3
- XGCKLPDYTQRDTR-UHFFFAOYSA-H indium(iii) sulfate Chemical compound [In+3].[In+3].[O-]S([O-])(=O)=O.[O-]S([O-])(=O)=O.[O-]S([O-])(=O)=O XGCKLPDYTQRDTR-UHFFFAOYSA-H 0.000 claims description 3
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 claims description 3
- 229940098779 methanesulfonic acid Drugs 0.000 claims description 3
- LNOPIUAQISRISI-UHFFFAOYSA-N n'-hydroxy-2-propan-2-ylsulfonylethanimidamide Chemical compound CC(C)S(=O)(=O)CC(N)=NO LNOPIUAQISRISI-UHFFFAOYSA-N 0.000 claims description 3
- 150000003839 salts Chemical class 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910000969 tin-silver-copper Inorganic materials 0.000 claims description 3
- 239000000080 wetting agent Substances 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004082 amperometric method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- XLYOFNOQVPJJNP-ZSJDYOACSA-N heavy water Substances [2H]O[2H] XLYOFNOQVPJJNP-ZSJDYOACSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- -1 but not limited to Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- HTXDPTMKBJXEOW-UHFFFAOYSA-N dioxoiridium Chemical compound O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910000457 iridium oxide Inorganic materials 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/04—Tubes; Rings; Hollow bodies
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
- B23K35/262—Sn as the principal constituent
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/001—Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D17/00—Constructional parts, or assemblies thereof, of cells for electrolytic coating
- C25D17/10—Electrodes, e.g. composition, counter electrode
- C25D17/12—Shape or form
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/30—Electroplating: Baths therefor from solutions of tin
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/54—Electroplating: Baths therefor from solutions of metals not provided for in groups C25D3/04 - C25D3/50
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/56—Electroplating: Baths therefor from solutions of alloys
- C25D3/60—Electroplating: Baths therefor from solutions of alloys containing more than 50% by weight of tin
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
Definitions
- the embodiments of this invention relate generally to soldering operations such as those used to create a seal and, more specifically, relate to soldering operations performed over a surface of a substrate containing apertures or voids (recessed structures) in the surface, or raised structures on the surface.
- a seal made with low melting temperature solder can be beneficial for certain devices such as devices formed on or in a surface of a semiconductor wafer.
- solder alloys are typically not compatible with some typically used semiconductor wafer processing techniques such as plasma enhanced chemical vapor deposition (PECVD) and deep reactive ion etch (RIE) processes.
- PECVD plasma enhanced chemical vapor deposition
- RIE deep reactive ion etch
- the embodiments of this invention provide a method that comprises providing a structure comprised of a substrate having a metal layer disposed on a surface and a metal feature disposed on the metal layer; immersing the structure in a plating bath contained in an electroplating cell, the plating bath comprising a selected solder material; applying a voltage potential to the structure, where the structure functions as a working electrode in combination with a reference electrode and a counter electrode that are also immersed in the plating bath; and maintaining the voltage potential at a predetermined value to deposit the selected solder material selectively only on the metal feature and not on the metal layer.
- the embodiments of this invention provide an apparatus that comprises a tank containing a plating bath of an electroplating cell, the plating bath comprising a selected solder material; a working electrode immersed in the plating bath, the working electrode comprised of a structure that comprises a semiconductor substrate having a metal layer disposed on a surface and a metal feature disposed on the metal layer; a reference electrode and a counter electrode immersed in the plating bath; and a power supply connected with a potentiostat configured to maintain a voltage potential of the working electrode at a predetermined constant value with respect to the reference electrode to deposit the selected solder material selectively only on the metal feature and not on the metal layer.
- FIGS. 1A, 1B and 1C collectively referred to as FIG. 1 , illustrate enlarged views of a structure wherein the various layer thicknesses and other dimensions are not necessarily drawn to scale. More specifically, FIG. 1A is a top view of the structure, FIG. 1B is a cross-sectional view taken along the section line labeled 1 B- 1 B in FIG. 1A , and FIG. 1C is a further enlarged view of a portion of the structure shown in FIG. 1B .
- FIG. 2 shows one example of a conventional electroplating cell.
- FIG. 3 depicts a non-limiting example of a three electrode electroplating cell that can be used to selectively plate solder on a patterned substrate in accordance with embodiments of this invention.
- FIG. 4 is a graph depicting amperometry plots of Indium plating on Cu/Ti using the electroplating cell of FIG. 3 .
- a substrate that contains at least one recessed feature such as a void or an opening or a trench in a surface of the substrate.
- the embodiments of this invention apply as well to a substrate having a raised feature disposed on the surface.
- a given substrate could include at least one recessed feature and at least one raised feature on the surface.
- the embodiments of this invention provide a method to selectively deposit solder plating onto a predefined plating area without requiring the use of a layer of photoresist during the solder plating operation.
- the use of the embodiments of this invention can be especially beneficial when there are pre-existing structures and/or pre-existing apertures or voids (e.g., deep trenches) on and in the surface of a semiconductor wafer, where the presence of such structures and/or voids would interfere with an ability to deposit and pattern photoresist to define regions where a selected solder material would be deposited.
- FIGS. 1A, 1B and 1C collectively referred to as FIG. 1 , for showing enlarged views of an exemplary structure of interest to the embodiments of this invention.
- FIG. 1A is a top view of the structure
- FIG. 1B is a cross-sectional view taken along the section line labeled 1 B- 1 B in FIG. 1A
- FIG. 1C is a further enlarged view of a portion of the structure shown in FIG. 1B .
- the structure is comprised of a substrate 10 , e.g., a Silicon (Si) substrate, having a metal layer 12 , e.g., a Titanium (Ti) layer, a Tantalum (Ta) layer, or a Titanium Tungsten alloy (TiW) layer, disposed on a top surface thereof.
- a metal structure also referred to herein as a metal feature, such as a ring 16 , e.g., a Copper (Cu) ring, is disposed on the Ti layer 12 .
- a ring 16 e.g., a Copper (Cu) ring
- an aperture or recess 14 formed through the Ti layer 12 and partially into the Si substrate 10 .
- the recess 14 could have a diameter in a range of about 200 ⁇ m to about 500 ⁇ m and a depth of about 100 ⁇ m (or deeper), the Ti layer 12 could have a thickness in a range of about 30 nm to about 60 nm, and the Cu ring 16 could have a height and a width that is less than about 10 ⁇ , for example in a range of about 1 ⁇ m to about 2 ⁇ m.
- the spacing (Sp) between an inner edge of the Cu ring 16 and the outer edge of the recess 14 could be, for example, about 10 ⁇ m or less.
- the Cu feature 16 could have a shape other than circular, such as an ovoid or a square or a rectangular shape, or a hexagonal shape, or any desired regular or irregular shape.
- the circular shape is shown simply for convenience.
- the recess 14 could have other than the circular top opening shape as shown, and in some embodiments the recess 14 could have other than the vertical sidewalls that are illustrated.
- FIG. 1C shows a portion of the structure, i.e., a portion of the Si substrate 10 , Ti layer 12 and metal (Cu) ring 16 on the left side of the view of FIG. 1B , after performing a plating operation to selectively form a solder plating layer 18 on the surface of the Cu ring 16 and not on the surface of the surrounding Ti layer 12 .
- the solder plating layer 18 can then be used to solder bond a cover (e.g., a solder, gold, or other type of solder wettable metal-containing cover) over the recess 14 so as to seal (e.g., hermetically seal) the recess 14 from the ambient.
- a cover e.g., a solder, gold, or other type of solder wettable metal-containing cover
- the recess 14 could contain any desired type of device or devices, such as one or more sensors, actuators, energy storage devices and/or micro-electro-mechanical systems (MEMS).
- MEMS micro-electro-mechanical systems
- the selected device or devices disposed within the recess 14 can be electrically contacted via the Si substrate 10 .
- solder plating operation may have involved depositing a dielectric layer (e.g. a layer of photoresist) over the structure followed by a photolithographic patterning operation to define and etch a circular trench in the dielectric layer so as to expose the top surface of the Cu ring 16 .
- a dielectric layer e.g. a layer of photoresist
- the desired solder plating material could be blanket deposited over the patterned photoresist layer so as to also cover the top surface of the Cu ring 16 , followed by resist liftoff and cleaning.
- this approach would involve a time-consuming multi-step deposition and liftoff process that would be complicated by the presence of the recess 14 in close proximity to the Cu ring 16 .
- the spacing (Sp) between the ring 16 and the edge of the recess 14 may be only about 10 ⁇ m, making it difficult to pattern the photoresist layer so close to the recess 14 .
- solder plating operation is performed without requiring the deposition and patterning of a photoresist layer. Instead the solder plating operation is performed using a multi-electrode electroplating cell with a selected solder or solder alloy and plating bath.
- FIG. 2 shows one example of a conventional electroplating cell 20 .
- the cell 20 includes a tank 22 that contains a tin plating bath 24 .
- Immersed in the bath 24 is a cathode 26 , i.e., a substrate to be plated, and an anode 28 , e.g., tin metal.
- the cathode 26 and the anode 28 are connected to a power supply 30 .
- the anode 28 is the metal to be plated on the cathode 26 (e.g., Tin) or an insoluble anode (e.g., platinized Titanium or Iridium oxide coated Titanium).
- Tin Tin
- an insoluble anode e.g., platinized Titanium or Iridium oxide coated Titanium
- FIG. 3 shows a more preferred example of an electroplating cell that can be used in accordance with embodiments of this invention to selectively deposit the solder plating layer 18 (e.g., a layer of Indium) only on the Cu ring 16 as in FIG. 1 , and not on the Ti layer 12 .
- FIG. 3 depicts a non-limiting example of a three electrode electroplating cell 40 that can be used to plate Indium solder on the patterned silicon wafer 10 .
- a tank 42 contains an Indium plating bath 44 . Immersed in the bath 44 is a working electrode 46 , a counter electrode 48 and a reference electrode 50 .
- the three electrodes are connected to the power supply via a potentiostat 52 .
- the potentiostat 52 functions by maintaining the potential of the working electrode 46 at a desired constant level with respect to the reference electrode 50 and passing the current at the counter electrode 48 .
- the working electrode 46 is the Si wafer 10 having the Cu ring 16 that is to be plated (as in FIGS. 1A and 1B )
- the reference electrode 50 can be comprised of Ag/AgCl in 3M KCl
- the counter electrode 48 can be comprised of a Pt mesh.
- the solder plating takes place under constant potential control.
- the reference electrode 50 via the potentiostat 52 , maintains a constant electrical potential between the working electrode 46 and the reference electrode 50 , and current flows between the counter electrode 48 and the working electrode 46 .
- Non-limiting examples of solder and solder alloys that can be used in accordance with embodiments of this invention include, in addition to Indium: Tin, Tin-Silver, Tin-Silver-Copper, Indium-Tin, Tin-Lead, Tin-Bismuth and Tin-Gold.
- Tin Tin-Silver
- Tin-Silver-Copper Indium-Tin
- Tin-Lead Tin-Lead
- Tin-Bismuth Tin-Gold.
- non-limiting examples of the composition of the Indium plating bath 44 that can be used in accordance with embodiments of this invention include: a source of Indium metal such as but not limited to Indium Sulfate, Indium Chloride, Indium Methanesulfonate, Indium Acetate or Indium oxide.
- the Indium plating bath 44 also includes a conductivity salt or acid such as, but not limited to, Sulfuric acid, Hydrochloric acid, Methane Sulfonic acid or Sulfamic acid.
- the Indium plating bath 44 also preferably includes a wetting agent or grain refiner such as, but not limited to, about 0.01% to about 2% of organic molecules such as a surfactant.
- the result was that selective Indium plating was achieved on the Cu ring 16 and not on the surrounding surface of the metal layer 12 .
- the Indium deposit 18 was smooth, but the deposition rate was low, i.e., less than 0.1 ⁇ m/min.
- the result was that selective Indium plating was achieved on the Cu ring 16 and not on the surrounding surface of the metal layer 12 .
- the Indium deposit 18 was smooth, and the deposition rate was 0.8 ⁇ m/min, i.e., a 4 ⁇ m thickness Indium deposit was achieved in 5 min.
- the result was that no selective Indium plating was achieved. Instead it was observed that the Indium plated on both the surface of the Cu ring 16 and on the surface of the Ti layer 12 .
- the Indium deposit 18 was found to be rough and not smooth, and the deposition rate was very low, less than 0.1 ⁇ m/min.
- the selective Indium plating on the Cu ring 16 over the Ti layer 12 was found to occur in a range from about 1.0V to about 2.0V, and the deposited Indium layer (solder plating layer 18 ) was observed to be visually smooth.
- a more optimum voltage potential range to achieve the smooth selective Indium plating on the Cu ring 16 was found to be in a range of about 1.875V to about 2.0V.
- at voltage potentials greater than about 2.0 V the Indium was found to (slowly) plate on both the Cu ring 16 and on the Ti layer 12 , and the deposited Indium layer was observed to be visually rough and not smooth.
- the embodiments of this invention provide a method and structure for selectively plating a solder material onto a metal structure disposed over a metal layer on a surface of a substrate using a voltage controlled three electrode plating cell.
- a metal feature shown in the drawings i.e., one Cu ring 16
- the recess or some other substrate structure it need not be enclosed within and surrounded by the metal feature 16 as shown in FIG. 1 .
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Abstract
Description
- The embodiments of this invention relate generally to soldering operations such as those used to create a seal and, more specifically, relate to soldering operations performed over a surface of a substrate containing apertures or voids (recessed structures) in the surface, or raised structures on the surface.
- A seal made with low melting temperature solder can be beneficial for certain devices such as devices formed on or in a surface of a semiconductor wafer. However, solder alloys are typically not compatible with some typically used semiconductor wafer processing techniques such as plasma enhanced chemical vapor deposition (PECVD) and deep reactive ion etch (RIE) processes. In general it can be difficult to deposit and pattern photoresist on a substrate surface, so as to selectively apply a desired solder, after complex structures are fabricated on or in the substrate surface such as deep vias (recessed structures) and/or raised structures having a large topography.
- In a first aspect thereof the embodiments of this invention provide a method that comprises providing a structure comprised of a substrate having a metal layer disposed on a surface and a metal feature disposed on the metal layer; immersing the structure in a plating bath contained in an electroplating cell, the plating bath comprising a selected solder material; applying a voltage potential to the structure, where the structure functions as a working electrode in combination with a reference electrode and a counter electrode that are also immersed in the plating bath; and maintaining the voltage potential at a predetermined value to deposit the selected solder material selectively only on the metal feature and not on the metal layer.
- In another aspect thereof the embodiments of this invention provide an apparatus that comprises a tank containing a plating bath of an electroplating cell, the plating bath comprising a selected solder material; a working electrode immersed in the plating bath, the working electrode comprised of a structure that comprises a semiconductor substrate having a metal layer disposed on a surface and a metal feature disposed on the metal layer; a reference electrode and a counter electrode immersed in the plating bath; and a power supply connected with a potentiostat configured to maintain a voltage potential of the working electrode at a predetermined constant value with respect to the reference electrode to deposit the selected solder material selectively only on the metal feature and not on the metal layer.
-
FIGS. 1A, 1B and 1C , collectively referred to asFIG. 1 , illustrate enlarged views of a structure wherein the various layer thicknesses and other dimensions are not necessarily drawn to scale. More specifically,FIG. 1A is a top view of the structure,FIG. 1B is a cross-sectional view taken along the section line labeled 1B-1B inFIG. 1A , andFIG. 1C is a further enlarged view of a portion of the structure shown inFIG. 1B . -
FIG. 2 shows one example of a conventional electroplating cell. -
FIG. 3 depicts a non-limiting example of a three electrode electroplating cell that can be used to selectively plate solder on a patterned substrate in accordance with embodiments of this invention. -
FIG. 4 is a graph depicting amperometry plots of Indium plating on Cu/Ti using the electroplating cell ofFIG. 3 . - The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. All of the embodiments described in this Detailed Description are exemplary embodiments provided to enable persons skilled in the art to make or use the invention and not to limit the scope of the invention which is defined by the claims.
- The embodiments of this invention will be described below primarily in the context of a substrate that contains at least one recessed feature such as a void or an opening or a trench in a surface of the substrate. However, the embodiments of this invention apply as well to a substrate having a raised feature disposed on the surface. Furthermore, in some use-cases of interest a given substrate could include at least one recessed feature and at least one raised feature on the surface.
- The embodiments of this invention provide a method to selectively deposit solder plating onto a predefined plating area without requiring the use of a layer of photoresist during the solder plating operation. The use of the embodiments of this invention can be especially beneficial when there are pre-existing structures and/or pre-existing apertures or voids (e.g., deep trenches) on and in the surface of a semiconductor wafer, where the presence of such structures and/or voids would interfere with an ability to deposit and pattern photoresist to define regions where a selected solder material would be deposited.
- Reference can be made to
FIGS. 1A, 1B and 1C , collectively referred to asFIG. 1 , for showing enlarged views of an exemplary structure of interest to the embodiments of this invention.FIG. 1A is a top view of the structure,FIG. 1B is a cross-sectional view taken along the section line labeled 1B-1B inFIG. 1A , andFIG. 1C is a further enlarged view of a portion of the structure shown inFIG. 1B . The structure is comprised of asubstrate 10, e.g., a Silicon (Si) substrate, having ametal layer 12, e.g., a Titanium (Ti) layer, a Tantalum (Ta) layer, or a Titanium Tungsten alloy (TiW) layer, disposed on a top surface thereof. A metal structure also referred to herein as a metal feature, such as aring 16, e.g., a Copper (Cu) ring, is disposed on theTi layer 12. Enclosed within an area defined by thering 16 is an aperture orrecess 14 formed through theTi layer 12 and partially into theSi substrate 10. As non-limiting dimensional examples therecess 14 could have a diameter in a range of about 200 μm to about 500 μm and a depth of about 100 μm (or deeper), theTi layer 12 could have a thickness in a range of about 30 nm to about 60 nm, and theCu ring 16 could have a height and a width that is less than about 10 μ, for example in a range of about 1 μm to about 2 μm. The spacing (Sp) between an inner edge of theCu ring 16 and the outer edge of therecess 14 could be, for example, about 10 μm or less. - The
Cu feature 16 could have a shape other than circular, such as an ovoid or a square or a rectangular shape, or a hexagonal shape, or any desired regular or irregular shape. The circular shape is shown simply for convenience. Likewise therecess 14 could have other than the circular top opening shape as shown, and in some embodiments therecess 14 could have other than the vertical sidewalls that are illustrated. -
FIG. 1C shows a portion of the structure, i.e., a portion of theSi substrate 10,Ti layer 12 and metal (Cu)ring 16 on the left side of the view ofFIG. 1B , after performing a plating operation to selectively form asolder plating layer 18 on the surface of theCu ring 16 and not on the surface of the surroundingTi layer 12. Thesolder plating layer 18 can then be used to solder bond a cover (e.g., a solder, gold, or other type of solder wettable metal-containing cover) over therecess 14 so as to seal (e.g., hermetically seal) therecess 14 from the ambient. In an exemplary end-use of the structure therecess 14 could contain any desired type of device or devices, such as one or more sensors, actuators, energy storage devices and/or micro-electro-mechanical systems (MEMS). The selected device or devices disposed within therecess 14 can be electrically contacted via theSi substrate 10. - In conventional practice the solder plating operation may have involved depositing a dielectric layer (e.g. a layer of photoresist) over the structure followed by a photolithographic patterning operation to define and etch a circular trench in the dielectric layer so as to expose the top surface of the
Cu ring 16. Next the desired solder plating material could be blanket deposited over the patterned photoresist layer so as to also cover the top surface of theCu ring 16, followed by resist liftoff and cleaning. As can be appreciated this approach would involve a time-consuming multi-step deposition and liftoff process that would be complicated by the presence of therecess 14 in close proximity to theCu ring 16. As was noted above the spacing (Sp) between thering 16 and the edge of therecess 14 may be only about 10 μm, making it difficult to pattern the photoresist layer so close to therecess 14. - In accordance with aspects of this invention the solder plating operation is performed without requiring the deposition and patterning of a photoresist layer. Instead the solder plating operation is performed using a multi-electrode electroplating cell with a selected solder or solder alloy and plating bath.
- As a point of reference
FIG. 2 shows one example of a conventionalelectroplating cell 20. In this example, thecell 20 includes a tank 22 that contains atin plating bath 24. Immersed in thebath 24 is acathode 26, i.e., a substrate to be plated, and ananode 28, e.g., tin metal. Thecathode 26 and theanode 28 are connected to apower supply 30. In an example theanode 28 is the metal to be plated on the cathode 26 (e.g., Tin) or an insoluble anode (e.g., platinized Titanium or Iridium oxide coated Titanium). On thecathode 26 reduction takes place: -
Mn++ne−→M -
2H++2e−→H2. - On the
anode 28 oxidation takes place: -
M→Mn++ne− -
2H2O→4H++O2+4e−. -
FIG. 3 shows a more preferred example of an electroplating cell that can be used in accordance with embodiments of this invention to selectively deposit the solder plating layer 18 (e.g., a layer of Indium) only on theCu ring 16 as inFIG. 1 , and not on theTi layer 12. More specifically,FIG. 3 depicts a non-limiting example of a threeelectrode electroplating cell 40 that can be used to plate Indium solder on the patternedsilicon wafer 10. In the illustrated embodiment atank 42 contains anIndium plating bath 44. Immersed in thebath 44 is a workingelectrode 46, acounter electrode 48 and areference electrode 50. The three electrodes are connected to the power supply via apotentiostat 52. The potentiostat 52 functions by maintaining the potential of the workingelectrode 46 at a desired constant level with respect to thereference electrode 50 and passing the current at thecounter electrode 48. In the illustrated exemplary embodiment the workingelectrode 46 is theSi wafer 10 having theCu ring 16 that is to be plated (as inFIGS. 1A and 1B ), thereference electrode 50 can be comprised of Ag/AgCl in 3M KCl, and thecounter electrode 48 can be comprised of a Pt mesh. - On the working
electrode 46 reduction takes place as follows: -
In3−+3e−→In -
2H++2e−→H2. - On the
counter electrode 48 oxidation takes place as follows: -
2H2O→4H++O2+4e−. - In the presently preferred embodiments of this invention the solder plating takes place under constant potential control. The
reference electrode 50, via thepotentiostat 52, maintains a constant electrical potential between the workingelectrode 46 and thereference electrode 50, and current flows between thecounter electrode 48 and the workingelectrode 46. - Non-limiting examples of solder and solder alloys that can be used in accordance with embodiments of this invention include, in addition to Indium: Tin, Tin-Silver, Tin-Silver-Copper, Indium-Tin, Tin-Lead, Tin-Bismuth and Tin-Gold. When using one of the exemplary solders and solder alloys other than Indium the composition of the plating
bath 44 is adjusted accordingly. - When Indium is used as the solder plating material, non-limiting examples of the composition of the
Indium plating bath 44 that can be used in accordance with embodiments of this invention include: a source of Indium metal such as but not limited to Indium Sulfate, Indium Chloride, Indium Methanesulfonate, Indium Acetate or Indium oxide. TheIndium plating bath 44 also includes a conductivity salt or acid such as, but not limited to, Sulfuric acid, Hydrochloric acid, Methane Sulfonic acid or Sulfamic acid. TheIndium plating bath 44 also preferably includes a wetting agent or grain refiner such as, but not limited to, about 0.01% to about 2% of organic molecules such as a surfactant. - Using the
electroplating cell 40 ofFIG. 3 the following was observed for an electroplating condition of 1V vs. the Ag/AgCl reference electrode 50, 2V vs. the Ag/AgCl reference electrode 50 and 3V vs. the Ag/AgCl reference electrode 50. Reference can also be made to the amperometry plots inFIG. 4 (obtained from detection of ions in solution based on electric current or changes in electric current) of Indium plating on Cu/Ti. - For the 1V vs. the Ag/
AgCl reference electrode 50 condition the result was that selective Indium plating was achieved on theCu ring 16 and not on the surrounding surface of themetal layer 12. TheIndium deposit 18 was smooth, but the deposition rate was low, i.e., less than 0.1 μm/min. - For the 2V vs. the Ag/
AgCl reference electrode 50 condition the result was that selective Indium plating was achieved on theCu ring 16 and not on the surrounding surface of themetal layer 12. TheIndium deposit 18 was smooth, and the deposition rate was 0.8 μm/min, i.e., a 4 μm thickness Indium deposit was achieved in 5 min. - For the 3V vs. the Ag/
AgCl reference electrode 50 condition the result was that no selective Indium plating was achieved. Instead it was observed that the Indium plated on both the surface of theCu ring 16 and on the surface of theTi layer 12. TheIndium deposit 18 was found to be rough and not smooth, and the deposition rate was very low, less than 0.1 μm/min. - That is, the selective Indium plating on the
Cu ring 16 over theTi layer 12 was found to occur in a range from about 1.0V to about 2.0V, and the deposited Indium layer (solder plating layer 18) was observed to be visually smooth. A more optimum voltage potential range to achieve the smooth selective Indium plating on theCu ring 16 was found to be in a range of about 1.875V to about 2.0V. However, at voltage potentials greater than about 2.0 V the Indium was found to (slowly) plate on both theCu ring 16 and on theTi layer 12, and the deposited Indium layer was observed to be visually rough and not smooth. - The embodiments of this invention provide a method and structure for selectively plating a solder material onto a metal structure disposed over a metal layer on a surface of a substrate using a voltage controlled three electrode plating cell. Although there is one metal feature shown in the drawings, i.e., one
Cu ring 16, in practice there could be many such features present and all can be simultaneously plated with the desired solder material during immersion in thebath 44. Furthermore, for those embodiments where the recess or some other substrate structure is present it need not be enclosed within and surrounded by themetal feature 16 as shown inFIG. 1 . - The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
- As such, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. As but some examples, the use of other similar or equivalent plating materials, metal-containing substrates to be plated, plating solutions, electrode materials and voltage potentials may be used by those skilled in the art. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention.
Claims (20)
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US14/967,861 US20170167042A1 (en) | 2015-12-14 | 2015-12-14 | Selective solder plating |
US15/851,846 US10407791B2 (en) | 2015-12-14 | 2017-12-22 | Selective solder plating |
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US14/967,861 US20170167042A1 (en) | 2015-12-14 | 2015-12-14 | Selective solder plating |
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CN113285009A (en) * | 2021-05-26 | 2021-08-20 | 杭州大和热磁电子有限公司 | TEC assembled by depositing gold-tin solder and preparation method |
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