US20070247918A1 - Semiconductor Integrated Circuit - Google Patents

Semiconductor Integrated Circuit Download PDF

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Publication number
US20070247918A1
US20070247918A1 US11/573,004 US57300404A US2007247918A1 US 20070247918 A1 US20070247918 A1 US 20070247918A1 US 57300404 A US57300404 A US 57300404A US 2007247918 A1 US2007247918 A1 US 2007247918A1
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Prior art keywords
nonvolatile memory
area
memory
memory area
bus
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US11/573,004
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Inventor
Yutaka Shinagawa
Takeshi Kataoka
Eiichi Ishikawa
Toshihiro Tanaka
Kazumasa Yanagisawa
Kazufumi Suzukawa
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Renesas Technology Corp
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Renesas Technology Corp
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Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SUZUKAWA, KAZUFUMI, TANAKA, TOSHIHIRO, YANAGISAWA, KAZUMASA, ISHIKAWA, EIICHI, KATAOKA, TAKESHI, SHINAGAWA, YUTAKA
Publication of US20070247918A1 publication Critical patent/US20070247918A1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Definitions

  • the present invention relates to a semiconductor integrated circuit having a rewritable non-volatile memory area that memorizes information depending on differences of threshold voltages, and particularly to a technology that pays attention to relationship between the guaranteed number of times when memory information is rewritten and a read speed of the memory information such as a technology that is effectively applicable to a microcomputer where a rewritable nonvolatile memory is mounted on a chip together with a central processing unit.
  • patent document 1 there is disclosed a technology where, when data such as a user program and the like are written in a user memory area of a flash memory, a flash firmware and a parameter of a default and flash identification information are stored in advance in a mask memory area of a mask ROM, version information or lot information is stored in a non-volatile memory and a CPU selects and carries out an optimum flash firmware and a parameter based on the version information, a rewrite process to the flash memory can be carried out under the optimum condition.
  • patent document 2 there is disclosed a technology that has an EEPROM for data and an EEPROM for program, stores a locking code in a designated area, and, by making use of the locking code, inhibits price data or programs stored in a rewritable memory such as the EEPROM for data and the EEPROM for program from being altered.
  • Patent Document 1 JP-A-2001-306543
  • Patent Document 2 JP-A-2002-245023
  • the present inventors studied, in a rewritable non-volatile memory typical in a flash memory, the relationship between the guaranteed numbers of times when memory information is rewritten and read speed of the memory information. For instance, for a flash memory on-chipped on a microcomputer and the like, normally, the read speed and the guaranteed number of times of rewrite operation are set same irrespective of memory areas. The inventors paid attention to inconveniences caused by this.
  • a memory current has to be increased, and, for this, a threshold voltage to a read determination level of a memory cell has to be largely lowered.
  • Vth window a threshold voltage difference between a threshold voltage in a write state and a threshold voltage in an erase state.
  • Vth window when the threshold voltage difference (Vth window ) is lowered to alleviate the rewrite stress, a threshold voltage cannot be so much lowered to a read determination level of a memory cell. That is, since a deep erase operation cannot be applied, a memory current cannot be set larger. When the memory current is small, a high-speed read operation such as 100 MHz becomes difficult. In a flash memory incorporated in a microcomputer, in an application that stores a program, a read speed same as an executing speed of the program is required; accordingly, the high-speed read is prioritized and the number of times of rewriting memory information cannot be guaranteed so much.
  • Such an on-chip flash memory cannot be applied to a data application where the number of times of rewrite operation such as around 100,000 times is necessary; accordingly, an externally-mounted EEPROM or an externally-mounted flash memory of a microcomputer has to be used to overcome this problem.
  • a nonvolatile memory or a nonvolatile memory area is divided depending on applications.
  • an attention is not paid to dividing a nonvolatile memory area.
  • the inventors found necessity of satisfying, in one semiconductor integrated circuit, to a nonvolatile memory, both of expediting read speeds corresponding to applications and guaranteeing many of the number of times of rewrite operation.
  • An object of the invention is to provide a semiconductor integrated circuit that can satisfy, to a nonvolatile memory, both of expediting read speeds corresponding to applications and guaranteeing many of the number of times of rewrite operation.
  • a semiconductor integrated circuit includes a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit.
  • the nonvolatile memory area has a first nonvolatile memory area (PGM) and a second nonvolatile memory area (DAT), which memorize information depending on the difference of threshold voltages.
  • the first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area.
  • the maximum variation width of a threshold voltage for memorizing information means the maximum difference between an initializing level of a threshold voltage (a threshold voltage level due to an erase operation) corresponding to a logical value of one data of memory information and a threshold voltage level (a threshold voltage level due to a write operation) corresponding to a logical value of other data.
  • the “maximum” means to consider not only a case where memory information to one memory cell is 1 bit but also a case where the memory information is two or more bits.
  • a distribution of initializing levels of the threshold voltage has only to be made lower than that of the second nonvolatile memory area.
  • a distribution of threshold voltage levels such as the threshold voltage levels due to the write operation has only to be made higher than that of the second nonvolatile memory area.
  • a read determination level such as a selection level of a read word line may be the same in both of the first nonvolatile memory area and second nonvolatile memory area.
  • the read determination level has to be higher in the first nonvolatile memory area than that of the second nonvolatile memory area.
  • the first nonvolatile memory area can be made larger in a read current of a memory cell.
  • the first nonvolatile memory area can be expedited in the read speed of memory information more than the second nonvolatile memory area.
  • a first nonvolatile memory ( 11 , 11 A) provided with the first nonvolatile memory area and a second nonvolatile memory ( 12 , 12 A) provided with the second nonvolatile memory area may be separately disposed.
  • one nonvolatile memory ( 11 B) provided with both of the first nonvolatile memory area and second nonvolatile memory area may be disposed.
  • the first nonvolatile memory area is used to store programs and the second nonvolatile memory area is used to store data.
  • a read speed same as an executing speed of the program is necessary; accordingly, a high-speed read operation is prioritized.
  • a program is not so frequently rewritten in comparison with data; accordingly, there is no problem even when the guaranteed number of times of rewrite operation may be small.
  • the data are assumed frequently rewritten; accordingly, the data area is necessarily guaranteed to be large in the number of times of rewrite operation.
  • a data area assumed here is not a volatile memory such as a work RAM of a central processing unit but an area where initializing parameters are stored. Since the data area is not a memory area where a high-speed access is necessary like the work RAM, there is no substantial disadvantage even when the read speed is slow.
  • a semiconductor integrated circuit has a two-bus configuration having a first bus and a second bus to the semiconductor integrated circuit, in a specific configuration a nonvolatile memory being connected to each of the buses. That is, a semiconductor integrated circuit includes a central processing unit ( 2 ), a volatile memory ( 3 ), a first bus ( 4 ) thereto the centralprocessing unit and the volatile memory are connected, a bus controller ( 5 ) connected to the first bus and a second bus ( 6 ) connected to the bus controller. To the first bus, a first nonvolatile memory ( 11 , 11 A) that memorizes information depending on difference of threshold voltages and can be electrically rewritten is connected.
  • a second nonvolatile memory ( 12 , 12 A) that memorizes information depending on difference of threshold voltages and can be electrically rewritten is connected.
  • the first nonvolatile memory is set larger in the maximum variation width of a threshold voltage for memorizing information than the second nonvolatile memory.
  • the first nonvolatile memory can be prioritized in expediting a read speed of memory information and the second nonvolatile memory can be prioritized in guaranteeing the number of times of rewrite operation more.
  • the maximum variation width of the threshold voltage can be made larger.
  • the first nonvolatile memory is used to store a program that the central processing unit executes and the second nonvolatile memory is used to store data that are used when the central processing unit executes a program.
  • the first nonvolatile memory includes a first access port ( 50 ) that is used in a read access operation to the first bus and a second access port ( 51 ) that is used in an access operation for rewriting memory information from the second bus, the central processing unit applying access control for rewriting memory information to a first memory.
  • the access port is divided in two parts, one being used for reading memory information and the other one being used for rewriting.
  • the read port can be readily optimized for expediting a read operation. For instance, in the read port, an input buffer that receives rewrite data is unnecessary. The input buffer accompanies input capacitance that becomes a load to a data output signal line.
  • an ECC circuit ( 13 ) that can detect and correct an error to data read from the first access port is disposed, there is no need of considering a verify operation in a rewrite operation. In the verify operation, from the nature thereof, the error correction can be inconveniently applied to read data.
  • a signal path that detours the ECC circuit becomes necessary, such an additional path forming an undesirable load to the read operation of the memory information.
  • an address space to the first nonvolatile memory seen from the first access port is desirably differentiated from an address space to the first nonvolatile memory seen from the second access port.
  • a rewrite control operation of memory information to the nonvolatile memory is carried out, for instance, when the central processing unit executes a rewrite control program.
  • the rewrite control program is included in, for instance, the first nonvolatile memory.
  • the central processing unit executes a rewrite control program internally transferred from the first nonvolatile memory to the volatile memory.
  • An instruction of a rewrite operation of memory information is given through a program that the central processing unit executes.
  • a write unit such as an external EPROM writer gives a rewrite command to instruct.
  • the central processing unit when a rewrite command is externally inputted, deciphers this to execute, according to a deciphered result, a rewrite control program that the first nonvolatile memory has, and thereby the memory information that the first nonvolatile memory holds can be subjected to a rewrite control operation.
  • a nonvolatile memory cell that the first nonvolatile memory has includes a memory transistor of which a threshold voltage is differentiated depending on a charge retention state of a charge storage area and a select transistor that can selectively connect the memory transistor to a bit line.
  • a gate insulating film of the select transistor is formed thinner than that of the memory transistor.
  • a semiconductor integrated circuit has, to the semiconductor integrated circuit, a two-bus configuration having a first bus and a second bus, a specific configuration where a first nonvolatile memory area (PGM) and a second nonvolatile memory area (DAT) are assigned to a nonvolatile memory ( 11 B) connected to the first bus being clearly specified.
  • a semiconductor integrated circuit includes a central processing unit, a volatile memory, a first bus to which the central processing unit and the volatile memory are connected, a bus controller connected to the first bus and a second bus connected to the bus controller, a nonvolatile memory being connected to the first bus.
  • the nonvolatile memory has a first nonvolatile memory area and a second nonvolatile memory area that stores information depending on the difference of the threshold voltage, the first nonvolatile memory area being set larger in the maximum variation width of the threshold voltage for memorizing information in comparison with the second nonvolatile memory area.
  • the first nonvolatile memory area can be prioritized in expediting a read speed of memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation more.
  • the maximum variation width of the threshold voltage can be made larger.
  • a read determination level that is given to the nonvolatile memory cell when, in the first nonvolatile memory area, memory information corresponding to a threshold voltage is read from a nonvolatile memory cell is same as the read determination level given to the nonvolatile memory cell when, in the second nonvolatile memory area, memory information corresponding to a threshold voltage is read from the nonvolatile memory cell.
  • the first nonvolatile memory area is used to store a program that the central processing unit executes and the second nonvolatile memory area is used to store data that are used when the central processing unit executes a program.
  • a hierarchal bit line structure made of a plurality of segmented areas ( 61 ), a plurality of first bit lines (LBL) intrinsic to the respective segmented areas, a second bit line (GBLr) common to the plurality of segmented regions, a select circuit ( 62 ) that selects the first bit line from the segmented area and a sense amplifier disposed between an output of the select circuit and the second bit line is adopted, a load of each of the first bit lines being made smaller in the second nonvolatile memory area than in the first nonvolatile memory area.
  • the central processing unit in a read access control to the nonvolatile memory, can control so that the number of access cycles to the second nonvolatile memory area may be larger than the number of access cycles to the first nonvolatile memory area to cope with the difference of the read speeds.
  • the nonvolatile memory includes a first access port that is used in a read access operation to the first bus and a second access port that is used in an access operation for rewriting memory information from the second bus, the central processing unit controlling an access operation for rewriting memory information to the nonvolatile memory.
  • the access port is divided in two parts, one being used for reading memory information and the other one being used for rewriting.
  • the read port can be readily optimized for expediting a read operation. For instance, in the read port, an input buffer that receives rewrite data is unnecessary. The input buffer accompanies input capacitance that becomes a load to a data output signal line.
  • an address space to the nonvolatile memory seen from the first access port is desirably differentiated from an address space to the nonvolatile memory seen from the second access port.
  • a rewrite control operation of memory information to a nonvolatile memory is carried out, for instance, when the central processing unit executes a rewrite control program.
  • the rewrite control program is included in, for instance, the first nonvolatile memory.
  • the central processing unit executes a rewrite control program internally transferred from the first nonvolatile memory to the volatile memory.
  • An instruction of a rewrite operation of memory information is given through a program that the central processing unit executes.
  • a write unit such as an external EPROM writer gives a rewrite command to instruct.
  • the central processing unit when a rewrite command is externally inputted in the external interface circuit, deciphers this to execute, according to a deciphered result, a rewrite control program that the first nonvolatile memory has, and thereby the memory information that the first nonvolatile memory holds can be subjected to a rewrite control operation.
  • a nonvolatile memory cell that the nonvolatile memory has includes a memory transistor of which threshold voltage is differentiated depending on a charge retention state of a charge storage area and a select transistor that can selectively connect the memory transistor to a bit line.
  • a gate insulating film of the select transistor is formed thinner than that of the memory transistor.
  • a semiconductor integrated circuit includes a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit, the nonvolatile memory area having a first nonvolatile memory area and a second nonvolatile memory area that stores information depending on the difference in a current amount that flows a memory cell.
  • Each of a memory cell in the first nonvolatile memory area and a memory cell in the second nonvolatile memory area has a first state (for instance, write state) and a second state (for instance, erase state).
  • a first state of the memory cell in the first memory area and a first state of the memory cell in the second memory area are controlled so that current amounts that flow the memory cells may be contained in a first range, in a second state of the memory cell in the first memory area, a current amount that flows the memory cell is controlled so as to be contained in a second range, and in a second state of the memory cell in the second memory area, a current amount that flows the memory cell is controlled so as to be contained in a third range different from the second range.
  • the second range and the third range partially overlap.
  • a further specific mode of the invention has a detection circuit that detects in which range of the first through third ranges a current that flows the memory cell is contained.
  • the detection circuit is for instance a sense amplifier, and, depending on a current amount on a sense side, in which range of the first through third ranges the current amount is contained can be detected.
  • FIG. 1 is a block diagram showing a first example of a data processor.
  • FIG. 2 is a characteristic diagram exemplifying threshold voltage distributions of a nonvolatile memory cell in a data area and a program area.
  • FIG. 3 is an explanatory diagram exemplifying relationship between rewrite time and the number of rewrite cycles.
  • FIG. 4 is a flow chart showing an erase procedure to a flash memory when a nonvolatile memory area is segmented into a program area PGM and a data area DA.
  • FIG. 5 is a flow chart showing a write procedure to a flash memory.
  • FIG. 6 is an explanatory diagram showing a specification of a flash memory when a nonvolatile memory area is segmented into a program area PGM and a data area DAT.
  • FIG. 7 is a timing chart exemplifying the access timing in a hierarchal bus configuration.
  • FIG. 8 is a sectional view exemplifying a device structure of a nonvolatile memory cell of a flash memory.
  • FIG. 9 is an explanatory diagram typically showing connection states of a nonvolatile memory cell of FIG. 8 in a hierarchal bit line structure and features thereof.
  • FIG. 10 is a block diagram showing a second example of a data processor.
  • FIG. 11 is a circuit diagram exemplifying a configuration of a flash memory.
  • FIG. 12 is a block diagram showing a third example of a data processor.
  • FIG. 13 is a block diagram showing a fourth example of a data processor.
  • FIG. 14 is a timing chart showing an example where, when a program area (PGM) and a data area (DAT) are made same in a memory array configuration, the program area (PGM) and the data area (DAT) are accessed at different bus cycles.
  • PGM program area
  • DAT data area
  • FIG. 15 is a circuit diagram exemplifying a memory array configuration where read speeds of the data area (DAT) and the program area (PGM) are made same.
  • FIG. 16 is a circuit diagram showing a mode where two flash memories are separately connected to a CPU bus and a peripheral bus.
  • CPU central processing unit
  • 11 , 11 A flash memory with a program area
  • VthP read determination level common to a data area and a program area
  • VthEP erase determination level of a program area
  • VthEd erase determination level of a data area
  • 61 A memory array for a program area
  • 61 B memory array for a data area
  • GBLr read global bit line
  • GBLw write global bit line
  • FIG. 1 shows a first example of a data processor.
  • the data processor (MCU) 1 is formed on one semiconductor substrate such as a silicon single crystal by use of a CMOS integrated circuit producing technology.
  • the data processor 1 includes: a central processing unit (CPU) 2 ; a random access memory (RAM) 3 as a volatile memory, which is used as a work area of the CPU 2 ; a CPU bus (BUSc) 4 as a first bus, to which the CPU 2 and the RAM 3 are connected; a bus controller (BSC) 5 connected to the CPU bus 4 ; and a peripheral bus (BUSp) 6 as a second bus, which is connected to the bus controller 5 , and has a hierarchal bus configuration.
  • CPU central processing unit
  • RAM random access memory
  • BUSc CPU bus
  • BSC bus controller
  • BUSp peripheral bus
  • peripheral circuits such as a timer (TMR) 7 , an analog/digital converter (A/D) 8 , an input/output port (I/O prt) 9 and a serial interface controller (SCI) 10 are connected.
  • TMR timer
  • A/D analog/digital converter
  • I/O prt input/output port
  • SCI serial interface controller
  • a flash memory 11 is connected to the CPU bus 4 .
  • a flash memory 11 As an electrically rewritable second nonvolatile memory that stores information depending on the difference of threshold voltage, a flash memory 12 is connected.
  • the flash memory 11 has, as a first nonvolatile memory area, a storage area (program area PGM) of a program that the CPU 2 executes.
  • the flash memory 12 has, as a second nonvolatile memory area, a storage area (data area DAT) of data that are used when the CPU 2 executes a program.
  • the CPU bus 4 In the hierarchal bus structure, the CPU bus 4 , from the nature in that circuit modules such as the CPU 2 and the RAM 3 that determine the data processing capability are connected, is formed into a high-speed bus in which wiring load is limited, and thereby a high-speed data transfer is intended. Many peripheral circuit modules such as the timer 7 and the A/D 8 that are connected to the peripheral bus 6 are operated after parameters are set from the CPU 2 and an external memory such as an EPROM that temporarily stores data is connected through the I/O port 9 connected to the peripheral bus 6 . Accordingly, the peripheral bus 6 may be a relatively low-speed bus. In FIG. 7 , access timings in the hierarchal bus configuration are exemplified.
  • a synchronous clock (peripheral clock) of the peripheral circuit module is stepped up to one fourth to an operation reference clock (CPU clock) of the CPU 2 and thereby the peripheral modules connected to the peripheral bus are accessed at a lower speed than the RAM 3 or the like connected to the CPU 2 .
  • Read data are determined on a data bus at a cycle next to an address determination cycle on an address bus.
  • the flash memory 11 having the program area PGM is connected to the CPU bus 4 and necessarily capable of reading at an execution speed of the CPU 2 .
  • the flash memory 12 having the data area DAT is connected to the peripheral bus 6 and may be able to read at a relatively low speed same as other peripheral modules.
  • the data area DAT is assumed being rewritten more frequently than the program area PGM.
  • the data area DAT that is frequently rewritten is used to store data such as parameter information that has no direct relation with the program execution; accordingly, necessity of reading memory information at a high-speed therefrom is low.
  • an on-chip nonvolatile memory area is segmented into a program area PGM that can be read at a high-speed and a data area DAT that allows rewriting many times.
  • threshold voltage distributions of nonvolatile memory cells in a data area and a program area are exemplified.
  • the program area PGM in order to secure a sufficient memory current necessary for a high-speed read operation, a memory threshold voltage of an erase state is set sufficiently low.
  • the determination level of an erase verify operation (erase determination level) at that time is set at VthEp.
  • the determination level in an erase verify operation (erase determination level) in the data area DAT is set at VthEd.
  • the determination level in a write verify operation is set at VthP same for both the program area PGM and the data area DAT.
  • the write determination level may be differed between the program area PGM and the data area DAT.
  • the difference is imparted to the threshold voltages of the nonvolatile memory cells.
  • Wp denotes the maximum variation width of the program area
  • Wd is the maximum variation width of the data area.
  • the maximum variation width can be grasped as the difference between the erase determination level and the write determination level. In essence, VthP ⁇ VthEp >VthP ⁇ VthEd is satisfied.
  • Each of the threshold voltage distributions exemplified in FIG. 2 is considered a normal distribution.
  • the threshold voltage distribution in an erase state of the program area and the threshold voltage distribution in an erase state of the data area are not inhibited from partially overlapping each other.
  • FIG. 3 exemplifies relationship between rewrite time and number of cycles of rewrite operation.
  • the characteristics are deteriorated. For instance, an erase time or a write time necessary for obtaining a predetermined threshold voltage increases. Since the occurrence of the deterioration depends on for instance a depth of the erase threshold voltage (difference between a threshold voltage of a write state and a threshold voltage of an erase state), when the erase operation is stopped at a shallow level to inhibit the characteristics from deteriorating, the number of times of rewrite operation can be extended. From the above, the guaranteed number of times of rewrite operation of the data area DAT becomes larger than that of the program area PGM.
  • a rewrite control of memory information to flash memories 11 and 12 is carried out when, for instance, the CPU 2 executes a rewrite control program.
  • the rewrite control program is stored in for instance the flash memory 11 .
  • the CPU 2 executes a rewrite control program internally transferred from the flash memory 11 to the RAM 3 .
  • a program that the CPU 2 executes gives an instruction of rewrite operation of memory information.
  • a rewrite command given from a rewrite device such as an external EPROM writer instructs.
  • the CPU 2 when a rewrite command is externally input, deciphers this, executes the rewrite control program in accordance with the deciphered result, and thereby memory information that the flash memories 11 and 12 have is subjected to rewrite control operation.
  • the CPU 2 executes erase and rewrite control operations to the flash memories 11 and 12 .
  • an external writer instructs erase and write operations of the flash memories 11 and 12 through the input/output port 9 .
  • the inside of the data processor 11 is initialized.
  • the CPU 2 starts executing a program in a program area designated by a vector of address No 0 or the like.
  • FIG. 4 an erase flow of a flash memory when a memory area is segmented into a program area PGM and a data area DAT is shown.
  • the CPU 2 determines an address to be erased.
  • the program area PGM and the data area DAT are different in the memory space; accordingly, depending on the address to be erased, which area thereof should be erased (or write) can be determined.
  • a block to be erased of the program area is selected (S 1 p ), and an erase voltage is applied on the selected block to be erased for a predetermined time (S 2 p ).
  • an erase verify operation is carried out to a nonvolatile memory cell that is an object to be erased to determine whether the threshold voltage thereof has become an erase determination level VthEp or less or not (S 3 p ).
  • the erase voltage is further applied (S 3 p )
  • steps S 2 p and S 3 p are repeated until the erase determination level VthEp or less is attained, and, when the erase determination level VthEp or less is attained, the erase operation is stopped.
  • a block to be erased in the data area is selected (S 1 d ) and an erase voltage is applied to the selected block to be erased for a predetermined time (S 2 d ). Subsequently, an erase verify operation is carried out to a nonvolatile memory cell to be erased to determine whether the threshold voltage has become an erase determination level VthEd or less or not (S 3 d ).
  • the erase voltage is further applied (S 2 d ), steps S 2 d and S 3 d are repeated until the erase determination level VthEd or less is attained, and, when the erase determination level VthEd or less is attained, the erase operation is stopped.
  • the erase determination levels VthEp and VthEd are varied for the respective areas, threshold voltage distributions different in the program area PGM and the data area DAT can be generated. At that time, an erase voltage applied and a pulse width that specifies an erase voltage application time are parameters affecting on the characteristics deterioration; accordingly, the optimum values of the both areas can be uniquely set to control the threshold voltage.
  • FIG. 5 shows a write flow to a flash memory.
  • a write operation is instructed to start, the CPU 2 internally transfers write data to a flash memory to be written (S 11 ) to allow selecting a word to be written in accordance with an address (S 12 ), followed by applying a write voltage to a memory cell to be written (S 13 ).
  • a write verify operation is carried out to a nonvolatile memory cell to be written to determine whether the threshold voltage has become a write determination level VthEP or more or not (S 14 ).
  • the write voltage is further applied (S 13 ), steps S 13 and S 14 are repeated until the write determination level VthP or more is attained, and, when the write determination level VthP or more is attained, the write operation is stopped.
  • a write verify determination level a write voltage and a pulse width that specifies the write voltage application time as well, optimum values may be uniquely set in the program area PGM and the data area DAT to control.
  • FIG. 6 a specification of a flash memory 11 , 12 when a memory area is segmented into a program area PGM and a data area DAT is shown.
  • an area being segmented into a program area PGM and a data area DAT, when the area is given features based on the specification, usability of users can be improved.
  • the guaranteed number of times of rewrite operation and the read speed have been already described.
  • the usability can be improved.
  • Specific numerical values of the guaranteed number of times of rewrite operation and the read speed shown in the drawing are only examples.
  • a nonvolatile memory cell 21 is formed with, in a P-type well area 22 disposed on a silicon substrate, a first MOS type first transistor 23 for storing information and a second MOS type transistor 24 (select MOS transistor) that selects the first transistor 23 .
  • the first transistor 23 includes a N-type diffusion layer (N-type impurity area) 30 that becomes a source line electrode connected to a source line, a charge storage area (for instance, silicon nitride film) 31 , insulating films (for instance, silicon oxide film) 32 and 33 disposed on front and back surfaces of the charge storage area 31 , a memory gate electrode (for instance, N-type polysilicon layer) 34 for applying a high voltage at the time of write and erase operation and an oxide film (for instance, silicon oxide film) 35 for use in protection of the memory gate electrode.
  • N-type diffusion layer for instance, silicon nitride film
  • insulating films for instance, silicon oxide film
  • an oxide film for instance, silicon oxide film
  • the second transistor 24 includes a N-type diffusion layer (N-type impurity area) 36 that becomes a bit line electrode connected to a bit line, a gate insulating film (for instance, silicon oxide film) 37 , a control gate electrode (for instance, N-type polysilicon layer) 38 and an insulating film (for instance, silicon oxide film) 29 that isolates the control gate electrode 38 and the memory gate electrode 34 .
  • N-type diffusion layer N-type impurity area
  • a film thickness of the gate insulating film 37 of the control gate electrode 38 is expressed with tc and a film thickness of an insulating film between the control gate electrode 38 and the charge storage area 31 is expressed with ti, a relationship of tc ⁇ tm ⁇ ti is realized. From the dimension differences between the gate insulating film 37 and the memory gate insulating films 31 , 32 and 33 , a gate withstand voltage of the second transistor 24 is set lower than the gate withstand voltage of the first transistor 23 .
  • drain written in a portion of a diffusion layer 36 means that the diffusion layer 36 functions as a drain electrode of the transistor in data read operation
  • source written in a portion of a diffusion layer 30 means that the diffusion layer 30 functions as a source electrode of the transistor in a data read operation.
  • the functions of the drain and source electrodes may be interchanged irrespective of the indication of drain and source.
  • a source side of a channel of a memory transistor to which a high voltage is supplied from a drain side and a drain side of a channel of a select transistor do not enter a conductive state of electrically low resistance. This is because the source side and the drain side do not have a common low resistance area such as a diffusion area. As a result, at this time, a high voltage on a memory transistor side is not applied to the select transistor. Accordingly, even when a gate insulating film of the select transistor is formed thinner than a gate insulating film of the memory transistor, at the time of a rewrite operation, a gate oxide film of the select transistor is not destroyed. This guarantees that a thin gate oxide film makes the conductance of the select transistor larger to expedite the read speed.
  • FIG. 9 features to the nonvolatile memory cell of FIG. 8 are represented.
  • a connection state of the nonvolatile memory cell 21 in the hierarchal bit line structure is exemplified.
  • the diffusion layer 36 is connected to a sub-bit line BL (hereinafter, simply referred to as bit line BL), the diffusion layer 30 is connected to a source line SL, the memory gate electrode 34 is connected to a memory gate control line ML and the control gate electrode 38 is connected to a control gate control line CL.
  • the sub-bit line BL is connected through an N-channel type switch MOS transistor (ZMOS) 39 to a main-bit line (also described as global bit line) GL.
  • ZMOS N-channel type switch MOS transistor
  • a plurality of nonvolatile memory cells 21 is connected to the sub-bit line BL and a plurality of the bit lines BL are connected to one main-bit line GL through the ZMOSs 39 respectively.
  • a first driver (word driver) 41 for driving the control gate control line CL, a second driver 42 for driving the memory gate control line ML, a third driver (Z driver) 43 for switch-driving the ZMOS 39 , and a fourth driver 44 for driving the source line SL are representatively shown.
  • Each of the drivers 42 and 44 is constituted of a high voltage MOS driver using a MOS transistor whose gate withstand voltage is high.
  • Each of the drivers 41 and 43 is constituted of a driver using a MOS transistor whose gate withstand voltage is relatively low.
  • a relatively high threshold voltage is set in the first transistor 23 of the nonvolatile memory cell 1 , for instance, with a memory gate voltage Vmg and a source line voltage Vs set to high voltage, a control gate voltage Vcg set to 1.8V, a write select bit line set to 0V (ground potential of the circuit), and a write non-select bit line set to 1.8V
  • the second transistor 24 of the write select bit line is turned on to pass current from the diffusion layer 30 to the diffusion layer 36 . Hot electrons generated in the vicinity of the charge storage area 31 on the control gate electrode 38 side by the current may be held in the charge storage area 31 .
  • the write select bit line potential is not limited to the ground potential. For example, it is sufficient to apply substantially 0.5V to pass a channel current.
  • the diffusion layer 30 functions as a drain and the diffusion layer 36 functions as a source.
  • the writing form is injection of hot electrons to the source side.
  • an erase operation where a relatively low threshold voltage is set to the first transistor 23 , for example, a high voltage is applied to the memory gate voltage Vmg, the second transistor 24 is turned on to set the diffusion layers 36 and 30 to the ground potential of the circuit, and the electrons held in the charge storage area 31 are discharged to the memory gate electrode 34 . At that time, with the second transistor 24 set in an off state or with the second transistor 24 set in an off-state and the source line set in a floating state as well, the erase operation can be performed.
  • the operations can be realized without applying a high voltage to the control gate control line CL and the bit line BL. It assures that the gate withstand voltage of the second transistor 24 may be relatively low. It neither requires for the ZMOS 39 to have a high voltage.
  • the first transistor 24 in an erase state of which the threshold voltage is set low is one of a depletion type
  • the first transistor 24 in a write state of which the threshold voltage is set high is one of an enhancement type
  • the second transistor 24 Since the second transistor 24 has a gate oxide film thickness thinner than that of the first transistor 23 and a smaller gate withstand voltage, the conductance of the whole nonvolatile memory cell 21 can be made relatively larger as compared with that in the case where both of a MOS transistor for storage and a MOS transistor for selection are formed with high voltage. Thus, the data read speed can be expedited.
  • FIG. 10 a second example of a data processor is shown.
  • a data processor 1 A of FIG. 10 is different from that shown in FIG. 1 in that a flash memory 11 A that is used in a program area is rewritten from a peripheral bus.
  • the flash memory 11 A separately includes a first access port (PRTr) 50 that is used in a read access to the CPU bus 4 and a second access port (PRTep) 51 that is used in an access for rewriting memory information from the peripheral bus 6 , the CPU 2 carrying out an access control operation for rewriting memory information to the flash memory 11 A through a bus controller 5 .
  • the CPU 2 executes a rewrite control program to apply a rewrite control operation to the flash memory 11 A.
  • the flash memory 11 A for instance includes the rewrite control program.
  • the CPU 2 executes a rewrite control program internally transferred from the flash memory 11 A to a RAM 3 .
  • a program that the CPU 2 executes instructs a rewrite operation of the memory information.
  • a rewrite command given through an I/O port 9 from a rewrite device such as an external EPROM writer instructs.
  • the CPU 2 when a rewrite command is externally input, deciphers this.
  • a rewrite control program that the flash memory 11 A has is executed, and thereby memory information that the flash memory 11 A has is subjected to a rewrite control operation.
  • the rewrite command includes a rewrite control code, an address to be rewritten, rewrite data and the like.
  • the flash memory 11 A has a memory mat 60 where a number of electrically erasable and writable nonvolatile memory cells 52 are disposed in matrix.
  • the nonvolatile memory cell 52 is formed into a stacked gate structure that includes a source (source line connection), a drain (bit line connection), a channel and a floating gate and a control gate (word line connection) that are stacked on the channel insulated from each other.
  • the nonvolatile memory cell 52 may be formed into a split-gate structure that includes the source (connected to a source line) described in FIGS. 8 and 9 , a drain (connected to a bit line), a channel and a select gate (connected to a word line) and a memory gate (connected to a memory gate control line) that are formed adjacently and insulated from each other on the channel.
  • the memory mat 60 has a plurality of memory arrays 61 .
  • a plurality of local bit lines LBL is disposed, the local bit line LBL being selected by a column select circuit (CSEL) 62 and a sense amplifier array (SAA) 63 receiving an output of the column select circuit 62 .
  • CSEL column select circuit
  • SAA sense amplifier array
  • An output of the sense amplifier array 63 is connected to a read global bit line GBLr common to the respective memory arrays.
  • the bit lines are formed into a hierarchal bit line structure and the sense amplifier amplifies according to a hierarchal sense method.
  • a pair of memory arrays 61 up and down in the drawing has a sense amplifier array 63 in common.
  • a write system has a write global bit line GBLw isolated from a read system, the write global bit line GBLw is communized to the respective memory arrays 61 .
  • a local bit line LBL corresponding to a write global bit line GBLw can be selectively connected or isolated through a detaching switch DSW.
  • the detaching switch DSW detaches the write global bit line GBLw from the local bit line LBL at least in a memory array to be read.
  • the read global bit line GBLr is set to 32 lines and the read global bit line GBLw is set to 1024 lines.
  • the write global bit line GBLw is utilized as well in a verify read operation.
  • a word line WL of a nonvolatile memory cell 52 is selectively driven in accordance with a decoded result of an address signal due to a row decoder (RDEC) 65 .
  • a drive level is determined depending on an erase, write or read operation to a flash memory.
  • a column select circuit 62 selects a local bit line LBL in accordance with a decoded result of an address signal by the column decoder (CDEC) 66 .
  • the detach switch DSW and the sense amplifier SA are controlled by the row decoder 65 in response to a read, erase or write operation to a memory array.
  • An address signal is supplied from an address bus (ABUS) 54 . Only one kind of address bus 54 is shown in the drawing.
  • an address space to the flash memory 11 A seen from the first access port 50 and an address space to the flash memory 11 A seen from the second access port 51 are differentiated; accordingly, in actuality, an address bus on a CPU 4 side and an address bus on a peripheral bus 6 side are separately connected.
  • the read global bit line GBLr is connected through a high-speed read sense amplifier circuit (RAMP) 67 to a data bus of the CPU 4 .
  • the write global bit line GBLw is connected to a write circuit (PE) 68 and a verify read circuit (VRF) 69 .
  • the write circuit 68 and verify read circuit 69 are connected through a column select circuit 70 to a data bus of the peripheral bus 6 .
  • the column select circuit 70 has a data latch of 1024 bits and, in a write operation, selectively connects the data latch of 1024 bits at a unit of 32 bits to a data bus of the peripheral bus 6 . The selection is carried out due to a select signal from a column decoder (CDEC) 71 .
  • CDEC column decoder
  • the column select circuit 70 sequentially and at a unit of 32 bits loads write control data that are sequentially outputted from the CPU 2 for instance at a unit of 32 bits and supplied through a bus controller to the peripheral bus 6 in a data latch.
  • the write circuit 68 applies a write voltage to a corresponding write bit line GBLw in accordance with a logical value of each of write control data of 1024 bits latched in the data latch through the column select circuit 70 .
  • a verify read operation 1024 bits of data read in the respective write bit lines GBLw are latched in parallel in the data latch, and the latched data are sequentially selected at a unit of 32 bits by the column select circuit 70 and outputted to the data bus of the peripheral bus 6 after amplification at the verify read circuit 69 .
  • the data read in the peripheral bus 6 in the verify read operation are verify determined at the CPU 2 .
  • the verify determination in the write operation at a unit of bit, whether a write logical value is obtained or not is determined, and the determination result is supplied for every corresponding bit from the CPU 2 to the write circuit 68 as new write control data.
  • the verify determination in an erase operation whether all bits have become logical values in erase state or not is determined.
  • control circuit (CNT) 69 through the CPU 4 from the CPU 2 , or through the peripheral bus 6 , memory control information is set and in accordance with this a control sequence corresponding to read, erase and write operations and a switching control of an operation power supply are carried out.
  • a channel area is formed, on the channel area a floating gate electrode is formed through a gate insulating film, and thereon through an oxide film a gate control electrode is formed.
  • the floating gate electrode is constituted of a polysilicon layer.
  • the control gate electrode is constituted of a polysilicon wiring and becomes a part of a word line WL.
  • operation voltages are as follows. For instance, in the write operation, with a word line voltage set at 10V, a bit line voltage set at 5V, a source line voltage set at 0V and a well voltage set at 0V, hot carriers are injected from a drain area to a floating gate. In the erase operation, with a word line voltage set at ⁇ 10V, a well voltage set at 10V and a bit line and a source line set at high impedance, electrons are extracted from the floating gate to a well area.
  • the operation is carried out.
  • high voltages are necessarily applied to a word line and a well area.
  • a first access port (PRTr) 50 that is a read port can be readily optimized for expediting a read operation. For instance, in the read port, an input buffer that receives rewrite data becomes unnecessary. Since an input buffer accompanies input capacitance that becomes a load for a data signal line, such input capacitance is desirably as small as possible for a high-speed bus. This is because the write data are in some cases inputted from an I/O port, furthermore, a verify read operation, even when the peripheral bus 6 that is a low-speed bus is used, does not affect on the rewrite characteristics of memory information.
  • FIG. 12 shows a third example of a data processor.
  • a data processor 1 B shown in FIG. 12 is different from that of FIG. 1 in that to data read from flash memories 11 A and 12
  • a error detection and correction circuits (ECC circuit) 13 and 14 that detect and correct an error are disposed.
  • the ECC circuit 13 is disposed between a first access port (PRTr) 50 of the flash memory 11 A and the data bus of the CPU bus 4 .
  • the flash memory 12 A for storing data as well separately has a first access port (PRTr) 54 that is used in a read access operation to the peripheral bus 6 and a second access port (PRTep) 55 that is used in a rewrite access operation of memory information from the peripheral bus 6 and an ECC circuit 14 is disposed between the first access port (PRTr) 54 of the flash memory 12 A and the data bus of the peripheral bus 6 .
  • PRTr first access port
  • PRTep second access port
  • an ECC circuit 13 when an ECC circuit 13 is incorporated to apply error correction, in the DAT area, by making use of a feature of reading at a low-speed, without disposing an ECC circuit 13 as a hardware on the flash memory 12 A side, in place thereof, a correction code of the ECC and storage data are read together and the CPU 2 may execute a program for use in ECC circuit to correct errors with a software. Furthermore, when a plurality of pieces of flash memory 11 A that constitutes a program area is on-chipped, through a common ECC circuit, lead data may be outputted to the CPU bus 4 .
  • FIG. 13 a fourth example of a data processor is shown.
  • a data processor 1 C shown in the drawing is different from that shown in FIG. 2 in that in a memory array of one flash memory 11 B a data area (DAT) and a program area (PGM) are disposed.
  • a flash memory 12 or 12 A exclusive for a data area is not disposed.
  • a first access port 50 is connected to a CPU bus 4 and between the first access port 50 and a data bus of the CPU bus 4 an ECC circuit 13 is interposed.
  • DAT data area
  • PGM program area
  • FIG. 15 in the flash memory 11 B, an example of a configuration of a memory array where a read speed is set same in the data area (DAT) and the program area (PGM) is exemplified.
  • DAT data area
  • PGM program area
  • the number of bits of the memory cell connecting to a sense amplifier SA in a hierarchal sense amplifier structure, in other words, a length of a local bit line LBL is made sufficiently small compared to that of the program area (PGM).
  • a memory array 61 B of the data area (DAT) is made smaller.
  • DAT data area
  • FIG. 15 configurations of a writing system and the like are omitted from showing; however, these are same as in FIG. 11 .
  • a term “DEC” generically calls a column decoder and a row decoder
  • a term “BIF” means a bus interface
  • a term “CNT” means a control circuit.
  • a length of a local bit line LBL of a memory array 61 A of the program area (PGM) may be shortened than that of a local bit line LBL of the data area (DAT).
  • a load of the local bit line LBL of the program area (PGM) can be made smaller and thereby a read speed can be more expedited.
  • FIG. 16 a mode where two flash memories are separately connected to a CPU bus and a peripheral bus is shown.
  • a flash memory 11 connected to a CPU bus 4 a hierarchal sense amplifier structure may be adopted to expedite a read speed. Since a flash memory 12 that is connected to the peripheral bus 6 is not intended to expedite, the hierarchal sense amplifier structure is less advantageously adopted.
  • a reference sign “MAT (PGM)” shows a memory mat that is rendered a program area and a reference sign “MAT (DAT)” shows a memory mat that is rendered a data area.
  • Nonvolatile memories different in the applications such as one that realizes a high-speed read operation and one in which the number of times of rewrite operation is particularly improved can be realized on one chip without varying producing conditions.
  • a port for use in a read operation can be readily optimized for expediting a read operation. For instance, in a port 50 for use in a read operation, an input buffer that receives rewrite data is unnecessary. The input buffer accompanies input capacitance that becomes a load to a data line for use in a data input operation. Furthermore, in the case where an ECC circuit 13 capable of detecting and correcting an error to data read from the first access port 50 is disposed between the first access port 50 and the CPU bus 4 as well, there is no need of considering a verify operation in a rewrite operation.
  • the CPU 2 connected to the CPU bus 4 can conveniently control a rewrite operation of memory information from the second access port 51 through the peripheral bus 6 .
  • an erase threshold voltage distribution of memory cells of the program area is made lower than an erase threshold voltage distribution of memory cells in the data area.
  • a write threshold voltage distribution of memory cells of the program area may be made higher than a write threshold voltage distribution of memory cells in the data area.
  • read determination levels such as a read word line select level may be the same. In the case of the latter, a read determination level may be higher in the program area than the data area.
  • a bus configuration of the data processor is not restricted to a two-bus configuration.
  • a three-bus configuration or a one-bus configuration can be adopted. It goes without saying that, on the data processor, a different circuit module other than the above can be on-chipped.
  • An electrically rewritable nonvolatile memory, without restricting to the flash memory, may be an EEPROM.
  • a voltage applied to a word line is varied to set a threshold voltage of a memory cell.
  • a current amount passing a sense amplifier may be measured to determine an erase state of the memory cell.
  • a threshold voltage distribution of the memory cell is considered different from one shown in FIG. 2 .
  • a memory Vth of a horizontal axis of FIG. 2 may be interchanged with a memory current amount.
  • the present invention can be widely applied to semiconductor integrated circuits such as microcomputers where a rewritable nonvolatile memory such as a flash memory is on-chipped and system LSIs and multi-tip modules that mount such a semiconductor integrated circuit and a separate semiconductor integrated circuit on a package substrate.
  • semiconductor integrated circuits such as microcomputers where a rewritable nonvolatile memory such as a flash memory is on-chipped and system LSIs and multi-tip modules that mount such a semiconductor integrated circuit and a separate semiconductor integrated circuit on a package substrate.

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US20120179953A1 (en) 2012-07-12
US8576643B2 (en) 2013-11-05
US7821824B2 (en) 2010-10-26
US8130571B2 (en) 2012-03-06
CN1993682A (zh) 2007-07-04
WO2006025091A1 (ja) 2006-03-09
JPWO2006025091A1 (ja) 2008-05-08
JP4554616B2 (ja) 2010-09-29
US7978545B2 (en) 2011-07-12
US20100220531A1 (en) 2010-09-02
US20090052238A1 (en) 2009-02-26

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