US20070141803A1 - Methods for making substrates and substrates formed therefrom - Google Patents

Methods for making substrates and substrates formed therefrom Download PDF

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Publication number
US20070141803A1
US20070141803A1 US11/505,668 US50566806A US2007141803A1 US 20070141803 A1 US20070141803 A1 US 20070141803A1 US 50566806 A US50566806 A US 50566806A US 2007141803 A1 US2007141803 A1 US 2007141803A1
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Prior art keywords
substrate
seed layer
layer
thermal expansion
expansion coefficient
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Abandoned
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US11/505,668
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English (en)
Inventor
Alice Boussagol
Bruce Faure
Bruno Ghyselen
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Soitec SA
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Soitec SA
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Assigned to S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A. reassignment S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES S.A. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FAURE, BRUCE, GHYSELEN, BRUNO, BOUSSAGOL, ALICE
Priority to KR1020087014900A priority Critical patent/KR20080078679A/ko
Priority to PCT/EP2006/070109 priority patent/WO2007071772A1/fr
Priority to TW095148275A priority patent/TWI324357B/zh
Priority to CN2006800478498A priority patent/CN101341580B/zh
Priority to EP06841567A priority patent/EP1979933A1/fr
Publication of US20070141803A1 publication Critical patent/US20070141803A1/en
Priority to US11/840,696 priority patent/US7615468B2/en
Priority to US12/536,082 priority patent/US7839001B2/en
Priority to US12/914,194 priority patent/US7939428B2/en
Assigned to SOITEC reassignment SOITEC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer

Definitions

  • the present invention relates to methods for making substrates and substrates for use in optics, electronics or opto-electronics and, in particular, substrates which may be used for making solar cells, light-emitting diodes and lasers.
  • a thin layer taken from a donor substrate is transferred onto a receiving supporting substrate to obtain substrates including a thin useful layer.
  • Useful layer is the layer of the substrate on which electronic components such as, for example, light-emitting diodes or other components may be made.
  • the thin layer is deposited on a receiving supporting substrate by a deposition technique.
  • This deposition technique may notably consist of epitaxy or chemical vapor deposition.
  • Such removal of the receiving support results in loss of materials, thereby putting a strain on the manufacturing costs of such substrates.
  • a method for making substrates which includes a useful thin layer method in which the receiving supporting substrate is removed in order to be recycled.
  • a useful thin layer method in which the receiving supporting substrate is removed in order to be recycled.
  • This method includes a step for transferring a seed layer on a receiving support by molecular adhesion at a bonding interface, a step for epitaxy of a useful layer on the seed layer and a step for applying stresses in order to lead to removal of the assembly (i.e., removal of the seed layer and of the useful layer from the receiving support at the bonding interface).
  • Seed layer is the material layer which allows development of the epitaxied useful layer.
  • the invention relates to a method for making substrates for optics, electronics, or opto-electronics which includes providing a donor substrate and a receiving substrate, wherein the receiving substrate has a thermal expansion coefficient; operably connecting the donor substrate to the receiving substrate; forming a seed layer on the receiving substrate, wherein the seed layer has a surface and a thermal expansion coefficient; and epitaxy of a useful layer on the seed layer, wherein the useful layer has a thermal expansion coefficient.
  • the thermal expansion coefficient of the receiving substrate is equal to or greater than the thermal expansion coefficient of the useful layer
  • the thermal expansion coefficient of the seed layer is about the same as the thermal expansion coefficient of the receiving substrate so that the seed layer and the receiving support expand in substantially the same way to avoid stressing or deforming the seed layer.
  • the method for making substrates includes providing a donor substrate and a receiving support; forming a seed layer from the donor substrate; transferring the seed layer onto the receiving support; and forming a useful layer on the seed layer.
  • the thermal expansion coefficient of the receiving support is equal to or greater than the thermal expansion coefficient of the useful layer
  • the thermal expansion coefficient of the seed layer is about equal to the thermal expansion coefficient of the receiving support so that the seed layer and the receiving support expand in substantially the same way to avoid stressing or deforming the seed layer.
  • the seed layer and the receiving support may substantially expand in the same way.
  • the receiving support may expand slightly less than the seed layer so that the seed layer may be placed under slight compression avoiding any deterioration of the seed layer.
  • the seed layer may consist of a material for which the thermal expansion coefficient is equal to (1+ ⁇ ) times that of the receiving support, with ⁇ of the order of 0.2, and preferably ⁇ equals 0.1.
  • the useful layer may consist of a material for which the thermal expansion coefficient may be larger than or equal to (1 ⁇ ′) times that of the receiving support, with a typical value of 0.2 for ⁇ ′.
  • the seed layer and/or the receiving support may be made of, for example, silicon, germanium, silicon carbide, GaN or sapphire.
  • the chemical composition of the seed layer advantageously, may be identical to that of the receiving support.
  • a composite substrate may be created using the method described herein.
  • the composite substrate may be used for optics, electronics, or opto-electronics,
  • the substrate may have at least one seed layer on a receiving support, and an epitaxied useful layer on the seed layer.
  • the thermal expansion coefficient of the receiving support may be identical to or slightly larger than the thermal expansion coefficient of the useful layer, and the thermal expansion coefficient of the seed layer may be substantially equal to the thermal expansion coefficient of the receiving support so that the seed layer and the receiving support-expand in substantially the same way to avoid stressing or deforming the seed layer.
  • FIG. 1 is a schematic illustration of the steps of an exemplary embodiment of a method for making a substrate.
  • FIG. 2 is a schematic illustration of the steps of an alternative exemplary embodiment of a method for making a substrate.
  • the method according to the invention includes a step for implanting atomic species at a determined depth in a donor substrate 1 in order to form a weakened area 2 .
  • the donor substrate may be boned upon or otherwise adhered onto a receiving substrate 3 by any appropriate means known in the art.
  • bonding may mean intimate contact of the donor substrate 1 with the receiving substrate 3 in order to join the donor substrate 1 and the receiving substrate 3 by molecular adhesion.
  • Bonding may be obtained according to various methods such as, for example, (1) having a surface of the donor substrate 1 come into direct contact with a surface of the receiving substrate; (2) forming a bonding layer in order to make a connecting layer on the surface of the donor substrate 1 , forming a bonding layer in order to make a second connecting layer on the surface of the receiving supporting substrate 3 and having the surfaces of the respective connecting layers of the donor substrate 1 and the donor substrate 3 come into contact with each other; and (3) forming a bonding layer on only one of both substrates.
  • the bonding layer may consist of, for example, an insulating layer or a dielectric layer.
  • the donor substrate 1 may be bonded onto the receiving substrate 3 by means of a bonding layer 4 deposited on the surface of the donor substrate and/or the receiving substrate 3 .
  • an annealing step may be applied at this stage for strengthening the bonding interface between the bonding layer 4 and the surface of the donor substrate 1 and/or the receiving substrate 3 . Nonetheless, bonding may be achieved according to any of the methods known to one skilled in the art.
  • a seed layer 5 may be detached from the donor substrate 1 at the weakened area 2 .
  • a useful layer 6 may be deposited on the surface of the seed layer 5 .
  • the useful layer 6 may be obtained by epitaxy, which is well known to one skilled in the art, according to step 300 .
  • the step 200 for implanting atomic species and for detaching the seed layer 5 corresponds to a SMART-CUT® method, a general description of which is found in the publication Silicon-On-Insulator Technology: Materials to VLSI, 2nd Edition of Jean-Pierre Colinge, Kluwer Academic Publishers, p. 50 and 51.
  • detachment of the seed layer 5 and of the donor substrate 1 may be achieved by an operation such as, for example, heat treatment, application of mechanical stresses, chemical etching, or a combination of at least two of these operations.
  • the seed layer 5 may consist of a material for which the thermal expansion coefficient is equal to (1+ ⁇ ) times that of the receiving support 3 , with ⁇ of the order of 0.2, and preferably ⁇ equals 0.1. It will however be observed that thermal expansion may vary with temperature, with the deposition technique, with the defects present inside the layers and also with the measurement techniques. Thus, when the structure is undergoing heat treatments (e.g., during detachment of the seed layer 5 and the useful layer 6 of the receiving substrate 3 ) the seed layer 5 and the receiving support 3 will substantially expand in the same way. The receiving support 3 will expand slightly less than the seed layer 5 so that the latter may be placed under slight compression, thereby avoiding deterioration of the seed layer 5 .
  • the useful layer 6 may consist of a material which has a thermal expansion coefficient which is larger than or equal to (1 ⁇ ′) times that of the receiving support 3 , with the value of ⁇ ′ between 0 and 0.8 and, preferably, between 0.2 and 0.3. Expansions of the different layers 5 , 6 and the receiving support 3 of the same order of magnitude during heat treatments may be obtained because of the closeness of the thermal expansion coefficients of the useful layer 6 , the seed layer 5 and the receiving support 3 . In this way, any risk of deterioration of the substrate or occurrence of a residual deflection of the final substrate may be avoided.
  • the seed layer 5 and/or the receiving support 3 may comprise a material such as, for example, silicon (e.g., ⁇ 111 ⁇ silicon), germanium, polycrystalline or monocrystalline silicon carbide, GaN, polycrystalline or monocrystalline AlN, and sapphire. Further, the chemical composition of the seed layer 5 may be identical with that of the receiving support 3 .
  • the method may also include steps for preparing the surface of the seed layer 5 .
  • These preparation steps may include, for example, polishing, annealing, smooth annealing operations (e.g., under hydrogen), annealing operations for strengthening the bond, sacrificial oxidization interface operations (i.e., for oxidizing and then removing the oxidized material), etching operations, etc.
  • Step 400 may lead to detachment at the bonding layer 4 of the assembly, consisting of the seed layer 5 and the useful layer 6 , from the receiving support 3 . If a self-supported substrate is desired, the assembly formed by the seed layer 5 and the useful layer 6 may only be able to be detached from the receiving support 3 if the thickness of the assembly is greater than or equal to 50 ⁇ m.
  • detachment may be accomplished by application of mechanical, thermal, electrostatic stresses; application of any type of etching (wet, dry, gas, etching, plasma etching, etc.) and/or application of any type of etching by irradiation such as laser irradiation (e.g., by chemical etchings at the bonding layer 4 ), or the like.
  • the receiving substrate 3 which may either be destroyed or recycled in order to reuse it during the making of a new substrate, may then be obtained on the one hand, and a structure consisting of the seed layer 5 and the useful layer 6 may be obtained on the other hand.
  • the useful layer 6 may be transferred onto a final supporting substrate 7 .
  • the final support 7 may be made of a material such as, for example, semi-conducting or semi-conductive materials (e.g., silicon, germanium, etc.), metals (e.g., copper), plastic materials and glasses. Since the resultant structure no longer undergoes any heat treatment, the final supporting substrate 7 may be made with any material which has a thermal expansion coefficient and/or a lattice parameter different from those of the useful layer 6 .
  • the useful layer 6 may be transferred onto the final supporting substrate 7 by bonding.
  • the bond may be obtained by applying a bonding layer 8 on one of the surfaces of the useful layer 6 and/or the final supporting substrate 7 . Similar to selecting the final substrate 7 , the bonding techniques applied in this step are not limited by temperature resistance, contaminations, the thermal expansion coefficient and/or the lattice parameter of the useful layer 6 .
  • the layer 8 used may comprise, for example, organic layers (e.g., insulating layers of the SiO 2 , Si 3 N 4 , or polyimides), conductive metal interfaces and seals (e.g., palladium silicide Pd 2 Si, tungsten silicide WSi 2 , SiAu, or PdIn).
  • the conductive interfaces may then provide the contact on the rear face of the layer.
  • the buried structure may consist of a triple junction based on amorphous silicon of the n-i-p type.
  • This buried structure may have a lower layer (i.e., a rear contact layer) consisting of metallization, such as silver (Ag) or aluminium (Al), on which a conducting transparent oxide may be deposited.
  • the rear contact layer on the one hand, may provide an electrical contact with which the triple junction solar cell may be connected and a rear mirror, on the other hand, allowing reflection of light which has not been absorbed by the solar cell.
  • the latter may consist of three amorphous silicon layers (of type n, i and p, respectively) successively deposited on the rear contact layer. It will be appreciated by those skilled in that art that when making LEDs, mirrors may also be buried in the bonding layer 8 .
  • the useful layer 6 and the seed layer 5 may be transferred onto the final supporting substrate 7 with or without the bonding layer 8 prior to removing the seed layer 5 .
  • atomic species may be implanted in the same way as previously discussed—at a determined depth of a donor substrate 1 —in order to form a weakened area 2 .
  • the donor substrate 1 in step 100 may then be adhered on a receiving substrate 3 by any appropriate means.
  • a seed layer 5 may be detached from the donor substrate 1 at the weakened area 2 .
  • a useful layer 6 may be deposited on the surface of the seed layer 5 . Detachment of the seed layer 5 and the donor substrate 1 may be achieved by an operation such as, for example, heat treatment, application of mechanical stresses and chemical etching, or a combination of at least two of these operations.
  • the seed layer 5 may originate from the thinning of the donor substrate (for example according to a BESOI type method) before depositing the useful layer 6 .
  • the final supporting substrate 7 may then be transferred onto the useful layer 6 by means of a bonding layer 8 . Stresses may be applied in order detach the structure, which may consist of the seed layer 5 , the useful layer 6 , the bonding layer 8 and the final supporting substrate 7 , from the receiving support 3 at the bonding layer 4 .
  • a receiving substrate 3 ready to be recycled, may be obtained on the one hand and a structure consisting of the seed layer 5 , the useful layer 6 , the bonding layer 8 and the final supporting substrate 7 may be obtained on the other hand.
  • the seed layer 5 may then be removed by any appropriate means in order to obtain the final substrate.
  • the substrates are intended for making solar cells (Example 1) and light-emitting diodes (Example 2). It should be noted, however, that the examples are not intended to be limiting as to the fields of application of the invention.
  • a weakened area 2 may be made by implanting atomic species at a determined depth in the donor substrate 1 which may be made of, for example, germanium (Ge).
  • the receiving substrate 3 which may also be made of Ge, may be bonded to the donor substrate 1 by means of a bonding layer 4 .
  • the bonding layer 4 preferably made of nitride or oxide, may be formed on the face of at least one of the donor 1 or receiving 3 substrates.
  • a seed layer 5 of Ge may be detached from the donor substrate 1 at the weakened area 2 using the SMART-CUT® method as described herein.
  • the seed layer 5 of Ge may have a thermal expansion coefficient (which is also noted as CTE) which varies from 4.6 to 6.67 10 ⁇ 6 for temperatures ranging from 25° C. to 600° C.
  • Detachment of the seed layer 5 and the donor substrate 1 may be achieved by an operation such as, for example, heat treatment, application of mechanical stresses and chemical etching, or a combination of at least two of these operations.
  • a useful gallium arsenide layer 6 may then be deposited on the surface of the seed layer 5 .
  • the CTE of AsGa may be from 5.00 to 7.4 10 ⁇ 6 for temperatures ranging from 25° C. to 600° C.
  • Different layers such as, for example, InP, AsGa, GaInP, InGaAs, InGaAlP, or InGaAsN epitaxied layers, may be successively deposited by epitaxy on the deposit of the AsGa layer in order to form an epitaxial stack for making junctions (e.g., triple junctions, quadruple junctions, etc.).
  • the useful layer 6 may have a crystalline quality at least equal to the crystalline quality which may be obtained by epitaxy on a massive Ge substrate.
  • the useful layer 6 and the seed layer 5 may then be transferred onto a final supporting substrate 7 .
  • the final support 7 may also be contacted with the epitaxial stack if the latter is made beforehand.
  • the final support 7 may be made of a material such as, for example, semi-conductors (e.g., silicon, germanium), plastic materials and glasses. Transfer of the useful layer 6 and the seed layer 5 onto the final supporting substrate 7 may be performed by bonding.
  • the bond may be performed using a bonding layer 8 made of, for example, insulating layers (e.g., SiO 2 , Si 3 N 4 , etc.), organic layers (e.g., polyimides), metal layers (e.g., palladium silicide Pd 2 Si and tungsten silicide WSi 2 ), and seals (e.g., SiAu, PdIn, etc.)
  • insulating layers e.g., SiO 2 , Si 3 N 4 , etc.
  • organic layers e.g., polyimides
  • metal layers e.g., palladium silicide Pd 2 Si and tungsten silicide WSi 2
  • seals e.g., SiAu, PdIn, etc.
  • the final supporting substrate 7 , the seed layer 5 and the useful layer 6 may then be detached by any appropriate means, for example, at the bonding layer 4 from the receiving support 3 .
  • the receiving support 3 may thereafter be recycled advantageously. This detachment may be obtained by applying stresses at the bonding interface such as, for example, mechanical stresses, thermal stresses, electrostatic stresses and stresses from laser irradiation. Thereafter, the seed layer may be removed in order to obtain the final substrate

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
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US11/505,668 2000-11-27 2006-08-16 Methods for making substrates and substrates formed therefrom Abandoned US20070141803A1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
KR1020087014900A KR20080078679A (ko) 2005-12-21 2006-12-21 기판들의 제조 방법, 특히 광학, 전자공학 또는 광전자공학분야들에 대한, 및 상기 방법에 의해 구현되는 기판
PCT/EP2006/070109 WO2007071772A1 (fr) 2005-12-21 2006-12-21 Procede de fabrication de substrats, en particulier pour les domaines optique, electronique ou opto-electronique, et substrat obtenu par ce procede
TW095148275A TWI324357B (en) 2005-12-21 2006-12-21 Method for the manufacture of substrates, in particular for the optical, electronic or optoelectronic areas, and the substrate obtained in accordance with the said method
CN2006800478498A CN101341580B (zh) 2005-12-21 2006-12-21 特别是用于光学、电子或光电子领域的基片的制造方法和根据所述方法获得的基片
EP06841567A EP1979933A1 (fr) 2005-12-21 2006-12-21 Procede de fabrication de substrats, en particulier pour les domaines optique, electronique ou opto-electronique, et substrat obtenu par ce procede
US11/840,696 US7615468B2 (en) 2000-11-27 2007-08-17 Methods for making substrates and substrates formed therefrom
US12/536,082 US7839001B2 (en) 2000-11-27 2009-08-05 Methods for making substrates and substrates formed therefrom
US12/914,194 US7939428B2 (en) 2000-11-27 2010-10-28 Methods for making substrates and substrates formed therefrom

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR05/13045 2005-12-21
FR0513045A FR2894990B1 (fr) 2005-12-21 2005-12-21 Procede de fabrication de substrats, notamment pour l'optique,l'electronique ou l'optoelectronique et substrat obtenu selon ledit procede

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/883,437 Continuation-In-Part US7265029B2 (en) 2000-11-27 2004-07-01 Fabrication of substrates with a useful layer of monocrystalline semiconductor material

Related Child Applications (2)

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US11/840,696 Continuation-In-Part US7615468B2 (en) 2000-11-27 2007-08-17 Methods for making substrates and substrates formed therefrom
US11/840,696 Continuation US7615468B2 (en) 2000-11-27 2007-08-17 Methods for making substrates and substrates formed therefrom

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US20070141803A1 true US20070141803A1 (en) 2007-06-21

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US11/505,668 Abandoned US20070141803A1 (en) 2000-11-27 2006-08-16 Methods for making substrates and substrates formed therefrom
US11/840,696 Expired - Lifetime US7615468B2 (en) 2000-11-27 2007-08-17 Methods for making substrates and substrates formed therefrom
US12/536,082 Expired - Lifetime US7839001B2 (en) 2000-11-27 2009-08-05 Methods for making substrates and substrates formed therefrom
US12/914,194 Active US7939428B2 (en) 2000-11-27 2010-10-28 Methods for making substrates and substrates formed therefrom

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US11/840,696 Expired - Lifetime US7615468B2 (en) 2000-11-27 2007-08-17 Methods for making substrates and substrates formed therefrom
US12/536,082 Expired - Lifetime US7839001B2 (en) 2000-11-27 2009-08-05 Methods for making substrates and substrates formed therefrom
US12/914,194 Active US7939428B2 (en) 2000-11-27 2010-10-28 Methods for making substrates and substrates formed therefrom

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US (4) US20070141803A1 (fr)
EP (1) EP1979933A1 (fr)
KR (1) KR20080078679A (fr)
CN (1) CN101341580B (fr)
FR (1) FR2894990B1 (fr)
TW (1) TWI324357B (fr)
WO (1) WO2007071772A1 (fr)

Cited By (29)

* Cited by examiner, † Cited by third party
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US20080261376A1 (en) * 2007-04-20 2008-10-23 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing SOI substrate
US20080286952A1 (en) * 2007-05-18 2008-11-20 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
US20090098739A1 (en) * 2007-10-10 2009-04-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
US20090111244A1 (en) * 2007-10-10 2009-04-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20090117680A1 (en) * 2007-11-01 2009-05-07 Shunpei Yamazaki Method for manufacturing photoelectric conversion device
US20090194163A1 (en) * 2008-02-05 2009-08-06 Twin Creeks Technologies, Inc. Method to form a photovoltaic cell comprising a thin lamina
US20090194153A1 (en) * 2008-02-05 2009-08-06 Twin Creeks Technologies, Inc. Photovoltaic cell comprising a thin lamina having low base resistivity and method of making
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