US20060278909A1 - Mis transistor and cmos transistor - Google Patents

Mis transistor and cmos transistor Download PDF

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Publication number
US20060278909A1
US20060278909A1 US10/560,706 US56070606A US2006278909A1 US 20060278909 A1 US20060278909 A1 US 20060278909A1 US 56070606 A US56070606 A US 56070606A US 2006278909 A1 US2006278909 A1 US 2006278909A1
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Prior art keywords
plane
channel mos
mos transistor
transistor
crystal planes
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Inventor
Takefumi Nishimuta
Hiroshi Miyagi
Tadahiro Ohmi
Shigetoshi Sugawa
Akinobu Teramoto
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Foundation for Advancement of International Science
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Toyota Industries Corp
Nigata Semitsu Co Ltd
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Assigned to TADAHIRO OHMI, KABUSHIKI KAISHA TOYOTA JIDOSHOKKI, NIIGATA SEIMITSU CO., LTD. reassignment TADAHIRO OHMI ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MIYAGI, HIROSHI, NISHIMUTA, TAKEFUMI, OHMI, TADAHIRO, SUGAWA, SHIGETOSHI, TERAMOTO, AKINOBU
Publication of US20060278909A1 publication Critical patent/US20060278909A1/en
Assigned to NIIGATA SEIMITSU CO., LTD., OHMI, TADAHIRO reassignment NIIGATA SEIMITSU CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
Assigned to FOUNDATION FOR ADVANCEMENT OF INTERNATIONAL SCIENCE reassignment FOUNDATION FOR ADVANCEMENT OF INTERNATIONAL SCIENCE ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: OHMI, TADAHIRO, NIIGATA SEIMITSU CO., LTD.
Priority to US12/604,015 priority Critical patent/US8314449B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes

Definitions

  • the present invention relates to a technology to adjust the gate width of an MIS (Metal Insulator Semiconductor) transistor.
  • MIS Metal Insulator Semiconductor
  • the MIS (Metal Insulator Semiconductor) transistor is known as a semiconductor device from the past.
  • a gate insulator comprised in a MIS transistor
  • thermal oxidation which is thermal oxidation treatment at approximately 800° C. or above using oxygen molecules and water molecules.
  • thermal oxidation technique as a preprocess of the thermal oxidation process forming the gate insulator, processing to remove surface attached contaminants such as organic matter, metals and particles, followed by cleaning using diluted hydrofluoric acid and hydrogenated water, silicon dangling bonds on the surface of the silicon substrate (there are other semiconductor substrates such as germanium) on which the gate insulator is to be formed, are terminated by hydrogen, controlling formation of a native oxide film on the surface of the silicon substrate, and the silicon substrate with a clean surface is introduced to the following thermal oxidation process.
  • heating of the silicon substrate is performed in an inert gas atmosphere such as argon (Ar).
  • an inert gas atmosphere such as argon (Ar).
  • surface-terminating hydrogen which terminates the silicon dangling bonds on the surface of the silicon substrate, is removed with at a temperature of about 600° C. or higher, and oxidation of the surface of the silicon substrate is performed at a temperature of about 800° C. or higher in an atmosphere where oxygen molecules or water molecules are introduced.
  • a gate insulator is formed on the surface (the (100) plane) of a silicon substrate with the (100) plane being the principal plane, based on a technique such as the above thermal oxidation technique, and the insulator is comprised in a transistor (the p-channel MIS transistor and the n-channel MIS transistor) with a MIS configuration.
  • CMOS transistor complementary MOS transistor
  • MOS Metal Oxide Semiconductor
  • One example of those devices is a single conductivity type (the p-channel or the n-channel) MOS transistor configured by forming a gate insulator by applying the above thermal oxidation processing to one crystal plane (the (100) plane) of a projecting part formed on a semiconductor substrate and by forming channels on a sidewall plane of the projecting part of the semiconductor substrate (Japanese laid-open unexamined patent publication No. 2002-110963).
  • channels are formed in the silicon substrate.
  • the channel width is provided by a length in a direction perpendicular to the direction of electron or hole movement along the channels formed along the one crystal plane.
  • the electron transfer or hole transfer of the above channels are required to be enhanced, in order to realize the above, a design such that the above channel width should be lengthened, and such as to reduce waste of electrons and holes within the channel is required.
  • Patent Document 1 Japanese laid-open unexamined patent publication No. 2002-110963
  • the MIS transistor has the following configuration.
  • One mode of the MIS transistor of the present invention is a MIS transistor, formed on a semiconductor substrate, comprising a semiconductor substrate with a projecting part of which the surfaces are at least two different crystal planes on a principal plane, a gate insulator for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode comprised by the gate insulator so as to be electrically insulated from the semiconductor substrate, and comprised on each of said at least two different crystal planes constituting the surface of the projecting part and a single conductivity type diffusion region (n-type or p-type conductivity type for example, and the single conductivity type diffusion means that the regions, formed both sides of the above gate electrode, have diffusion regions of the same conductivity type) formed in the projecting part facing each of said at least two different crystal planes constituting the surface of the projecting part and individually formed on both sides of the gate electrode.
  • a single conductivity type diffusion region n-type or p-type conductivity type for example,
  • the channel width of a channel formed along with the gate insulator between the single conductivity diffusion regions individually formed on both sides of the gate electrodes is indicated by summation of the channel widths of each channel generated along said at least two different crystal planes.
  • the above gate insulator covers at least a part of each of said at least two different crystal planes, which configure the surface of the projecting part, so that said at least two different crystal planes are continuously covered.
  • Another mode of the MIS transistor of the present invention is a MIS transistor formed on a semiconductor substrate, comprising a semiconductor substrate with a projecting part of which the surfaces are at least two different crystal planes on a principal plane, a gate insulator for covering at least a part of each of said at least two different crystal planes constituting the principal plane and the surface of the projecting part, a gate electrode comprised by the gate insulator so as to be electrically insulated from the semiconductor substrate, and comprised on each of said at least two different crystal planes constituting the principal plane and the surface of the projecting part and a single conductivity type diffusion region formed in the projecting part facing each of said at least two different crystal planes constituting the principal plane and surface of the projecting part and individually formed on both sides of the gate electrodes.
  • the channel width of the channel generated along the principal plane may be complemented with the channel width of the channel generated along a crystal plane, different from the principal plane, of said at least two crystal planes.
  • the above gate insulator covers at least a part of each of said at least two different crystal planes, which configure the principal plane and the surface of the projecting part, so that the principal plane and said at least two different crystal planes are continuously covered.
  • each of the above modes of the MIS transistor comprises a signal transistor.
  • each of the above modes of the MIS transistor has a configuration characterized in that the semiconductor substrate is a silicon substrate and the principal plane and said at least two different crystal planes are any two different crystal planes from the (100) plane, the (110) plane and the (111) plane.
  • the channel generated along the gate insulator of the MIS transistor is generated along said at least two different crystal planes.
  • the channel width can be acquired in a direction different from a crystal plane, which directly enlarges the element area. It is possible to control the reduction of the amount of energy which is effective for driving a transistor, for each unit length of channel width in the channel generated along the gate insulator.
  • the gate insulator is formed by exposing the surface of the silicon substrate to plasma of a prescribed inert gas so as to remove the hydrogen, and that the hydrogen content at an interface of the silicon substrate and the gate insulator is 10 11 /cm 2 or less in units of surface density.
  • Such a configuration allows the control of reduction in the energy amount which is effective for driving a transistor, for each unit length of the channel width in the channel generated along the gate insulator.
  • the channel length modulation effect which is reduction of the effective gate length and an increase in the drain current, caused by the shift of a pinch-off point (a point where the channel carrier density becomes approximately 0) in the saturation region in the transistor characteristics.
  • CMOS transistor of the present invention supposes that an n-channel MOS transistor is formed only on the principal plane of the semiconductor substrate, and in the above each mode of the MIS transistor, and in the above each mode of MIS transistors, a p-channel MOS transistor comprises the gate insulator as an oxide film and the single conductivity type diffusion region as a p-type diffusion region.
  • CMOS transistor of the present invention supposes that an n-channel MOS transistor and a p-channel MOS transistor be comprised on a silicon substrate with the (100) plane as its principal plane, and the n-channel MOS transistor comprises a gate oxide film covering a part of the principal plane alone, a gate electrode configured on the principal plane by the gate oxide film so as to be electrically insulated from the silicon substrate, and an n-type diffusion region formed in the silicon substrate facing the principal plane and formed on both sides of the gate electrode, and the p-channel MOS transistor comprises a p-type diffusion region equivalent to the single conductivity type diffusion region in each mode of the MIS transistor described above, a gate oxide film equivalent to the gate insulator in each mode of the MIS transistor described above, and the (100) crystal plane and a second crystal plane is the (110) crystal plane corresponding to said at least two crystal planes in each mode of the MIS transistor described above.
  • a gate insulator in a p-channel MOS transistor, which is a direct cause of the large element area of the CMOS transistor, a gate insulator can be formed on a crystal plane oriented in a different direction from a crystal plane, which directly causes the element area of the CMOS transistor to be large. For that reason, in the p-channel MOS transistor, the channel width of a channel generated along the gate insulator can be generated in a different direction from a direction, which directly causes the element area to be large. Then, the current driving capacity of the p-channel MOS transistor and the current driving capacity of the n-channel MOS transistor can be matched without variation in element area between the MOS transistors.
  • the channel width can be acquired along said at least two different crystal planes in the p-channel MOS transistor, it is possible that the element area and the current driving capacity of the p-channel MOS transistor and the n-channel MOS transistor, which is formed only on the principal plane, can be approximately matched.
  • FIG. 1 is a cross-sectional diagram showing an example of a plasma processing device using a radial line slot antenna
  • FIG. 2 is an analysis result of silicon-hydrogen bonding on the surface of a silicon substrate 103 in FIG. 1 by an infrared spectrograph;
  • FIG. 3 is a relationship between pressure in a processing chamber and thickness of an oxide film formed when the gas pressure in the processing chamber 101 of FIG. 1 is changed while keeping the pressure ratio of Kr/O 2 at 97/3 in the processing chamber;
  • FIG. 4 is a diagram comparing growth rates of Kr/O 2 plasma oxide films with growth rates of dry thermal oxide films
  • FIG. 5 is a diagram comparing Dit at midgap of the Kr/O 2 plasma oxide film with that of the dry thermal oxide film;
  • FIG. 6 is an example of a configuration of a p-channel MOS transistor
  • FIG. 7 is a diagram of a part extracted from FIG. 6 ;
  • FIG. 8 is an example of a configuration of a CMOS transistor
  • FIG. 9 is a diagram of a part extracted from FIG. 8 ;
  • FIG. 10A shows drain voltage versus normalized drain current characteristic
  • FIG. 10B shows drain voltage versus normalized drain current characteristic
  • FIG. 10C shows drain voltage versus normalized drain current characteristic.
  • a transistor of the embodiment of the present invention has an MIS (Metal Insulator Semiconductor) configuration.
  • a gate insulator of the MIS transistor is formed based on a gate insulator thin film formation technique, in which a thin gate insulator of an MIS transistor is formed with high performance electrical characteristics, as disclosed in Japanese laid-open unexamined patent publication No. 2002-261091.
  • gate insulator of the MIS transistor there are a variety such as an oxide film, a nitride film and an oxynitride film described in Japanese laid-open unexamined patent publication No. 2002-261091, and also many varieties for semiconductor substrates with different crystal planes such as silicon and germanium. Any of the above gate insulators or the semiconductor substrates can be used in the embodiment of the present invention; however in order to facilitate comprehension of the explanation, the following description takes the example of a MOS (Metal Oxide Semiconductor) configuration transistor with a silicon (Si) substrate with its surfaces of at least two of the (100) crystal plane, the (110) crystal plane and the (111) crystal plane as a semiconductor substrate, and an oxide film as a gate insulator.
  • MOS Metal Oxide Semiconductor
  • FIG. 1 is a cross-sectional diagram showing an example of a plasma processor device 100 using a radial line slot antenna.
  • a vacuum vessel (processing chamber) 101 is evacuated, argon (Ar) gas is introduced into the vessel from a shower plate 102 , and later the introduced gas is changed to krypton (Kr) gas.
  • Pressure in the vacuum processing chamber 101 is set around 133 Pa (1 Torr).
  • a silicon substrate 103 is placed on a sample holder 104 with a heating mechanism and the temperature of the sample is set around 400° C. If the temperature of the silicon substrate 103 falls within the range of 200-550° C., the results described below will be almost the same.
  • the silicon substrate 103 is treated with diluted hydrofluoric acid cleaning in the immediately preceding pretreatment processing step, and as a result, the dangling bonds of silicon on the surface are terminated with hydrogen.
  • 2.45 GHz microwaves are provided from a coaxial waveguide 105 to a radial line slot antenna 106 , and microwaves are emitted in the processing chamber 101 from the radial line slot antenna 106 via a dielectric plate 107 configured on a part of the wall of the processing chamber 101 .
  • the emitted microwaves excite the Kr gas introduced from the shower plate 102 into the processing chamber 101 , and high-density Kr plasma is formed directly below the shower plate 102 . If the frequency of the provided microwaves is approximately within the range from 900 MHz to 10 GHz, the results explained below are almost the same.
  • the distance between the shower plate 102 and the substrate 103 is set at 6 cm in the present embodiment. A shorter distance between the two enables higher speed film formation.
  • the present embodiment shows an example of film formation using a plasma device with a radial line slot antenna
  • other methods can be used to excite plasma by emitting microwaves within the processing chamber.
  • the surface of the silicon substrate 103 receives low-energy Kr ion irradiation, and the terminating hydrogen on the surface is removed.
  • FIG. 2 shows a result of analysis of silicon-hydrogen bonding on the silicon substrate surface by an infrared spectrograph, and demonstrates the removal effect of the terminating hydrogen on the silicon surface by the Kr plasma excited by emitting microwaves with a power density of 1.2 W/cm 2 under 133 Pa (1 Torr) pressure in the processing chamber 101 .
  • Reference to FIG. 2 discloses that only 1 second of Kr plasma irradiation causes most of the optical absorption in the vicinity of a wave number of 2100 cm ⁇ 1 , which is characteristic of the silicon-hydrogen bond, to disappear, and with approximately 30 seconds of irradiation, the optical absorption disappears almost completely. In other words, approximately 30 seconds of Kr plasma irradiation can remove hydrogen terminating the silicon surface. In the present embodiment, Kr plasma irradiation is continued for 1 minute and completely removes the terminating hydrogen on the surface.
  • a Kr/O 2 gas mixture with a partial pressure ratio of 97/3 is introduced from the shower plate 102 .
  • the pressure in the processing chamber is maintained at around 133 Pa (1 Torr).
  • Kr* which is in an intermediate excitation state, and O 2 molecules collide, effectively generating a large amount of atomic oxygen O*.
  • the surface of the silicon substrate 103 is oxidized by this atomic oxygen O*.
  • O* this atomic oxygen
  • the use of the present thin film formation method enables oxidation processing by the atomic oxygen at the significantly low temperature of around 400° C.
  • FIG. 3 shows the relationship between the thickness of the formed oxide film and the pressure in the processing chamber in a case where, maintaining the pressure ratio of Kr/O 2 at 97/3 within the processing chamber, the gas pressure within the processing chamber 101 is changed.
  • the temperature of the silicon substrate 103 is set at 400° C., and the oxidation processing is carried out for 10 minutes.
  • Reference to FIG. 3 reveals that the oxidation rate is highest when the pressure within the processing chamber 101 is around 133 Pa (1 Torr), and thus this pressure or pressure conditions around this pressure are optimal.
  • the optimal pressure is not limited to the case that the plane orientation of the silicon substrate 103 is the (100) plane, but is the same for any silicon surface with any plane orientation.
  • a semi-conductor integrated circuit device comprising a MOS transistor and a capacitor can be completed after well-known electrode formation process, protective film formation process, and hydrogen sintering processing process etc.
  • the present gate insulator thin film formation method hydrogen, remaining at the interface between a silicon substrate and a silicon oxide film formed as the gate insulator of a MOS transistor, is removed, and the interface is flattened.
  • a low Dit at midgap at the interface can be attained and favorable electrical characteristics (low leakage current characteristics, low Dit at midgap, high voltage resistance, high hot carrier resistance, constant threshold voltage characteristics etc.) can be acquired even though the gate insulator is thinned.
  • favorable electrical characteristics can still be acquired from the plane orientation.
  • FIG. 4 shows the growth rate of a Kr/O 2 plasma oxide film, when oxidizing the (100) plane, the (111) plane and the (110) plane of a silicon substrate with the plasma processing device 100 of FIG. 1 , in comparison with growth rates of dry thermal oxide films.
  • the growth rate of the oxide film is higher than the growth rate when forming a dry thermal oxide film on the (100) plane, suggesting that the film quality of the dry thermal oxide film formed on the (111) plane and the (110) plane are inferior.
  • FIG. 5 shows a comparison result of Dit at midgap of the Kr/O 2 plasma oxide film formed as above and that of the dry thermal oxide film.
  • Reference to FIG. 5 discloses that the Dit at midgap of the Kr/O 2 plasma oxide film formed on the (100) plane of a silicon and the Kr/O 2 plasma oxide film formed on the (111) plane of a silicon and the (110) plane of a silicon are all lower than those of the dry thermal oxide film formed on the (100) plane of a silicon, and an oxide film with extremely high quality can be acquired.
  • a dry thermal oxide film formed on the (111) plane of a silicon and the (110) plane of a silicon has an extremely high Dit at midgap as predicted from the result in FIG. 4 , and it is possible that various problems may be caused such as change in threshold voltage by carrier capture and increase in gate leakage current when used as a gate insulator of an MOS transistor.
  • FIG. 6 and FIG. 7 are examples of configurations of a 3-dimentional p-channel MOS transistor.
  • FIG. 7 is a diagram of a part extracted from FIG. 6 .
  • a p-channel MOS transistor 700 shown in FIG. 6 as an example, is formed on a Si substrate 702 with a principal plane of the (100) plane on which the p-type region is formed as shown in FIG. 7 .
  • a projecting part 704 with a width W and a height H is formed in the p-type region of the Si substrate 702 .
  • the top plane of the projecting part 704 is defined by the (100) plane, and the both sidewall planes are defined by the (110) planes.
  • a silicon oxide film is evenly formed on the Si substrate 702 of FIG. 6 by the plasma processing device 100 explained in FIG. 1 , and on top of the film, a polysilicon gate electrode 706 shown in FIG. 6 is formed on the p-type region of the Si substrate 702 .
  • the patterning of the silicon oxide film is performed following the patterning of the gate electrode 706 , and a gate insulator 708 is formed in a region surrounded by a bold line and broken line shown in FIG. 6 so as to fit the gate electrode 706 .
  • p-type diffusion regions 710 a and 710 b including the above projecting part 704 are formed on both sides of the gate electrode 706 as shown in FIG. 6 by ion implantation of a p-type impurity by using the gate electrode 706 as a self-aligning mask.
  • the p-channel MOS transistor 700 is formed on the above p-type region on the Si substrate 702 .
  • the p-channel MOS transistor 700 described in the present example, has a gate length of L, and the gate electrode 706 covers flat parts of the Si substrate 702 for a gate width of W′/2 on both sides of the projecting part 704 . Consequently the gate width on the (100) plane of the gate electrode 706 including the top part of the projecting part 704 A is expressed by W+W′. Meanwhile, the gate width on the (110) plane of the gate electrode 706 is formed on both sidewalls, and thus is expressed by 2H.
  • the current driving capacity of the p-channel MOS transistor 700 formed on the p-type region is expressed by an equation pp (W+W′)+2 ⁇ p2 H, where ⁇ p1 represents the hole mobility in the (100) plane and ⁇ p2 represents the hole mobility in the (110) plane.
  • the configuration of the p-channel MOS transistor shown in this example has a convex configuration with two sidewalls in order to configure a crystal plane other than the (100) plane, which is the principal plane; however a configuration may comprise only one sidewall.
  • the channel width depends on the length of H and W alone.
  • the p-channel MOS transistor configured as above, low Dit at midgap is achieved and the flicker noise can be reduced in each of the interfaces between the semiconductor substrate with different plane orientations and the gate insulator. Additionally, by assuming a channel configuration shown by shaded area in FIG. 6 , it is possible to reduce the channel length modulation effect, and therefore favorable electrical characteristics can be stably acquired.
  • the MOS transistor with such convex configuration is a stable element reducing variation in the electrical characteristics in each element.
  • the gate width of the p-channel MOS transistor can be acquired not only on the principal plane of the semiconductor substrate (the (100) plane, for example) but also on a crystal plane oriented in different directions as described above (the (110) plane, for example). Additionally, it is possible that the gate width can be acquired from the projecting part itself alone without using the principal plane. Thus, the channels generated between the p-type diffusion regions 710 a and 710 b along the gate insulator are generated on crystal planes other than the principal plane.
  • the electrical characteristics of the channel are favorable for any crystal plane (in other words, reduction in the energy amount effective for driving a transistor per unit length of the channel width is controlled), it is possible to make the element area of the p-channel MOS transistor small in practice by choosing a large value for H instead of for the value of W+W′, and gaining channel width in the vertical direction in FIG. 6 .
  • the (100) plane of the Si substrate is the principal plane and the (110) plane of the Si substrate is the sidewall plane; however, a transistor may be configured by arbitrarily combining the (100) plane, the (110) plane and the (111) plane, and an effect similar to the above should be acquired from any combination.
  • the p-channel MOS transistor is set forth; however, the n-channel MOS transistor can also comprise both the 3-dimensional configuration and the effect similar to the above.
  • CMOS Complementary Metal Oxide Semiconductor
  • FIG. 8 and FIG. 9 are configuration examples of a CMOS transistor comprising a p-channel MOS transistor and an n-channel MOS transistor.
  • FIG. 9 is a diagram of a part extracted from FIG. 8 .
  • a CMOS transistor 900 in FIG. 8 is formed on a Si substrate 910 with a principal plane of the (100) plane on which an n-type region A and a p-type region B, separated by an element separation region 905 , are formed as shown in FIG. 9 , and a projecting part 910 B with its width of W 1B and both sidewalls height of H B are formed on the p-type region B.
  • the top plane of the projecting part 910 B is defined by the (100) plane
  • the sidewall plane is defined by the (110) plane.
  • a silicon oxide film is evenly formed on the Si substrate 910 of FIG. 9 by the plasma processing device 100 explained in FIG. 1 , and over the film, polysilicon gate electrodes 930 A and 930 B shown in FIG. 8 are formed on the region A and the region B, respectively.
  • the patterning of the silicon oxide film is performed as the patterning of the gate electrodes 930 A and 930 B, and a gate insulator 920 A is formed so as to correspond to the gate electrode 930 A and a gate insulator 920 B is formed so as to correspond to the gate electrode 930 B in a plane surrounded by bold lines and broken lines shown in FIG. 8 .
  • n-type diffusion regions 910 a and 910 b are formed on both sides of the gate electrode 930 A in the n-type region A by ion implantation of an n-type impurity using the gate electrode 930 A as a self-aligning mask.
  • the p-type diffusion regions 910 c and 910 d including the projecting part 910 B are formed in the regions both sides of the gate electrode 930 B.
  • the n-channel MOS transistor 940 A is formed on the above n-type region A and the p-channel MOS transistor 940 B is formed on the above p-type region B on the Si substrate 910 .
  • the n-channel MOS transistor 940 A has a gate length of L gA
  • the p-channel MOS transistor 940 B has a gate length of L gB .
  • the gate electrode 930 A covers the (100) plane of the Si substrate 910 with a width of W A as shown in FIG. 8 . Consequently, the gate width of the n-channel MOS transistor is expressed by W A .
  • the gate electrode 930 B covers the flat part of the Si substrate 910 with a gate width of W 2B /2 on each side of the projecting part 910 B.
  • the gate width on the (100) plane of the gate electrode 930 B including the top part of the projecting part 910 B is represented by W 1B +W 2B
  • the gate width on the (110) plane of the gate electrode 930 B is formed on both sidewalls and thus is represented by 2H B .
  • the current driving capacity of the n-channel MOS transistor 940 A formed on the n-type region A is expressed by an equation ⁇ n1 W A , where ⁇ n1 represents the electron mobility of the (100) plane.
  • the current driving capacity of the p-channel MOS transistor 940 B formed on the p-type region B is expressed by an equation ⁇ p1 (W 1B +W 2B )+2 ⁇ p2 H B , where ⁇ p1 represents hole mobility in the (100) plane and ⁇ p2 represents hole mobility in the (110) plane.
  • the current driving capacity of the n-channel MOS transistor 940 A can be set equal to the current driving capacity of the p-channel MOS transistor 940 B.
  • element areas of the n-channel MOS transistor 940 A can be the same as those of the p-channel MOS transistor 940 B, and both of the current driving capacities can be equal to each other.
  • the configuration of the p-channel MOS transistor shown in this example has a convex configuration with two sidewalls in order to configure a crystal plane other than the (100) plane, which is the principal plane; however a configuration may comprise only one sidewall.
  • CMOS transistor configured as above, low Dit at midgap is achieved in the interface between semiconductor substrate and the gate insulator, therefore the flicker noise can be reduced, and favorable electrical characteristics can be stably acquired. For this reason, a CMOS transistor with such a configuration is a stable element with variation in the electrical characteristics of the element reduced. Specifically, because the current driving capacity of the n-channel MOS transistor and that of the p-channel MOS transistor can be matched, reduction in driving capacity etc. caused by the variation of the electrical characteristics of each MOS transistor can be suppressed.
  • the gate width of the p-channel MOS transistor can be acquired not only on the principal plane of the Si substrate (the (100) plane, for example), but also on a crystal plane of the projecting part formed on the principal plane (the (110) plane, for example) and oriented in a different direction. Therefore, the channels generated between the p-type diffusion regions 910 c and 910 d, along the gate insulator are generated not only on the principal plane of the semiconductor substrate but also on the other crystal plane.
  • the electrical characteristics in the above channels are favorable to any crystal plane as described above (in other words, reduction in the amount of energy effective for driving a transistor per unit length of the channel width is controlled), it is possible to make the element area of the p-channel MOS transistor small according to the element area of the n-channel MOS transistor by using a large value of H B instead of the value of W 1B +W 2B , and gaining channel width in the vertical direction in FIG. 8 .
  • the (100) plane of the Si substrate is the principal plane and the (110) plane of the Si substrate is the sidewall plane; however, a transistor may be configured by arbitrarily combining the (100) plane, the (110) plane and the (111) plane, and an effect similar to the above should be acquired from any combination.
  • FIG. 10A - FIG. 10C show the relationship between the drain voltage and the normalized drain current when a silicon oxide film is formed on the (100) plane of a silicon substrate, the (111) plane of a silicon substrate and the (110) plane of a silicon substrate, respectively, by the plasma processing device 100 in FIG. 1 and a p-channel MOS transistor with the silicon oxide film as a gate insulator is formed.
  • FIG. 10A and FIG. 10B show both of the cases that the silicon oxide film is formed by the Kr/O 2 plasma processing and that the silicon oxide film is formed by dry thermal oxidation processing.
  • FIG. 10A and FIG. 10B show both of the cases that the silicon oxide film is formed by the Kr/O 2 plasma processing and that the silicon oxide film is formed by dry thermal oxidation processing.
  • FIG. 10C because an oxide film is not formed on the (110) plane of a silicon by dry thermal oxidation processing, only an example of a gate oxide film formed by Kr/O 2 plasma processing is shown.
  • the result of FIG. 10A is of a p-channel MOS transistor with a gate length of 10 ⁇ m and a gate width of 50 ⁇ m
  • the results in FIG. 10B and FIG. 10C are of the p-channel MOS transistor with a gate length 10 am and a gate width of 300 ⁇ m.
  • Reference to FIG. 10A - FIG. 10C describes that it is possible to increase the drain current of the p-channel MOS transistor, that is mutual conductance or current driving capacity, by forming a transistor on any crystal surface except for the (100) plane of a silicon, such as the (111) plane or the (110) plane, to acquire a current driving force of about 1.3 times as much as that of the p-channel MOS transistor formed on the (100) plane when the p-channel MOS transistor is formed on the (111) plane of a silicon, and to acquire a current driving force of about 1.8 times as much as that of the p-channel MOS transistor formed on the (100) plane when the p-channel MOS transistor is formed on the (110) plane of a silicon.
  • the MOS transistor configured in 3-dimensions using crystal planes oriented in different plane directions in FIG. 6 and FIG. 8 has a high current driving capacity.
  • the above 3-dimensional MIS transistor and CMOS transistor can be applied to various circuits.
  • the CMOS transistor of the embodiment of the present invention can be applied to a pass-transistor circuit, inverter circuit, a push-pull amplifier and so on.
  • a pass-transistor circuit for example, the CMOS transistor of the embodiment of the present invention can be applied to a pass-transistor circuit, inverter circuit, a push-pull amplifier and so on.
  • CMOS transistor only the n-channel MOS transistor or the p-channel MOS transistor without using the CMOS transistor can be applied to the above circuits.
  • MIS transistor or the CMOS transistor of the embodiment of the present invention can be applied to analog circuits.
  • channel width can be acquired on a crystal plane formed by projection from a prescribed crystal plane, which determines the element area.
  • reduction of the amount of energy effective for driving a transistor in unit length of the channel width can be substantially controlled. For that reason, acquisition of further channel width is practically possible while controlling increase in element area.
  • CMOS transistor As the element area of the p-channel MOS transistor, which directly causes the element area of a CMOS transistor to be large, can be small.
  • both of the current driving capacities can be matched without causing variation in their element areas.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110147815A1 (en) * 2009-12-21 2011-06-23 Renesas Electronics Corporation Semiconductor device and production method thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100428476C (zh) * 2006-07-10 2008-10-22 中芯国际集成电路制造(上海)有限公司 互补金属氧化物半导体器件
JPWO2008007748A1 (ja) 2006-07-13 2009-12-10 国立大学法人東北大学 半導体装置
CN112071863A (zh) * 2020-09-04 2020-12-11 Tcl华星光电技术有限公司 一种阵列基板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391506A (en) * 1992-01-31 1995-02-21 Kawasaki Steel Corporation Manufacturing method for semiconductor devices with source/drain formed in substrate projection.
US20020185676A1 (en) * 2001-05-31 2002-12-12 Hisayo Momose Semiconductor device
US20030049895A1 (en) * 2001-07-19 2003-03-13 Stmicroelectronics S.R.I. Semiconductor integrated electronic device and corresponding manufacturing method
US6555451B1 (en) * 2001-09-28 2003-04-29 The United States Of America As Represented By The Secretary Of The Navy Method for making shallow diffusion junctions in semiconductors using elemental doping
US20030102497A1 (en) * 2001-12-04 2003-06-05 International Business Machines Corporation Multiple-plane finFET CMOS
US20040102052A1 (en) * 2000-12-28 2004-05-27 Tadahiro Ohmi Semiconductor device and its manufacturing method
US7202534B2 (en) * 2001-12-13 2007-04-10 Tadahiro Ohmi Complementary MIS device

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US655451A (en) * 1899-11-22 1900-08-07 Morgan & Wright Valve for pneumatic tires.
DE3780895T2 (de) * 1986-09-24 1993-03-11 Nec Corp Komplementaerer feldeffekt-transistor mit isoliertem gate.
JPS63228662A (ja) * 1987-03-18 1988-09-22 Toshiba Corp 相補型ｍｏｓ半導体装置の製造方法
JPH01276669A (ja) * 1988-04-27 1989-11-07 Toshiba Corp 半導体装置
JPH03155165A (ja) * 1989-11-14 1991-07-03 Toshiba Corp 半導体装置およびその製造方法
JPH05136382A (ja) * 1991-11-08 1993-06-01 Nec Corp 相補型ゲートアレイ
JPH07249768A (ja) * 1994-03-14 1995-09-26 Toshiba Corp Ｍｉｓ型半導体装置及びその製造方法
FR2720191B1 (fr) 1994-05-18 1996-10-18 Michel Haond Transistor à effet de champ à grille isolée, et procédé de fabrication correspondant.
JPH08264764A (ja) * 1995-03-22 1996-10-11 Toshiba Corp 半導体装置
JPH0923011A (ja) * 1995-07-05 1997-01-21 Hitachi Ltd 半導体装置及びその製造方法
US5932911A (en) * 1996-12-13 1999-08-03 Advanced Micro Devices, Inc. Bar field effect transistor
US6245615B1 (en) * 1999-08-31 2001-06-12 Micron Technology, Inc. Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
JP2002118255A (ja) * 2000-07-31 2002-04-19 Toshiba Corp 半導体装置およびその製造方法
JP4044276B2 (ja) 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6649480B2 (en) * 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6974729B2 (en) * 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
JP2005056870A (ja) * 2003-06-12 2005-03-03 Toyota Industries Corp ダイレクトコンバージョン受信の周波数変換回路、その半導体集積回路及びダイレクトコンバージョン受信機
JP2005006127A (ja) * 2003-06-12 2005-01-06 Toyota Industries Corp ミキサ回路
JP2008002226A (ja) 2006-06-26 2008-01-10 Sekisui Jushi Co Ltd フェンス

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5391506A (en) * 1992-01-31 1995-02-21 Kawasaki Steel Corporation Manufacturing method for semiconductor devices with source/drain formed in substrate projection.
US20040102052A1 (en) * 2000-12-28 2004-05-27 Tadahiro Ohmi Semiconductor device and its manufacturing method
US20020185676A1 (en) * 2001-05-31 2002-12-12 Hisayo Momose Semiconductor device
US20030049895A1 (en) * 2001-07-19 2003-03-13 Stmicroelectronics S.R.I. Semiconductor integrated electronic device and corresponding manufacturing method
US6555451B1 (en) * 2001-09-28 2003-04-29 The United States Of America As Represented By The Secretary Of The Navy Method for making shallow diffusion junctions in semiconductors using elemental doping
US20030102497A1 (en) * 2001-12-04 2003-06-05 International Business Machines Corporation Multiple-plane finFET CMOS
US7202534B2 (en) * 2001-12-13 2007-04-10 Tadahiro Ohmi Complementary MIS device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110147815A1 (en) * 2009-12-21 2011-06-23 Renesas Electronics Corporation Semiconductor device and production method thereof
US8502319B2 (en) * 2009-12-21 2013-08-06 Renesas Electronics Corporation Semiconductor device and production method thereof

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