US20060176091A1 - Delay locked loop circuit - Google Patents

Delay locked loop circuit Download PDF

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Publication number
US20060176091A1
US20060176091A1 US11/289,753 US28975305A US2006176091A1 US 20060176091 A1 US20060176091 A1 US 20060176091A1 US 28975305 A US28975305 A US 28975305A US 2006176091 A1 US2006176091 A1 US 2006176091A1
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Prior art keywords
clock signal
signal
delay
logic level
current
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US11/289,753
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English (en)
Inventor
Shiro Sakiyama
Yusuke Tokunaga
Shiro Dosho
Toru Iwata
Takashi Hirata
Hideki Yoshii
Yasuyuki Doi
Makoto Hattori
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Panasonic Corp
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Matsushita Electric Industrial Co Ltd
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Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DOI, YASUYUKI, HATTORI, MAKOTO, YOSHII, HIDEKI, DOSHO, SHIRO, HIRATA, TAKASHI, IWATA, TORU, SAKIYAMA, SHIRO, TOKUNAGA, YUSUKE
Publication of US20060176091A1 publication Critical patent/US20060176091A1/en
Priority to US12/033,707 priority Critical patent/US7705645B2/en
Assigned to PANASONIC CORPORATION reassignment PANASONIC CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators

Definitions

  • the present invention relates to a delay locked loop circuit.
  • the delay locked loop circuit (DLL) is used for detecting an optimum strobe point of a clock signal for a data signal during a memory access, or the like.
  • DDR single data rate
  • the delay locked loop circuit detects a 1 ⁇ 2 phase of a reference clock signal
  • DDR double data rate
  • the delay locked loop circuit detects a 1 ⁇ 4 phase or 3 ⁇ 4 phase of the reference clock signal.
  • the delay locked loop circuit is used for timing sequence control of a word line, a sense amplifier, or the like.
  • FIG. 16 shows a structure of a conventional delay locked loop circuit.
  • a delay circuit 100 includes four delay elements 101 which are connected in series. The delay circuit 100 delays reference clock signal CLKr by one cycle to output delayed clock signal CLKd.
  • a phase comparator 102 compares the phases of reference clock signal CLKr and delayed clock signal CLKd to output signal UP and signal DN according to the comparison result.
  • a charge pump circuit 103 (including a loop filter) controls the delay circuit 100 based on signal UP and signal DN.
  • the delay locked loop circuit having such a structure becomes stable when the phase of delayed clock signal CLKd is delayed from the phase of reference clock signal CLKr by one cycle, and at this point in time, the delay of delayed clock signal CLKd is locked.
  • the delay element 101 at the first stage of the delay circuit 100 outputs a clock signal delayed by a 1 ⁇ 4 phase (90°).
  • the delay element 101 at the third stage of the delay circuit 100 outputs a clock signal delayed by a 3 ⁇ 4 phase (270°).
  • the driving capacity and load capacity are different between reference clock signal CLKr and the delay element 101 . Therefore, it is difficult to improve the accuracy for 1 ⁇ 4 phase and 3 ⁇ 4 phase.
  • the delayed clock signal is generated to have a delay of 1 ⁇ 4 phase or 3 ⁇ 4 phase from the reference clock signal irrespective of the duty ratio of the reference clock signal.
  • the duty ratio of the reference clock signal is lower than 25%, the 1 ⁇ 4 phase-delayed clock signal does not rise or fall during an on-duty period of the reference clock signal, and therefore, the conventional delay locked loop circuit cannot be used with DDR. That is, there is a possibility that the conventional delay locked loop circuit does not normally operate with a reference clock signal whose duty ratio is not 50%.
  • the conventional delay locked loop circuit In the conventional delay locked loop circuit, based on its principle, signals UP and DN having extremely short pulses are output even after the delay of delayed clock signal CLKd is locked. Therefore, the conventional delay locked loop circuit has static jitters. Although the static jitters can be suppressed by decreasing a delay gain, the decrease of the delay gain deteriorates the response speed achieved till the delay is locked, i.e., delays the locking time. Alternatively, the static jitters can be suppressed by increasing the capacitance of a loop filter to have a larger filter time constant. However, in this case, the circuit scale increases.
  • an objective of the present invention is to realize a delay locked loop circuit which does not have static jitters based on its principle and is capable of generating a delayed clock signal with high accuracy irrespective of the duty ratio of a reference clock signal.
  • a measure taken by the present invention for achieving the above objective is a delay locked loop circuit, comprising: a delay element for generating a delayed clock signal which transitions from a first logic level to a second logic level with a delay from a first transition of a reference clock signal from a first logic level to a second logic level; a signal generation circuit for generating first and second signals which complementarily change according to the first transition of the reference clock signal, a second transition of the reference clock signal from the second logic level to the first logic level, and a transition of the delayed clock signal; a charge pump circuit for performing, according to the first and second signals, a first operation during an interval extending from the first transition of the reference clock signal to the transition of the delayed clock signal and a second operation during an interval extending from the transition of the delayed clock signal to the second transition of the reference clock signal, the first operation being any one of a push operation and a pull operation, and the second operation being the other of the push operation and the pull operation; and a loop filter which receives an output of the charge pump
  • FIG. 1 shows a structure of a delay locked loop circuit according to embodiment 1.
  • FIG. 2 shows a structure of a delay element.
  • FIG. 3 is a timing chart of the delay element.
  • FIG. 4 is a timing chart of the delay locked loop circuit according to embodiment 1.
  • FIG. 5 shows a structure of a delay locked loop circuit according to embodiment 2.
  • FIG. 6 is a timing chart of the delay locked loop circuit according to embodiment 2.
  • FIG. 7 shows a structure of a delay locked loop circuit according to embodiment 3.
  • FIG. 8 is a timing chart of the delay locked loop circuit according to embodiment 3.
  • FIG. 9 shows a structure of a delay locked loop circuit according to embodiment 4.
  • FIG. 10 is a timing chart of the delay locked loop circuit according to embodiment 4.
  • FIG. 11 is a variation of a charge pump circuit and loop filter shown in FIG. 9 .
  • FIG. 12 shows a structure of a delay locked loop circuit according to embodiment 5.
  • FIG. 13 is a timing chart of the delay locked loop circuit according to embodiment 5.
  • FIG. 14 shows a structure of a delay element constructed as a differential circuit.
  • FIG. 15 shows a structure of a delay locked loop circuit according to embodiment 6.
  • FIG. 16 shows a structure of a conventional delay locked loop circuit.
  • FIG. 1 shows a structure of a delay locked loop circuit according to embodiment 1 of the present invention.
  • the delay locked loop circuit of embodiment 1 includes a delay element 10 , a signal generation circuit 20 , a charge pump circuit 30 , and a loop filter 40 .
  • the delay element 10 receives reference clock signal CLKr and outputs delayed clock signal CLKd.
  • the delay amount of delayed clock signal CLKd is controlled according to control voltage Vc output from the loop filter 40 .
  • the signal generation circuit 20 outputs a logical product of reference clock signal CLKr and the inverse of delayed clock signal CLKd as signal UP and a logical product of reference clock signal CLKr and delayed clock signal CLKd as signal DN.
  • the charge pump circuit 30 includes a current source 301 , a switch 302 for controlling conduction/interruption of current I 1 supplied by the current source 301 according to signal UP, a current source 303 , and a switch 304 for controlling conduction/interruption of current I 2 supplied by the current source 303 according to signal DN.
  • signal UP is at Hi (high) level
  • the charge pump circuit 30 outputs current I 1 to the outside (push operation).
  • signal DN is at Hi level
  • the charge pump circuit 30 introduces current I 2 from the outside (pull operation).
  • the loop filter 40 includes a capacitance 401 .
  • the loop filter 40 integrates the output of the charge pump circuit 30 to generate control voltage Vc.
  • FIG. 2 shows a structure of the delay element 10 .
  • an inversion circuit 11 logically inverts signal IN input to the delay element 10 to output signal INV.
  • the inversion circuit 11 includes a PMOS transistor 111 and an NMOS transistor 112 which are connected in series, an NMOS transistor 113 which is connected between the transistors 111 and 112 , and an NMOS transistor 114 which is connected in parallel with the NMOS transistor 113 .
  • the gates of transistors 111 and 112 are each supplied with signal IN.
  • Signal INV is output from the connection point of the transistors 111 and 113 .
  • the gate of the NMOS transistor 113 is supplied with control voltage Vc which is output from the loop filter 40 .
  • the gate of the NMOS transistor 114 is supplied with a predetermined voltage.
  • a wave-shaping circuit 12 shapes the waveform of signal INV to generate signal OUT which is output from the delay element 10 .
  • the wave-shaping circuit 12 includes an inverter 121 and an NMOS transistor 122 .
  • the inverter 121 receives signal INV and outputs signal OUT.
  • the drain and gate of the NMOS transistor 122 are connected to the input terminal and output terminal of the inverter 121 , respectively.
  • the source of the NMOS transistor 122 is supplied with a predetermined voltage, e.g., the ground voltage.
  • the transistor 111 which functions as a switch when signal IN is at Lo (low) level, the transistor 111 which functions as a switch is turned on while the transistor 112 which also functions as a switch is turned off. As a result, the subsequent stage of the inversion circuit 11 is supplied with electric charges from the power supply node so that signal INV rises to Hi level.
  • the transistor 111 When signal IN is at Hi level, the transistor 111 is turned off while the transistor 112 is turned on. As a result, the electric charges supplied to the subsequent stage are extracted out to the ground node so that signal INV falls to Lo level.
  • FIG. 3 is a timing chart of the delay element 10 .
  • signal INV When signal IN falls, signal INV immediately transitions from Lo level to Hi level. On the other hand, even when signal IN rises, signal INV does not immediately transitions from Hi level to Lo level but transitions relatively moderately. This is because extraction of the electric charges by the transistors 113 and 114 to the ground node is restricted. Signal INV having such a blunt waveform is shaped by the wave-shaping circuit 12 and output as signal OUT which has sharp rising and falling edges. The wave-shaping circuit 12 also produces the effect of suppressing ringing which would occur in signal INV.
  • FIG. 4 is a timing chart of the delay locked loop circuit according to embodiment 1.
  • Reference clock signal CLKr and delayed clock signal CLKd respectively correspond to signal IN and signal OUT shown in FIG. 3 .
  • Signal UP is at Hi level during a period extending from a rising of reference clock signal CLKr to a rising of delayed clock signal CLKd.
  • Signal DN is at Hi level during a period extending from a rising of delayed clock signal CLKd to a falling of reference clock signal CLKr. That is, within an on-duty period of reference clock signal CLKr, signal UP is at Hi level before the rising of delayed clock signal CLKd, and signal DN is at Hi level after the rising of delayed clock signal CLKd.
  • FIG. 1 shows that is, within an on-duty period of reference clock signal CLKr, signal UP is at Hi level before the rising of delayed clock signal CLKd, and signal DN is at Hi level after the rising of delayed clock signal CLKd.
  • control voltage Vc When reference clock signal CLKr rises, signal UP transitions to Hi level. Accordingly, current I 1 is supplied from the charge pump circuit 30 to the loop filter 40 , and control voltage Vc gradually increases.
  • control voltage Vc When control voltage Vc is relatively low, the delay amount of delayed clock signal CLKd is relatively large. On the contrary, when control voltage Vc is relatively high, the delay amount of delayed clock signal CLKd is relatively small. Therefore, the increase of control voltage Vc results in the decrease of the delay amount of delayed clock signal CLKd.
  • a certain time period is passed after the rising of reference clock signal CLKr, delayed clock signal CLKd rises. As a result, signal DN rises to Hi level, so that current I 2 is introduced from the loop filter 40 to the charge pump circuit 30 . Accordingly, control voltage Vc gradually decreases to the original level.
  • the rising of delayed clock signal CLKd occurs at a time point determined by internally dividing the on-duty period of reference clock signal CLKr in a certain ratio.
  • This ratio is determined according to the relationship between currents I 1 and I 2 . That is, in the delay locked loop circuit of embodiment 1, a feedback system works to attain equilibrium between the amount of charges transferred by the push operation of the charge pump circuit 30 and the amount of charges transferred by the pull operation of the charge pump circuit 30 and becomes stable at the time where the ratio between Hi periods of signal UP and signal DN is equal to the ratio between the reciprocal of current I 1 and the reciprocal of current I 2 .
  • delayed clock signal CLKd can be adjusted so as to rise at a time point which internally divides the on-duty period of reference clock signal CLKr in a desired ratio.
  • the rising of delayed clock signal CLKd occurs just at the midpoint of the on-duty period of reference clock signal CLKr. That is, it is possible to obtain delayed clock signal CLKd which rises at the midpoint of the on-duty period of reference clock signal CLKr irrespective of whether or not the duty ratio of reference clock signal CLKr is 50%.
  • a delayed clock signal which has no static jitters based on its principle and is highly accurate irrespective of the duty ratio of a reference clock signal can be generated.
  • the delay locked loop circuit of embodiment 1 may be constructed to operate based on the logic opposite to that described above.
  • FIG. 5 shows a structure of a delay locked loop circuit according to embodiment 2 of the present invention.
  • the delay locked loop circuit of embodiment 2 includes a signal generation circuit 20 whose structure is different from that of the signal generation circuit 20 of embodiment 1.
  • the signal generation circuit 20 of embodiment 2 outputs a logical product of reference clock signal CLKr and the inverse of delayed clock signal CLKd as signal UP and reference clock signal CLKr as signal DN.
  • the delay locked loop circuit of embodiment 2 is described only as to the differences from the delay locked loop circuit of embodiment 1.
  • FIG. 6 is a timing chart of the delay locked loop circuit according to embodiment 2.
  • Signal UP is at Hi level during a period extending from a rising of reference clock signal CLKr to a rising of delayed clock signal CLKd.
  • Signal DN is the same as reference clock signal CLKr.
  • the magnitude of an electric current flowing from the charge pump circuit 30 to the outside push current
  • the magnitude of an electric current flowing from the outside to the charge pump circuit 30 pulse current
  • the structure of the signal generation circuit 20 is simpler than that of the signal generation circuit 20 of embodiment 1.
  • the circuit scale of the entire delay locked loop circuit is decreased.
  • FIG. 7 shows a structure of a delay locked loop circuit according to embodiment 3 of the present invention.
  • the delay locked loop circuit of embodiment 3 includes a charge pump circuit 30 whose structure is different from that of the charge pump circuit 30 of embodiment 2.
  • the charge pump circuit 30 of embodiment 3 includes a current source 305 , a switch 306 for controlling conduction/interruption of electric current I 3 supplied by the current source 305 according to signal UP, a current source 307 , and a switch 308 for controlling conduction/interruption of electric current I 4 supplied by the current source 307 according to signal DN in addition to the components of the charge pump circuit 30 of embodiment 2.
  • the delay locked loop circuit of embodiment 3 is described only as to the differences from the delay locked loop circuit of embodiment 2.
  • FIG. 8 is a timing chart of the delay locked loop circuit according to embodiment 3.
  • the magnitude of an electric current flowing from the charge pump circuit 30 to the outside push current
  • the magnitude of an electric current flowing from the outside to the charge pump circuit 30 pulse current
  • delayed clock signal CLKd can be adjusted so as to rise at a time point which internally divides the on-duty period of reference clock signal CLKr in a desired ratio.
  • currents I 2 , I 3 and I 4 are equal in magnitude and the magnitude of current I 1 is three times the magnitude of current I 2 , I 3 or I 4
  • the magnitude of a current which is supplied to the loop filter 40 when the switches 302 and 304 of the charge pump circuit 30 are closed is equal to the magnitude of a current which is introduced from the loop filter 40 when the switches 304 and 306 of the charge pump circuit 30 are closed.
  • the rising of delayed clock signal CLKd occurs just at the midpoint of the on-duty period of reference clock signal CLKr.
  • the structure of the signal generation circuit 20 is simpler than that of the signal generation circuit 20 of embodiment 1.
  • the circuit scale of the entire delay locked loop circuit is decreased.
  • FIG. 9 shows a structure of a delay locked loop circuit according to embodiment 4 of the present invention.
  • the delay locked loop circuit of embodiment 4 includes a charge pump circuit 30 whose structure is different from those of the charge pump circuit 30 of embodiment 2 and the charge pump circuit 30 of embodiment 3.
  • the charge pump circuit 30 of embodiment 4 includes a current source 309 for supplying electric current I 5 whose polarity is the same as that of the current supplied by the current source 301 in addition to the components of the charge pump circuit 30 of embodiment 3. That is, in the charge pump circuit 30 of embodiment 4, current I 5 is always supplied from the current source 309 irrespective of the state of signals UP and DN.
  • the delay locked loop circuit of embodiment 4 is described only as to the differences from the delay locked loop circuit of embodiment 3.
  • FIG. 10 is a timing chart of the delay locked loop circuit according to embodiment 4.
  • the magnitude of an electric current flowing from the charge pump circuit 30 to the outside push current
  • the magnitude of an electric current flowing from the outside to the charge pump circuit 30 pulse current
  • delayed clock signal CLKd can be adjusted so as to rise at a time point which internally divides the on-duty period of reference clock signal CLKr in a desired ratio.
  • the structure of the signal generation circuit 20 is simpler than that of the signal generation circuit 20 of embodiment 1.
  • the circuit scale of the entire delay locked loop circuit is decreased.
  • the charge pump circuit 30 includes a resistance 311 (resistance value R1) which receives the inverse of signal UP (hereinafter, “signal /UP”), a resistance 312 (resistance value R2) which receives signal DN, and a resistance 313 (resistance value R3).
  • One end of the resistance 313 is connected to a connection point of the resistances 311 and 312 , and the other end of the resistance 313 is supplied with ground voltage Vss.
  • the loop filter 40 includes a capacitance 401 and an operational amplifier 402 .
  • the negative feedback portion of the operational amplifier 402 is connected to the capacitance 401 .
  • the inversion input terminal of the operational amplifier 402 is connected to a connection point of the resistances 311 , 312 and 313 of the charge pump circuit 30 .
  • the non-inverted input terminal of the operational amplifier 402 is supplied with voltage Va.
  • a current which has a magnitude of Vdd/2/R flows from the connection point of the resistances 311 , 312 , and 313 to the ground node.
  • current Vdd/R flows from the output side of the operational amplifier 402 to the connection point of the resistances 311 , 312 , and 313 via the capacitance 401 .
  • control voltage Vc gradually increases.
  • the delay locked loop circuit including the charge pump circuit 30 and the loop filter 40 which are shown in FIG. 11 operates in the same way as does the delay locked loop circuit of embodiment 4 shown in FIG. 9 . Since switches are not used in the variation shown in FIG. 11 , deterioration in current accuracy which would occur due to switching noise does not occur. Further, the delay locked loop circuit of this variation operates with a lower voltage as compared with the delay locked loop circuit shown in FIG. 9 .
  • FIG. 12 shows a structure of a delay locked loop circuit according to embodiment 5.
  • the delay locked loop circuit of embodiment 5 includes a combination of any two of the delay locked loop circuits of embodiments 1 to 4.
  • the first delay locked loop circuit includes a delay element 10 r , a signal generation circuit 20 r , a charge pump circuit 30 r and a loop filter 40 r .
  • the second delay locked loop circuit includes a delay element 10 f , a signal generation circuit 20 f , a charge pump circuit 30 f and a loop filter 40 f .
  • the first and second delay locked loop circuits output delayed clock signals CLKdr and CLKdf, respectively.
  • the logic level of each of delayed clock signals CLKdr and CLKdf changes after some delay from rising and falling of reference clock signal CLKr.
  • the specific structures of the first and second delay locked loop circuits are the same as those described in embodiments 1 to 4.
  • the delay locked loop circuit of embodiment 5 further includes a clock generation circuit 50 . Hereinafter, only the distinctive features of embodiment 5 will be described.
  • the clock generation circuit 50 generates delayed clock signal CLKd from delayed clock signals CLKdr and CLKdf.
  • FIG. 13 is a timing chart of the delay locked loop circuit of embodiment 5. There are various methods for generating delayed clock signal CLKd. For example, as shown in FIG. 13 , delayed clock signal CLKd rises at the rising of delayed clock signal CLKdr and falls at the rising of delayed clock signal CLKdf.
  • delayed clock signal CLKd rises just at the midpoint of the on-duty period of reference clock signal CLKr and falls just at the midpoint of the off-duty period of reference clock signal CLKr.
  • the on-duty period of delayed clock signal CLKd is just a half of a cycle of reference clock signal CLKr (T/2).
  • the duty ratio of delayed clock signal CLKd is 50% irrespective of the duty ratio of reference clock signal CLKr.
  • the logic level of delayed clock signal CLKd changes with a delay of 1 ⁇ 4 phase (90°) and a delay of 3 ⁇ 4 phase (270°) from reference clock signal CLKr. Further, the duty ratio of reference clock signal CLKr is corrected.
  • the delay element 10 r and the delay element 10 f are more robust against noise.
  • the delay element 10 r and the delay element 10 f each can be formed by the differential circuit shown in FIG. 14 .
  • a delay element 10 A shown in FIG. 14 includes inversion circuits 11 a and 11 b , each of which is the same as the inversion circuit 11 shown in FIG. 2 , and a wave-shaping circuit 12 A which has a differential amplifier.
  • the inversion circuits 11 a and 11 b receive signals IN + and IN ⁇ , respectively, as differential input signals.
  • the wave-shaping circuit 12 A shapes the waveform of signals output from the inversion circuits 11 a and 11 b to output signals OUT + and OUT ⁇ .
  • reference clock signal CLKr is input as signal IN + and the inverse of reference clock signal CLKr is input as signal IN ⁇
  • signals OUT + and OUT ⁇ correspond to delayed clock signals CLKdr and CLKdf, respectively.
  • the delay element is thus formed by the differential circuit, inphase noise generated in the power supply, or the like, is canceled. As a result, a delayed clock signal can be generated with higher accuracy.
  • FIG. 15 shows a structure of a delay locked loop circuit according to embodiment 6.
  • the delay locked loop circuit of embodiment 6 is substantially the same as that of the delay locked loop circuit of embodiment 5 except that reference clock signal CLKr and the inverse thereof (hereinafter, referred to as “reference clock signal /CLKr”), which are in an antiphase relationship, are supplied to the first and second delay locked loop circuits of the delay locked loop circuit of embodiment 5.
  • reference clock signal /CLKr reference clock signal
  • the first and second delay locked loop circuits output delayed clock signals CLKdr and CLKdf, respectively.
  • the logic levels of delayed clock signals CLKdr and CLKdf change after some delay from the rising (or falling) of reference clock signals CLKr and /CLKr, respectively. That is, the second delay locked loop circuit outputs delayed clock signal CLKdf whose logic level substantially changes with some delay from the rising (or falling) of reference clock signal CLKr.
  • Delayed clock signal CLKd generated by the clock generation circuit 50 is the same as that of embodiment 5.
  • the first and second delay locked loop circuits can have the same polarity and therefore can be realized by delay locked loop circuits of the same type.
  • the circuit design can more readily be achieved.
  • new delayed clock signal CLKd is generated from delayed clock signals CLKdr and CLKdf which are generated by the delay elements 10 r and 10 f , respectively, but the present invention is not limited thereto.
  • Delayed clock signal CLKd may be generated from signals other than delayed clock signals CLKdr and CLKdf.
  • delayed clock signal CLKd may be generated from signals which are generated based on delayed clock signals CLKdr and CLKdf and whose logic levels change with the delay of a predetermined phase from the rising (or falling) of reference clock signals CLKr and /CLKr, for example, signal UP and signal DN which are generated by the signal generation circuits 20 r and 20 f , respectively.
  • the output clock signal of the delay locked loop circuits of embodiments 1 to 4 is not limited to delayed clock signal CLKd generated by the delay element 10 .
  • the output clock signal may be signal UP generated by the signal generation circuit 20 or, in the case of embodiment 1, may be signal DN generated by the signal generation circuit 20 . Since signal UP is a result of the waveform shaping of delayed clock signal CLKd, it is rather preferable that signal UP is output from the delay locked loop circuit.
  • control voltage Vc increases (or decreases) during an on-duty (or off-duty) period of reference clock signal CLKr and then returns to the original level.
  • This change of control voltage Vc can be realized based on signals UP and DN which complementarily change according to the rising and falling of reference clock signal CLKr and the rising of delayed clock signal CLKd (or the falling of delayed clock signal CLKd if delayed clock signal CLKd falls with some delay from any one of the rising and falling of reference clock signal CLKr). Therefore, various circuit structures which are different from the signal generation circuits 20 and charge pump circuits 30 described in the above embodiments can be realized.
  • the structures of the signal generation circuit 20 and charge pump circuit 30 may be modified such that, in the timing chart of FIG. 6 , signal UP transitions to logic level Hi during an interval extending from the rising of delayed clock signal CLKd to the falling of reference clock signal CLKr.
  • signal UP transitions to logic level Hi during an interval extending from the rising of delayed clock signal CLKd to the falling of reference clock signal CLKr.
  • the effects achieved by the present invention remain the same.

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JP2006254401A (ja) 2006-09-21
JP4549958B2 (ja) 2010-09-22

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