JP4549958B2 - 遅延ロックドループ回路 - Google Patents

遅延ロックドループ回路 Download PDF

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Publication number
JP4549958B2
JP4549958B2 JP2005264131A JP2005264131A JP4549958B2 JP 4549958 B2 JP4549958 B2 JP 4549958B2 JP 2005264131 A JP2005264131 A JP 2005264131A JP 2005264131 A JP2005264131 A JP 2005264131A JP 4549958 B2 JP4549958 B2 JP 4549958B2
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JP
Japan
Prior art keywords
clock signal
change
logic level
signal
reference clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005264131A
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English (en)
Japanese (ja)
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JP2006254401A5 (enExample
JP2006254401A (ja
Inventor
史朗 崎山
志郎 道正
祐介 徳永
徹 岩田
貴士 平田
康之 土居
英喜 吉井
慎 服部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2005264131A priority Critical patent/JP4549958B2/ja
Priority to US11/289,753 priority patent/US20060176091A1/en
Publication of JP2006254401A publication Critical patent/JP2006254401A/ja
Priority to US12/033,707 priority patent/US7705645B2/en
Publication of JP2006254401A5 publication Critical patent/JP2006254401A5/ja
Application granted granted Critical
Publication of JP4549958B2 publication Critical patent/JP4549958B2/ja
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)
JP2005264131A 2005-02-09 2005-09-12 遅延ロックドループ回路 Expired - Fee Related JP4549958B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2005264131A JP4549958B2 (ja) 2005-02-09 2005-09-12 遅延ロックドループ回路
US11/289,753 US20060176091A1 (en) 2005-02-09 2005-11-30 Delay locked loop circuit
US12/033,707 US7705645B2 (en) 2005-02-09 2008-02-19 Delay locked loop circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005033625 2005-02-09
JP2005264131A JP4549958B2 (ja) 2005-02-09 2005-09-12 遅延ロックドループ回路

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2010108178A Division JP4815005B2 (ja) 2005-02-09 2010-05-10 遅延ロックドループ回路

Publications (3)

Publication Number Publication Date
JP2006254401A JP2006254401A (ja) 2006-09-21
JP2006254401A5 JP2006254401A5 (enExample) 2008-04-10
JP4549958B2 true JP4549958B2 (ja) 2010-09-22

Family

ID=36779333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005264131A Expired - Fee Related JP4549958B2 (ja) 2005-02-09 2005-09-12 遅延ロックドループ回路

Country Status (2)

Country Link
US (2) US20060176091A1 (enExample)
JP (1) JP4549958B2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7475310B2 (en) * 2006-08-09 2009-01-06 Advantest Corporation Signal output circuit, and test apparatus
US7459949B2 (en) * 2007-01-30 2008-12-02 Mosaid Technologies Incorporated Phase detector circuit and method therefor
JP5389524B2 (ja) * 2009-05-14 2014-01-15 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 遅延回路
US8076963B2 (en) * 2009-09-15 2011-12-13 Qualcomm Incorporated Delay-locked loop having a delay independent of input signal duty cycle variation
US8970260B1 (en) * 2013-11-21 2015-03-03 Nxp B.V. Output drivers
KR102005337B1 (ko) * 2014-01-09 2019-07-30 에스케이하이닉스 주식회사 전압 변환 장치
CN106600853B (zh) * 2016-12-06 2019-06-18 青岛海信智能商用系统股份有限公司 用于充电底座的充电或信号传输防抖动电路及充电底座
JP7724679B2 (ja) * 2021-10-28 2025-08-18 旭化成エレクトロニクス株式会社 遅延パルス生成回路

Family Cites Families (26)

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Publication number Priority date Publication date Assignee Title
JPS5257760A (en) * 1975-11-07 1977-05-12 Hitachi Ltd Phase lock loop circuit
JPS6036908Y2 (ja) * 1977-11-30 1985-11-01 三洋電機株式会社 自動位相制御方式の位相比較器
JPS5619769A (en) 1979-07-26 1981-02-24 Ricoh Co Ltd Ink-jet recording device
NL8302228A (nl) 1983-06-22 1985-01-16 Optische Ind De Oude Delft Nv Meetstelsel voor het onder gebruikmaking van een op driehoeksmeting berustend principe, contactloos meten van een door een oppervlakcontour van een objectvlak gegeven afstand tot een referentieniveau.
JPH07109212B2 (ja) 1986-09-16 1995-11-22 株式会社ブリヂストン 防振ゴムの取付ボルト用キヤツプ
JPS6372937U (enExample) * 1986-10-31 1988-05-16
US5675620A (en) * 1994-10-26 1997-10-07 At&T Global Information Solutions Company High-frequency phase locked loop circuit
JPH08180678A (ja) * 1994-12-27 1996-07-12 Hitachi Ltd ダイナミック型ｒａｍ
KR100245077B1 (ko) * 1997-04-25 2000-02-15 김영환 반도체 메모리 소자의 딜레이 루프 럭크 회로
JPH118552A (ja) * 1997-06-18 1999-01-12 Nec Eng Ltd 位相同期発振器
JP2908398B1 (ja) * 1998-01-14 1999-06-21 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路および発振器の遅延素子
US5969552A (en) * 1998-01-15 1999-10-19 Silicon Image, Inc. Dual loop delay-locked loop
KR100301043B1 (ko) * 1998-08-08 2001-09-06 윤종용 지연동기루프의위상비교기및지연동기방법
US6100735A (en) * 1998-11-19 2000-08-08 Centillium Communications, Inc. Segmented dual delay-locked loop for precise variable-phase clock generation
US6204705B1 (en) * 1999-05-28 2001-03-20 Kendin Communications, Inc. Delay locked loop for sub-micron single-poly digital CMOS processes
KR100366618B1 (ko) * 2000-03-31 2003-01-09 삼성전자 주식회사 클럭 신호의 듀티 사이클을 보정하는 지연 동기 루프 회로및 지연 동기 방법
JP3807593B2 (ja) * 2000-07-24 2006-08-09 株式会社ルネサステクノロジ クロック生成回路および制御方法並びに半導体記憶装置
US6868504B1 (en) * 2000-08-31 2005-03-15 Micron Technology, Inc. Interleaved delay line for phase locked and delay locked loops
JP2002158582A (ja) * 2000-11-20 2002-05-31 Mitsubishi Electric Corp Ｐｌｌ回路
US8934597B2 (en) * 2003-03-12 2015-01-13 Infineon Technologies Ag Multiple delay locked loop integration system and method
US7091763B1 (en) * 2003-11-03 2006-08-15 Lattice Semiconductor Corporation Clock generation
US7528638B2 (en) * 2003-12-22 2009-05-05 Micron Technology, Inc. Clock signal distribution with reduced parasitic loading effects
US7499513B1 (en) * 2004-12-23 2009-03-03 Xilinx, Inc. Method and apparatus for providing frequency synthesis and phase alignment in an integrated circuit
KR100644127B1 (ko) * 2005-01-03 2006-11-10 학교법인 포항공과대학교 무한의 위상 이동 기능을 가지는 전압 제어 지연 라인을기반으로 하는 듀얼 루프 디엘엘
US7199625B1 (en) * 2005-09-20 2007-04-03 Infineon Technologies Ag Delay locked loop structure providing first and second locked clock signals
US7405604B2 (en) * 2006-04-20 2008-07-29 Realtek Semiconductor Corp. Variable delay clock circuit and method thereof

Also Published As

Publication number Publication date
US7705645B2 (en) 2010-04-27
US20080303567A1 (en) 2008-12-11
JP2006254401A (ja) 2006-09-21
US20060176091A1 (en) 2006-08-10

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