US20040263437A1 - Current drive circuit and drive method thereof, and electroluminescent display apparatus using the circuit - Google Patents

Current drive circuit and drive method thereof, and electroluminescent display apparatus using the circuit Download PDF

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Publication number
US20040263437A1
US20040263437A1 US10/801,172 US80117204A US2004263437A1 US 20040263437 A1 US20040263437 A1 US 20040263437A1 US 80117204 A US80117204 A US 80117204A US 2004263437 A1 US2004263437 A1 US 2004263437A1
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United States
Prior art keywords
current
drive
circuit
voltage component
currents
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Abandoned
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US10/801,172
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English (en)
Inventor
Reiji Hattori
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Assigned to CASIO COMPUTER CO., LTD., HATTORI, REIJI reassignment CASIO COMPUTER CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HATTORI, REIJI
Publication of US20040263437A1 publication Critical patent/US20040263437A1/en
Priority to US11/854,341 priority Critical patent/US8094095B2/en
Abandoned legal-status Critical Current

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3283—Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
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    • G11C27/02—Sample-and-hold arrangements
    • G11C27/024—Sample-and-hold arrangements using a capacitive memory element
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    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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Definitions

  • the present invention relates to a current drive apparatus, a drive method of the current drive apparatus, and a display apparatus using the current drive apparatus, and more particularly to a current drive apparatus including a structure to operate a plurality of loads by applying a predetermined current thereto, a drive method thereof, and a display apparatus which displays desired image information in a display panel by using the current drive apparatus.
  • a light emitting element type display including a display panel in which a plurality of organic electroluminescence elements (which will be referred to as “organic EL elements” hereinafter), inorganic electroluminescence elements (which will be referred to as “inorganic EL elements” hereinafter), or self-luminous type light emitting elements (optical elements) such as light emitting diodes are arranged in a matrix form.
  • organic EL elements organic electroluminescence elements
  • inorganic electroluminescence elements which will be referred to as “inorganic EL elements” hereinafter
  • self-luminous type light emitting elements such as light emitting diodes
  • Such a display generally includes a display panel in which display pixels including light emitting elements are arranged in the vicinity of respective intersects of scanning lines arranged in a row direction and data lines arranged in a column direction, a data driver which generates a predetermined drive current according to display data and supplies it to each display element through the data lines, and a scanning driver which causes display pixels in a predetermined row to enter a selection state by applying a scanning signal with a predetermined timing.
  • a display panel in which display pixels including light emitting elements are arranged in the vicinity of respective intersects of scanning lines arranged in a row direction and data lines arranged in a column direction
  • a data driver which generates a predetermined drive current according to display data and supplies it to each display element through the data lines
  • a scanning driver which causes display pixels in a predetermined row to enter a selection state by applying a scanning signal with a predetermined timing.
  • a current specification type drive mode which sequentially repeats in accordance with each row for one screen the operation which generates drive currents having individual current values according to the display data with respect to a plurality of display pixels, simultaneously supplies the currents to the display pixels in a specific row and causes the light emitting element of each display pixel to emits the light with a predetermined brightness gradation
  • PWM pulse width modulation
  • the drive currents having predetermined current values or a fixed current value according to the display data must be supplied to a plurality of the display pixels in each row at the same time or within the same display period.
  • a display having applied thereto a circuit configuration which includes a plurality of driver chips (semiconductor chips) each having a predetermined number of output terminals as the above-described data drivers, individually generates the drive currents in the respective driver chips and supplies the drive currents to the respective light emitting elements through a data line at the same time.
  • the display to which the above-described data driver including a plurality of the driver chips is applied has the following problems.
  • the conventional data driver having a plurality of the driver chips includes a circuit used to individually generate a drive current in accordance with each driver chip and has a structure to simultaneously supply the drive currents to the respective light emitting elements from the respective driver chips through respective output terminals. Therefore, when irregularities are generated in current values of the drive currents outputted from a plurality of the driver chips, irregularities occur in the light emitting state in each display pixel (brightness gradation of the light emitting element), and the display heterogeneity is produced. Thus, irregularities in the drive currents must be suppressed as much as possible between the respective driver chips and between the respective output terminals.
  • the data driver since there is a limit in the number of output terminals which can be set in one semi-conductor chip due to a problem of an increase in signal delay owing to an increase in wiring length or to a reduction in production yield with an increase in the number of elements in one chip, the data driver must be necessarily configured by using a plurality of the driver chips. If the semiconductor chips are different from each other, irregularities in the drive currents between the output terminals further become large, and it is very difficult to suppress irregularities in the drive currents in the same driver chip while suppressing the same between the driver chips.
  • the light emitting element type display which has been currently developed has a problem that it has not reached establishment of a technique to generate an analog output signal which can realize the sufficient gradation display when generating a drive current having an analog signal component from a digital input signal which becomes display data by digital-to-analog conversion.
  • a current drive apparatus has an advantage to suppress irregularities in currents between output terminals of a current drive apparatus which operates by applying currents to a plurality of loads, and also suppress irregularities between chips when the current drive apparatus constructed by a plurality of driver chips. Further, it has an advantage to obtain the excellent display characteristic with display irregularities being suppressed in a display apparatus including the current drive apparatus.
  • a current drive apparatus which operates a plurality of loads by applying currents thereto, comprising: a plurality of output terminals to which the loads are connected, respectively; a single current generation circuit which outputs an operating current having a predetermined current value; and a plurality of current storage circuits which are provided in accordance with each of the output terminals, sequentially fetch and hold the operating current and simultaneously output drive currents based on the operating current to the respective output terminals.
  • the operating current has a current value according to an input signal
  • the current storage circuit includes a voltage component holding portion which fetches the operating current outputted from the current generation circuit and holds a voltage component corresponding to a current value of the operating current
  • the voltage component holding portion has a capacitance element in which an electric charge corresponding to the operating current is written.
  • Each of the current storage circuits preferably includes a pair of current storage sections which are arranged in parallel and in which an operation to fetch and hold the operating current and an operation to output the drive current based on the held operating current are alternately carried out in parallel, or includes current storage sections on front and rear stages which are arranged in series and in which an operation to fetch and hold the operating current and supply the held current to the current storage section on the rear stage and an operation to fetch and hold the supplied current and output the drive current based on the held current are carried out in parallel.
  • the current drive apparatus may include a signal input current storage circuit between the current generation circuit and a plurality of the current storage circuits, which fetches and holds the operating current and supplies a current based on the held operating current to a plurality of the current storage circuits so that the drive currents have the same current value at the respective output terminals, and include a pulse width control circuit which controls a pulse width of each of the drive current in accordance with an input signal.
  • At least a plurality of the current storage circuits and the output terminals in the current drive apparatus are formed on at least one semiconductor chip, and the current generation circuit is formed on a semiconductor chip different from the former semiconductor chip or formed in the former semiconductor chip.
  • a current drive apparatus which operates a plurality of loads by applying currents thereto, comprising: a plurality of output terminals to which the load are connected, respectively; a single reference current generation circuit which generates and outputs a plurality of reference currents having current values different from each other; at least one reference current storage circuit which fetches and holds each of the plurality of reference currents and outputs a plurality of gradation reference currents based on the respective reference currents; a plurality of current generation circuits which select any of the respective gradation reference currents and generate a gradation current in accordance with an input signal; and a plurality of current storage circuits which sequentially fetch and hold the respective gradation currents and simultaneously output drive currents based on the gradation currents to the respective output terminals.
  • the reference current generation circuit can include a plurality of reference current generation sections which generate and output the respective reference currents and are arranged in parallel, the input signal is a digital signal having a plurality of bits, and a current value of the reference current outputted from each of the reference current generation sections can have a weight corresponding to each bit of the digital signal.
  • the reference current storage circuit preferably includes a plurality of reference current storage sections which individually fetch the respective reference currents outputted from the reference current generation circuit, hold voltage components corresponding to the respective reference currents and output the gradation reference currents based on the respective voltage components, and each of the current generation circuits selects any of the gradation reference currents outputted from the respective reference current storage sections based on a bit value of the input signal, adds the selected gradation reference current and generates the gradation current.
  • the current storage circuit can include a voltage component holding portion which fetches the gradation current outputted from the current generation circuit and holds a voltage component corresponding to a current value of the gradation current, and the voltage component holding portion has a capacitance element in which the an electric charge corresponding to the gradation current is written as the voltage component.
  • a display apparatus which supplies a drive current corresponding to a display signal to each display pixel of a display panel including a plurality of display pixels, comprising: a display panel which includes a plurality of display pixels having optical elements which are arranged in the vicinity of intersections of a plurality of scanning lines arranged in a line direction and a plurality of signal lines arranged in a row direction; a signal drive circuit including any of a structure of the first current drive apparatus which includes a single current generation circuit which generates and outputs an operating current having a current value based on the display signal, and a plurality of current storage circuits which are provided in accordance with the respective signal lines, sequentially fetch the operating current outputted from the current generation circuit and simultaneously output a drive current based on the operating current to a plurality of the signal lines, or a structure of the second current drive apparatus which includes a single reference current generation circuit which generates and outputs a plurality of reference currents having current values different
  • FIG. 1 is a primary structural view showing a first embodiment of a current drive apparatus according to the present invention
  • FIG. 2 is a circuit structural view showing a concrete example of a current generation circuit applicable to the embodiment
  • FIG. 3 is a circuit structural view showing a concrete example of a structure consisting of a current storage circuit and a switch circuit applicable to the embodiment;
  • FIGS. 4A and 4B are conceptual views showing a basic operation in the current storage circuit applicable to the embodiment
  • FIG. 5A is a view of an equivalent circuit showing a structure when an electric charge is accumulated in a capacitance between a gate and a source of a transistor;
  • FIG. 5B is a graph showing an aged change in voltage of the capacitance when the electric charge is accumulated in the capacitance between the gate and the source of the transistor;
  • FIG. 6 is a primary structural view showing a second embodiment of a current drive apparatus according to the present invention.
  • FIG. 7 is a primary structural view showing a third embodiment of a current drive apparatus according to the present invention.
  • FIG. 8 is a primary structural view showing a fourth embodiment of a current drive apparatus according to the present invention.
  • FIG. 9 is a primary structural view showing a fifth embodiment of a current drive apparatus according to the present invention.
  • FIG. 10 is a primary structural view showing a sixth embodiment of a current drive apparatus according to the present invention.
  • FIG. 11 is a primary structural view showing a seventh embodiment of a current drive apparatus according to the present invention.
  • FIG. 12 is a primary structural view showing an eighth embodiment of a current drive apparatus according to the present invention.
  • FIG. 13 is a primary structural view showing a ninth embodiment of a current drive apparatus according to the present invention.
  • FIG. 14 is a schematic structural view showing an example of an entire structure of a display apparatus according to the present invention.
  • FIG. 15 is a block diagram showing a primary structure of a data driver, a scanning driver and a display panel applied to the display apparatus according to the embodiment;
  • FIG. 16 is a schematic structural view showing another example of a scanning driver applied to the display apparatus according to the present invention.
  • FIG. 17 is a circuit configuration view showing an example of a basic structure of a pixel drive circuit applicable to the display apparatus according to the present invention.
  • FIGS. 18A and 18B are conceptual views respectively showing a basic operation in the pixel drive circuit applicable to the embodiment.
  • FIG. 19 is a timing chart showing a display timing of image information in the display apparatus according to the embodiment.
  • FIG. 20 is a schematic block diagram showing a primary structure of still another example of the display apparatus according to the present invention.
  • a current drive apparatus, a drive method thereof, and a display apparatus to which the current drive apparatus is applied according to the present invention will now be described based on illustrated embodiments.
  • FIG. 1 is a primary structural view showing a first embodiment of a current drive apparatus according to the present invention.
  • the current drive apparatus has a structure to sequentially hold a current with a predetermined current value supplied from a single current generation circuit in a current storage circuit provided in accordance with each output terminal and thereafter simultaneously output the currents to loads (display elements) through each of the output terminals.
  • the current drive apparatus comprises: a single current generation circuit 10 A which generates and outputs an operating current Ic having a predetermined current value used to control a drive stage of each load LD (display element) connected to each of a plurality of output terminals Tout; a shift register 20 A which sets a timing when supplying the operating current Ic supplied from the current generation circuit 10 A to each of later-described current storage circuits 30 A; a plurality of current storage circuits 30 A which are provided in accordance with output terminals Tout, sequentially fetch and hold (store) the operating current Ic supplied from the current generation circuit 10 A with a predetermined timing based on the shift register 20 A; and a plurality of switch circuits 40 A which control a supply state of the operating current Ic from the current generation circuit 10 A to each of the current storage circuits 30 A based on a timing set by a switch changeover signal (shift output) SR outputted from the shift register 20 A with a predetermined timing.
  • a single current generation circuit 10 A which generates and outputs
  • loads LD display elements
  • the loads LD are illustrated in a case that they are applied in a simple matrix type display panel, they are not restricted thereto, and they can be applied to an active matrix type display panel including such a pixel drive circuit as shown in FIG. 17.
  • FIG. 2 is a circuit structural view showing a concrete example of the current generation circuit applicable to this embodiment.
  • the current generation circuit 10 A substantially generates each operating current Ic having a current value required to drive each of a plurality of the loads in a predetermined drive state, and outputs it to individual current storage circuits 30 A provided so as to correspond to each of a plurality of the loads.
  • the current generation circuit 10 A is constituted by, e.g., a control current generation circuit 11 on a front stage and an output current generation circuit 12 on a rear stage, as shown in FIG. 2.
  • the operating currents Ic generated by the current generation circuit 10 A may have current values different from each other in accordance with a drive stage of each load, or may have the same current value with respect to all the loads. The detail will be described later.
  • the current generation circuit illustrated in this embodiment is just an example applicable to the current drive apparatus according to the present invention, and it is not restricted to this circuit configuration.
  • the current generation circuit a structure comprising the control current generation circuit 11 and the current mirror circuit portion 12 is illustrated, but it is not restricted thereto.
  • it may have a circuit configuration consisting of only the control current generation circuit.
  • CT 1 having a circuit configuration comprising: a resistance R 11 having one end side connected to a high-potential power supply Vdd; a pnp type bipolar transistor (which will be referred to as a “pnp transistor” hereinafter) Q 11 having an emitter connected to the other end side of the resistance R 11 and a collector connected to an output junction N 11 of the control current generation circuit 11 connected to the output current generation circuit 12 on the rear stage; and a P-channel field effect type transistor (which will be referred to as a “PMOS transistor” hereinafter) M 11 having a source connected to a base of the pnp transistor Q 11 , a drain connected to a set terminal Tset to which a set signal SET is inputted and a gate connected to an input terminal Tin to which a digital input signal IN 1 is inputted.
  • a PMOS transistor P-channel field effect type transistor
  • the unit circuits are connected in parallel for the number of bits of the digital input signals (in this embodiment, description will be given as to a case that unit circuits CT 1 to CT 6 corresponding to digital input signals IN 1 to IN 6 of six bits are provided). That is, emitters of the pnp transistors Q 11 to Q 16 of the respective unit circuits CT 1 to CT 6 are connected to the output junction N 11 in common, and there are provided the PMOS transistors M 11 to M 16 having sources connected to the bases of the pnp transistors Q 11 to Q 16 , drains connected to the set terminal Tset and gates connected to input terminals Tin to which the digital input signals IN 1 to IN 6 are inputted.
  • the input signals IN 1 to IN 6 are digital signals (voltage components) consisting of a plurality of bits used to control a drive state of each load
  • the set signal SET is a signal voltage which is supplied from a non-illustrated control portion with a timing according to a drive cycle and the like of the loads.
  • Such a control current generation circuit 11 generates control currents having current values corresponding to current values of the input signals IN 1 to IN 6 by setting the set signal SET to a predetermined voltage level and setting the input signals IN 1 to IN 6 having the respective bits to a high level or a low level, and outputs the control currents to the output current generation circuit 12 on the rear stage through the output junction N 11 .
  • the output current generation circuit 12 is constituted by a current mirror circuit, and comprises: an npn type bipolar transistor (which will be referred to as an “npn transistor” hereinafter) Q 21 having a collector and a base connected to the output junction N 11 of the control current generation circuit 11 ; a resistance R 21 connected between an emitter of the npn transistor Q 21 and a low-potential power supply Vss; an npn transistor Q 22 having a collector connected to an output terminal Tcs where an output current (operating current) Ic having a predetermined current component is outputted and a base connected to the output junction N 11 of the control current generation circuit 11 ; and a resistance R 22 connected between an emitter of the npn transistor Q 22 and the low-potential power supply Vss.
  • an npn type bipolar transistor which will be referred to as an “npn transistor” hereinafter
  • Q 21 having a collector and a base connected to the output junction N 11 of the control current generation circuit 11
  • the output current Ic is generated by the control current generation circuit 11 , and has a current value according to a predetermined current ratio stipulated by the current mirror circuit structure with respect to a current value of the control current inputted through the output junction N 11 .
  • the current component flows down so as to be pulled in a direction of the current generation circuit 10 A from the current storage circuit 30 A side.
  • the current value of the control current generated by the control current generation circuit 11 is set larger than the current value of the output current generated by the current mirror circuit portion 12 .
  • the current value of the control value is reduced by the current mirror circuit portion 12 with a predetermined ratio in order to stipulate the current value of the output current (that is, the current value processed in the control signal generation circuit 11 is set larger than the current value of the output current Ic). Therefore, it is possible to improve a processing speed concerning conversion and generation to the output current Ic from the input signals IN 1 to 1 N 6 in the control signal generation circuit 11 of the current generation circuit 10 A.
  • the shift register 20 a shown in FIG. 1 sequentially applies a shift output generated based on control signals (a shift start signal, a shift clock signal and others) supplied from a non-illustrated control portion while sequentially shifting in one direction to each of the switch circuits 40 A provided in accordance with the respective loads as a switch changeover signal (switch-on signal) SR.
  • control signals a shift start signal, a shift clock signal and others
  • the switch circuits 40 A shown in FIG. 1 perform the on operation with different timings based on the switch changeover signals SR sequentially supplied from the shift register 20 A, set the output current (operating current) Ic from the current generation circuit 10 A in the write state to supply it to the current storage circuits 30 A provided in accordance with the respective loads, and control in such a manner that the output current Ic can be fetched and held in each current storage circuit 30 A.
  • the switch circuit 40 A for example, a field effective type transistor can be applied.
  • the switch circuits 40 A can be formed on the same substrate by using the same manufacturing process as that of the circuit element applied to the later-described current storage circuits 30 A. The detail will be described with reference to FIG. 3.
  • FIG. 3 is a circuit configuration view showing a concrete example of a structure of a current storage circuit and a switch circuit applicable to this embodiment
  • FIGS. 4A and 4B are conceptual views showing a basic operation in the current storage circuit applicable to this embodiment.
  • the current storage circuit 30 A substantially sequentially fetches the operating current Ic outputted from the current generation circuit 10 A with a predetermined timing based on the shift register 20 A, holds a voltage component corresponding to this current, and simultaneously outputs a drive current based on the held voltage component to each load through each output terminal Tout.
  • this current storage circuit 30 A can comprise, e.g., a voltage component holding portion 31 (including the switch circuit 40 A) on a front stage and a drive current generation portion 32 constructed by a current mirror circuit on a rear stage.
  • the current storage circuit illustrated in this embodiment is just an example applicable to the current drive apparatus according to the present invention, and it is not restricted to this circuit configuration. Furthermore, in this embodiment, as the current storage circuit, although a structure including the drive current generation portion having the voltage component holding and the current mirror circuit is illustrated, the current storage circuit is not restricted thereto, and it may have a circuit configuration having, e.g., only the voltage component holding.
  • the voltage component holding portion 31 comprises: a PMOS transistor M 31 having a source connected to a junction N 31 , a drain connected to an output terminal Tcs of the current generation circuit 10 A and a gate connected to a shift output terminal Tsr of the shift register; a PMOS transistor M 32 having a source and a drain respectively connected to a high-potential power supply Vdd and a junction N 32 and a gate connected to the junction N 31 ; a PMOS transistor M 33 having a source and a drain respectively connected to the junction N 32 and the output terminal Tcs of the current generation circuit 10 A and a gate connected to the shift output terminal Tsr of the shift register 20 A; a storage capacitance C 31 connected between the high-potential power supply Vdd and the junction N 31 ; and a PMOS transistor M 34 having a source and a drain respectively connected and the junction N 32 and an output junction N 33 to the drive current generation portion 32 on the rear stage and a gate connected to an
  • the PMOS transistors M 31 and M 33 which perform on/off operation based on the switch changeover signal SR from the shift register 20 A constitute the above-described switch circuit 40 A.
  • the storage capacitance C 31 provided between the high-potential power supply Vdd and the junction N 31 may be a parasitic capacitance between the gate and the source of the PMOS transistor M 32 .
  • the above-described drive current generation portion 32 comprises: npn transistors Q 31 and Q 32 constituted by the current mirror circuit, each of which has a collector and a base connected to an output junction N 33 of the voltage component holding 31 and an emitter connected to a junction N 34 ; a resistance R 31 connected between the junction N 34 and a low-potential power supply Vss; an npn transistor Q 33 having a collector connected to an output terminal Tout from which an output current (drive current Idv) is outputted and a base connected to the output junction N 33 of the voltage component holding 31 ; and a resistance R 32 connected between the emitter of the npn transistor Q 33 and the low-potential power supply Vss.
  • the output current (drive current Idv) has a current value corresponding to a predetermined current ratio stipulated by the current mirror circuit configuration with respect to a current value of the control current outputted from the voltage component holding portion 31 and inputted through the output junction N 33 .
  • the output current by supply the output current having the negative polarity to the output terminal Tout (load LD) (that is, by setting the current flow direction of the drive current Idv to a direction of the low-potential power supply Vss from the output terminal Tout side), the current component flows down so as to be pulled in the direction of the current storage circuit 30 A from the load LD side.
  • a current value of the control current outputted from the voltage component holding portion 31 is set larger than a current value of the output current generated by the current mirror circuit of the drive current generation portion 32 .
  • the current value of the control current is reduced by the current mirror circuit with a predetermined ratio in order to stipulate the current value of the output current. That is, by setting the current value processed inside the voltage component holding 31 larger than the current value of the drive current Idv, it is possible to increase a processing speed concerning the fetch holding (storage) and the output operation of the operating current Ic in the voltage component holding 31 of the current storage circuit 30 A.
  • the current storage operation and the current output operation are executed with respect to the drive cycle of the load with a predetermined timing by which overlap in time is not generated.
  • the PMOS transistor M 34 as the output control circuit performs the off operation by applying a high-level output enable signal EN from the control portion through the output control terminal Ten.
  • the operating currents Ic having the current component with negative polarity corresponding to the input signals IN 1 to IN 6 used to control the drive states of the loads are supplied from the current generation circuit 10 A through the input terminal Tcs (output terminal Tcs of the current generation circuit 10 A), and the low-level switch changeover signal SR is applied with a predetermined timing from the shift register 20 A through the shift output terminal Tsr.
  • the PMOS transistors M 31 and M 33 as the input control circuits (switch circuits 40 A) perform the on operation.
  • the voltage level as the low level corresponding to the operating currents Ic with the negative polarity is applied to the junction N 31 (namely, the gate terminal of the PMOS transistor M 32 and one end of the storage capacitance C 31 ), and a potential difference is generated between the high-potential power supply Vdd and the junction N 31 (between the gate and the source of the PMOS transistor M 32 ).
  • the PMOS transistor M 32 carries out the on operation, a write current Iw equivalent to the operating current Ic flows down so as to be pulled in a direction of the input terminal Tcs through the PMOS transistors M 32 and M 33 from the high-potential power supply.
  • the electric charges corresponding to the potential difference generated between the high-potential power supply Vdd and the junction N 31 , i.e., between the gate and the source of the PMOS transistor M 32 are stored in the storage capacitance C 31 , and the electric charges are held as a voltage component corresponding to the operating current Ic.
  • the electric charges stored in the storage capacitance C 31 are held even after pulling of the write current Iw is stopped by applying the high-level switch changeover signal SR from the shift register 20 A through the shift output terminal Tsr upon completion of the current storage operation to the PMOS transistors M 31 and M 33 which perform the off operation.
  • the PMOS transistor M 34 performs the on operation by applying the output enable signal EN on the low level from the control portion through the output control terminal Ten.
  • the drive control current Iac inputted to the current mirror circuit portion 32 is converted into a drive current Idv having a current value corresponding to a predetermined current ratio stipulated by the current mirror circuit configuration, and supplied to each load LD through each output terminal Tout.
  • the high-level output enable signal EN from the control portion through the output control terminal Ten upon completion of the current output operation, and supply is stopped when the PMOS transistor M 34 carries out the off operation.
  • the operating current Ic having a predetermined current value according to the drive state of each load is sequentially generated and outputted by the single current generation circuit 10 A, and the switch changeover signal SR sequentially outputted from the shift register 20 A is sequentially applied to the switch circuits 40 A provided in accordance with the respective output terminals Tout in synchronization with the output timing of the operating current Ic.
  • the switch circuits 40 A sequentially perform the on operation with different timings synchronized with the output timing of the operating current Ic.
  • the write current Iw corresponding to the operating current Ic outputted from the current generation circuit 10 A sequentially flows down and is written in the current storage circuits 30 A, and held as the voltage component (the above-described current storage operation). Sequentially, in the current output period, output of the switch changeover signal SR from the shift register 20 A in the current write period is terminated, all the switch circuits 40 A perform the off operation, and the operating current Ic according to the drive states of the loads is held in all the current storage circuits 30 A. Thereafter, the output enable signal EN is applied to the respective current storage circuits 30 A from the control portion in common with the same timing. As a result, the currents according to the voltage component held in the current storage circuits 30 A are simultaneously supplied as the drive currents Idv to the loads through the output terminals Tout (the above-described current output operation).
  • the loads can be caused to operate with a predetermined drive cycle.
  • the current storage circuits are individually provided to the single current generation circuit so as to correspond to a plurality of the output terminals, the current having a predetermined current value concerning the drive control over the loads is generated by the current generation circuit, and this current is sequentially stored in each current storage circuit with a predetermined timing. Then, the operating current supplied from the single current generation circuits can be held in accordance with respective output terminals by outputting the currents to the respective loads from the respective current storage circuits through the respective output terminals at the same time, and the drive current for each output terminal can be set based on the operating current. Therefore, the drive currents in which irregularities between the respective output terminals are suppressed can be supplied, thereby driving the respective loads with the uniform operating characteristic.
  • the element structure of the bipolar transistor or the MOS transistor applied to the current drive apparatus illustrated in this embodiment is not restricted, and it may be appropriately subjected to design change in accordance with the element characteristic, a manufacturing technique, a product cost and others.
  • the element structure of the bipolar transistor or the MOS transistor constituting the current storage circuit according to this embodiment is not particularly restricted, and it may be appropriately subjected to design change in accordance with the element characteristic, the product technique, the product cost and others.
  • the MOS transistor constituting the voltage component holding element in order to obtain necessary operating speed, preferably, as described below, it is possible to excellently apply a transistor having the mobility ⁇ e of the MOS transistor being approximately 200 cm 2 /Vs or a larger value.
  • FIG. 5A shows an equivalent circuit of a structure when the electric charges are stored in the capacitance between the gate and the source of the transistor
  • FIG. 5B is a graph showing an aged change in voltage of the capacitance when the electric charges are stored in the capacitance between the gate and the source of the transistor.
  • FIG. 5A corresponds to an equivalent circuit when predetermined electric charges are stored in the storage capacitance C 31 in the voltage component holding portion 31 of the current storage circuit shown in FIG. 3, and corresponds to a case that the PMOS transistors M 32 and M 33 are ON and in the conductive state and the PMOS transistor M 34 is OFF and in the open state.
  • the transistor M corresponds to the PMOS transistor M 32
  • the capacitance C corresponds to the storage capacitance C 31 which is a sum total of a wiring capacitance, a storage capacitance and a gate capacitance of the transistor M.
  • FIG. 5B corresponds to a change of a time t relative to a drain voltage V(t) of the transistor M 32 , i.e., the voltage of the capacitance C 31 .
  • the drain current Id can be represented by the following expression (1).
  • the capacitance C is a sum total of the wiring capacitance, the storage capacitance, and the gate capacitance of the transistor M as described above.
  • a change of the time t relative to the drain voltage V(t) of the transistor M, i.e., the voltage of the capacitance C obtained by solving the above expression is substantially as shown in FIG. 5B.
  • the time constant ⁇ is in proportion to a value of the capacitance C and in inverse proportion to the 1 ⁇ 2-th power of the mobility ⁇ e.
  • the mobility ⁇ e of the transistor M in order to drive at least the 1 ⁇ 4 VGA panel, the mobility ⁇ e of the transistor M must have a value of approximately 200 cm 2 /Vs or a larger value, or the capacitance C must have a value smaller than approximately 0.5 pF.
  • the time constant ⁇ is in proportion to a value of the capacitance C and in inverse proportion to the 1 ⁇ 2-th power of the mobility ⁇ e of the transistor, the time constant ⁇ can be further decreased when the capacitance C is further reduced or the mobility ⁇ e is further increased, thereby driving the higher-definition display panel.
  • the structure of the transistor realizing the mobility or the capacitance value is not particularly restricted, for example, a polysilicon MOS transistor having a continuous grain boundary formed on an insulating substrate or an MOS transistor formed on a monocrystal silicon substrate can satisfy the above conditions, and it can be preferably used.
  • FIG. 6 is a primary structural view showing a second embodiment of a current drive apparatus according to the present invention.
  • the same or equivalent reference numerals denote structures equivalent to those in the above-described first embodiment, thereby simplifying or eliminating their explanation.
  • the current drive apparatus includes a pair of current storage sections in accordance with an output terminal to which a load is connected, and is constituted to execute in parallel an operation to sequentially fetch a current having a predetermined current value supplied from a single current generation circuit by the current storage section on one side and hold a corresponding voltage component and operation to simultaneously output the current based on the voltage component which has been already held in the current storage section on the other side through the output terminal.
  • the current drive apparatus comprises: a single current generation circuit 10 B which sequentially generates and outputs an operating current Ic having a predetermined value according to a drive stage of the load; a plurality of current storage circuits 30 B each including a pair of current storage sections 31 a and 31 b which are provided as a pair in accordance with each output terminal Tout in parallel, alternately (selectively) fetch the operating current Ic supplied from the current generation circuit 10 B with individual timings and hold a corresponding voltage component; a shift register 20 B (shift register sections 21 a and 21 b ) which is provided as a pair in accordance with the current storage sections 31 a and 31 b constituting the current storage circuit 30 B and sets a timing when supplying the operating current Ic fed from the current generation circuit 10 B to each of the current storage sections 31 a and 31 b ; a plurality of input side switch circuits 40 B having switches 41 a and 41 b which are provided as a pair in accordance with
  • the current generation circuit 10 B, the shift register 20 B (shift register sections 21 a and 21 b ), the current storage circuit 30 B (current storage sections 31 a and 32 b ) and the input side switch circuit 40 B (switches 41 a and 41 b ) have the structures equivalent to those in the above-described first embodiment, thereby eliminating the detailed explanation.
  • the first shift register section 21 a sequentially outputs a shift output as a switch changeover signal SR 1 with a predetermined timing to the first switch 41 a provided in accordance with the first current storage section 31 a in the current storage circuit 30 B provided in accordance with each output terminal Tout.
  • the second shift register section 21 b sequentially outputs a shift output as a switch changeover signal SR 2 with a timing which does not overlap the timing of the shift output from the shift register section 21 a in time to the second switch 41 b provided in accordance with the second current storage section 31 b in the current storage circuit 30 B provided in accordance with each output terminal Tout.
  • the output side switch circuit 50 B is synchronized with the output timings of the switch changeover signals SR 1 and SR 2 from the shift register sections 21 a and 21 b based on an output selection signal SEL outputted from a non-illustrated control portion, and operates so as to select the current storage section (non-selected current storage section side) of the switch which is not performing the on operation in the input side switch circuit 40 B.
  • each switch 41 a sequentially effects the on operation only in a predetermined period, and electric charges corresponding to an operating current Ic supplied from the current generation circuit 10 B are sequentially written in each current storage section 31 a as a voltage component.
  • the switch changeover signal SR 2 is not outputted from the second shift register section 21 b , and all the switches 41 b are in the off state.
  • the output selection signal SEL which changes over and sets the output side switch circuit 50 B provided in accordance with each output terminal Tout to the current storage section 31 b side is outputted in common, and an output enable signal EN 2 is outputted to all the current storage sections 31 b with a predetermined timing in common.
  • a current based on the electric charges which have been already held in each current storage section 31 b is simultaneously outputted as a drive current Idv to each load through each output terminal Tout with the same timing.
  • the output selection signal SEL used to change over and set the output side switch circuit 50 B to the current storage section 31 a side is outputted from the control portion in common, and the output enable signal EN 1 is outputted to all the current storage sections 31 a with a predetermined timing in common.
  • a current based on the electric charges held in each current storage section 31 a in the first operation period is simultaneously outputted as the drive current Idv to each load through each output terminal Tout with the same timing.
  • the operating current outputted from the single current generation circuit is sequentially fetched and held in each current storage circuit (current storage section), and outputted with a predetermined timing at the same time.
  • the current with the uniform current characteristic supplied from the single current source can be held in accordance with each output terminal, and irregularities in the drive current between the respective output terminals can be suppressed.
  • a pair of the current storage sections are provided in accordance with each output terminal, and the operation to sequentially write the electric charges corresponding to the current outputted from the current generation circuit on one current storage section side and the operation to simultaneously output the current based on the electric charges held on the other current storage section side are executed in parallel.
  • the waiting time for the current write operation to the current storage section can be reduced or eliminated, the supply time of the drive current to each load can be extended, and the drive state of each load can be finely controlled. Furthermore, the time to fetch the operating current into each current storage section and hold it can be prolonged, thereby stably carrying out the holding operation in the current storage section.
  • FIG. 7 is a primary structural view showing a third embodiment of a current drive apparatus according to the present invention.
  • the same or equivalent reference numerals denote the structures equivalent to those in the first and second embodiments, thereby simplifying or eliminating their explanation.
  • the current drive apparatus has current storage sections on two stages provided in series in accordance with each output terminal to which a load is connected, and is constituted so as to execute an operation to sequentially hold a current having a predetermined current value supplied from a single current generation circuit by the current storage section on the front stage and an operation to hold the current supplied from the current storage section on the front stage by the current storage section on the rear stage and then collectively outputs it through the output terminal.
  • the current drive apparatus comprises: a single current generation circuit 10 C which sequentially generates and outputs an operating current Ic having a predetermined current value according to a drive state of the load; a plurality of current storage circuits 30 C each including a current storage section 32 a on a front stage and a current storage section 32 b on a rear stage provided in series in accordance with each output terminal Tout; a shift register 20 C which sets a timing when supplying the operating current Ic fed from the current generation circuit 10 C to the current storage section 32 a on the front stage; and switch circuits 40 C each of which controls a supply state of the operating current Ic from the current generation circuit 10 C to each current storage circuit 30 C.
  • the current generation circuit 10 C, the shift register 20 C, the current storage circuit 30 C (current storage sections 32 a and 32 b ) and the switch circuit 40 C applied to this embodiment have the structures equivalent to, e.g., those in the above-described first embodiment, thereby eliminating their detailed explanation.
  • each current storage circuit 30 C the operating current Ic supplied from the current generation circuit 10 B is fetched into the current storage section 32 a with a predetermined timing, a corresponding voltage component is held, and a current based on the held voltage component is supplied to the current storage section 32 b on the rear stage with a predetermined timing based on a first output enable signal EN 1 fed from a non-illustrated control portion or circuit.
  • the current storage section 32 b on the rear stage fetches the current fed from the current storage section 32 a on the front stage, holds a corresponding voltage component, and outputs a current based on the held voltage component through the output terminal Tout based on a second enable signal EN 2 fed from the control portion.
  • a switch changeover signal SR from the shift register 20 C is sequentially outputted to the switch circuit 40 C provided in accordance with each current storage circuit 30 C.
  • the switch circuit 40 C sequentially performs the on operation only in a predetermined period, and electric charges (voltage component) corresponding to an operating current Ic supplied from the current generation circuit 10 C is sequentially written in the current storage section 32 a on the front stage.
  • the first output enable signal EN 1 is outputted from the control portion to all the current storage sections 32 a on the front stage in common.
  • the current held in each current storage section 32 a in the first operation period is collectively supplied to the current storage section 32 b on the rear stage and held (supply operation period).
  • the current drive apparatus of this embodiment like the above-described first embodiment, since the drive current of each output terminal is set based on the operating current fed from the single current generation circuit, irregularities in the drive current between the respective output terminals can be suppressed. Moreover, like the above-described second embodiment, the supply time of the drive current to each load can be prolonged, and the drive state of each load can be finely controlled. Additionally, the time to fetch the current into each current storage section and hold it can be extended, thereby stably executing the holding operation in the current storage section.
  • FIG. 8 is a primary structural view showing a fourth embodiment of a current drive apparatus according to the present invention.
  • the same or equivalent reference numerals denote structures equivalent to those in the first to third embodiments mentioned above, thereby simplifying or eliminating their explanation.
  • the current drive apparatus determines as one group a structure including the predetermined number of output terminals, current storage circuits provided in accordance with the output terminals, a shift register and switch circuits, forms each group on an individual semiconductor chip, provides a single current generation circuit with respect to each group (semiconductor chip), and supplies a current having a predetermined current value in common.
  • the current drive apparatus comprises: a predetermined number of output terminals Tout equivalent to, e.g., the structure described in conjunction with the second embodiment (see FIG. 6); a plurality of current storage circuits 30 D (current storage sections 33 a and 33 b ) provided in accordance with the output terminals Tout; a shift register 20 D (shift register sections 23 a and 23 b ); a plurality of input side switch circuits 40 D (switches 43 a and 43 b ); a plurality of semiconductor chips CP 1 , CP 2 , . . .
  • CPn on which circuit configurations having a plurality of output side switch circuits SOD are respectively formed; and a single current generation circuit 10 D which sequentially generates an operating current Ic having a predetermined current value according to a drive stage of a load connected to each output terminal Tout with respect to each of the semiconductor chips CP 1 , CP 2 , . . . , CPn and supplies it in common.
  • the current generation circuit 10 D, the shift register 20 D (shift register sections 23 a and 23 b ), the current storage circuit 30 D (current storage sections 33 a and 33 b ), the current storage circuit 30 D (current storage sections 33 a and 33 b ), the input side switch circuit 40 D (switches 43 a and 43 b ) and the output side switch circuit 50 D have the structures equivalent to, e.g., those in the second embodiment mentioned above, thereby eliminating their detailed explanation.
  • the current generation circuit 10 D may be formed on a specific semiconductor chip among a plurality of the semiconductor chips CP 1 , CP 2 , CPn each having a circuit configuration including the current storage circuit 30 D formed thereto.
  • the same circuit may be formed on each of the semiconductor chips CP 1 , CP 2 , . . . CPn, and any one of them may be used to cause other semiconductor chips to enter non-operating state or to be bypassed.
  • the current generation circuit 10 D may be formed on a semiconductor chip different from a plurality of the semiconductor chips CP 1 , CP 2 , . . . CPn.
  • each of the semiconductor chips CP 1 , CP 2 , . . . CPn applied to this embodiment is formed of a semiconductor material such as single crystal silicone, and its material is not restricted in particular.
  • the operating current Ic outputted from the current generation circuit 10 D is supplied to the respective semiconductor chips CP 1 , CP 2 , . . . CPn in common, it is sequentially fetched into one of a pair of the current storage sections 33 a and 33 b in the current storage circuit 30 D provided in accordance with each of the semiconductor chips CP 1 , CP 2 , . . . CPn, and a corresponding voltage component is held.
  • a current based on the voltage component held in the other current storage section is simultaneously outputted to the corresponding load through the output terminal Tout of each of the respective semiconductor chips CP 1 , CP 2 , . . . CPn. These operations are alternately and continuously executed.
  • the current drive apparatus of this embodiment only the single current generation circuit is provided with respect to semiconductor chips, and individual current circuits are not provided in accordance with the respective semiconductor chips. Accordingly, the circuit configuration formed on each semiconductor chip can be simplified, and the number of terminals can be reduced, thereby achieving minimization of the apparatus scale or decrease in the product cost. Moreover, even if a plurality of semiconductor chips are provided in accordance with the number of the output terminals connected to the loads, since the current having the uniform current characteristic supplied from the single current source can be held in the current storage circuit in each semiconductor chip, irregularities in the drive current between the respective output terminals and between the respective semiconductor chips can be suppressed, thereby driving each load with the uniform operation characteristic.
  • the data driver is constituted by a plurality of driver chips (semiconductor chips), by sequentially repeating for each row the operation to sequentially supply a predetermined current according to display data outputted from the single current generation circuit to the current storage circuit formed on each driver chip and simultaneously supply the light emitting drive current (drive current) to each light emitting element with a predetermined timing, the display data for one screen of the display panel can be written in each display pixel and the light emitting operation can be performed with a predetermined brightness gradation. Therefore, image information of the high-definition and large-screen size can be excellently display while suppressing occurrence of display irregularities.
  • FIG. 9 is a primary structural view showing a fifth embodiment of a current drive apparatus according to the present invention.
  • the same or equivalent reference numerals denote structures equivalent to those in the first to fourth embodiments mentioned above, thereby simplifying or eliminating their explanation.
  • the current drive apparatus can be preferably applied to driving of, e.g., a simple matrix type display panel (see FIG. 2), and this can be applied to a drive mode which displays a desired image by performing a pulse width modulation (PWM) drive mode by supplying a current having a fixed current and set to a supply time (pulse width) according to display data from each output terminal to each display element (load).
  • PWM pulse width modulation
  • the current drive apparatus have a plurality of semiconductor chips, comprises a circuit configuration which is the same as one group including, e.g., the predetermined number of output terminals, current storage circuits provided in accordance with the output terminals, a shift register and switch circuits described according to the fourth embodiment, and has a structure that each single input current storage circuit is provided to an input portion of this circuit configuration.
  • the operation to fetch a fixed current into the current storage circuit for each output terminal on the semiconductor chip can be simultaneously performed on the respectively semiconductor chips in parallel.
  • the current drive apparatus includes a circuit configuration which is equivalent to, e.g., the structure described in conjunction with the fourth embodiment and have the predetermined number of output terminals Tout, a plurality of current storage circuits 30 E (current storage sections 34 a and 34 b ) provided in accordance with the output terminals Tout, a shift register 20 E (shift register sections 24 a and 24 b ), a plurality of input side switch circuits 40 E (switches 44 a and 44 b ), and a plurality of output side switch circuits 50 E. Furthermore, this apparatus comprises: a plurality of semiconductor chips CP 1 , CP 2 , . . .
  • CPn each having an input switch circuit 60 E which performs the on/off operation based on a shift output (switch changeover signal) from a non-illustrated shift register or control portion being formed thereon on a front stage of the circuit configuration, i.e., at an input portion to which the operating current Ic outputted from the current generation circuit 10 E is supplied and an input current storage circuit 70 E which fetches and holds an operating current Ic outputted from a current generation circuit 10 E; and the single current generation circuit 10 E which supplies the predetermined operating current Ic to the respective semiconductor chips CP 1 , CP 2 , . . . CPn in common.
  • the current generation circuit 10 E, the shift register 20 E (shift register sections 24 a and 24 b ), the current storage circuit 30 E (current storage sections 34 a and 34 b ), the input side switch circuit 40 E (switches 44 a and 44 b ) and the output side switch circuit 50 E applied to this embodiment have the structures equivalent to those in the fourth embodiment mentioned above, thereby eliminating the detailed description.
  • the input switch circuit 60 E provided to each of the semiconductor switches CP 1 , CP 2 , . . . CPn performs the on operation based on a shift output (switch changeover signal) sequentially outputted from a non-illustrated shift register (or a control portion), sets the operating current Ic outputted from the current generation circuit 10 E to the write state in order to feed this current to each of the semiconductor chips CP 1 , CP 2 , . . . CPn, and controls in such a manner that the operating current Ic is fetched into and held in the input current storage circuit 70 E.
  • a shift output switch changeover signal
  • the input current storage circuit 70 E has the structure equivalent to, e.g., that of the current storage circuit in the first embodiment mentioned above, fetches the operating current Ic outputted from the current generation circuit 10 E with a predetermined timing that the input switch circuit 60 E enters the on state, holds a corresponding voltage component, and outputs the operating current Ic based on the held voltage component to the current storage circuit 30 E (any one of the current storage sections 34 a and 34 b ) through the input side switch circuit 40 E (any one of the switches 44 a and 44 b ) in each semiconductor chip based on an output enable signal outputted from a non-illustrated control portion.
  • the operating current Ic having a predetermined current value outputted from the current generation circuit 10 E is supplied to each of the semiconductor chips CP 1 , CP 2 , . . . CPn in common, it is sequentially fetched into the input current storage circuit 70 E through the input switch circuit 60 E provided in accordance with each of the semiconductor chips CP 1 , CP 2 , . . . CPn with a predetermined timing, and a corresponding voltage component is held.
  • a current based on the voltage component held in the input current storage circuit 70 E is supplied to one storage section of the current storage circuit 30 E (e.g., the first current storage section 34 a ) through one switch in the input side switch circuit 40 E in common (e.g., the first switch 44 a ) in each of the semiconductor chips CP 1 , CP 2 , . . . CPn, and a corresponding voltage component is held.
  • a current based on the voltage component which has been already held in the other one storage section in the current storage circuit 30 E e.g., the second current storage section 34 b
  • the operating current Ic outputted from the current generation circuit 10 E is again sequentially fetched into and held in the input current storage circuit 70 E through the input switch circuit 60 E provided in accordance with each of the semiconductor chips CP 1 , CP 2 , . . . CPn with a predetermined timing.
  • the current based on the voltage component held in the input current storage circuit 70 E is supplied to the other one storage section in the current storage circuit 30 E (e.g., the current storage section 34 b ) through the other one switch in the input side switch circuit 40 E (e.g., the switch 44 b ) in each of the semiconductor chips CP 1 , CP 2 , CPn in parallel, and a corresponding voltage component is held.
  • the other one storage section in the current storage circuit 30 E e.g., the current storage section 34 b
  • the other one switch in the input side switch circuit 40 E e.g., the switch 44 b
  • the current based on the voltage component held in one storage section in the current storage circuit 30 E (e.g., the current storage section 34 a ) in the first operation period is simultaneously outputted to the respective output terminals Tout as a drive current Idv.
  • the operation to sequentially hold the operating current Ic outputted from the current generation circuit 10 C in the input current storage circuit 70 E in the input portion, supply it to the current storage circuit 30 E on the rear stage and fetch it into one storage section in the current storage circuit 30 E and the operation to output the current held in the other storage section as the drive current Idv to the respective output terminals Tout at same time are alternately and continuously executed.
  • a current outputted from the single current generation is sequentially fetched into the input current storage circuit provided in accordance with each semiconductor chip, it is then fetched into and held in the current storage circuit on the rear stage provided in accordance with each output terminal in parallel in each semiconductor chip, and it is collectively outputted with a predetermined timing.
  • irregularities in the drive current between the respective output terminals can be suppressed, and the operation to fetch the current into the current storage circuit corresponding to the output terminal of each semiconductor chip can be performed between the respective semiconductor chips in parallel. Therefore, the time required to fetch and hold the current in each current storage circuit can be prolonged, thereby stably effecting the holding operation in the current storage section.
  • the operating current Ic fetched and held by the input current storage circuit 70 E provided in accordance with each of the semiconductor chips CP 1 , CP 2 , . . . CPn is sequentially fetched into and held in a plurality of the current storage circuits 30 E provided in the respective semiconductor chips CP 1 , CP 2 , . . . CPn, and it is outputted from the respective output terminals Tout at the same time with a predetermined timing.
  • the drive current Idv supplied to each load through each output terminal Tout becomes a constant current having the same current value with each timing.
  • PWM pulse width modulation
  • each load can be caused to operate by pulse width modulation (PWM).
  • PWM pulse width modulation
  • This PWM control circuit 65 E may be integrally formed in each of the semiconductor chips CP 1 , CP 2 , . . . CPn, or it may be formed on a semiconductor chip different from the respective semiconductor chips so as to be electrically connected to the respective semiconductor chips CP 1 , CP 2 , . . . CPn.
  • FIG. 10 is a primary structural view showing a sixth embodiment of a current drive apparatus according to the present invention.
  • the same or equivalent reference numerals denote structures equivalent to those in the first to fifth embodiments mentioned above, thereby simplifying or eliminating their explanation.
  • a current drive apparatus has a structure that an input current storage circuit provided in accordance with each semiconductor chip has a pair of current storage sections provided in parallel.
  • the current drive apparatus in the structure of the fifth embodiment (see FIG. 9), has a structure that an input current storage circuit 70 F provided at an input portion of each of semiconductor chips CP 1 , CP 2 , . . . CPn includes a pair of current storage sections 71 a and 71 b arranged in parallel with each other and individual switch circuits 60 F and 80 F used to selectively connect one of the current storage sections 71 a and 71 b are provided on the input side and the output side of the input current storage circuit 70 F.
  • Any other structure applied to this embodiment has a structure equivalent to that of the fifth embodiment mentioned above, thereby eliminating the detailed structure.
  • an operating current Ic outputted from the current generation circuit 10 F is supplied to the respective semiconductor chips CP 1 , CP 2 , . . . CPn in common, and it is applied to the switch circuits 60 F and 80 F provided at the input portion of each of the semiconductor chips CP 1 , CP 2 , . . . CPn.
  • the operation to sequentially fetch the operating current Ic into one of a pair of the current storage sections 71 a and 72 b of the current storage circuit 70 F and hold a corresponding voltage component and the operation to supply the operating current Ic based on the voltage component which has been already held on the other side to a plurality of the current storage circuits 30 F on the rear stages are alternately and continuously executed in parallel.
  • the operation to sequentially fetch an operating current Ic fed from the input current storage circuit 70 F into one of the current storage sections 35 a and 35 b with a predetermined timing and the operation to collectively output the current based on the voltage component held on the other side through the output terminal are alternately and continuously executed in parallel.
  • the current drive apparatus of this embodiment in the state that the current outputted from the single current generation circuit is sequentially written into one input current storage section of the input current storage circuit provided in accordance with each semiconductor chip, the current held in the other input current storage section is supplied to, fetched into and held in the current storage section provided in accordance with each output terminal.
  • the time required to fetch and hold the current in each input current storage section can be prolonged, and the holding operation in the input current storage section can be stably carried out.
  • the waiting time of the operation to write the current to each semiconductor chip can be reduced or eliminated, the supply time of the drive current to the load can be prolonged, thereby finely controlling the drive state.
  • the drive current Idv supplied to each load through each output terminal Tout becomes a constant current having the same current value with each timing.
  • the PMW control circuit 60 F applying the pulse width modulation (PWM) drive mode and adjusting the supply time (pulse width) of the constant current to each load, each load can be operated in a desired drive state.
  • PWM pulse width modulation
  • FIG. 11 is a primary structural view showing a seventh embodiment of a current drive apparatus according to the present invention.
  • the same or equivalent reference numerals denote structures equivalent to those in the first to sixth embodiments, thereby simplifying or eliminating their explanation.
  • the current drive apparatus has a structure that a plurality of reference currents supplied from the single reference current generation circuit including a plurality of reference current generation sections which generate and output reference currents having current values set so as to have weightings different from each other are individually held in a plurality of the reference current storage sections provided in accordance with the reference currents and predetermined currents according to drive states of loads are sequentially generated based on the predetermined number of digital input signals.
  • the current drive apparatus comprises: a reference current generation circuit (reference current generation circuit) 10 G including four reference current generation sections 11 a to 11 d which individually generate and output reference currents I 1 , I 2 , I 4 and I 8 to which weightings of, e.g., 1:2:4:8 are set; a shift register SFR which sets a timing when collectively supplying the respective reference currents I 1 , I 2 , I 4 and I 8 fed from the reference current generation circuit 10 G to a reference current storage circuits 90 G in parallel; the current storage circuits 90 G each having a plurality of reference current storage sections 91 a to 91 d which individually fetch and hold reference currents I 1 , I 2 , I 4 and I 8 supplied from the reference current generation circuit 10 G; input side switch circuits SWA each of which controls supply states of the reference currents I 1 , I 2 , I 4 and I 8 from the reference current generation circuit 10 G (reference current generation sections 11 a to 11 ).
  • the structure having the reference current generation circuit 10 G, the reference current storage circuit 90 G, the input side switch circuit SWA and the output side switch circuit SWB has a function as a current generation circuit which generates and outputs the current Is having a predetermined value according to a drive state of each load.
  • the structure having the current storage circuits 30 G and the switch circuits 40 G has a function as a current storage circuit described in conjunction with the foregoing embodiments.
  • the structure including the predetermined number of the output terminals Tout, the current storage circuits 30 G respectively provided in accordance with the output terminals Tout, the input side switch circuits 40 G, the reference current storage circuit 90 G which generates the predetermined current Is supplied to the current storage circuits 30 G and the input side and output side switch circuits SWA and SWB is determined as each group, and each group is formed on each of the semiconductor chips CP 1 , CP 2 , . . . CP 2 .
  • the single reference current generation circuit 10 G is provided with respect to the groups (semiconductor chips) in such a manner that the reference currents I 1 , I 2 , I 4 and I 8 outputted from the reference current generation circuit 10 G are supplied in common.
  • the reference current generation sections 11 a to 11 d have the circuit structure (see FIG. 2) equivalent to the current generation circuit described in accordance with the foregoing embodiments, and it is possible to apply a structure obtained by appropriately designing the circuit configuration in such a manner that a ratio of the current values of the reference currents generated by the reference current generation sections 11 a to 11 d becomes, e.g., 1:2:4:8.
  • the shift register SFR, the reference current storage circuits 90 G (reference current storage section 91 a to 91 d ) and the input side switch circuit SWA applied to this embodiment have the structures equivalent to those described in conjunction with the foregoing embodiments, thereby eliminating the detailed explanation.
  • the reference currents I 1 , I 2 , I 4 and I 8 to which the current values are set so as to have the weighting of 1:2:4:8 by the reference current generation sections 11 a to 11 d constituting the reference current generation circuit 10 G are generated and outputted, and a switch changeover signal SRs sequentially outputted from the shift register SFR is sequentially applied to each input side switch circuit SWA.
  • the switch circuit SWA sequentially performs the on operation with different timings only in a predetermined period, the reference currents I 1 , I 2 , I 4 and I 8 outputted from the reference current generation circuit 10 G are simultaneously supplied to the reference current storage sections 91 a to 91 d , and corresponding voltage components are individually held in the respective reference current storage sections.
  • the output side switch circuits SWB to which the high-level digital input signals IN 1 to IN 4 are applied perform the on-operation, the reference currents based on the held voltage components are selectively outputted, and these reference currents are combined (added).
  • the currents Is having the current values according to the signal levels of the digital input signals IN 1 to IN 4 are generated.
  • the switch changeover signals SR from a non-illustrated shift register are sequentially outputted to the switch circuits 40 G.
  • the switch circuits 40 G sequentially carry out the on operation only in a predetermined period, the currents Is supplied from the reference current storage circuit 90 G through the output side switch circuit SWB are sequentially supplied and fetched into the current storage circuits 30 G, and corresponding voltage components are held.
  • the output enable signal EN is outputted from a non-illustrated control portion to all the current storage sections 30 G with a predetermined timing in common, currents based on the voltage components held in the current storage circuits 30 G are simultaneously outputted as drive currents Idv to the respective loads through the respective output terminals Tout with the same timing.
  • the loads can be operated in a predetermined drive cycle.
  • a plurality of the reference current storage sections in which the reference currents to which the current values are set so as to have weightings different from each other are arbitrarily selected based on the predetermined number of the digital input signals, and the reference currents held in the selected reference current storage sections are combined.
  • predetermined currents of the analog signals corresponding to the drive states of the loads are generated, the operation to hold the currents in the current storage circuits provided at the respective output terminals is sequentially executed, and the held currents are simultaneously supplied to the respective loads as the drive currents with a predetermined timing.
  • each load can be operated in the drive state excellently corresponding to the input signal with a relatively simple apparatus structure.
  • the reference currents having the uniform current characteristic outputted from the single current generation circuit are supplied to the reference current storage circuits provided in accordance with each semiconductor chip in common, and the drive currents are generated based on the reference currents.
  • the drive currents are generated based on the reference currents.
  • the reference currents outputted from the single reference current generation circuit can be sequentially supplied to the respective driver chips, the light emitting drive currents (analog signals) having the current values excellently corresponding to display data (digital input signals) can be sequentially generated based on the reference currents and simultaneously supplied to the respective light emitting elements with a predetermined timing. Therefore, it is possible to realize the display apparatus which can excellently suppress irregularities in the light emitting drive currents between the respective output terminals and between the respective driver chips and perform multigradation display excellently corresponding to the display data while suppressing generation of display irregularities.
  • FIG. 12 is a primary structural view showing an eighth embodiment of a current drive apparatus according to the present invention.
  • the same or equivalent reference numerals denote structures equivalent to those in the seventh embodiment mentioned above, thereby simplifying or eliminating their explanation.
  • the current drive apparatus is configured to comprise in accordance with each semiconductor chip a pair of reference current storage circuit portions including a plurality of reference current storage sections which fetch and hold a plurality of reference currents outputted from the reference current generation circuit and alternately execute the operation to sequentially hold reference currents supplied from a single reference current generation circuit by a reference current storage circuit portion on one side and the operation to generate predetermined currents according to drive states of loads by a reference current storage circuit portion on the other side based on the reference currents which have been already held in parallel.
  • the current drive apparatus has a structure that a reference current storage circuit 90 H provided to each of semiconductor chips CP 1 , CP 2 , . . . CPn comprises a pair of four-bit reference current storage circuit portions 92 a and 92 b (respective reference current storage circuit portions correspond to the reference current storage sections 91 a to 91 d shown in FIG. 11) arranged in parallel with each other and individual switch circuits SWA and SWB used to selectively connect to one of the four-bit reference current storage circuit portions 92 a and 92 b are provided on the input side and the output side of the reference current storage circuit 90 H.
  • the four-bit reference current generation circuit 10 H has, e.g., the same structure as those of the reference current generation sections 11 a to 11 d illustrated in FIG. 11, and a structure having four sets of reference current generation sections which generate and output the reference currents I 1 , I 2 , I 4 and I 8 to which current values are set so as to have weightings different from each other. It is to be noted that other structures applied to this embodiment have the structures equivalent to those in the seventh embodiment mentioned above, thereby eliminating the detailed explanation.
  • reference currents I 1 , I 2 , I 4 and I 8 to which current values are set so as to have weightings different from each other are supplied from the four-bit current generation circuit 10 H to the semiconductor chips CP 1 , CP 2 , . . . CPn in common, and switch changeover signals SRs sequentially outputted from the shift register SFR are sequentially applied to the input side switch circuit SWA.
  • the reference currents are sequentially fetched into and individually held in one of a pair of the four-bit reference current storage circuit portions 92 a and 92 b of the reference current storage circuit 90 H.
  • output enable signals ENa and ENb are applied to the four-bit reference current storage circuit on the other side from a non-illustrated control portion in common, and digital input signals IN 1 to IN 4 are applied to an output side switch circuit SWB.
  • the operation by which the reference currents I 1 , I 2 , I 4 and I 8 which have been already held are selectively outputted, their current components are combined (added) and currents Is having current values according to signal levels of the digital input signals IN 1 to IN 4 are alternately and continuously executed.
  • FIG. 13 is a primary structural view showing a ninth embodiment of a current drive apparatus according to the present invention.
  • the same or equivalent reference numerals denote structures equal to those in the foregoing embodiments, thereby simplifying or eliminating their explanation.
  • the current drive apparatus has a structure that the structures which are applied to the current drive apparatuses according to the foregoing embodiments and formed to the semiconductor chips are stratified and a plurality of output terminals provided to an upper semiconductor chip are connected to input portions of a plurality of lower semiconductor chips.
  • the present invention is applied to the structure described in connection with the eighth embodiment mentioned above, it can be likewise applied to any other embodiments.
  • the current drive apparatus comprises: upper semiconductor chips CP 11 , CP 12 , . . . CPy to which reference currents I 1 , I 2 , I 4 and I 8 to which current values are set so as to have weightings different from each other are supplied from a four-bit reference current generation circuit 10 J in common; and lower semiconductor chips CP 21 , CP 22 , CPz having input terminals T 2 in connected to a plurality of output terminals T 1 out according to the respective upper semiconductor chips CP 11 , CP 12 , . . . CPy. Output terminals T 2 out individually connected to a plurality of loads.
  • each of the upper semiconductor chips CP 11 , CP 12 , . . . CPy comprises: a reference current storage circuit 90 J including a pair of four-bit reference current storage circuit portions 93 a and 93 b ; and individual switch circuits SWA and SWB used to selectively connect to one of the four-bit reference current storage circuit portions 93 a and 93 b .
  • the operation to fetch and hold reference currents I 1 , I 2 , I 4 and I 8 fed from the four-bit reference current generation circuit 10 J to one of four-bit reference current storage circuit portions (e.g., the first circuit portion 93 a ) with a predetermined timing based on a shift output (switch changeover signal) Sra from the shift register SFR and the operation which selectively executes the operation to supply the reference currents I 1 , I 2 , I 4 and I 8 held in the other four-bit reference current storage circuit portion (e.g., the second circuit 93 b ) to the lower semiconductor chips CP 21 , CP 22 , CPz are alternately performed in parallel. That is, the semiconductor chips CP 11 , CP 12 , . .
  • CPy do not include the current generation circuit used to generate a current having a predetermined value based on an input signal or a current storage circuit on the rear stage such as shown in FIG. 12, and they are configured to output the held reference currents I 1 , I 2 , I 4 and I 8 and supply them to the lower semiconductor chips CP 21 , CP 22 , . . . CPz through the output terminal T 1 out and the input terminal T 2 in.
  • each of the lower semiconductor chips CP 21 , CP 22 , . . . CPz comprises: a reference current storage circuit 90 K including a pair of four-bit reference current storage circuit portions 94 a and 94 b which fetch and hold reference currents I 1 , I 2 , I 4 and I 8 fed from the upper semiconductor chips CP 11 , CP 12 , . . .
  • reference currents I 1 , I 2 , I 4 and I 8 having current values whose weightings are different from each other are supplied from the four-bit reference current generation circuit 10 J to the upper semiconductor chips CP 1 , CP 12 , . . . CPy in common, and the input side switch circuit SWA is switched to one of a pair of the four-bit reference current storage circuit portions 93 a and 93 b constituting the reference current storage circuit 90 J.
  • the reference currents I 1 , I 2 , I 4 and I 8 are individually fetched into and held in the four-bit reference current storage circuit portions, and the output side switch circuit SWB is switched to the other circuit portion in the reference current storage circuit 90 J based on output enable signals ENa and Enb and a selection control signal SEL outputted from a non-illustrated control portion.
  • the reference currents I 1 , I 2 , I 4 and I 8 which have been already held on the other side are supplied as they are to the input terminals T 2 in of the lower semiconductor chips CP 21 , CP 22 , . . . CPz through the respective output terminals T 1 out.
  • the input side switch circuit SWC is switched to one of a pair of the four-bit reference current storage circuit portions 94 a and 94 b constituting the reference current storage circuit 90 K.
  • the reference currents I 1 , I 2 , I 4 and I 8 are individually fetched into and held in the four-bit reference current storage circuit portions.
  • the output side switch circuit SWD is switched to the other circuit portion in reference current storage circuit 90 K based on the output enable signals ENc and End and the digital input signals IN 1 to IN 4 , and arbitrary reference current storage sections are selected.
  • the reference currents I 1 , I 2 , I 4 and I 8 which have been already held on the other side are arbitrary selected and combined, and currents Is having predetermined current values according to drive states of the loads are generated and supplied to the current storage circuit 30 J on the rear stage.
  • the switch circuits 40 J sequentially perform the on operation only in a predetermined period based on the shift output SR from the shift register, the currents Is fed from the reference current storage circuit 90 K through the output side switch circuit SWO are sequentially written and held in the respective current storage sections 30 J, and the output enable signal EN is applied from the control portion with a predetermined timing to drive the loads.
  • the currents held in the respective current storage sections 30 J are simultaneously outputted as the drive currents Idv to the respective loads via the respective output terminals T 2 out with the same timing.
  • the semiconductor chips each including the current storage circuit having a function to fetch predetermined currents and simultaneously output them with a predetermined timing are connected to each other so as to have a hierarchical structure. Therefore, by only supplying the predetermined currents or the reference currents to the small number of the upper semiconductor chips, the currents or the reference currents are sequentially supplied to a plurality of the lower semiconductor chips, and the predetermined drive currents are collectively supplied to the more loads through the respective output terminals. Thus, it is possible to suppress irregularities in the drive currents between the respective semiconductor chips and between the output terminals provided to the same semiconductor chip.
  • the time required to fetch and hold the predetermined current in each reference current storage circuit portion can be prolonged, thereby stably performing the holding operation in the reference current storage circuit portion. Furthermore, since the waiting time in the operation to write the reference current to each semiconductor chip can be further reduced or substantially eliminated, and the supply time of the drive currents to the loads can be extended, thereby finely controlling the drive states.
  • the circuit configurations formed on the upper semiconductor chips CP 11 , CP 12 , . . . CPy are different from those formed on the lower semiconductor chips CP 21 , CP 22 , . . . CPy.
  • the semiconductor chips having the same circuit configuration when applied to the structure described in conjunction with the first embodiment or the fourth embodiment, it is possible to apply the semiconductor chips having the same circuit configuration.
  • FIG. 14 is a schematic block diagram showing an example of an entire structure of a display apparatus according to the present invention
  • FIG. 15 is a block diagram showing primary structures of a data drive and a display panel applied to the display apparatus according to this embodiment
  • FIG. 16 is a schematic structural view showing another example of a scanning driver applied to the display apparatus according to the present invention.
  • a display apparatus 100 comprises: a display panel (pixel array) 110 in which later-described pixel drive circuits DC and a plurality of display pixels consisting of light emitting elements (optical elements: e.g., organic EL elements OEL) are arranged in a matrix form in the vicinity of intersections of a plurality of scanning lines SL as well as power supply liens VL arranged so as to be parallel to each other and a plurality of data lines DL, as schematically shown in FIG.
  • a display panel pixel array 110 in which later-described pixel drive circuits DC and a plurality of display pixels consisting of light emitting elements (optical elements: e.g., organic EL elements OEL) are arranged in a matrix form in the vicinity of intersections of a plurality of scanning lines SL as well as power supply liens VL arranged so as to be parallel to each other and a plurality of data lines DL, as schematically shown in FIG.
  • a scanning driver scanning drive circuit 120 which is connected to the scanning lines SL and controls a display pixel group for each row into a selected state by sequentially applying a high-level scanning signal Vsel to the scanning lines SL with a predetermined timing
  • a data driver signal drive circuit 130 which is connected to the data lines DL and controls a supply state of a signal current (gradation current Ipix) according to display data to the data lines DL
  • a power supply driver (power supply drive circuit) 140 which is connected to the power supply lines VL arranged in parallel with the scanning lines SL and causes a predetermined signal current (gradation current, drive current) according to the display data to flow to the display pixel group by sequentially applying a high-level or low-level power supply voltage Vsc to the power supply lines Vsc to the display pixel group
  • a system controller 150 which generates and outputs a scanning control signal, a data control signal and a power supply control signal which control operating states of at least the scanning driver 120 , the
  • each of the display pixels arranged on the display panel in the matrix form has a pixel drive circuit DC which controls the later-described write operation to the display pixel and the light emitting operation of the light emitting element based on a scanning signal Vsel applied from the scanning driver 120 to the scanning line SL, a signal current supplied from the data driver 130 to the data line DL and a power supply voltage Vsc applied from the power supply driver 140 to the power supply line VL, and a light emitting element (organic EL elements OEL) whose light emitting brightness is controlled in accordance with a current value of a drive current supplied thereto.
  • a pixel drive circuit DC which controls the later-described write operation to the display pixel and the light emitting operation of the light emitting element based on a scanning signal Vsel applied from the scanning driver 120 to the scanning line SL, a signal current supplied from the data driver 130 to the data line DL and a power supply voltage Vsc applied from the power supply driver 140 to the power supply line VL, and
  • the pixel drive circuit DC generally has a function to control the selection/non-selection state of the display pixel based on the scanning signal, fetch the gradation current according to the display data in the selection state and hold it as a voltage level, and apply the drive current according to the held voltage level in the non-selection state and maintain the operation of causing light emission of the light emitting elements in a predetermined period.
  • the light emitting element which is subjected to light emission control by the pixel drive circuit it is not restricted to the organic EL element, and it is possible to excellently apply a self-luminous type light emitting element (optical elements) such as an inorganic EL element or light emitting diode.
  • the scanning driver 120 controls so as to write a gradation current Ipix based on display data supplied from the data driver 130 through the data lines DL into the display pixels with the display pixels being in the selection state by sequentially applying the high-level scanning signals Vsel to the respective scanning lines SL based on a scanning control signal supplied from the system controller 150 .
  • the scanning driver 120 comprises shift blocks SB 1 , SB 2 , . . . SBn on a plurality of stages shift registers and buffers in accordance with the respective scanning lines SL, and shift outputs generated while being sequentially shifted from the upper part to the lower part of the display panel 110 by the shift registers based on scanning control signals (a scanning start signal SSTR, a scanning clock signal SCLK and others) fed from the system controller are applied to the respective scanning lines SL as scanning signals Vsel having a predetermined voltage level (high-level) through the buffers.
  • scanning control signals a scanning start signal SSTR, a scanning clock signal SCLK and others
  • the data driver 130 fetches and holds the display data supplied from the display signal generation circuit 160 with a predetermined timing based on various kinds of data control signals (an output enable signal OE, a data latch signal STB, a sampling start signal STR, a shift clock signal CLK and others) fed from the system controller 150 , converts a gradation voltage (digital input signal) corresponding to the display data into a current component, and supplies it as a gradation current Ipix (analog output signal) to the respective data lines DL with a predetermined timing.
  • data control signals an output enable signal OE, a data latch signal STB, a sampling start signal STR, a shift clock signal CLK and others
  • a plurality of reference currents generated with current values being weighted in advance by the single reference current generation circuit are individually fetched into and held in the reference current storage circuits provided to the respective driver chips, and currents obtained by selecting and combining arbitrary reference currents based on the display data consisting of the digital signals are simultaneously outputted to the respective data lines provided to the display panel through the respective output terminals as the gradation currents (drive currents) corresponding to the brightness gradation of the light emitting elements.
  • the display apparatus since the current components having the negative polarity are supplied to the data lines as the gradation currents, the currents corresponding to the gradation currents flow so as to be pulled in a data driver (current drive apparatus) direction via the output terminals from the data line (display panel) side. Therefore, the display apparatus according to this embodiment can be excellently applied to the display panel having the structure that the later-described current write type pixel drive circuit is provided to each display pixel to which the light emitting element is arranged.
  • the system controller 150 operates each driver with a predetermined timing by respectively outputting a scanning control signal and a data control signal which control the operation state (the above-described scanning shift start signal SSTR or the scanning clock signal SCLK, the shift start signal STR or the shift clock signal CLK, the latch signal STB, the output enable signal OE, and others) to the scanning driver 120 , the data driver 130 and the power supply driver 140 , causes it to generate and output a scanning signal Vsel, a gradation current Ipix, a power supply voltage Vsc, executes a drive control operation in the later-described drive circuit, and controls the display panel 110 to display image information based on a predetermined video signal.
  • the system controller 150 constitutes the control portion described in conjunction of the current drive apparatus concerning each of the foregoing embodiments.
  • the power supply driver 140 pulls a write current (sink current) corresponding to the gradation current Ipix based on the display data in the data driver 130 direction via the display pixels (pixel drive circuit) from the power supply lines VL by applying the low-level power supply voltage Vscl (e.g., a voltage level equal to or below a ground potential) to the power supply lines VL in synchronization with a timing that the display pixel group for each row is set to the selection state by the scanning driver 120 based on the power supply control signal fed from the system controller 150 .
  • Vscl low-level power supply voltage
  • this power supply driver 140 causes a drive current corresponding to the gradation current Ipix based on the display data to flow in the organic EL element OEL direction from the power supply liens VL via the display pixels (pixel drive circuits) by applying a high-level power supply voltage Vsch to the power supply lines VL in synchronization with a timing that the display pixel group for each row is set to the non-selection state by the scanning driver 120 .
  • the power supply driver 140 generally comprises voltage shift blocks VSB 1 , VSB 2 , . . . VSBn on a plurality of stages consisting of shift registers and buffers in accordance with each power supply line VL like the shift blocks SB 1 , SB 2 , . . . SBn of the above-described driver 120 .
  • Shift outputs generated while being sequentially shifted from the upper part toward the lower part of the display panel 110 based on power supply control signals (a power supply start signal VSTR, a power supply clock signal VCLK and others) synchronized with the scanning control signals fed from the system controller are applied to the respective power supply lines VL as power supply voltages Vscl and Vsch having a predetermined voltage level (a low level in the selection state set by the scanning driver and a high level in the non-selection state set by the same) through the buffers.
  • power supply control signals a power supply start signal VSTR, a power supply clock signal VCLK and others
  • the display signal generation circuit 160 extracts a brightness gradation signal component from, e.g., a video signal supplied from the outside of the display apparatus, and supplies it to the data driver 130 as display data for each line of the display panel 110 .
  • the display signal generation circuit 160 may have a function to extract the timing signal component and supply it to the system controller 150 as well as a function to extract the brightness gradation signal component.
  • the system controller 150 generates the scanning control signal, the data control signal and the power supply control signal which are supplied to the scanning driver 120 , the data driver 130 and the power supply driver 140 based on the timing signal fed from the display signal generation circuit 160 .
  • FIG. 17 is a circuit structural view showing an example of a basic structure of a pixel drive circuit applicable to the display apparatus according to the present invention
  • FIGS. 18A and 18B are conceptual views showing a basic operation of the pixel drive circuit applicable to this embodiment.
  • FIG. 19 is a timing chart showing a display timing of image information in the display apparatus according to this embodiment.
  • the pixel drive circuit DCx comprises an NMOS thin film transistor Tr 1 having a gate terminal connected to a scanning line SL, a source terminal connected to a power supply line VL and a drain terminal connected to a junction N 1 ; an NMOS thin film transistor Tr 2 having a gate terminal connected to the scanning line SL, and source and drain terminals respectively connected to a data line DL and a junction N 2 ; an NMOS thin film transistor Tr 3 having a gate terminal connected to the junction N 1 , and source and drain terminals respectively connected to a power supply line VL and the junction N 2 ; and a capacitor Cs connected between the junction N 1 and the junction N 2 , in the vicinity of each intersection of the scanning line SL and the data line DL arranged so as to be orthogonal to the display panel 110 .
  • the light emitting element (organic EL element OEL) has an anode terminal connected to the junction N 2 and a cathode terminal connected to a ground potential, respectively.
  • the capacitor Cs may be a parasitic capacitance formed between the gate and the source of the thin film transistor Tr 3 . It is to be noted that the organic EL element OEL is used as the light emitting element in this example, but the light emitting element is not restricted thereto as described above.
  • the write operation periods Tse set for the respective lines are set so as not overlap in time.
  • a high-level scanning signal Vsel (Vslh) is applied to the scanning line SL in a specific line (i-th line) from the scanning driver 120
  • a low-level power supply voltage Vscl is applied to the power supply line VL in this line (i-th line) from the power supply driver 140 .
  • the gradation current having the negative polarity (-Ipix) corresponding to display data of the line fetched by the data driver 130 is supplied to each data line DL.
  • the thin film transistors Tr 1 and Tr 2 constituting the pixel drive circuit DCx perform the on operation, and the low-level power supply voltage Vscl is applied to the junction N 1 (that is, the gate terminal of the thin film transistor Tr 3 and one end of the capacitor Cs), and the operation to pull in the gradation current having the negative polarity (-Ipix) via the data line DL is carried out.
  • a voltage level having a lower potential than the low-level power supply voltage Vscl is applied to the junction N 2 (that is, the source terminal of the thin film transistor Tr 3 and the other end of the capacitor Cs).
  • the thin film transistors Tr 1 and Tr 2 constituting the pixel drive circuit DCx perform the off operation, application of the power supply voltage Vsc to the junction N 1 (that is, the gate terminal of the thin film transistor Tr 3 and one end of the capacitor Cs) is interrupted, and application of the voltage level to the junction N 2 (that is, the source terminal of the think film transistor Tr 3 and the other end of the capacitor Cs) due to the operation to pull in the gradation current by the data driver 130 is interrupted.
  • the capacitor Cs holds the electric charges stored in the above-described write operation.
  • the capacitor Cs holds the charge voltage in the write operation, and a potential difference between the junctions N 1 and N 2 (between the gate and the source of the thin film transistor Tr 3 ) is thereby held and the thin film transistor Tr 3 maintains the on state. Further, since a power supply voltage Vsch having a voltage level higher than the ground potential is applied to the power supply line VL, the potential applied to the anode terminal (junction N 2 ) of the organic EL element OEL becomes higher than the potential (ground potential) of the cathode terminal.
  • a predetermined drive current Ib flows through the organic EL element OEL from the power supply line VL through the thin film transistor Tr 3 and the junction N 2 in a forward bias direction, and the organic EL element OEL emits the light.
  • the potential difference (charge voltage) held by the capacitor Cs corresponds to a potential difference when causing the write current Ia corresponding to the gradation current Ipix to flow in the thin film transistor Tr 3
  • the drive current flowing through the organic EL element OEL has a current value equivalent to the write current Ia.
  • the drive current is continuously supplied through the thin film transistor Tr 3 based on a voltage component corresponding to the display data (gradation current) written in the selection period Tse.
  • the organic EL element OEL continues the operation to emit the light with the brightness gradation corresponding to the display data.
  • the thin film transistors Tr 1 to Tr 3 applied to the pixel drive circuit according to this embodiment are not particularly restricted, all of the thin film transistors Tr 1 to Tr 3 can be constituted by n-channel type transistors, and hence an n-channel type amorphous silicon TFT can be excellently applied. In such a case, the pixel drive circuit having the stable drive characteristic can be relatively inexpensively manufactured by applying the already established manufacturing technique.
  • the potential difference (charge voltage) held in the capacitor Cs becomes a potential difference required for passing the write current Ia corresponding to the gradation current Ipix to the thin film transistor Tr 3 . Therefore, the drive current Ib flowing down through the organic EL element OEL is maintained at a current value equivalent to the write current Ia. Thus, it is possible to suppress degradation of the display state such as generation of display irregularities due to an aged change, thereby maintaining the excellent display state.
  • FIG. 20 is a schematic block diagram showing a primary structure of another example of the display apparatus according to the present invention.
  • the display apparatus (display panel) adopting the active matrix type drive mode including the pixel drive circuit for each display pixel of the display panel
  • the present invention is not restricted thereto.
  • a simple matrix (passive matrix) type display panel such as an organic EL element OEL or a light emitting diode LED having an anode and a cathode respectively connected to the scanning line and the data line in the vicinity of an intersection of the data line DL extending from the data driver 130 B and the scanning line SL extending from the scanning driver 120 B.
  • OEL organic EL element
  • a light emitting diode LED having an anode and a cathode respectively connected to the scanning line and the data line in the vicinity of an intersection of the data line DL extending from the data driver 130 B and the scanning line SL extending from the scanning driver 120 B.
  • the light emitting diode LED is used as the light emitting element.
  • the gradation control can be executed by individually supplying the light emitting drive current having a predetermined current value corresponding to the display data to each light emitting element, the excellent multi-gradation display can be realized while increasing the display speed of image information.
  • the single current generation circuit currents having a predetermined fixed current value are generated, the currents are sequentially fetched and held in the respective current storage circuits provided in accordance with a plurality of the output terminals of the respective driver chips, and the held currents are simultaneously outputted to the respective data lines arranged in the display panel through the respective output terminals in a predetermined display period in an individual supply time (pulse width) based on the display data consisting of the digital signals by applying the known pulse width modulation (PWM) drive mode.
  • PWM pulse width modulation
  • a display apparatus including the image drive circuit to which a current specification mode including a conformation to apply the gradation current from the data line is applied as well as a current specification mode which pulls in the gradation current from the data line, has a light emitting control transistor which controls supply of the drive current to the light emitting element and a write control transistor which controls the write operation of the gradation current, supplies the drive current by causing the light emitting control transistor to perform the on operation based on the write current after holding the write current according to the display data, and causes the light emitting elements to emit the light with a predetermined brightness gradation.
  • the light emitting element arranged in each display pixel is not particularly restricted, and it is possible to adopt any other light emitting element than the organic EL element or the light emitting diode described above as long as it performs the light emitting operation with a predetermined brightness gradation according to a current value of the light emitting drive current supplied thereto.
  • the current drive apparatus according to the present invention is not restricted to such a display drive apparatus.
  • the current drive apparatus it is possible to apply the current drive apparatus to a drive circuit of a device including many elements which drive by application of a current, such as a drive circuit of a printer head formed by arranging many light emitting diodes.
  • the current drive apparatus according to the present invention to the signal drive circuit (data driver) of the display apparatus, it is possible to suppress irregularities in the drive current between the driver chips (semiconductor chips) and between the output terminals provided to the same driver chip and restrain generation of display irregularities, thereby improving the display image quality.

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KR20040034684A (ko) 2004-04-28
CN101276540B (zh) 2010-09-01
CA2462134A1 (en) 2004-01-08
CN101276540A (zh) 2008-10-01
DE60336109D1 (de) 2011-04-07
CA2462134C (en) 2010-01-05
ATE499674T1 (de) 2011-03-15
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US20080174527A1 (en) 2008-07-24
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US8094095B2 (en) 2012-01-10

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