US20040238895A1 - Semiconductor device with silicon-germanium gate electrode and method for manufacturing thereof - Google Patents

Semiconductor device with silicon-germanium gate electrode and method for manufacturing thereof Download PDF

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US20040238895A1
US20040238895A1 US10/840,258 US84025804A US2004238895A1 US 20040238895 A1 US20040238895 A1 US 20040238895A1 US 84025804 A US84025804 A US 84025804A US 2004238895 A1 US2004238895 A1 US 2004238895A1
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film
sige
forming
cap
semiconductor device
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Akiyoshi Mutou
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Sharp Corp
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Semiconductor Leading Edge Technologies Inc
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    • A—HUMAN NECESSITIES
    • A63—SPORTS; GAMES; AMUSEMENTS
    • A63J—DEVICES FOR THEATRES, CIRCUSES, OR THE LIKE; CONJURING APPLIANCES OR THE LIKE
    • A63J1/00—Stage arrangements
    • A63J1/02—Scenery; Curtains; Other decorations; Means for moving same
    • A63J1/028—Means for moving hanging scenery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/2807—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B66—HOISTING; LIFTING; HAULING
    • B66D—CAPSTANS; WINCHES; TACKLES, e.g. PULLEY BLOCKS; HOISTS
    • B66D1/00—Rope, cable, or chain winding mechanisms; Capstans
    • B66D1/60—Rope, cable, or chain winding mechanisms; Capstans adapted for special purposes

Definitions

  • the present invention relates to a semiconductor device and to a method for manufacturing thereof. More specifically the present invention relates to a gate electrode including a thin SiGe film and to a method for manufacturing thereof.
  • MOSFET metal oxide semiconductor field effect transistor
  • SiGe silicon germanium
  • MOSFET silicon germanium
  • the width of the gate electrode (hereafter referred to as “gate length”) must be reduced with the above-described miniaturization of the MOSFET, the thickness of the gate electrode must also be reduced from the point of view of the stability and the processing accuracy of gate wiring patterns. For example, according to the ITRS Roadmap of 2001 Edition, the thickness of a gate electrode must be reduced to 35 nm to 70 nm in a semiconductor device of the 35-nm-gate-length generation.
  • a silicide film may be formed above the SiGe film.
  • the thickness reduction of the SiGe film as the gate electrode is demanded. Furthermore, when a cap Si film is formed on the SiGe film to form a silicide film, since the thickness of the SiGe film must be the value of the entire thickness of the gate electrode minus the thickness of the silicon film, the SiGe film must further be thinned.
  • FIGS. 13A to 13 C are SEM photographs showing the cross section of the thinned SiGe film grown on a gate dielectric film composed of a SiO 2 film. Specifically, FIG. 13A shows the case where the SiGe film of a thickness of 150 nm is formed, FIG. 13B shows the case where the SiGe film of a thickness of 50 nm is formed, and FIG. 13C shows the case where the SiGe film of a thickness of 20 nm is formed.
  • FIG. 13A shows, when the SiGe film is relatively thick (150 nm), the continuous film free of voids is attained.
  • FIG. 13B shows, when the growth time is shortened to make the thickness of the SiGe film 50 nm, voids (refer to circled portions in FIG. 13B) generate in the SiGe film.
  • the growth time is further shortened to make the thickness of the SiGe film 20 nm, the film becomes discontinuous due to surface roughness as FIG. 13C shows.
  • the above-described defective film is formed due to the thinning of the SiGe film, it is difficult to form the SiGe film having a uniform Ge content in the boundary between the gate dielectric film and the gate electrode.
  • a gate electrode is formed using dry etching, locally defective processing caused by the non-uniformity of the thickness of the SiGe film. Since the voids generated in the SiGe film causes variation in the wiring resistance of the gate wirings and the driving ability of the transistor, the yield of transistor manufacturing is affected.
  • the present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide novel and useful method for manufacturing a semiconductor device.
  • a more specific object of the present invention is to form a high-quality thin SiGe film free of voids on a gate dielectric film.
  • the semiconductor device comprises a gate dielectric film formed on a substrate and a gate electrode formed on the gate dielectric film.
  • the gate electrode includes a seed Si film formed on the gate dielectric film; a thin SiGe film formed on the seed Si film and having a thickness of 50 nm or less; and a thin cap Si film formed on the thin SiGe film and having a thickness of 0.5 nm to 5 nm.
  • a gate dielectric film is first formed on a substrate.
  • a seed Si film is formed on the gate dielectric film.
  • a thin SiGe film on the seed Si film at a temperature between 450° C. and 494° C., and a thin cap Si film is continuously formed with a thickness of 0.5 nm to 5 nm on the thin SiGe film at the same temperature.
  • the thin cap Si film, the thin SiGe film, and the seed Si film is patterned to form a gate electrode. Source-drain regions are formed in an upper layer of the substrate through ion implantation using the gate electrode as a mask.
  • a gate dielectric film is first formed on a substrate.
  • a seed Si film is formed on the gate dielectric film.
  • a thin SiGe film is formed on the seed Si film at a temperature between 450° C. and 494° C., and a thin cap Si film is continuously formed with a thickness of 0.5 nm to 5 nm on the thin SiGe film at the same temperature.
  • An upper Si film is formed on the thin cap Si film at a temperature higher than a temperature of forming the thin SiGe film.
  • the upper Si film, the thin cap Si film, the thin SiGe film, and the seed Si film are patterned to form a gate electrode. Source-drain regions are formed in an upper layer of the substrate through ion implantation using the gate electrode as a mask.
  • FIG. 1 is a schematic cross-sectional view for illustrating a semiconductor device according to a first embodiment of the present invention
  • FIGS. 2A to 2 D are process sectional views for illustrating a method for manufacturing the semiconductor device shown in FIG. 1:
  • FIGS. 3A and 3B are graphs showing the relationship between the Ge content in a thin SiGe film and the depletion rate in an MOS capacitor;
  • FIG. 4 is a graph showing the relationship between the growth temperature of a thin SiGe film, and the growth rate and the uniformity of the film thickness on the surface of the thin SiGe film;
  • FIGS. 5A to 5 C are SEM photographs showing the cross sections of a thin SiGe film when the growth pressure of the thin SiGe film was varied
  • FIGS. 6A and 6B are SEM photographs showing the cross sections of a thin SiGe film as formed and after forming a thin cap Si film thereon;
  • FIG. 7 is a schematic cross-sectional view for illustrating a semiconductor device according to a second embodiment of the present invention.
  • FIG. 8 is a process sectional view for illustrating a method for manufacturing the semiconductor device according to a second embodiment of the present invention.
  • FIGS. 9A and 9B are SEM photographs showing the cross sections of the thin SiGe film after heat treatment corresponding to the growth of the upper Si film in the case when a thin cap Si film is formed and not formed on the thin SiGe film;
  • FIGS. 10A and 10B are SEM photographs showing the cross sections of a thin SiGe film when the growth temperature of the upper Si film is changed in the formation of the upper Si film on the thin SiGe film through the thin cap Si film;
  • FIG. 11 is a schematic cross-sectional view for illustrating a semiconductor device according to a third embodiment of the present invention.
  • FIGS. 12A and 12B are process sectional views for illustrating a method for manufacturing the semiconductor device according to a third embodiment of the present invention.
  • FIG. 13 is a schematic cross-sectional view for illustrating a semiconductor device according to a fourth embodiment of the present invention.
  • FIGS. 14A and 14B are process sectional views for illustrating a method for manufacturing the semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 15 is a schematic cross-sectional view for illustrating a semiconductor device according to a fifth embodiment of the present invention.
  • FIGS. 16A and 16B are process sectional views for illustrating a method for manufacturing the semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 17 is a schematic cross-sectional view for illustrating a semiconductor device according to a sixth embodiment of the present invention.
  • FIG. 18 is a schematic cross-sectional view for illustrating a semiconductor device according to a seventh embodiment of the present invention.
  • FIGS. 19A to 19 C are SEM photographs showing the cross section of the thinned SiGe film grown on a gate dielectric film composed of a SiO 2 film.
  • FIG. 1 is a schematic cross-sectional view for illustrating a semiconductor device according to a first embodiment of the present invention.
  • a silicon substrate serving as the substrate 2 has element regions on which semiconductor elements such as transistors are formed, and isolation regions for isolating the element regions, in which field insulating films (also referred to as “element-isolating insulating films”) 4 are formed.
  • Well regions are formed in the element regions of the substrate 2 .
  • a gate dielectric film 6 is formed on the substrate 2 in the element regions.
  • a SiO 2 film, a Si 3 N 4 film, or a SiON film (hereafter collectively referred to as “SiO 2 film or the like”) can be used.
  • the thickness of the gate dielectric film 6 composed of a SiO 2 film or the like is, for example, 1.0 nm to 1.5 nm.
  • a high-dielectric-constant film high-k dielectric film
  • a laminated film composed of a SiO 2 film or the like and a high-dielectric-constant film can also be used as the gate dielectric film 6 .
  • the thickness of the SiO 2 film or the like is less than 1.0 nm.
  • the high-dielectric-constant film for example, a metal oxide such as Al 2 O 3 , HfO 2 , ZrO 2 , and La 2 O 3 , a metal nitride, a metal oxynitride, a metal silicate such as HfSiO x and ZrSiO x , or a metal aluminate such as HfAlO x and ZrAlO x , can be used.
  • a gate electrode composed of the laminate of a seed Si film 8 , a thin SiGe film 10 , and a thin cap Si film 12 .
  • Source-drain regions 14 sandwiching a channel region (not shown) underneath the gate electrode are formed in the upper layer of the silicon substrate 2 .
  • an amorphous Si film serving as the seed Si film 8 .
  • the thickness of the seed Si film 8 is preferably 1 nm to 5 nm.
  • a thin SiGe film 10 As a lower electrode film.
  • the thickness of the thin SiGe film 10 is preferably 50 nm or below.
  • the thin SiGe film 10 is represented by a composition formula of Si (1-x) Ge x , and the Ge content X is preferably 0.15 or more and smaller than 0.4 (15% or more and smaller than 40%), and more preferably about 0.3 (30%) (described later).
  • the thin SiGe film 10 is preferably grown at a growth temperature of 450° C. or above and below 494° C. (described later).
  • the thin SiGe film 10 is also preferably a polycrystalline thin SiGe film grown under a growth pressure of 30 Pa or amorphous SiGe grown under a growth pressure 150 Pa or above (described later).
  • a thin cap Si film 12 On the thin SiGe film 10 is formed a thin cap Si film 12 .
  • the thickness of the thin cap Si film 12 is preferably 0.5 nm to 5 nm (described later). It is preferable that the thin SiGe film 10 and the thin cap Si film 12 are continuously formed using the same apparatus at the same temperature.
  • FIGS. 2A to 2 D are process sectional views for illustrating a method for manufacturing the semiconductor device shown in FIG. 1.
  • FIG. 2A shows, field insulating films 4 are formed in the isolation regions of a silicon substrate 2 using STI (shallow trench isolation) method. Then, the ions of a conductive impurity are implanted into the element regions (not shown) of the silicon substrate 2 , and annealing is performed to form well regions.
  • STI shallow trench isolation
  • a SiO 2 film or the like (described above) with a thickness of, for example, 1.0 nm to 1.5 nm is formed as a gate dielectric film 6 on the silicon substrate 2 using a method such as thermal oxidation (or thermal nitriding or thermal oxynitriding) or plasma oxidation (or plasma nitriding or plasma oxynitriding).
  • a high-k dielectric film can be formed as the gate dielectric film 6 in place of the SiO 2 film or the like, or together with the SiO 2 film or the like.
  • the thickness of the SiO 2 film or the like is less than 1.0 nm.
  • the high-k dielectric film can be grown using an ALD (atomic layer deposition) method or an MOCVD (metal organic chemical vapor deposition) method.
  • an amorphous Si film as a seed Si film 8 with a thickness of, for example, 1 nm to 5 nm is formed on the gate dielectric film 6 using a CVD (chemical vapor deposition) method.
  • CVD chemical vapor deposition
  • a batch-type vertical LPCVD apparatus can be used for the formation of the seed Si film 8 .
  • the conditions for forming the seed Si film 8 in the LPCVD apparatus are, for example, an SiH 4 flow rate of 1 slm, a growth temperature of 475° C., and a growth time of 5 to 20 minutes.
  • FIG. 2B shows, a thin SiGe film 10 is formed on the seed Si film 8 using the above-described LPCVD apparatus. Specifically, the seed Si film 8 and the thin SiGe film 10 are continuously formed.
  • the Ge content X in the thin SiGe film 10 represented by the composition formula, Si (1-x) Ge x is preferably 0.15 or more and smaller than 0.4 (15% or more and smaller than 40%), and most preferably 0.3 (30%).
  • the own examinations by the present inventor on the Ge content will be described below.
  • the present inventor examined the relationship between the Ge content in a thin SiGe film formed on a gate dielectric film through a seed Si film and the depletion rate in an MOS capacitor.
  • FIGS. 3A and 3B are graphs showing the relationship between the Ge content in a thin SiGe film and the depletion rate in an MOS capacitor.
  • FIGS. 3A and 3B are graphs showing the Ge-content dependency of the depletion rate in an MOS capacitor.
  • FIG. 3A is a graph showing the Ge-content dependency of the depletion rate in a PMOS capacitor
  • FIG. 3B is a graph showing the Ge-content dependency of the depletion rate in an NMOS capacitor.
  • the depletion rate means the percentage of the inverted capacitance to the accumulated capacitance in an MOS capacitor.
  • FIG. 3A shows, the depletion rate on a PMOS capacitor is improved with increase in the Ge content, and although the improving effect is not satisfactory when the Ge content is less than 0.15 (15%), the improving effect is saturated when the Ge content is 0.3 (30%) or more. This shows that increase in the Ge content to 0.15 (15%) or more improves the depletion rate of the PMOS capacitor, and improve the driving ability of the PMOS transistor.
  • FIG. 3B shows, although the depletion rate of an NMOS capacitor little changes when the Ge content is 0.3 (30%) or less, the depletion rate is lowered when the Ge content is 0.4 (40%), and the driving ability of the NMOS transistor is lowered.
  • the Ge content in the thin SiGe film 10 is preferably 0.15 or more and smaller than 0.4 (15% or more and smaller than 40%), and most preferably 0.3 (30%) as described above.
  • the growth temperature of the thin SiGe film 10 is preferably 450° C. or above and 494° C. or below, and most preferably 475° C.
  • the own examinations by the present inventor on the growth temperature will be described below.
  • the present inventor examined the relationship between the growth temperature of a thin SiGe film formed on a gate dielectric film composed of a SiO 2 film through a seed Si film, and the growth rate and the uniformity of the film thickness on the surface of the thin SiGe film.
  • FIG. 4 is a graph showing the relationship between the growth temperature of a thin SiGe film, and the growth rate and the uniformity of the film thickness on the surface of the thin SiGe film.
  • the uniformity of the film thickness on the surface means the variation ⁇ (%) of the thickness of the thin SiGe film measured at 49 points on the surface.
  • the thin SiGe film having a Ge content of 0.3 (30%) was grown under a flow-rate ratio of H 2 -diluted 10% GeH 4 to SiH 4 of 0.96.
  • the growth rate increases with the elevation of the growth temperature, the uniformity of the film thickness on the surface of the thin SiGe film (film thickness variation ⁇ ) worsens.
  • the value of film thickness variation ⁇ increases to larger than 2%, and the uniformity of the film thickness on the surface worsens. If the growth temperature is even higher, the value of the surface roughness of the thin SiGe film increases, and the consequent etching process of the gate electrode will become difficult.
  • the growth temperature is preferably 494° C. or below, and more preferably 475° C.
  • the growth temperature of below 450° C. is not preferable from the point of view of productivity, because the growth rate of the thin SiGe film is lowered, and therefore the throughput is lowered.
  • the growth temperature of the thin SiGe film 10 is preferably 450° C. or above and 494° C. or below, and most preferably 475° C.
  • the quality of the thin SiGe film 10 varies depending on the growth pressure.
  • the growth pressure of the thin SiGe film 10 is preferably below 30 Pa, or 150 Pa or above, and more preferably 10 Pa.
  • the own investigation by the present inventor will be described below.
  • the present inventor investigated the conformation of the thin SiGe film by varying the growth pressure of the thin SiGe film formed on a gate dielectric film composed of a SiO 2 film through a seed Si film.
  • FIGS. 5A to 5 C are SEM photographs showing the cross sections of a thin SiGe film when the growth pressure of the thin SiGe film was varied. Specifically, FIGS. 5A, 5B, and 5 C are SEM photographs showing film morphology of thin SiGe film when the growth pressure of the thin SiGe film was 30 Pa, 20 Pa, and 200 Pa, respectively.
  • FIG. 5A shows, when the thin SiGe film was formed under a pressure of 30 Pa, voids (in the circled portions) were formed in the thin SiGe film.
  • FIG. 5B shows, when the thin SiGe film was formed under a pressure of 20 Pa, the number of voids (in the circled portions) decreased significantly, and the film quality was improved.
  • the film deposition rate is low when the thin SiGe film is grown under a pressure lower than 30 Pa, impurities such as hydrogen are released during the deposition of the film, and a polycrystalline thin SiGe film having a low impurity content and a low amorphous-component content can be formed.
  • a void-free polycrystalline thin SiGe film of small volume change due to change in temperature that excels in thermal stability can be obtained.
  • FIG. 5C shows, when the thin SiGe film was formed under a pressure of 200 Pa, no voids were formed in the thin SiGe film, and the surface roughness was significantly improved. This is because the film deposition rate is high when the thin SiGe film is grown under a pressure of 200 Pa or above, and the deposition of film is quicker than the crystalline growth of the film.
  • the results of X-ray diffraction analysis showed that the thin SiGe film was amorphous. Thereby, a viod-free amorphous thin SiGe film that excels in surface flatness can be obtained.
  • the growth pressure of the thin SiGe film 10 is preferably below 30 Pa, or 150 Pa or above, and more preferably 10 Pa.
  • FIG. 2B shows, a thin cap Si film 12 is formed on the thin SiGe film 10 using the above-described LPCVD apparatus. Specifically, the thin SiGe film 10 and the thin cap Si film 12 are continuously formed at the same temperature.
  • the present inventor examined the effect of forming the thin cap Si film 12 on the thin SiGe film 10 .
  • FIGS. 6A and 6B are SEM photographs showing the cross sections of a thin SiGe film as formed and after forming a thin cap Si film thereon.
  • the Ge content in the thin SiGe film is 0.3 (30%)
  • the growth temperature is 475° C.
  • the growth pressure is 10 Pa
  • the thickness of the grown film is 50 nm.
  • the growth temperature of the thin cap Si film is 475° C., the same as the growth temperature of the thin SiGe film
  • the flow rate of SiH 4 is 1 slm
  • the thickness of the grown film is 5 nm.
  • the present inventor confirmed the growth rate of the thin cap Si film is 0.25 nm/min at the above-described growth condition.
  • the cap Si film cannot be thickened, i.e. the thick cap Si film cannot be applied to the mass production, since throughput is lowered.
  • the growth temperature is raised for improving the throughput, there are problems that voids generate in the thin SiGe film and the surface of the SiGe film is roughened.
  • FIG. 6A shows, when the thin cap Si film is not formed, that is, immediately after forming the thin SiGe film 10 , there are voids in the thin SiGe film 10 (in the circled portions).
  • FIG. 6B shows, by forming the thin cap Si film 12 , voids in the thin SiGe film 10 disappear, and a high-quality thin SiGe film can be obtained.
  • the reason why voids disappear is that the formation of the thin cap Si film 12 lowers the surface energy compared with the case when the thin SiGe film 10 is exposed on the surface, and thermally stabilizes the thin SiGe film 10 .
  • the present inventor confirmed the problems of increase in surface roughness of the thin SiGe film and the formation of voids in the film when the thin SiGe film 10 and the thin cap Si film 12 are not continuously formed, or not formed at the same temperature, that is, the temperature is changed.
  • Increase in surface roughness causes increase in non-uniformity of impurity introduction in the consequent process, or increase in non-uniformity of gate processing.
  • the formation of voids deteriorates electrical properties due to the acceleration of the reduction and decomposition of the gate dielectric film even if the voids are minute.
  • the occurrence of such problems can be prevented by continuously forming the thin SiGe film 10 and the thin cap Si film 12 at the same temperature.
  • the thin cap Si film 12 , the thin SiGe film 10 , the seed Si film 8 , and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed.
  • conductive impurity ions are implanted using the gate electrode as the mask to form the source-drain region 14 on the upper layer of the silicon substrate 2 .
  • the thin SiGe film 10 is formed on the gate dielectric film 6 through the seed Si film 8 at low growth temperature (450° C. or above and 494° C. or below), and a thin cap Si film 12 of a thickness of 0.5 nm to 5 nm is formed thereon at the same growth temperature.
  • a void-free high-quality thin SiGe film 10 can be formed on the gate dielectric film 6 .
  • the thin SiGe film 10 that excels in the uniformity of film thickness can be formed in the boundary between the gate dielectric film 6 and the gate electrode, and a uniform Ge content in the boundary can be achieved.
  • the thickness of the thin SiGe film 10 can be reduced, and high-performance transistors can be manufactured in high reproducibility. Further a high quality thin SiGe film can be attained with restraint of deterioration of throughput, since the thickness of the thin cap Si film 12 is within the range of 0.5 nm to 5 nm.
  • the thin SiGe film 10 is a thin film having a favorable film-thickness uniformity, local defective processing such as the dent of the silicon substrate 2 caused by voids in the thin SiGe film during dry etching for forming the gate electrode can be avoided. Thereby, the process margin in the gate processing can be enlarged, and high-performance transistors can be stably manufactured.
  • FIG. 7 is a schematic cross-sectional view for illustrating a semiconductor device according to a second embodiment of the present invention.
  • the semiconductor device according to the second embodiment shown in FIG. 7 differs from the above-described semiconductor device according to the first embodiment in that an upper Si film 16 is further formed on the thin cap Si film 12 .
  • a gate electrode formed on a silicon substrate 2 through a gate dielectric film 6 comprises a seed Si film 8 , a thin SiGe film 10 of a thickness of 50 nm or below, a thin cap Si film 12 of a thickness of 0.5 nm to 5 nm, and an upper Si film 16 of a thickness of 60 nm to 120 nm.
  • the total thickness of the gate electrode is preferably 80 nm to 160 nm.
  • FIG. 8 is a process sectional view for illustrating a method for manufacturing the semiconductor device according to the second embodiment.
  • an upper Si film 16 is formed on the thin cap Si film 12 using a LPCVD method.
  • the upper Si film 16 can be formed using the above-described batch-type vertical LPCVD apparatus, and the growth conditions of the upper Si film 16 are, for example, an SiH 4 flow rate of 1 slm, a growth temperature of 530° C., and a growth pressure of 100 Pa.
  • the present inventor examined the effect obtained from the structure having the thin cap Si film 12 underneath the upper Si film 16 .
  • FIGS. 9A and 9B are SEM photographs showing the cross sections of the thin SiGe film after heat treatment corresponding to the growth of the upper Si film in the case when a thin cap Si film is formed and not formed on the thin SiGe film.
  • FIG. 9B is a photograph showing the state of the thin SiGe film after the heat treatment corresponding to the growth of the upper Si film 16 without forming a thin cap Si film after forming a thin SiGe film on the gate dielectric film through a seed Si film; and FIG.
  • FIG. 9B is a photograph showing the state of the thin SiGe film after the heat treatment corresponding to the growth of the upper Si film 16 when a thin cap Si film is formed on the thin SiGe film after forming the thin SiGe film on the gate dielectric film through a seed Si film.
  • the Ge content of the thin SiGe film is 0.3 (30%)
  • the growth temperature is 475° C.
  • the thickness of the grown film is 40 nm
  • the growth pressure is 200 Pa.
  • heat treatment corresponding to the growth of the upper Si film 16 heat treatment is performed at a temperature of 530° C. for about 60 minutes. This heat treatment corresponds the growth of the upper Si film with a thickness of 120 nm.
  • FIG. 9A shows, when no thin cap Si film is formed, the film configuration of the thin SiGe film, which was continuous and flat before heat treatment (i.e., immediately after the growth of the thin SiGe film) is significantly changed, the surface roughness is enlarged, and a discontinuous film is formed (refer to the circled portion in FIG. 9A). In addition, voids are formed in the thin SiGe film after heat treatment.
  • FIG. 9B shows, when the thin cap Si film is formed, the thin SiGe film after heat treatment is maintained continuous, and the flatness is also maintained. Furthermore, no voids are formed in the thin SiGe film after heat treatment.
  • the formation of the thin cap Si film 12 between the thin SiGe film 10 and the upper Si film 16 can restrict the formation of voids in the thin SiGe film during the formation of the upper Si film 16 .
  • the temperature for forming the upper Si film 16 is preferably higher than the temperature for forming the underlying thin cap Si film 12 and the thin SiGe film 10 , for example, 530° C. to 620° C. Since the formation of the upper Si film 16 at such a high temperature increases the growth rate and improves the throughput, the productivity of semiconductor device is improved.
  • FIGS. 10A and 10B are SEM photographs showing the cross sections of a thin SiGe film when the growth temperature of the upper Si film is changed in the formation of the upper Si film on the thin SiGe film through the thin cap Si film after forming the thin SiGe film on the gate dielectric film through the seed Si film.
  • FIG. 10A is a photograph showing the state of the laminated film when the upper Si film is formed under the condition of an SiH 4 flow rate of 1 slm, a temperature of 530° C., and a pressure of 100 Pa; and FIG.
  • 10B is a photograph showing the state of the laminated film when the upper Si film is formed under the condition of an SiH 4 flow rate of 0.6 slm, a temperature of 620° C., and a pressure of 20 Pa.
  • the Ge content of the thin SiGe film is 0.3 (30%)
  • the growth temperature is 475° C.
  • the thickness of the grown film is 40 nm.
  • the growth temperature of the thin cap Si film is 475° C., the same as the growth temperature of the thin SiGe film, and the thickness of the grown film is 5 nm.
  • FIGS. 10A and 10B show, when the upper Si film is formed under either condition, no voids are formed in the thin SiGe film, and a continuous thin SiGe film can be formed.
  • the upper Si film 16 , the thin cap Si film 12 , the thin SiGe film 10 , the seed Si film 8 , and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed. Finally, conductive impurity ions are implanted using the gate electrode as the mask to form the source-drain region 14 in the upper layer of the silicon substrate 2 . Performing the above-described processes attains the semiconductor device shown in FIG. 7.
  • a thin SiGe film 10 is formed on a gate dielectric film 6 through a seed Si film 8 at low growth temperature, and a thin cap Si film 12 of a thickness of 0.5 nm to 5 nm is continuously formed thereon at the same growth temperature.
  • a void-free high-quality thin SiGe film 10 can be formed on the gate dielectric film 6 .
  • the uniform thin SiGe film 10 can be formed in the boundary between the gate dielectric film 6 and the gate electrode, and a uniform Ge content in the boundary can be achieved. Therefore, the thickness of the thin SiGe film 10 can be reduced, and high-performance transistors can be manufactured in high reproducibility.
  • the thin SiGe film 10 is a thin film having a favorable film-thickness uniformity, local defective processing such as the dent of the silicon substrate 2 caused by voids in the thin SiGe film 10 during dry etching for forming the gate electrode can be avoided. Thereby, the process margin in the gate processing can be enlarged, and high-performance transistors can be stably manufactured.
  • an upper Si film 16 is formed on the thin cap Si film 12 at a temperature higher than the growth temperature of the thin SiGe film 10 . Therefore, the throughput is increased, and the productivity is improved, since the upper Si film 16 is formed at high deposition rate with maintaining quality of the thin SiGe film 10 .
  • FIG. 11 is a schematic cross-sectional view for illustrating a semiconductor device according to a third embodiment of the present invention.
  • the semiconductor device according to the third embodiment shown in FIG. 11 differs from the above-described semiconductor device according to the second embodiment in that sides of the gate electrode are covered by sidewalls 20 , and that silicide layers 22 are formed in upper portions of the upper Si film 16 and source-drain regions 14 . Further, extension regions 18 having an impurity concentration lower than the source-drain regions 14 in the substrate 2 below the sidewalls 20 .
  • the semiconductor device has the silicide layers 22 formed using a well-known salicide technique in uppermost layer of the gate electrode and the source-drain regions 14 .
  • the thickness of NiSi layers serving as the silicide layers 22 is, for example, about 10 nm.
  • FIGS. 12A and 12B are process sectional views for illustrating a method for manufacturing the semiconductor device according to a third embodiment of the present invention.
  • the upper Si film 16 , the thin cap Si film 12 , the thin SiGe film 10 , the seed Si film 8 , and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art.
  • FIG. 12A shows, extension regions 18 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a low concentration using the gate electrode as a mask.
  • an insulating film such as SiO 2 or Si 3 N 4 is formed over the entire of the substrate 2 , and the insulating film is etched using an anisotropic dry etching method.
  • sidewalls 20 are formed on the sides of the gate electrode.
  • Source-drain regions 14 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a high concentration using the gate electrode and sidewalls 20 as a mask.
  • Ni film/TiN film are formed with thickness of 11 nm/10 nm over the entire of the substrate, and a heat treatment is performed.
  • Ni film is reacted with the upper Si film 16 and the source-drain regions 14 , and NiSi layers 22 are formed.
  • quality of the thin SiGe film is maintained during the heat treatment by the presence of the cap Si film 12 .
  • the semiconductor device shown in FIG. 11 is attained by getting rid of the Ni film/TiN film which has not reacted using chemical solution.
  • the NiSi layers 22 are formed in upper portions of the upper Si film 16 and source-drain regions 14 using salicide technique.
  • the quality of the thin SiGe film 10 can be maintained even if the heat treatment for forming the NiSi layers 22 is done in addition to the effects attained in the second embodiment.
  • FIG. 13 is a schematic cross-sectional view for illustrating a semiconductor device according to a fourth embodiment of the present invention.
  • the semiconductor device according to the fourth embodiment shown in FIG. 13 differs from the above-described semiconductor device according to the first embodiment in that thin SiGe film 10 made by stacking a plurality of SiGe layers 10 a and 10 b . This difference will be described as follows.
  • the thin SiGe film 10 by stacking a first SiGe layer 10 a and a second SiGe layer 10 b .
  • the first and second SiGe layers 10 a and 10 b differ in Ge content X of formula Si (1-x) Ge x representing the first and second SiGe layers 10 a and 10 b respectively.
  • the first and second SiGe layers 10 a and 10 b are continuously formed at the same growth temperature.
  • each Ge content X of the SiGe layers 10 a and 10 b is 0.15 or more and smaller than 0.4.
  • the film thickness of the first SiGe layer 10 a may differ from the film thickness if the second SiGe layer 10 b .
  • Total thickness of the SiGe layers 10 a and 10 b is preferably 50 nm or below.
  • the thin cap Si film 12 of the thickness of 0.5 nm to 5 nm.
  • the first and second SiGe layer 10 a and 10 b and the thin cap Si film 12 are continuously formed at the same temperature.
  • FIGS. 14A and 14B are process sectional views for illustrating a method for manufacturing the semiconductor device according to the fourth embodiment.
  • the gate dielectric film 6 is formed on the substrate 2 , and the seed Si film 8 is formed on the gate dielectric film 6 .
  • the first SiGe layer 10 a is formed on the seed Si film 8
  • the second SiGe layer 10 b is formed on the first SiGe layer 10 a
  • the thin cap Si film 12 is formed on the second SiGe layer 10 b .
  • the forming temperature is preferably 450° C. or above and 494° C. or below, and most preferably 475° C.
  • the first and second SiGe layers having different Ge content are formed by changing the flow-rate ratio of H 2 -diluted 10% GeH 4 to SiH 4 .
  • FIG. 14B shows, the thin cap Si film 12 , the second SiGe layer 10 b , the first SiGe layer 10 a , the seed Si film 8 , and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed.
  • conductive impurity ions are implanted using the gate electrode as the mask to form the source-drain region 14 in the upper layer of the silicon substrate 2 . Performing the above-described processes attains the semiconductor device shown in FIG. 13.
  • the thin SiGe film 10 is formed by two SiGe layers 10 a and 10 b
  • the thin SiGe film 10 may be formed by stacking three or more SiGe layers.
  • the thin SiGe film 10 is formed by the SiGe layers having different Ge content
  • the thin SiGe film 10 may be formed by stacking an amorphous SiGe layer and a polycrystalline SiGe layer.
  • the amorphous SiGe layer can be grown under a growth pressure 150 Pa
  • the polycrystalline SiGe layer can be grown under a growth pressure of 30 Pa.
  • an upper Si may be formed on thin cap Si film 12 using the same manner as in the manufacturing method according to the second embodiment (The same applies to second to fifth embodiments described later.).
  • FIG. 15 is a schematic cross-sectional view for illustrating a semiconductor device according to a fifth embodiment of the present invention.
  • the gate electrode comprises a plurality of SiGe layers 10 a and 10 b and a plurality of thin cap Si films 12 a and 12 b .
  • the SiGe layers and the thin cap films are stacked alternately.
  • each Ge content X of the SiGe layers 10 a and 10 b is 0.15 or more and smaller than 0.4.
  • the film thickness of the first SiGe layer 10 a may differ from the film thickness if the second SiGe layer 10 b .
  • Total thickness of the SiGe layers 10 a and 10 b is preferably 50 nm or below.
  • the each film thickness of the first and second thin cap Si films 12 a and 12 b is preferably 0.5 nm to 5 nm.
  • FIGS. 16A and 16B are process sectional views for illustrating a method for manufacturing the semiconductor device according to the fifth embodiment.
  • the gate dielectric film 6 is formed on the substrate 2 , and the seed Si film 8 is formed on the gate dielectric film 6 .
  • the first SiGe layer 10 a is formed on the seed Si film 8 , and the first thin cap Si film 12 a is formed on the first SiGe layer 10 a .
  • the second SiGe layer 10 b is formed on the first thin cap Si film 12 a , and the second thin cap Si film 12 b is formed on the second SiGe layer 10 b .
  • the structure shown in FIG. 16A is attained.
  • the first SiGe layer 10 a , the first thin cap Si film 12 a , the second SiGe layer 10 b and the second thin cap Si film 12 b are continuously formed at the same temperature.
  • the forming temperature is preferably 450° C. or above and 494° C. or below, and most preferably 475° C.
  • FIG. 16B shows, the second thin cap Si film 12 b , the second SiGe layer 10 b , the first thin cap Si film 12 a , the first SiGe layer 10 a , the seed Si film 8 , and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed.
  • conductive impurity ions are implanted using the gate electrode as the mask to form the source-drain region 14 in the upper layer of the silicon substrate 2 . Performing the above-described processes attains the semiconductor device shown in FIG. 15.
  • the first and second SiGe layers 10 a and 10 b may be formed under the same growth condition, and may be formed under the different growth conditions as described in the fourth embodiment.
  • a sixth embodiment is attained by applying the fourth embodiment to the third embodiment.
  • FIG. 17 is a schematic cross-sectional view for illustrating a semiconductor device according to a sixth embodiment of the present invention.
  • the thin SiGe film 10 by stacking a first SiGe layer 10 a and a second SiGe layer 10 b .
  • the first and second SiGe layers 10 a and 10 b differ in Ge content X of formula Si (1-x) Ge x representing the first and second SiGe layers 10 a and 10 b respectively.
  • the first and second SiGe layers 10 a and 10 b are continuously formed at the same growth temperature.
  • each Ge content X of the SiGe layers 10 a and 10 b is 0 . 15 or more and smaller than 0.4.
  • the film thickness of the first SiGe layer 10 a may differ from the film thickness if the second SiGe layer 10 b .
  • Total thickness of the SiGe layers 10 a and 10 b is preferably 50 nm or below.
  • the thin cap Si film 12 of the thickness of 0.5 nm to 5 nm.
  • the first and second SiGe layer 10 a and 10 b and the thin cap Si film 12 are continuously formed at the same temperature.
  • the upper Si film 16 of the thickness of 60 nm to 120 nm is formed on the thin cap Si film 12 .
  • the gate dielectric film 6 is formed on the substrate 2 , and the seed Si film 8 is formed on the gate dielectric film 6 .
  • the first SiGe layer 10 a , the second SiGe layer 10 b and the thin cap Si film 12 are continuously formed on the seed Si film 8 at the same temperature.
  • the upper Si film 16 is formed on the thin cap Si film 12 at a temperature higher than the growth temperature of the first SiGe layer 10 a.
  • the upper Si film 16 , thin cap Si film 12 , the second SiGe layer 10 b , the first SiGe layer 10 a , the seed Si film 8 , and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed. Extension regions 18 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a low concentration using the gate electrode as a mask. sidewalls 20 are formed on the sides of the gate electrode. Source-drain regions 14 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a high concentration using the gate electrode and sidewalls 20 as a mask. Further, NiSi layers 22 are formed in upper portions of the upper Si film 16 and source-drain regions 14 using salicide technique. Performing the above-described processes attains the semiconductor device shown in FIG. 17.
  • a seventh embodiment is attained by applying the fifth embodiment to the third embodiment.
  • FIG. 18 is a schematic cross-sectional view for illustrating a semiconductor device according to a seventh embodiment of the present invention.
  • each Ge content X of the SiGe layers 10 a and 10 b is 0.15 or more and smaller than 0.4.
  • the film thickness of the first SiGe layer 10 a may differ from the film thickness if the second SiGe layer 10 b .
  • Total thickness of the SiGe layers 10 a and 10 b is preferably 50 nm or below.
  • the each film thickness of the first and second thin cap Si films 12 a and 12 b is preferably 0.5 nm to 5 nm.
  • the upper Si film 16 of the thickness of 60 nm to 120 nm is formed on the thin cap Si film 12 .
  • the gate dielectric film 6 is formed on the substrate 2 , and the seed Si film 8 is formed on the gate dielectric film 6 .
  • the first SiGe layer 10 a , the first thin cap Si film 12 a , the second SiGe layer 10 b and the second thin cap Si film 12 b are continuously formed on the seed Si film 8 at the same temperature.
  • the upper Si film 16 is formed on the second thin cap Si film 12 b at a temperature higher than the growth temperature of the first SiGe layer 10 a.
  • the upper Si film 16 , the second thin cap Si film 12 b , the second SiGe layer 10 b , the first thin cap Si film 12 a , the first SiGe layer 10 a , the seed Si film 8 , and the gate dielectric film 6 are sequentially patterned using lithography technique and etching technique well known in the art. Thereby, the gate electrode of the MOSFET is formed. Extension regions 18 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a low concentration using the gate electrode as a mask. sidewalls 20 are formed on the sides of the gate electrode.
  • Source-drain regions 14 are formed in the upper portion of the substrate 2 by ion implantation of impurities with a high concentration using the gate electrode and sidewalls 20 as a mask. Further, NiSi layers 22 are formed in upper portions of the upper Si film 16 and source-drain regions 14 using salicide technique. Performing the above-described processes attains the semiconductor device shown in FIG. 18.
  • a high-quality thin SiGe film free of voids can be formed on a gate dielectric film.

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Effective date: 20050915

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION