US20030057484A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

Info

Publication number
US20030057484A1
US20030057484A1 US10/254,680 US25468002A US2003057484A1 US 20030057484 A1 US20030057484 A1 US 20030057484A1 US 25468002 A US25468002 A US 25468002A US 2003057484 A1 US2003057484 A1 US 2003057484A1
Authority
US
United States
Prior art keywords
trench
semiconductor substrate
semiconductor device
region
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/254,680
Other languages
English (en)
Inventor
Masahisa Sonoda
Hiroaki Tsunoda
Eiji Sakagami
Hidemi Kanetaka
Kenji Matsuzaki
Takanori Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANETAKA, HIDEMI, MATSUMOTO, TAKANORI, MATSUZAKI, KENJI, SAKAGAMI, EIJI, SONODA, MASAHISA, TSUNODA, HIROAKI
Publication of US20030057484A1 publication Critical patent/US20030057484A1/en
Priority to US10/948,661 priority Critical patent/US7368342B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Definitions

  • This invention relates to a semiconductor device and method for manufacturing the semiconductor device, and more particularly to a semiconductor device having an isolation of an STI and its manufacturing method.
  • STI Shallow Trench Isolation
  • FIG. 4 is an enlarged cross-sectional view of a semiconductor device 400 having conventional STI made by a process of its manufacturing.
  • a gate-insulating film 20 is formed on a top surface of a semiconductor substrate 10 .
  • a gate electrode 30 of an amorphous silicon film overlies the gate-insulating film 20 .
  • a silicon nitride film 40 is deposited on the gate electrode 30 .
  • a silicon oxide film 50 is deposited on the silicon nitride film 40 .
  • the silicon nitride film 40 and the silicon oxide film 50 are selectively etched off to obtain a predetermined pattern by using a photolithography technique. After that, using the silicon oxide film 50 as a mask, the gate electrode 30 , the gate-insulating film 20 and the semiconductor substrate 10 are selectively removed by etching. By this etching, the trench 60 is formed to reach the semiconductor substrate 10 .
  • the side and bottom surface portions of the trench 60 are oxidized by an RTO (rapid thermal oxidation) in an oxygen O 2 atmosphere heated to 1000° C.
  • RTO rapid thermal oxidation
  • FIG. 4 the trench 60 and its surrounding structure after the RTO treatment are shown in an enlarged scale.
  • a silicon oxide film 70 is formed by the RTO.
  • the silicon oxide film 70 protects the surface of the semiconductor substrate 10 , etc. from the air.
  • the diffusion coefficient of an oxidation seed diffusing into silicon single crystal is smaller than that of an oxidation seed diffusing into amorphous silicon.
  • Stresses rise in the periphery of the boundary portions (e.g. sides, edges and corners) between the side surface and the bottom surface of the trench 60 during the oxidation progress.
  • the diffusion coefficient of an oxidation seed on the periphery of the boundary portions, where a relatively large stress rises, is smaller than that of an oxidation seed on the flat surface portions, where a relatively small stress rises.
  • a gas including fluorocarbon e.g. CF 4 , C 3 F 8 , and so on
  • RIE process e.g. CF 4 , C 3 F 8 , and so on
  • the boundary portions 80 which are provided at the bottom portion of the trench 60 of the semiconductor device 400 , are more difficult to be oxidized than the flat surface portions inside the trench 60 .
  • the oxide film becomes thinner and thinner toward the boundary portions 80 .
  • the oxide film provided on the boundary portions 80 is thinner than the oxide film provided on their flat surfaces.
  • the boundary portions 80 are sharpened, and have curved surfaces, each of which has a small curvature radius.
  • the stress which rises in the boundary portions 80 includes not only the stress concentrated by the oxidation, but also includes the stress from an amorphous silicon, a silicon nitride film and a silicon oxide film which are deposited on the semiconductor substrate 10 .
  • the stress concentration in the boundary portions 80 of the trench 60 easily causes crystal defects 90 in the boundary portions 80 .
  • the crystal defects 90 cause e.g. a leakage of the carrier, therefore the crystal defects 90 interfere with the normal operations of the semiconductor devices. As a result, they cause a lower yield of the semiconductor devices.
  • a semiconductor device comprising: a semiconductor substrate having a substrate top surface on which a device is to be formed; a gate electrode formed on said substrate top surface and electrically insulated from the semiconductor substrate by a gate-insulating film; a trench formed through the gate electrode into the semiconductor substrate to electrically insulate a device region for forming a device from the remainder region of the substrate top surface; and a boundary portion which is defined between a side surface of the trench and a bottom surface of the trench; wherein said boundary portion has spherical shapes having a curvature radius not smaller than 80 nm.
  • a semiconductor device comprising: a semiconductor substrate having a substrate top surface on which a device is to be formed; a gate electrode formed on said substrate top surface and electrically insulated from the semiconductor substrate by a gate-insulating film; a trench formed through the gate electrode into the semiconductor substrate to electrically isolate a device region for forming a device from the remainder region of the substrate top surface; and oxidation films formed on a side surface of the trench and a bottom surface of the trench, respectively; wherein the thickness of the oxidation film formed on the side surface is same as that of the oxidation film formed on the bottom surface.
  • a method for manufacturing a semiconductor device comprising: forming a gate-insulating film on a semiconductor substrate; forming a gate electrode on the gate-insulating film to be electrically insulated from the semiconductor substrate; etching the gate electrode, the gate insulting film and the semiconductor substrate to form a trench which is used to electrically isolate a device region for forming a device from the remainder region on the substrate top surface; further etching the inside of the trench using a gas containing Cl 2 or HBr.
  • FIG. 1A is an enlarged cross-sectional view of a trench and its surrounding structure in a semiconductor device 100 having an STI under a process step of its manufacturing according to an embodiment of the invention
  • FIG. 1B is an enlarged cross-sectional view of the trench and its surrounding structure in the semiconductor device 100 next step of the manufacturing process of FIG. 1A;
  • FIG. 1C is an enlarged cross-sectional view of the trench and its surrounding structure in the semiconductor device 100 next step of the manufacturing process of FIG. 1B;
  • FIG. 2A is an enlarged cross-sectional view of the boundary portion 80 shown in FIG. 4;
  • FIG. 2B is an enlarged cross-sectional view of the boundary portion 80 shown in FIG. 1B;
  • FIG. 3 is a diagram showing a graph that illustrates a relation between the curvature radius of the boundary portion 80 and a ratio of incidence of the leakage by the crystal defects at the standby state in the semiconductor device;
  • FIG. 4 is an enlarged cross-sectional view of a trench and its surrounding structure in a conventional semiconductor device 400 having the STI.
  • FIGS. 1A, 1B and 1 C are enlarged cross-sectional views of a trench and its surrounding structure in a semiconductor device 100 having STI according to an embodiment of the invention.
  • the semiconductor device 100 is manufactured in the order of the steps shown in FIG. 1A, FIG. 1B and FIG. 1C.
  • a gate-insulating film 20 is provided on a substrate,top surface 12 of a semiconductor substrate 10 .
  • a gate electrode 30 of the amorphous silicon is provided on the gate-insulating film 20 .
  • a silicon nitride film 40 is then deposited on the gate electrode 30 .
  • a silicon oxide film 50 is deposited on the silicon nitride film 40 .
  • the silicon oxide film 50 , the silicon nitride film 40 and the gate electrode 30 are selectively etched into a predetermined pattern by using the photolithography technique.
  • the gate-insulating film 20 and semiconductor substrate 10 are selectively removed by an etching.
  • a trench 60 is formed to penetrate the gate-insulating film 20 and reach the semiconductor substrate 10 .
  • an RIE process under a high-pressure atmosphere in which an etching gas including Cl 2 and HBr is used, is added to the ordinary RIE process.
  • the side and bottom surface portions of the trench 60 are oxidized by RTO in oxygen O 2 atmosphere held at 1000° C.
  • FIG. 1B the trench 60 and the surrounding structure of the trench 60 after RTO treatment are shown in an enlarged scale.
  • This oxidation process may be implemented in a hydrogen H 2 and oxygen O 2 atmosphere or in ozone O 3 atmosphere in lieu of oxygen O 2 atmosphere.
  • the curvature radius of the boundary portions 80 may be larger when the oxidation process is implemented in the hydrogen H 2 and oxygen O 2 atmosphere or in the ozone O 3 atmosphere than when it is implemented in the oxygen O 2 atmosphere.
  • the trench 60 is formed in the substrate surface of the semiconductor substrate 10 .
  • the trench 60 electrically isolates a device region for forming a device from the remainder region of the substrate top surface.
  • the boundary portions 80 are defined as portions between the bottom surface of said trench 60 and the side surface of said trench 60 .
  • the boundary portions 80 have a curvature radius not smaller than 80 nm.
  • the side surface 62 and the bottom surface 64 of the trench 60 is substantially planer. Namely, the curvature radiuses of the side surface 62 and the bottom surface 64 is substantially infinitely large.
  • the RIE process using Cl 2 and HBr is further applied to the ordinary RIE process.
  • an oxidation process using hydrogen H 2 and oxygen O 2 atmosphere or an ozone O 3 atmosphere after the ordinary etching step, can make the curvature radius of the boundary portions 80 large.
  • the curvature radius of the boundary portions 80 can be large. And when the oxidation process is implemented in the hydrogen H 2 and oxygen O 2 atmosphere after the ordinary etching step, the curvature radius of the boundary portions 80 can also be large. Furthermore, when the oxidation process is implemented in the ozone O 3 atmosphere after the ordinary etching step, the curvature radius of the boundary portions 80 can also be large. Any one of these processes may be used. Of course, the RIE process using Cl 2 and HBr and any one of the oxidation processes using the Cl 2 and HBr atmosphere or using the ozone O 3 atmosphere may be combined.
  • boundary portions 80 can be formed in spherical shapes having a large curvature radius, may be used in the instant embodiment.
  • a silicon oxide material 90 is deposited to fill the trench 60 by using the HDP (High Density Plasma) technique. Then the silicon oxide material 90 is planarized by CMP, and the semiconductor substrate 10 is thereafter heated at approximately 900° C. in a nitrogen atmosphere. After the semiconductor substrate 10 is next exposed to NH 4 F solution, the silicon nitride film 40 is removed by phosphation at approximately 150° C. Thereafter, doped polysilicon 92 containing phosphor is deposited on the silicon oxide material 90 and the gate electrode 30 by low-pressure CVD.
  • HDP High Density Plasma
  • an ONO film (a three-component film consisting of an oxide film, a nitride film and a oxide film) 101 , an amorphous silicon film 103 containing phosphor, WSi film 105 and a silicon oxide film 107 are deposited using LP-CVD (Low-Pressure Chemical Vapor Deposition).
  • LP-CVD Low-Pressure Chemical Vapor Deposition
  • the silicon oxide film 107 is selectively removed by RIE etching into a predetermined pattern by photolithography. Using the silicon oxide film 107 as a mask, the ONO film 101 , the amorphous silicon film 103 and the WSi film 105 are selectively removed by RIE etching.
  • the semiconductor device 100 having isolations of the trench 60 is completed.
  • FIG. 2A and 2B show an enlarged cross-sectional view of the boundary portions 80 shown in FIG. 4 and the boundary portions 80 shown in FIG. 1B, respectively.
  • the cross-sectional views in FIG. 2A and 2B show the states of the boundary portions 80 in which the silicon oxide films 70 are removed.
  • the stress concentration in the boundary portions 80 of the trench 60 causes crystal defects 90 in the boundary portions 80 easily.
  • the crystal defects 90 adversely affect the normal operations of the semiconductor device 400 , and cause trouble in the semiconductor devices 400 . For example, if the crystal defects 90 in the boundary portions 80 go through a well portion, then carriers leak from the well portion. Thus, a leakage occurs at the standby state in the semiconductor device 400 .
  • the curvature radius of the boundary portions 80 in the semiconductor device 100 in accordance with the instance embodiment is large, as shown in FIG. 2B, a stress does not easily concentrate in the boundary portions 80 . Since the stress is hardly concentrated in the boundary portions 80 , crystal defects 90 hardly occur in the boundary portions 80 . Therefore, the semiconductor device 100 can function well, and the semiconductor device 100 hardly breaks down.
  • the curvature radius of the boundary portions 80 is not smaller than approximately 80 nm. In order that the curvature radius of the boundary portions 80 are easily understood, the radii are illustrated by broken line circles in FIG. 2A and FIG. 2B.
  • FIG. 3 is a graph showing the relation between the curvature radius of the boundary portions 80 and the ratio of the leakage caused by crystal defects at the standby state of the semiconductor device.
  • the curvature radius of the boundary portions 80 in the conventional semiconductor device 400 is smaller than approximately 50 nm.
  • the ratio of the leakage becomes more than approximately 3%.
  • the curvature radius of the boundary portions 80 in the semiconductor device 100 according to the instant embodiment is larger than approximately 80 nm.
  • the ratio of the leakage becomes approximately 0%.
  • the graph in FIG. 3 indicates that when the curvature radius of the boundary portions 80 at the bottom of the trench 60 becomes large, the ratio of the leakage decreases.
  • the curvature radius of the boundary portions 80 of the semiconductor device 100 according to the instant embodiment is larger than that of the conventional semiconductor device 400 , the stress does not rise easier on the boundary portions 80 of the semiconductor device 100 than on that of the conventional semiconductor device 400 . Therefore, crystal defects 90 hardly occur in the boundary portions: 80 of the semiconductor device 100 .
  • the normal operations of the semiconductor device 100 are not interfered with. For example, the crystal defects 90 do not arise at the boundary portions 80 , so that carriers do not leak from the well portion. Thus, a leakage occurs at the standby state in the semiconductor device 100 .
  • a stress does not concentrate on the periphery of the boundary portions (e.g. sides, edges and corners) between the surfaces of the trench used for STI. Therefore, crystal defects do not occur in the boundary portions, and failures do not arise in the device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
US10/254,680 2001-09-27 2002-09-26 Semiconductor device and method of manufacturing the same Abandoned US20030057484A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/948,661 US7368342B2 (en) 2001-09-27 2004-09-24 Semiconductor device and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001-296391 2001-09-27
JP2001296391A JP2003100860A (ja) 2001-09-27 2001-09-27 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/948,661 Division US7368342B2 (en) 2001-09-27 2004-09-24 Semiconductor device and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US20030057484A1 true US20030057484A1 (en) 2003-03-27

Family

ID=19117642

Family Applications (2)

Application Number Title Priority Date Filing Date
US10/254,680 Abandoned US20030057484A1 (en) 2001-09-27 2002-09-26 Semiconductor device and method of manufacturing the same
US10/948,661 Expired - Fee Related US7368342B2 (en) 2001-09-27 2004-09-24 Semiconductor device and method of manufacturing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US10/948,661 Expired - Fee Related US7368342B2 (en) 2001-09-27 2004-09-24 Semiconductor device and method of manufacturing the same

Country Status (4)

Country Link
US (2) US20030057484A1 (ko)
JP (1) JP2003100860A (ko)
KR (3) KR20030027743A (ko)
CN (1) CN1411048A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095093B2 (en) 2001-06-29 2006-08-22 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing a semiconductor device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070059874A1 (en) * 2005-07-06 2007-03-15 Sematech, Inc. Dual Metal Gate and Method of Manufacture
JP4322856B2 (ja) * 2005-09-29 2009-09-02 株式会社東芝 化学反応装置及び燃料電池システム
KR100897958B1 (ko) 2007-10-15 2009-05-18 주식회사 동부하이텍 반도체 장치의 소자 분리막 및 이의 형성방법
JP5966301B2 (ja) * 2011-09-29 2016-08-10 富士通株式会社 化合物半導体装置及びその製造方法
CN114864477B (zh) * 2021-01-20 2024-09-20 长鑫存储技术有限公司 半导体结构及其制造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081662A (en) * 1996-05-27 2000-06-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including trench isolation structure and a method of manufacturing thereof
US6482701B1 (en) * 1999-08-04 2002-11-19 Denso Corporation Integrated gate bipolar transistor and method of manufacturing the same
US6600189B1 (en) * 1997-06-30 2003-07-29 Kabushiki Kaisha Toshiba Semiconductor device and semiconductor device manufacturing method

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0620108B2 (ja) * 1987-03-23 1994-03-16 三菱電機株式会社 半導体装置の製造方法
JPH09162168A (ja) 1995-12-05 1997-06-20 Nissan Motor Co Ltd 半導体装置の製造方法
US5882982A (en) * 1997-01-16 1999-03-16 Vlsi Technology, Inc. Trench isolation method
US6165854A (en) * 1998-05-04 2000-12-26 Texas Instruments - Acer Incorporated Method to form shallow trench isolation with an oxynitride buffer layer
JP3472482B2 (ja) * 1998-06-30 2003-12-02 富士通株式会社 半導体装置の製造方法と製造装置
JP3420103B2 (ja) 1999-04-13 2003-06-23 Ｎｅｃエレクトロニクス株式会社 素子分離用シリコンシャロートレンチエッチング方法
JP3566880B2 (ja) 1999-04-28 2004-09-15 シャープ株式会社 素子分離領域の形成方法
US6140206A (en) * 1999-06-14 2000-10-31 Chartered Semiconductor Manufacturing Ltd. Method to form shallow trench isolation structures
US6207534B1 (en) * 1999-09-03 2001-03-27 Chartered Semiconductor Manufacturing Ltd. Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing
US6277710B1 (en) * 1999-11-15 2001-08-21 Chartered Semiconductor Manufacturing Ltd. Method of forming shallow trench isolation
JP2003007864A (ja) * 2001-06-22 2003-01-10 Nec Corp 不揮発性半導体記憶装置の製造方法
US6720235B2 (en) * 2002-09-10 2004-04-13 Silicon Integrated System Corp. Method of forming shallow trench isolation in a semiconductor substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6081662A (en) * 1996-05-27 2000-06-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device including trench isolation structure and a method of manufacturing thereof
US6600189B1 (en) * 1997-06-30 2003-07-29 Kabushiki Kaisha Toshiba Semiconductor device and semiconductor device manufacturing method
US6482701B1 (en) * 1999-08-04 2002-11-19 Denso Corporation Integrated gate bipolar transistor and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7095093B2 (en) 2001-06-29 2006-08-22 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing a semiconductor device
US20060244098A1 (en) * 2001-06-29 2006-11-02 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing a semiconductor device

Also Published As

Publication number Publication date
JP2003100860A (ja) 2003-04-04
KR20040111236A (ko) 2004-12-31
US20050040439A1 (en) 2005-02-24
KR20040111237A (ko) 2004-12-31
CN1411048A (zh) 2003-04-16
KR100538726B1 (ko) 2005-12-26
US7368342B2 (en) 2008-05-06
KR100470573B1 (ko) 2005-02-21
KR20030027743A (ko) 2003-04-07

Similar Documents

Publication Publication Date Title
KR100338767B1 (ko) 트렌치 소자분리 구조와 이를 갖는 반도체 소자 및 트렌치 소자분리 방법
US7683455B2 (en) Semiconductor device and method of manufacturing thereof
US6797579B2 (en) Semiconductor device having trench isolation structure and method of fabricating the same
KR100224700B1 (ko) 반도체장치의 소자분리방법
US6855591B2 (en) Nonvolatile memory device having STI structure and method of fabricating the same
US20020127818A1 (en) Recess-free trench isolation structure and method of forming the same
US6602792B2 (en) Method for reducing stress of sidewall oxide layer of shallow trench isolation
US7368342B2 (en) Semiconductor device and method of manufacturing the same
US6211021B1 (en) Method for forming a borderless contact
KR20000073114A (ko) 선택적 에피택셜 성장을 이용한 트렌치 소자 분리 방법
US7095093B2 (en) Semiconductor device and method of manufacturing a semiconductor device
US6503815B1 (en) Method for reducing stress and encroachment of sidewall oxide layer of shallow trench isolation
US6872632B2 (en) Method of fabricating semiconductor device
US6521509B2 (en) Semiconductor device and method of manufacturing the same
JP2953447B2 (ja) 溝分離型半導体装置の製造方法
US6624041B2 (en) Method for forming trench type isolation film using annealing
JP3844896B2 (ja) 半導体素子の隔離構造及びその形成方法
US7501326B2 (en) Method for forming isolation layer of semiconductor device
US6537917B2 (en) Method for fabricating electrically insulating layers
KR20000015466A (ko) 트렌치 격리의 제조 방법
KR100459693B1 (ko) 반도체 장치의 트렌치 소자분리방법
KR20010038051A (ko) 수소 플로우를 이용한 트랜치형 소자분리막 형성방법

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SONODA, MASAHISA;TSUNODA, HIROAKI;SAKAGAMI, EIJI;AND OTHERS;REEL/FRAME:013334/0672

Effective date: 20020919

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION