US20030032221A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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US20030032221A1
US20030032221A1 US10/187,414 US18741402A US2003032221A1 US 20030032221 A1 US20030032221 A1 US 20030032221A1 US 18741402 A US18741402 A US 18741402A US 2003032221 A1 US2003032221 A1 US 2003032221A1
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film
semiconductor
semiconductor film
silicon
laser light
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Kenji Kasahara
Shunpei Yamazaki
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Publication of US20030032221A1 publication Critical patent/US20030032221A1/en
Priority to US11/785,633 priority Critical patent/US7998845B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
    • H10D86/0225—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials using crystallisation-promoting species, e.g. using a Ni catalyst
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0251—Manufacture or treatment of multiple TFTs characterised by increasing the uniformity of device parameters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes

Definitions

  • the present invention relates to a semiconductor device including a circuit composed of a thin film transistor (hereinafter referred to as TFT) and a method of manufacturing the same.
  • TFT thin film transistor
  • the present invention relates to an electro-optical device represented by a liquid crystal display panel and to an electronic equipment incorporating the above-mentioned electro-optical device as a part thereof.
  • the term semiconductor device defined in this specification refers to all the devices which can operate by utilizing a semiconductor characteristic, and the electro-optical device, a semiconductor circuit and the electronic equipment are all included in a category of the semiconductor device.
  • the thin film transistor is formed by using a semiconductor thin film (film thickness: approximately several to several hundreds of nm) formed on a substrate having an insulating surface and the TFT is adapted to constitute a large-area integrated circuit.
  • An active matrix type liquid crystal module, an EL module, and a contact image sensor are known as a typical example thereof.
  • the TFT using a silicon film having a crystalline structure (typically, a polysilicon film) as an active layer (hereinafter, referred to as polysilicon TFT) is high in a field effect mobility and thus can be used to form a circuit having various functions.
  • the liquid crystal module mounted onto a liquid crystal display device includes on one substrate a pixel portion and a driver circuit such as a shift register circuit, level shifter circuit, buffer circuit, or sampling circuit which is based on a CMOS circuit.
  • the pixel portion performs an image display for each functional block and the driver circuit controls the pixel portion.
  • a TFT (pixel TFT) is arranged in each of several tens to several millions of pixels and each pixel TFT is provided with a pixel electrode.
  • An opposing electrode is provided on an opposite substrate side with a liquid crystal interposed between the two electrodes, to thereby form a kind of capacitor with the liquid crystal used as a dielectric.
  • a voltage applied to each pixel is then controlled by a switching function of the TFT to control the application of charge to the capacitor to drive the liquid crystal, thereby displaying an image through the control of an amount of transmitted light.
  • the pixel TFT is composed of an n-channel TFT and adapted to drive the liquid crystal by applying a voltage as a switching element.
  • the liquid crystal is driven with an alternating current and a method called a frame inversion driving is employed in many cases.
  • a frame inversion driving is employed in many cases.
  • it is important to sufficiently lower an OFF current value (a drain current caused to flow at the time of TFT being in OFF state) in order to reduce the power consumption.
  • the semiconductor film when irradiated with a laser light for crystallization or for improvement in crystallinity, the semiconductor film is instantly melted from the surface thereof and then the melted semiconductor film due to heat conduction to the substrate is cooled to solidify from the substrate side. Through the solidifying process, recrystalization is performed to form a semiconductor film having a crystalline structure with a large grain size.
  • the semiconductor film once melted causes a volume expansion to form unevennesses called ridges on the semiconductor surface.
  • the surface having the ridge serves as an interface with a gate insulating film so that element characteristics are largely influenced.
  • an excimer laser or Ar laser is used for laser annealing in many cases.
  • a method of performing the laser annealing described below has been preferably used because it is suited for mass production with high productivity. That is, a pulse oscillation type laser beam having a high output is processed by an optical system so as to be a square spot whose side is of several centimeters or be linear With a length of, for example, 10 cm or more on a surface to be irradiated and the laser beam is scanned on the surface to be irradiated with the irradiation point relatively changed with respect to there.
  • linear beam a linear laser beam
  • the reason the scanning, is performed in the direction perpendicular to the line direction is that the direction enables the most efficient scanning. Because of the high productivity, the linear beam obtained by processing laser having a high output by an appropriate optical system has been mainly used for the laser annealing.
  • the linear beam is applied while being overlapped by gradually shifting it in a transverse direction thereof so that an entire surface of an amorphous silicon film is subjected to the laser annealing, thereby making it possible to crystallize or improve the crystallinity.
  • the technique of the laser annealing is indispensable in order to form a semiconductor film having higher electric characteristics in a lower cost.
  • the present invention has been made in view of the above-mentioned problems and provides a technique for solving such problems.
  • An object of the present invention is accordingly to provide a semiconductor device such as an electro-optical device represented by an active matrix type liquid crystal display device which is formed by using a TFT and in which an improvement in operational characteristic and a low power consumption are realized.
  • an object of the present invention is to obtain a TFT which has a low OFF current value with a reduced variation.
  • the levelness (a root mean square roughness (rms) and a peak to valley value (P-V value)) is high in a main surface of the semiconductor film which contains germanium in a concentration of several %, preferably, 0.1 to 10 atoms % and which is subjected to a laser light irradiation as compared with a case of performing the laser light irradiation to the semiconductor film containing no germanium.
  • rms root mean square roughness
  • P-V value peak to valley value
  • the invention disclosed in this specification relates to a semiconductor device comprising a thin film transistor having a semiconductor layer formed on an insulating film, characterized in that:
  • the semiconductor layer formed of a semiconductor film containing silicon as a main component and containing germanium, is used as an active layer;
  • the active layer has a P-V value of less than 70 nm which indicates a surface roughness of a main surface thereof.
  • a semiconductor device comprising a thin film transistor having a semiconductor layer formed on an insulating film, characterized in that:
  • the semiconductor layer formed of a semiconductor film containing silicon as a main component and containing germanium, is used as an active layer;
  • the active layer has an rms of less than 10 nm which indicates a surface roughness of a main surface thereof.
  • a semiconductor device comprising a thin film transistor having a semiconductor layer formed on an insulating film, characterized in that:
  • the semiconductor layer formed of a semiconductor film containing silicon as a main component and containing germanium, is used as an active layer and
  • the active layer has an rms of less than 10 nm and a P-V value of less than 70 nm which each indicate a surface roughness of a main surface thereof.
  • the semiconductor device is characterized in that the semiconductor film contains the germanium in a concentration of 0.1 to 10 atoms % and serves as a silicon film having a crystalline structure.
  • the semiconductor device is characterized in that the semiconductor film contains a metal element in a concentration of 1 ⁇ 10 16 /cm 3 to 5 ⁇ 10 18 /cm 3 and serves as a silicon film having a crystalline structure.
  • the metal element is a metal element for accelerating a crystallization of silicon and is at least one element selected from the group consisting of Fe, Ni, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu and Au.
  • the invention relates to a method of manufacturing a semiconductor device, characterized by comprising:
  • the method of manufacturing a semiconductor device is characterized in that an energy density of the laser light in the fourth step is higher than that of the laser light of the second step.
  • a step of adding a metal element for accelerating a crystallization may be provided before the second step.
  • a method of manufacturing a semiconductor device characterized by comprising:
  • the method of manufacturing a semiconductor device is characterized in that an energy density of the laser light in the fifth step is higher than that of the laser light in the third step.
  • FIGS. 1A to 1 E are views showing the present invention:
  • FIG. 2 is a graph showing a root mean square roughness (rms) obtained by an AFM
  • FIG. 3 is a graph showing a P-V value obtained by the AFM
  • FIGS. 4A to 4 F are views showing manufacturing steps of the present invention (Embodiment 1);
  • FIGS. 5A to 5 D are views showing manufacturing steps of the present invention (Embodiment 1);
  • FIGS. 6A to 6 D are views showing manufacturing steps of an active matrix substrate (Embodiment 2);
  • FIGS. 7A to 7 C are views showing manufacturing steps of the active matrix substrate (Embodiment 2);
  • FIG. 8 is a view showing the active matrix substrate (Embodiment 2);
  • FIG. 9 is an external view of an AM-LCD (Embodiment 3):
  • FIG. 10 shows an example of a liquid crystal display device in section (Embodiment 4);
  • FIGS. 11A and 11B are respectively a top view of an EL module and a sectional view thereof (Embodiment 5);
  • FIGS. 12A to 12 F each show an example of electronic equipment (Embodiment 6);
  • FIGS. 13A to 13 D each show an example of the electronic equipment (Embodiment 6);
  • FIGS. 14A to 14 C each show an example of the electronic equipment (Embodiment 6).
  • FIGS. 15A to 15 C are microphotographs showing surfaces of a silicon germanium film and a silicon film.
  • an amorphous semiconductor film 3 containing germanium is formed on an insulating surface.
  • a base insulating film is formed on a quartz substrate or glass substrate.
  • the insulating film mainly containing silicon for example, an oxide silicon film, a nitride silicon film or an oxynitride film, or a laminate thereof is formed on a glass substrate 1 as a base insulating film 2 (FIG. 1A).
  • the base insulating film 2 is provided for the purpose of preventing diffusion of impurities from the substrate and in some cases it is not particularly necessary to provide the film depending on the substrate to be used.
  • the amorphous semiconductor film 3 containing germanium is formed by a plasma CVD method, a low pressure CVD method, or other methods as appropriate.
  • a plasma CVD method reaction gas made of SiH 1 and GeH 1 , and optionally a reaction gas made of GeH 4 that is diluted with SiH 4 and H 2 are introduced into a reaction chamber to perform a high frequency discharge with a frequency of 1 to 200 MHZ for decomposition, thereby depositing the amorphous semiconductor film on the substrate.
  • the reaction gas Si 2 H 6 or SiF 4 , and GeF 4 may be used instead of SiH 4 and GeH 4 , respectively.
  • the low pressure CVD method it is possible to employ such reaction gases.
  • the reaction gas is diluted with He and the amorphous semiconductor film is deposited on the substrate at a temperature of 400 to 500° C.
  • the above-mentioned gases used in the present invention are those purified up to a high purity in order to reduce a concentration of an impurity element such as oxygen, nitrogen or carbon which is taken in the deposited amorphous semiconductor film.
  • the thickness of the deposited amorphous semiconductor film is set to 20 to 100 nm.
  • the amorphous semiconductor film containing germanium is crystallized by heat treatment (FIG. 1B).
  • the heat treatment it is necessary to perform the heat treatment at 600° C. or more for 10 hours or more.
  • Irradiation with laser light is then performed to improve a crystallization rate and to repair defects remaining in a crystal grain (FIG. 1C).
  • a crystallization rate is then performed to improve a crystallization rate and to repair defects remaining in a crystal grain (FIG. 1C).
  • large unevennesses are formed in the surface thereof.
  • the laser light is applied to the amorphous semiconductor film containing germanium although the unevennesses are similarly formed, it is small enough to maintain the levelness of the surface.
  • excimer laser having a wavelength of 400 nm or less, or a second harmonic (wavelength: 532 nm) to a fourth harmonic (wavelength: 266 nm) of YAG laser or YVO 4 laser are used as a light source.
  • the laser light above is condensed into a linear or spot shape by the optical system to be irradiated with its energy density set to 100 to 700 mJ/cm 2 and the processing is performed by scanning the laser beam thus condensed over a predetermined region of the substrate.
  • pulse laser a case of using pulse laser is described here by way of example, but continuous oscillation type laser may be also used. It is preferred that in order to obtain the crystal having a large grain size upon the crystallization of the amorphous semiconductor film, solid laser capable of the continuous oscillation is used in combination with the application of a second harmonic to a fourth harmonic of a fundamental wave.
  • the second harmonic (wavelength: 532 nm) or third harmonic (wavelength: 355 nm) of Nd: YVO 4 laser (fundamental wave: 1064 nm) may be applied.
  • the laser light emitted from the continuous oscillation type YVO 4 laser with an output of 10 W is transformed into a harmonic by a nonlinear optical element.
  • YVO 4 crystal and nonlinear optical element are put into a resonator to emit the harmonic.
  • it is formed into a laser light of a rectangular or elliptic shape on the irradiation surface by the optical system to be applied to a member to be processed.
  • the required energy density at that time is approximately 0.01 to 100 MW/cm 2 (preferably, 0.1 to 10 MW/cm 2 ).
  • the irradiation may be performed in such a manner that the semiconductor film is moved relative to the laser light at a speed of approximately 10 to 2,000 cm/s.
  • a halogen lamp, xenon lamp, mercury lamp, metal halide lamp, or the like can be used as the light source.
  • the above-mentioned heat treatment is not always suitable, so that the crystallization of the amorphous silicon film may be performed only through the irradiation with the laser light (the pulse oscillation type excimer laser or the continuous oscillation type laser (second harmonic of YVO 4 laser)).
  • the laser light the pulse oscillation type excimer laser or the continuous oscillation type laser (second harmonic of YVO 4 laser)
  • a technique disclosed in JP 07-130652 A or JP 08-78329 A may be used in which a metal element for accelerating the crystallization of the silicon is introduced and a crystalline silicon film is formed by heat treatment at a temperature lower than that in the conventional case.
  • an oxide film (not shown) formed by the laser irradiation is removed by diluted hydrofluoric acid or the like to apply the laser light (with the energy density higher than the previously applied laser light) in an inert atmosphere or in a vacuum again.
  • the leveled semiconductor film is patterned to form a semiconductor layer 6 having a desired shape by a known patterning method (FIG. 1D). It is desirable that before the formation of a mask made of resist a thin oxide film is formed on the surface thereof with ozone water.
  • the surface of the semiconductor layer is then washed with an etchant containing hydrofluoric acid to form an insulating film mainly containing silicon and serving as a gate insulating film 7 .
  • the surface washing and formation of the gate insulating film are desirably conducted continuously without an exposure to the outside air.
  • the surface of the gate insulating film 7 is washed and thereafter a gate electrode 8 is formed.
  • An impurity element such as P or As
  • imparting an n-type conductivity to the semiconductor in this case, phosphorous
  • the heat treatment, strong light irradiation or laser light irradiation is performed for activating the impurity element.
  • plasma damage applied to the gate insulating film or that applied to an interface between the gate insulating film and the semiconductor layer can be recovered.
  • the second harmonic of the YAG laser is applied from the front or rear side in an atmosphere of a room temperature to 300° C. to activate the impurity element.
  • YAG laser is preferable as the activation means in terms of less maintenance.
  • Subsequent steps are as follows: forming an interlayer insulating film 12 , performing a hydrogenation, forming contact holes reaching the source region and the drain region, and forming a source electrode 13 and a drain electrode 14 to complete TFT (n-channel TFT) (FIG. 1E).
  • the surface of a channel forming region 11 of the TFT thus obtained may have a root mean square roughness (rms) of less than 10 nm and a P-V value of less than 70 nm.
  • the present invention is not limited to the TFT structure shown in FIG. 1E but may employ an LDD structure (a lightly doped drain structure) in which an LDD region is interposed between the channel forming region and the drain region (or the source region) as necessary.
  • LDD structure a lightly doped drain structure
  • This structure is a structure in which a region added with an impurity element in a low concentration is provided between the channel forming region and the source or drain region formed by adding the impurity element in a high concentration.
  • the region is called the LDD region.
  • GOLD gate-drain overlapped LDD
  • GOLD gate-drain overlapped LDD
  • n-channel TFT is employed here for the description, but it goes without saying that a p-channel TFT can be formed by using a p-type impurity element instead of the n-type impurity element.
  • top gate type TFT is described herein as an example, but the present invention can be applied irrespective of the TFT structure and the present invention can be applied, for example, to a bottom gate type (reverse stagger type) TFT or a forward stagger type TFT.
  • a base film is formed on a glass substrate.
  • the base insulating film is composed of a two-layer structure including a first oxynitride silicon film with a thickness of 50 to 100 nm which is formed by using SiH 4 , NH 3 , and N 2 O as reaction gases and a second oxynitride silicon film with a thickness of 100 to 150 nm which is formed by using SiH 4 and N 2 O as the reaction gases, the two films being laminated.
  • an amorphous semiconductor film is formed.
  • an amorphous silicon film, an amorphous silicon film containing 1.7% germanium to silicon, and an amorphous silicon film containing 3.5% germanium to silicon are formed by a plasma CVD method, respectively.
  • a nickel containing layer is formed by applying a nickel acetate solution containing nickel in a concentration of 10 ppm in terms of weight by a spinner.
  • a dehydrogenation process is then performed at 500° C. for 1 hour to reduce a hydrogen concentration in the film, followed by heat treatment at 550° C. for 4 hours to form the semiconductor films each having a crystalline structure.
  • FIGS. 2 and 3 show the root mean square (rms) of the unevenness on the surface
  • FIG. 3 shows a peak to valley (P-V) value of the unevenness (a difference in height between the maximum value and the minimum value).
  • the values of FIGS. 2 and 3 both are measured in a region of 3 ⁇ m ⁇ 3 ⁇ m.
  • a laser light (XeCl: wavelength of 308 nm) is then irradiated in an atmosphere or in an oxygen atmosphere.
  • an excimer laser light (wavelength: 400 nm or less) and a second harmonic or a third harmonic of YAG laser are used.
  • a pulse laser light with a repetition frequency of approximately 10 to 1,000 Hz is used and the laser light is condensed into 100 to 500 mJ/cm 2 by an optical system to be applied with an overlap ratio of 90 to 95% for scanning of the silicon film surface.
  • the root mean square roughness (rms) after the irradiation with the laser light the silicon film containing no germanium has approximately 10 to 30 nm, whereas in the film allowed to contain the germanium the root mean square (rms) of the unevenness on the surface is suppressed to less than 10 nm.
  • the silicon film containing no germanium has approximately 70 to 100 nm. whereas in the film allowed to contain the germanium the P-V value of the unevenness of the surface is suppressed to less than 70 nm.
  • FIGS. 15A to 15 C are microphotographs in cases of irradiating films with a laser light in an atmosphere with the number of shots set to 13 , the repetition frequency set to 30 Hz, and the energy density set to 521 mJ/cm 2 .
  • FIG. 15C shows a case of a silicon film.
  • the semiconductor films containing the germanium are high in levelness with less unevenness in comparison with the semiconductor film containing no germanium (FIG. 15C).
  • the semiconductor film obtained according to the above-mentioned method has a high orientation ratio with respect to ⁇ 101 ⁇ lattice plane.
  • the crystal grains are oriented largely to ⁇ 101 ⁇ lattice plane and it can be also observed that the crystal grains tend to orient toward ⁇ 311 ⁇ plane that is placed in an intermediate position between ⁇ 001 ⁇ plane and ⁇ 111 ⁇ plane.
  • the ratios of the crystal grains whose angles to the surface of the semiconductor layer are 10° or less are 20% or more in ⁇ 101 ⁇ lattice plane, 3% or less in ⁇ 001 ⁇ plane, and 5% or less in ⁇ 111 ⁇ plane, respectively.
  • the detection is performed by using an electron backscatter diffraction pattern method.
  • the distribution of crystal orientation is obtained by the electron backscatter diffraction pattern (EBSP), which is a method of performing an analysis of the crystal orientation from the backscatter of primary electrons with a dedicated detector provided in the scanning electron microscopy (SEM).
  • EBSP electron backscatter diffraction pattern
  • SEM scanning electron microscopy
  • the further averaged information on the crystal orientation can be obtained.
  • the measurement is performed in a region of 100 ⁇ m ⁇ 100 ⁇ m at approximately 10,000 points (interval: 1 ⁇ m) to 40,000 points (interval: 0.5 ⁇ m).
  • the crystal orientation of each crystal rain is completely determined by the mapping, it is possible to statistically display the condition of the orientation of the crystal rains to a film. If the distribution is concentrated around ⁇ 101 ⁇ lattice plane, in the actual film ⁇ 101 > orientation of each crystal grain is in a direction substantially perpendicular to the substrate. At this time, it can be supposed that the grains are arranged around there with some fluctuations.
  • an acceptable value to the fluctuation angle for example, by 5 degrees or 10 degrees and the ratio of the crystal grains with the angle less than the above value is indicated by numeric values.
  • the acceptable deviation angle is set to 5 or 10 degrees as described above and the ratio of the crystal grains whose angles all within the range is called the orientation rate of crystal.
  • the crystalline silicon film formed by the conventional method is influenced by the substrate or the base insulating film at the time of crystallization and thus a plurality of crystal grains are deposited. Therefore, although there is the tendency of orientating to ⁇ 111 ⁇ plane, the ratio of crystal grains oriented toward the plane direction is low.
  • the semiconductor device which has a low OFF current value with a reduced variation can be obtained.
  • FIGS. 4 and 5 An example of manufacturing TFTs conducted laser irradiation or two times is shown in FIGS. 4 and 5.
  • Reference numeral 20 in FIG. 4A denotes a substrate having an insulating surface
  • reference numeral 21 denotes an insulating film that becomes a blocking layer
  • reference numeral 22 denotes a semiconductor film having an amorphous structure.
  • the base insulating film 21 is formed on the substrate 20 from an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO, ⁇ N ⁇ ), as shown in FIG. 4A.
  • a typical example is a two layer structure as the base insulating film 21 .
  • the structure is employed, in which a first silicon oxynitride film formed to have a thickness of 50 to 100 nm using SiH 4 , NH 3 , and N 2 O as reaction gas, and a second silicon oxynitride film formed to have a thickness of 100 to 150 nm using SiH 4 and N 2 O as reaction gas are laminated.
  • a silicon nitride film (SiN film) with a film thickness of 10 nm or less or a second silicon oxynitride film (SiN ⁇ O ⁇ film, where x>>y) as one layer of the base insulating film 21 .
  • Nickel has a tendency to easily move to regions including oxygen with a high concentration, and therefore it is extremely effective to use a silicon nitride film as the base insulating film that contacts the semiconductor film.
  • a three layer structure in which a first silicon oxynitride film, a second silicon oxynitride film, and a silicon nitride film are laminated in order may also be used.
  • the first semiconductor film 22 containing germanium with an amorphous structure is then formed on the base insulating film.
  • a film such as an amorphous silicon germanium film is typically applied, and is formed to have a thickness of 10 to 100 nm by plasma CVD, reduced pressure CVD, or sputtering. It is preferable to reduce the concentration of impurities such as oxygen and nitrogen contained in the first semiconductor film 22 to a concentration of 5 ⁇ 10 18 /cm 3 or less (atomic concentration measured using secondary ion mass spectrometry. (SIMS)) in order to obtain a semiconductor film with a satisfactory crystalline structure by later crystallizing.
  • SIMS secondary ion mass spectrometry
  • Crystallization is performed next using the technique disclosed in Japanese Patent Application Laid-open No. Hei 8-78329 as a technique for crystallizing the first semiconductor film 22 .
  • the technique in Japanese Patent Application Laid-open No. Hei 8-78329 is that a metallic element for promoting crystallization is selectively added to the amorphous silicon film, and heat treatment is performed. A semiconductor film is thus formed which has a crystalline structure spreading out from the region to which the metallic element is added.
  • a nickel acetate solution containing 1 to 100 ppm by weight of a metallic element (nickel is used here) which has a catalytic action for promoting crystallization is applied to the surface of the first semiconductor film 22 by a spinner to form a nickel containing layer 23 .
  • a metallic element nickel is used here
  • a means for forming an extremely thin film by sputtering, evaporation, or plasma processing may also be employed as an other means for forming the nickel containing layer 23 .
  • the nickel containing layer may be formed selectively by forming a mask.
  • Heat treatment is performed next to perform crystallization.
  • silicides are formed at portions of the semiconductor film which are in contact with the metallic element that promotes crystallization of semiconductor, and then crystallization proceeds with the silicides acting as nuclei.
  • a first semiconductor film 24 a with a crystalline structure is thus formed as shown in FIG. 4C. Note that it is desirable that the concentration of oxygen contained in the first semiconductor film 24 a after crystallization be is 5 ⁇ 10 18 /cm 3 or less.
  • Heat treatment for dehydrogenation is here performed at 450° C. for one hour, and then heat treatment for crystallization is performed for 4 to 24 hours at 550 to 650° C.
  • one kind or a plurality of kinds selected from the group consisting of infrared light, visible light, and ultraviolet light in the case of performing crystallization by irradiating strong light.
  • Light emitted from a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp is typically used.
  • a light source of a lump may be turned on for 1 to 60 seconds, preferably 30 and 60 seconds, and this operation may be repeated one to 10 times to heat the semiconductor film instantaneously to a temperature on the order of 600 to 1000° C.
  • heat treatment for emitting hydrogen contained in the first semiconductor film 24 a may also be performed before irradiating strong light.
  • crystallization may also be performed by using heat treatment and irradiation of strong light at the same time. Considering productivity, it is preferable that crystallization be performed by strong light irradiation.
  • the metallic element (nickel here) remains in the first semiconductor film 24 a thus obtained. Although the metallic element is not distributed uniformly through the film, a concentration exceeding 1 ⁇ 10 19 /cm 3 remains on average. It is of course possible to form various types of semiconductor elements such as TFTs even in this state, but the metallic element is removed by a gettering method described later.
  • Laser light (first laser light) is next irradiated to first semiconductor film 24 a with the crystalline in an atmosphere or in an oxygen atmosphere, in order to increase crystallinity (proportion of crystalline components to the total volume of the film) and in order to repair defects remaining in crystal grains. Unevenness is formed in the surface and a thin oxide film 25 is formed if laser light (a first laser light) is irradiated (See FIG. 4D).
  • the laser light (a first laser light) used is excimer laser light with a wavelength of 400 nm or less, or second harmonic or third harmonic of YAG laser.
  • light emitted from an ultraviolet light lamp may also be used as a substitute for the excimer laser light.
  • pulse laser light with a repetition frequency of approximately 10 to 1000 Hz is used, the pulse laser light is condensed to 100 to 500 mJ/cm 2 by an optical system, and irradiation is performed with an overlap ratio of 90 to 95%, whereby the silicon film surface may be scanned.
  • the oxide film 25 is removed (See FIG. 1E).
  • Laser light (second laser light) is then irradiated to the first semiconductor film with the crystalline structure in a nitrogen atmosphere or in a vacuum.
  • the P-V value Peak to Valley value: difference between the maximum value and the minimum value of height
  • leveled semiconductor film 24 b is performed (See FIG. 1F).
  • the laser light (the second laser light) used is excimer laser light with a wavelength of 400 nm or less, or second harmonic and third harmonic of YAG laser.
  • light emitted from an ultraviolet light lamp may also be used as a substitute for the excimer laser light.
  • the energy density of the second laser light is made larger than the energy density of the first laser light, preferably from 30 to 60 mJ/cm 2 larger.
  • an oxide film (referred to as a chemical oxide film) is formed by using an ozone containing aqueous solution (typically ozone water) to form a barrier layer 26 of an oxide film with a total thickness of 1 to 10 nm. Then, a second semiconductor film 27 containing an inert gas element is formed on the barrier layer 26 (FIG. 5A).
  • the barrier layer 26 functions as an etching stopper in selectively removing the second semiconductor film 106 alone later.
  • the chemical oxide can also be formed similarly by processing with an aqueous solution in which an acid such as sulfuric acid, hydrochloric acid, or nitric acid is mixed with aqueous hydrogen peroxide as a substrate for the ozone containing aqueous solution. It may also be used as another method of forming the barrier layer 26 that ozone is generated by irradiating ultraviolet light in an oxygen atmosphere and the surface of the semiconductor film with the crystalline structure is oxidized. In addition, an oxide film with a thickness on the order of 1 to 10 nm may also be deposited as a barrier layer with a method such as plasma CVD, sputtering, or evaporation as an another method for forming the barrier layer 26 .
  • a method such as plasma CVD, sputtering, or evaporation as an another method for forming the barrier layer 26 .
  • a thin oxide film may also be formed by heating with a clean oven at a temperature on the order of 200 to 350° C., as an another method of forming the barrier layer 26 .
  • a method of forming the barrier layer 26 there are no particular limitations on a method of forming the barrier layer 26 , provided that it is formed by one of, or a combination of, the above stated methods.
  • the barrier layer 26 needs to have a film quality or a film thickness in order that nickel within the first semiconductor film is capable of moving to the second semiconductor film by later gettering.
  • the second semiconductor film 27 containing the inert gas element is formed by sputtering here to form gettering sites.
  • the conditions in sputtering are suitably regulated in order that the inert gas element is not added to the first semiconductor film.
  • One element, or a plurality of elements, selected from the group consisting of helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used as the inert gas element.
  • argon (Ar) which is low cost gas.
  • a target of silicon is used in an atmosphere containing the inert gas element here to form the second semiconductor film.
  • gettering can be performed utilizing the Coulomb force of phosphorous in addition to gettering with rare gas element in the case of forming the second semiconductor film by using a target containing phosphorous which is an impurity element with a single conductivity type.
  • a heat treatment is performed next to perform gettering, for reducing the concentration of the metallic element (nickel) in, or removing the metallic element from, the first semiconductor film (FIG. 5B).
  • a treatment of irradiating strong light or thermal treatment may be performed as the heat treatment.
  • the metallic element moves in the direction of the arrow in FIG. 5B (that is, in the direction from the substrate side toward the surface of the second semiconductor film), to perform removing the metallic element or lowering the concentration of the metallic element, contained in the first semiconductor film 24 b covered by the barrier layer 26 .
  • the distance where the metallic element move during gettering may be a distance at least on the order of the thickness of the first semiconductor film, and gettering can be accomplished in a relatively short amount of time.
  • gettering is performed in order that all of the nickel is made to move to the second semiconductor film 27 without segregating in the first semiconductor film 24 b and that nickel contained in the first semiconductor film 24 b hardly exists. That is, gettering is performed so that the concentration of the nickel within the first semiconductor film becomes equal to or less than 1 ⁇ 10 18 /cm 3 , preferably equal to or less than 1 ⁇ 10 17 /cm 3 .
  • gettering indicates emission of a metallic element from a region to be gettered (the first semiconductor film here) by thermal energy, and movement of the metallic element to gettering sites by diffusion. Accordingly, gettering is dependent upon the processing temperature, and proceeds in a shorter amount of time with higher temperature.
  • a light source of a lump for heating is turned on for 1 to 60 seconds, preferably for 30 to 60 seconds, and this operation is repeated for 1 to 10 times, preferably between 2 and 6 times, in the case of using a process of irradiating strong light as the heat treatment for gettering.
  • the light emission strength of the light source may be set arbitrarily, the semiconductor film made to be instantaneously heated to a temperature of 600 to 1000° C., preferably 700 and 750° C.
  • heating may be conducted in a nitrogen atmosphere at a temperature of 450 to 800° C. for 1 to 24 hours, for example, at 550° C. for 14 hours. Strong light may also be irradiated in addition to the thermal treatment.
  • the second semiconductor film only is selectively removed with using the barrier layer 26 as an etching stopper, and the barrier layer formed of the oxide film 26 is also removed.
  • Dry etching which does not utilize a ClF 3 plasma, or wet etching by using an alkaline solution such as hydrazine or an aqueous solution containing tetraethyl-ammonium-hydroxide (chemical formula (CH 3 ) 4 NOH)) can be performed as the method of selectively etching only the second semiconductor film.
  • an alkaline solution such as hydrazine or an aqueous solution containing tetraethyl-ammonium-hydroxide (chemical formula (CH 3 ) 4 NOH)
  • CH 3 ) 4 NOH tetraethyl-ammonium-hydroxide
  • the barrier layer may be
  • the leveled semiconductor film 24 b is next formed into a semiconductor layer 28 with a desired shape by using a known patterning technique (FIG. 5C). It is preferable to form a thin oxide film on the surface by using ozone water before forming a resist mask.
  • this embodiment can be freely combined with the Embodiment Modes of the invention.
  • preset embodiment may also be combined with other known gettering method.
  • a semiconductor layer is formed into a predetermined shape by gettering, and then it is performed to irradiating second laser light in an inert gas atmosphere or in a vacuum to perform leveling after removing an oxide film, without irradiating the second laser light before gettering.
  • FIGS. 6 to 8 An embodiment of the present invention is described with reference to FIGS. 6 to 8 .
  • a method of simultaneously manufacturing a pixel portion and TFTs (n-channel TFTs and a p-channel TFT) of a driver circuit provided in the periphery of the pixel portion on the same substrate is described in detail.
  • a base insulating film 101 is formed on a substrate 100 , and a first semiconductor film having a crystalline structure is obtained. Then, the semiconductor film is etched to have a desired shape to form semiconductor layers 102 to 106 separated from one another in an island shape.
  • a glass substrate (# 1737 ) is used as the substrate 100 .
  • a semiconductor film having an amorphous structure is formed to have a thickness of 54 nm (preferably 25 to 80 nm) with SiH 4 as a film deposition gas and at a film deposition temperature of 300° C. by using plasma CVD.
  • Si 2 H 6 or SiF 4 instead of SiH 4 and GeF 4 instead of GeH 4 may be used.
  • the base film 101 is shown in a form of a two-layer structure, but a single layer of the insulating film or a structure in which two or more layers thereof are laminated may be adopted.
  • a plasma CVD apparatus may be a single wafer type one or a batch type one.
  • the base insulating film and the semiconductor film may be continuously formed in the same film formation chamber without exposure to an atmosphere.
  • an extremely thin oxide film with a thickness of about 2 nm is formed from ozone water on the surface. Then, in order to control a threshold value of a TFT, doping of a minute amount of impurity element (boron or phosphorous) is performed.
  • impurity element boron or phosphorous
  • an ion doping method is used in which diborane (B 2 H 6 ) is plasma-excited without mass-separation, and boron is added to the amorphous silicon film under the doping conditions: an acceleration voltage of 15 kV; a gas flow rate of diborane diluted to 1% with hydrogen of 30 sccm: and a dosage of 2 ⁇ 10 12 /cm 2 .
  • a nickel acetate salt solution containing nickel of 10 ppm in weight is applied using a spinner.
  • a method of spraying nickel elements to the entire surface by sputtering may also be used.
  • heat treatment is conducted to perform crystallization, thereby forming a semiconductor film having a crystalline structure.
  • a heating process using an electric furnace or irradiation of strong light may be conducted for this heat treatment.
  • the heating process using an electric furnace it may be conducted at 500 to 650° C. for 4 to 24 hours.
  • the heating process (550° C. 1 or 4 hours) for crystallization is conducted, thereby obtaining a silicon film having a crystalline structure.
  • crystallization is performed by using the heating process using a furnace, crystallization may be performed by means of a lamp annealing apparatus.
  • a crystallization technique using nickel as a metal element that promotes crystallization of silicon is used here, other known crystallization techniques, for example, a solid-phase growth method and a laser crystallization method, may be used.
  • first laser light XeCl: wavelength of 308 nm
  • Excimer laser light with a wavelength of 400 nm or less, or second harmonic wave or third harmonic wave of a YAG laser is used for the laser light.
  • pulse laser light with a repetition frequency of approximately 10 to 1000 Hz is used, the pulse laser light is condensed to 100 to 500 mJ/cm 2 by an optical system, and irradiation is performed with an overlap ratio of 90 to 95%, whereby the silicon film surface may be scanned.
  • an oxide film is formed on the surface by the first laser light irradiation since the irradiation is conducted in an atmosphere or in an oxygen atmosphere.
  • second laser light irradiation is performed in a nitrogen atmosphere or in a vacuum, thereby leveling the semiconductor film surface.
  • Excimer laser light with a wavelength of 400 nm or less, or second harmonic wave or third harmonic wave of a YAG laser is used as the laser light (second laser light).
  • the energy density of the second laser light is made larger than that of the first laser light, preferably made larger by 30 to 60 mJ/cm 2 .
  • the surface is processed with ozone water for 120 seconds, thereby forming a barrier layer comprised of an oxide film with a thickness or 1 to 5 nm in total.
  • the film deposition conditions with sputtering in this embodiment are: a film deposition pressure of 0.3 Pa; a gas (Ar) flow rate of 50 sccm; a film deposition power of 3 kW; and a substrate temperature of 150° C.
  • the atomic concentration of the argon element contained in the amorphous silicon film is 3 ⁇ 10 20 /cm 3 to 6 ⁇ 10 20 /cm 3
  • the atomic concentration of oxygen is 1 ⁇ 10 19 /cm 3 to 3 ⁇ 10 19 /cm 3 .
  • the amorphous silicon film containing the argon element, which is the gettering site is selectively removed with the barrier layer as an etching stopper, and then, the barrier layer is selectively removed by dilute hydrofluoric acid. Note that there is a tendency that nickel is likely to move to a region with a high oxygen concentration in gettering, and thus, it is desirable that the barrier layer comprised of the oxide film is removed after gettering.
  • a mask made of resist is formed, and an etching process is conducted thereto to obtain a desired shape, thereby forming the island-like semiconductor layers 102 to 106 separated from one another. After the formation of the semiconductor layers, the mask made of resist is removed.
  • the oxide film is removed with the etchant containing hydrofluoric acid, and at the same time, the surface of the silicon film is cleaned. Thereafter, an insulating film containing silicon as its main constituent, which becomes a gate insulating film 107 , is formed.
  • a first conductive film 108 a with a thickness of 20 to 100 nm and a second conductive film 108 b with a thickness of 100 to 400 nm are formed in lamination.
  • a 50 nm thick tantalum nitride film and a 370 nm thick tungsten film are sequentially laminated on the gate insulating film 107 .
  • a conductive material for forming the first conductive film and the second conductive film an element selected from the group consisting of Ta, W, Ti, Mo, Al and Cu, or an alloy material or compound material containing the above element as its main constituent is employed.
  • a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorous, or an AgPdCu alloy may be used as the first conductive film and the second conductive film.
  • the present invention is not limited to a two-layer structure.
  • a three-layer structure may be adopted in which a 50 nm thick tungsten film, an alloy film of aluminum and silicon (Al—Si) with a thickness of 500 nm, and a 30 nm thick titanium nitride film are sequentially laminated.
  • tungsten nitride may be used in place of tungsten of the first conductive film
  • an alloy film of aluminum and titanium (Al—Ti) may be used in place of the alloy film of aluminum and silicon (Al—Si) of the second conductive film
  • a titanium film may be used in place of the titanium nitride film of the third conductive film.
  • a single layer structure may also be adopted.
  • masks 110 to 115 are formed by an exposure step, and a first etching process for forming gate electrodes and wirings is performed.
  • the first etching process is performed with first and second etching conditions.
  • An ICP (inductively coupled plasma) etching method may be preferably used for the etching process.
  • the ICP etching method is used, and the etching conditions (an electric energy applied to a coil-shape electrode, an electric energy applied to an electrode on a substrate side, a temperature of the electrode on the substrate side, and the like) are appropriately adjusted, whereby a film can be etched to have a desired taper shape.
  • chlorine-based gases typified by Cl 2 , BCl 3 , SiCl 4 , and CCl 4
  • fluorine-based gases typified by CF 4 , SF 6 , and NF 3
  • O 2 can be appropriately used as etching gases.
  • RF (13.56 MHZ) power of 150 W is applied also to the substrate (sample stage) to apply a substantially negative self-bias voltage.
  • a W film is etched to form an end portion of the first conductive layer into a tapered shape.
  • an etching rate to W is 200.39 nm/min
  • an etching rate to TaN is 80.32 nm/min.
  • a selection ratio of W to TaN is about 2.5.
  • a taper angle of W is approximately 26°.
  • the first etching conditions are changed to the second etching conditions without removing the masks 110 to 115 made of resist.
  • CF 4 and Cl 2 are used as etching gases, the flow rate of the gases is set to 30/30 sccm, and RF (13.56 MHZ) power of 500 W is applied to a coil-shape electrode with a pressure of 1 Pa to generate plasma, thereby performing etching for about 30 seconds.
  • RF (13.56 MHZ) power of 20 W is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage.
  • both the W film and the TaN film are etched at the same level. With the second etching conditions, an etching rate to W is 58.97 nm/min. and an etching rate to TaN is 66.43 nm/min. Note that an etching time may be increased by 10 to 20% in order to conduct etching without remaining residue on the gate insulating film.
  • the shape of the mask made of resist is made appropriate, whereby the end portion of the first conductive layer and the end portion of the second conductive layer each have a tapered shape due to the effect of the bias voltage applied to the substrate side.
  • the angle of the tapered portion is sufficiently set to 15 to 45°.
  • first shape conductive layers 117 to 121 composed of the first conductive layer and the second conductive layer (first conductive layers 117 a to 121 a and second conductive layers 117 b to 121 b ) are formed by the first etching process.
  • the insulating film 107 that becomes the gate insulating film is etched by approximately 10 to 20 nm, and becomes a gate insulating film 116 in which regions which are not covered by the first shape conductive layers 117 to 121 are thinned.
  • a second etching process is conducted without removing the masks made of resist.
  • SF 6 , Cl 2 and O 2 are used as etching gases
  • the flow rate of the gases is set to 24/12/24 sccm
  • RF (13.56 MHZ) power of 700 W is applied to a coil-shape electrode with a pressure of 1.3 Pa to generate plasma, thereby performing etching for 25 seconds.
  • RF (13.56 MHZ) power of 10 W is also applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage.
  • an etching rate to W is 227.3 nm/min
  • an etching rate to TaN is 32.1 nm/min
  • a selection ratio of W to TaN is 7.1
  • an etching rate to SiON that is the insulating film 116 is 33 . 7 nm/min
  • a selection ratio of W to SiON is 6.83.
  • the selection ratio with respect to the insulating film 116 is high as described above.
  • reduction in the film thickness can be suppressed.
  • the film thickness of the insulating film 116 is reduced by only about 8 nm.
  • the taper angle of W becomes 70°.
  • second conductive layers 124 b to 129 b are formed.
  • the first conductive layers are hardly etched to become first conductive layers 124 a to 129 a (FIG. 6C).
  • the first conductive layers 124 a to 129 a have substantially the same size as the first conductive layers 117 a to 122 a.
  • the width of the first conductive layer may be reduced by approximately 0.3 ⁇ m, namely, approximately 0.6 ⁇ m in the total line width in comparison with before the second etching process. However, there is almost no change in size of the first conductive layer.
  • first doping process is conducted to obtain the state of FIG. 6D.
  • the doping process may be conducted by ion doping or ion implantation. Ion doping is conducted with the conditions of a dosage of 1.5 ⁇ 10 14 atoms/cm 2 and an accelerating voltage of 60 to 100 keV.
  • impurity element imparting n-type conductivity phosphorous (P) or arsenic (As) is typically used.
  • first conductive layers and second conductive layers 124 to 128 become masks against the impurity element imparting n-type conductivity, and first impurity regions 130 to 134 are formed in a self-aligning manner.
  • the impurity element imparting n-type conductivity is added to the first impurity regions 130 to 134 in a concentration range of 1 ⁇ 10 16 to 1 ⁇ 10 17 /cm 3 .
  • the region having the same concentration range as the first impurity region is also called an n ⁇ region.
  • the first doping process is performed after the removal of the masks made of resist in this embodiment, the first doping process may be performed without removing the masks made of resist.
  • the mask 135 is a mask for protecting a channel forming region and a periphery thereof of a semiconductor layer forming a p-channel TFT of a driver circuit
  • the mask 136 is a mask for protecting a channel forming region and a periphery thereof of a semiconductor layer forming one of n-channel TFTs of the driver circuit
  • the mask 137 is a mask for protecting a channel forming region, a periphery thereof, and a storage capacitor of a semiconductor layer forming a TFT of a pixel portion.
  • phosphorous (P) is doped.
  • impurity regions are formed in the respective semiconductor layers in a self-aligning manner with the second conductive layers 124 b to 126 b as masks. Of course, phosphorous is not added to the regions covered by the masks 135 to 137 . Thus, second impurity regions 138 to 140 and a third impurity region 142 are formed.
  • the impurity element imparting n-type conductivity is added to the second impurity regions 138 to 140 in a concentration range of 1 ⁇ 10 20 to 1 ⁇ 10 21 /cm 3 .
  • the region having the same concentration range as the second impurity region is also called an n + region.
  • the third impurity region is formed at a lower concentration than that in the second impurity region by the first conductive layer, and is added with the impurity element imparting n-type conductivity in a concentration range of 1 ⁇ 10 18 to 1 ⁇ 10 19 /cm 3 .
  • the third impurity region has a concentration gradient in which an impurity concentration increases toward the end portion of the tapered portion.
  • the region having the same concentration range as the third impurity region is called an ⁇ region.
  • the regions covered by the masks 136 and 137 are not added with the impurity element in the second doping process, and become first impurity regions 144 and 145 .
  • fourth impurity regions 149 , 150 and fifth impurity regions 151 , 152 are formed in which an impurity element imparting p-type conductivity is added to the semiconductor layer forming the p-channel TFT and to the semiconductor layer forming the storage capacitor.
  • the impurity element imparting p-type conductivity is added to the fourth impurity regions 149 and 150 in a concentration range of 1 ⁇ 10 20 to 1 ⁇ 10 21 /cm 3 .
  • the impurity element imparting p-type conductivity is added at a concentration that is 1.5 to 3 times as high as that of phosphorous.
  • the fourth impurity regions 149 , 150 have a p-type conductivity.
  • the region having the same concentration range as the fourth impurity region is also called a p + region.
  • fifth impurity regions 151 and 152 are formed in regions overlapping the tapered portion of the second conductive layer 125 a, and are added with the impurity element imparting p-type conductivity in a concentration range of 1 ⁇ 10 18 to 1 ⁇ 10 20 /cm 3 .
  • the region having the same concentration range as the fifth impurity region is also called a p ⁇ region.
  • the impurity regions having n-type or p-type conductivity are formed in the respective semiconductor layers.
  • the conductive layers 124 to 127 become gate electrodes of a TFT.
  • the conductive layer 128 becomes one of electrodes, which forms the storage capacitor in the pixel portion.
  • the conductive layer 129 forms a source wiring in the pixel portion.
  • an insulating film (not shown) that covers substantially the entire surface is formed.
  • a 50 nm thick silicon oxide film is formed by plasma CVD.
  • the insulating film is not limited to a silicon oxide film, and other insulating films containing silicon may be used in a single layer or a lamination structure.
  • a step of activating the impurity element added to the respective semiconductor layers is conducted.
  • a rapid thermal annealing (RTA) method using a lamp light source a method of irradiating light emitted from a YAG laser or excimer laser from the back surface, heat treatment using a furnace, or a combination thereof is employed.
  • a step of forming the insulating film may be conducted after the activation is conducted.
  • a first interlayer insulating film 153 is formed of a silicon nitride film, and heat treatment (300 to 550° C. for 1 to 12 hours) is performed, thereby conducting a step of hydrogenating the semiconductor layers (FIG. 7C).
  • This step is a step of terminating dangling bonds of the semiconductor layers by hydrogen contained in the first interlayer insulating film 153 .
  • the semiconductor layers can be hydrogenated irrespective of the existence of an insulating film (not shown) formed of a silicon oxide film.
  • a material containing aluminum as its main constituent is used for the second conductive layer, and thus, it is important to apply the heating process condition that the second conductive layer can withstand in the step of hydrogenation.
  • plasma hydrogenation (using hydrogen excited by plasma) may be conducted.
  • a second interlayer insulating film 154 is formed from an organic insulating material on the first interlayer insulating film 153 .
  • an acrylic resin film with a thickness of 1.6 ⁇ m is formed.
  • a contact hole that reaches the source wiring 129 , contact holes that respectively reach the conductive layers 127 and 128 , and contact holes that reach the respective impurity regions are formed.
  • a plurality of etching processes are sequentially performed.
  • the second interlayer insulting film is etched with the first interlayer insulating film as the etching stopper, the first interlayer insulating film is etched with the insulating film (not shown) as the etching stopper, and then, the insulating film (not shown) is etched.
  • wirings and pixel electrode are formed by using Al, Ti, Mo, W and the like.
  • As the material of the electrodes and pixel electrode it is desirable to use a material excellent in reflecting property, such as a film containing Al or Ag as its main constituent or a lamination film of the above film.
  • source electrodes or drain electrodes 155 to 160 , a gate wiring 162 , a connection wiring 161 , and a pixel electrode 163 are formed.
  • a p-channel TFT 202 , and an n-channel TFT 203 and a pixel portion 207 having a pixel TFT 204 comprised of an n-channel TFT and a storage capacitor 205 can be formed on the same substrate (FIG. 8).
  • the above substrate is called an active matrix substrate for the sake of convenience.
  • the pixel TFT 204 (n-channel TFT) has a channel forming region 167 , the first impurity region (n 31 region) 145 formed outside the conductive layer 127 forming the gate electrode, and the second impurity region (n + region) 140 functioning as a source region. Further, in the semiconductor layer functioning as one of the electrodes of the storage capacitor 205 , the fourth impurity region 150 and the fifth impurity region 152 are formed.
  • the storage capacitor 205 is constituted of the second electrode 128 and the semiconductor layers 150 , 152 , and 168 with the insulating film (the same film as the gate insulating film) 116 as dielectric.
  • the n-channel TFT 201 (first n-channel TFT) has a channel forming region 164 , the third impurity region (n ⁇ region) 142 that overlaps a part of the conductive layer 124 forming the gate electrode through the insulating film, and the second impurity region (n + region) 138 functioning as a source region or a drain region.
  • the p-channel TFT 202 has a channel forming region 165 , the fifth impurity region (p ⁇ region) 151 that overlaps a part of the conductive layer 125 forming the gate electrode through the insulating film, and the fourth impurity region (p + region) 149 functioning as a source region or a drain region.
  • the n-channel TFT 203 (second n-channel TFT) has a channel forming region 166 , the first impurity region (n ⁇ region) 144 outside the conductive layer 126 forming the gate electrode, and the second impurity region (n + region) 139 functioning as a source region or a drain region.
  • the above TFTs 201 to 203 are appropriately combined to form a shift resister circuit, a buffer circuit, a level shifter circuit, a latch circuit and the like, thereby forming the driver circuit 206 .
  • the n-channel TFT 201 and the p-channel TFT 202 may be complementarily connected to each other.
  • the structure of the n-channel TFT 203 is appropriate for the buffer circuit having a high driving voltage with the purpose of preventing deterioration due to a hot carrier effect.
  • the structure of the n-channel TFT 201 which is a GOLD structure, is appropriate for the circuit in which the reliability takes top priority.
  • a semiconductor film that is high in levelness and in orientation rate of crystal obtained by the present embodiment is formed for use in an active layer of TFT, whereby withstand pressure and reliability of TFT are increased.
  • the active matrix substrate for forming a reflection type display device is shown in this embodiment.
  • the pixel electrode is formed of a transparent conductive film
  • a transmission type display device can be formed although the number of photomasks is increased by one.
  • this embodiment can be freely combined with any of Embodiment Modes and Embodiment 1.
  • This embodiment describes a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate fabricated in Embodiment 2. The description is given with reference to FIG. 9.
  • an oriented film is formed on the active matrix substrate of FIG. 8 and subjected to rubbing treatment.
  • an organic resin film such as an acrylic resin film is patterned to form columnar spacers in desired positions in order to keep the substrates apart.
  • the columnar spacers may be replaced by spherical spacers sprayed onto the entire surface of the substrate.
  • An opposite substrate is prepared next.
  • the opposite substrate has a color filter in which colored layers and light-shielding layers are arranged with respect to the pixels.
  • a light-shielding layer is also placed in the driving circuit portion.
  • a planarization film is formed to cover the color filter and the light-shielding layer.
  • an opposite electrode is formed from a transparent conductive film in the pixel portion.
  • An oriented film is formed over the entire surface of the opposite substrate and is subjected to rubbing treatment.
  • the opposite substrate is bonded to the active matrix substrate on which the pixel portion and the driving circuits are formed, using a sealing member.
  • the sealing member has filler mixed therein and the filler, together with the columnar spacers, keeps the distance between the two substrates while they are bonded.
  • a liquid crystal material is injected between the substrates and an encapsulant (not shown) is used to completely seal the substrates.
  • a known liquid crystal material can be used.
  • the active matrix liquid crystal display device is thus completed. If necessary, the active matrix substrate or the opposite substrate is cut into pieces of desired shapes.
  • the display device may be appropriately provided with a polarizing plate using a known technique.
  • FPCs are attached to the substrate using a known technique.
  • a pixel portion 304 is placed in the center of an active matrix substrate 301 .
  • a source signal line driving circuit 302 for driving source signal lines is positioned above the pixel portion 304 .
  • Gate signal line driving circuits 303 for driving gate signal lines are placed to the left and right of the pixel portion 304 .
  • the gate signal line driving circuits 303 are symmetrical with respect to the pixel portion in this embodiment, the liquid crystal module may have only one gate signal line driving circuit on one side of the pixel portion.
  • a designer can choose the arrangement that suits better considering the substrate size or the like of the liquid crystal module.
  • the symmetrical arrangement of the gate signal line driving circuits shown in FIG. 9 is preferred in terms of circuit operation reliability, driving efficiency, and the like.
  • Signals are inputted to the driving circuits from flexible printed circuits (FPC) 305 .
  • the FPCs 305 are press-fit through an anisotropic conductive film or the like after opening contact holes in the interlayer insulating film and resin film and forming a connection electrode 309 so as to reach the wiring lines arranged in given places of the substrate 301 .
  • the connection electrode is formed from ITO in this embodiment.
  • a sealing agent 307 is applied to the substrate along its perimeter surrounding the driving circuits and the pixel portion.
  • An opposite substrate 306 is bonded to the substrate 301 by the sealing agent 307 while a spacer formed in advance on the active matrix substrate keeps the distance between the two substrates constant (the distance between the substrate 301 and the opposed substrate 306 ).
  • a liquid crystal element is injected through an area of the substrate that is not coated with the sealing agent 307 .
  • the substrates are then sealed by an encapsulant 308 .
  • the liquid crystal module is completed through the above steps.
  • this embodiment can be freely combined with any structures in Embodiment Modes, Embodiment 1 and Embodiment 2.
  • Embodiment 2 shows an example of reflective display device in which a pixel electrode is formed from a reflective metal material. Shown in this embodiment is an example of transmissive display device in which a pixel electrode is formed from a light-transmitting conductive film.
  • a pixel electrode 601 is formed from a light-transmitting conductive film.
  • the light-transmitting conductive film include an ITO (indium tin oxide alloy) film, an indium oxide-zinc oxide alloy (In 2 O 3 —ZnO) film, a zinc oxide (ZnO) film, and the like.
  • connection holes are formed in an interlayer insulating film 600 .
  • a connection electrode 602 overlapping the pixel electrode is formed next.
  • the connection electrode 602 is connected to a drain region through the contact hole.
  • source electrodes or drain electrodes of other TFTs are formed.
  • An active matrix substrate is completed as above.
  • a liquid crystal module is manufactured from this active matrix substrate in accordance with Embodiment 3.
  • the liquid crystal module is provided with a backlight 604 and a light guiding plate 605 , and is covered with a cover 606 to complete the active matrix liquid crystal display device of which a partial sectional view is shown in FIG. 10.
  • the cover is bonded to the liquid crystal module using an adhesive or an organic resin.
  • the substrates may be framed so that the space between the frame and the substrates is filled with an organic resin for bonding. Since the display device is of transmissive type, the active matrix substrate and the opposite substrate each needs a polarizing plate 603 to be bonded.
  • FIGS. 11A and 11B an example of manufacturing a light emitting display device provided with an EL (electro luminescence) element is shown in FIGS. 11A and 11B.
  • FIG. 11A is a top view of an EL module
  • FIG. 11B is a sectional view taken along a line A-A′ of FIG. 11A.
  • a substrate 900 having an insulating surface for example, a glass substrate, a crystallized glass substrate, a plastic substrate or the like
  • a pixel portion 902 On a substrate 900 having an insulating surface (for example, a glass substrate, a crystallized glass substrate, a plastic substrate or the like), a pixel portion 902 , a source side driver circuit 901 , and a gate side driver circuit 903 are formed.
  • the pixel portion and the driver circuits can be obtained in accordance with the above-described embodiments.
  • reference numeral 918 indicates a sealing member
  • reference numeral 919 indicates a DLC film.
  • the pixel portion and the driver circuit portions are covered by the sealing member 918 , and the sealing member is covered by a protective film 919 . Further, the protective film 919 is sealed by a cover member 920 using an adhesive. It is desirable that the cover member 920 is made of the same material as the substrate 900 , for example, is a glass substrate in order to withstand deformation due to heat or external force.
  • the cover member 920 is processed to have the recess shape (with a depth of 3 to 10 ⁇ m) shown in FIG. 11B by sandblasting or the like. It is desirable that the cover member 920 is further processed to form a recess portion (with a depth of 50 to 200 ⁇ m) into which a drying agent 921 can be arranged. Further, in the case where multiple EL modules are manufactured, after the substrate and the cover member are attached with each other, segmentation may be conducted using a CO 2 laser or the like such that end surfaces match with each other.
  • reference numeral 908 indicates a wiring for transmitting signals input to the source side driver circuit 901 and the gate side driver circuit 903 , and receives a video signal and a clock signal from an FPC (flexible printed circuit) 909 that is an external input terminal.
  • FPC flexible printed circuit
  • PWB printed wiring board
  • An insulating film 910 is provided on the substrate 900 , the pixel portion 902 and the gate side driver circuit 903 are formed above the insulating film 910 , and the pixel portion 902 is constituted of a plurality of pixels including a current control TFT 911 and a pixel electrode 912 electrically connected to a drain of the current control TFT 911 . Further, the ate side driver circuit 903 is formed by using a CMOS circuit in which an n-channel TFT 913 and a p-channel TFT 914 are combined.
  • the above TFTs (including 911 , 913 , and 914 ) may be manufactured in accordance with the n-channel TFT 201 and the p-channel TFT 202 in Embodiment 2.
  • a material of the insulating film provided between the TFT and the EL element it is appropriate to use a material that not only blocks diffusion of impurity ions such as alkali metal ions or alkaline-earth metal ions but also positively adsorbs the impurity ions such as alkali metal ions or alkaline-earth metal ions, and further to use a material that can withstand a subsequent process temperature.
  • a silicon nitride film containing a large amount of fluorine is given as an example.
  • the concentration of fluorine contained in the silicon nitride film is 1 ⁇ 10 19 /cm 3 or more, and preferably, the composition ratio of fluorine in the silicon nitride film is 1 to 5%. Fluorine in the silicon nitride film bonds to alkali metal ions or alkaline-earth metal ions, and is adsorbed into the film.
  • an organic resin film containing particulates comprised of a stibium (Sb) compound, a stannum (Sn) compound or an indium (In) compound, which adsorbs alkali metal ions, alkallin-earth metal ions or the like
  • an organic resin film containing particulates of stibium pentoxide Sb 2 O 5 .nH 2 O.
  • this organic resin film contains particulates with an average particle size of 10 to 20 nm, and has high light transmission properties.
  • the stibium compound typified by the stibium pentoxide particulates is likely to adsorb impurity ions such as alkali metal ions or alkaline-earth metal ions.
  • the pixel electrode 912 functions as an anode of a light emitting element (EL element). Further, banks 915 are formed at both ends of the pixel electrode 912 , and an EL layer 916 and a cathode 917 of the light emitting element are formed on the pixel electrode 912 .
  • EL element light emitting element
  • a light emitting layer, a charge transportation layer and a charge injection layer may be freely combined to form an EL layer (layer for light emission and movement of carrier for light emission).
  • a low molecular weight organic EL material or a high molecular weight organic EL material man be used.
  • a thin film formed from a light emitting material that emits light by singlet excitation (fluorescence) (singlet compound) or a thin film formed from a light emitting material that emits light by triplet excitation (phosphorescence) (triplet compound) can be used.
  • an inorganic material such as silicon carbide can be used for the charge transportation layer or the charge injection layer. Known materials can be used for the organic EL materials or inorganic materials.
  • a cathode 917 also functions as a wiring common to all the pixels, and is electrically connected to the FPC 909 through the connection wiring 908 . Further, all the elements contained in the pixel portion 902 and the gate side driver circuit 903 are covered by the cathode 917 , the sealing member 918 and the protective film 919 .
  • the sealing member 918 is desirably formed from a material that does not permeate moisture or oxygen as much as possible.
  • the protective film 919 comprised of a DLC film or the like is provided at least on the surface (exposed surface) of the sealing member 918 as shown in FIGS. 11A and 11B. Further, the protective film may be provided on the entire surface including the back surface of the substrate. Here, it is necessary that attention is paid to in order that the protective film is not deposited to the portion where the external input terminal (FPC) is provided. A mask may be used in order not to form the protective film. Alternatively, the external input terminal portion may be covered by a tape formed of Teflon (registered trademark) or the like, which is used as a masking tape in a CVD apparatus in order not to form the protective film.
  • Teflon registered trademark
  • the light emitting element is sealed by the sealing member 918 and the protective film with the above-described structure, whereby the light emitting element can be completely shut from the outside.
  • a substance that promotes deterioration due to oxidization of the EL layer, such as moisture or oxygen from permeating from the outside Therefore, the light emitting device with high reliability can be obtained.
  • a pixel electrode is a cathode, and an EL layer and an anode are laminated to thereby provide light emission in an opposite direction to that in FIGS. 11A and 11B.
  • the driver circuit and the pixel portion formed by implementing the present invention can be used in various modules (active matrix type liquid crystal module, active matrix type EL module and active matrix type EC module). That is, the present invention can be implemented in all of electronic equipments integrated with the modules at display portions thereof.
  • FIGS. 12 to 14 As such electronic equipment there are pointed out a video camera, a digital camera, a head mount display (goggle type display), a car navigation system, a projector, a car stereo, a personal computer, a portable information terminal (mobile computer, cellular phone or electronic book) and the like. Examples of these are shown in FIGS. 12 to 14 .
  • FIG. 12A shows a personal computer including a main body 2001 , an image input portion 2002 , a display portion 2003 and a keyboard 2004 .
  • the present invention can be applied to the display portion 2003 .
  • FIG. 12B shows a video camera including a main body 2101 , a display portion 2102 , a voice input portion 2103 , operation switches 2104 , a battery 2105 and an image receiving portion 2106 .
  • the present invention can be applied to the display portion 2102 .
  • FIG. 12C shows a mobile computer including a main body 2201 , a camera portion 2202 , an image receiving portion 2203 , an operation switch 2204 and a display portion 2205 .
  • the present invention can be applied to the display portion 2205 .
  • FIG. 12D shows a goggle type display including a main body 2301 a display portion 2302 and an ann portion 2303 .
  • the present invention can be applied to the display portion 2302 .
  • FIG. 12E shows a player using a record medium recorded with programs (hereinafter, referred to as record medium) including a main body 2401 , a display portion 2402 , a speaker portion 2403 , a record medium 2404 and an operation switch 2405 .
  • the player uses DVD (Digital Versatile Disc) or CD as the record medium and can enjoy music, enjoy movie and carry out game or Internet.
  • the present invention can be applied to the display portion 2402 .
  • FIG. 12F shows a digital camera including a main body 2501 , a display portion 2502 , an eye contact portion 2503 , operation switches 2504 and an image receiving portion (not illustrated).
  • the present invention can be applied to the display portion 2502 .
  • FIG. 13A shows a front type projector including a projection equipment 2601 and a screen 2602 .
  • the present invention can be applied to the liquid crystal module 2808 forming a part of the projection equipment 2601 .
  • FIG. 13B shows a rear type projector including a main body 2701 a projection equipment 2702 , a mirror 2703 and a screen 2704 .
  • the present invention can be applied to the liquid crystal module 2808 forming a part of the projection equipment 2702 .
  • FIG. 13C is a view showing an example of a structure of the projection equipment 2601 and 2702 in FIG. 13A and FIG. 13B.
  • the projection equipment 2601 or 2702 is constituted by a light source optical system 2801 , mirrors 2802 , and 2804 through 2806 , a dichroic mirror 2803 , a prism 2807 , a liquid crystal display equipment 2808 , a phase difference plate 2809 and a projection optical system 2810 .
  • the projection optical system 2810 is constituted by an optical system including a projection lens.
  • this embodiment shows an example of three plates type, this embodiment is not particularly limited thereto but may be of, for example, a single plate type. Further, person of executing this embodiment may pertinently provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference or an IR film in an optical path shown by arrow marks in FIG. 13C.
  • FIG. 13D is a view showing an example of a structure of the light source optical system 2801 in FIG. 13C.
  • the light source optical system 2801 is constituted by a reflector 2811 , a light source 2812 , lens arrays 2813 and 2814 , a polarization conversion element 2815 and a focusing lens 2816 .
  • the light source optical system shown in FIG. 13D is only an example and this example is not particularly limited thereto.
  • a person of executing this embodiment may pertinently provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference or an IR film in the light source optical system.
  • FIG. 14A shows a cellular phone including a main body 2901 , a sound output portion 2902 , a sound input portion 2903 , a display portion 2904 , an operation switch 2905 , an antenna 2906 and an image input portion (CCD, image sensor or the like) 2907 .
  • the present invention can be applied to display portion 2904 .
  • FIG. 14B shows a portable book (electronic book) including a main body 3001 , display portions 3002 and 3003 , a record medium 3004 , an operation switch 3005 and an antenna 3006 .
  • the present invention can be applied to display portions 3002 and 3003 .
  • FIG. 14C shows a display including a main body 3101 , a support base 3102 and a display portion 3103 .
  • the present invention can be applied to display portion 3103 .
  • the display shown in FIG. 14C is small and medium type or large type, for example, screen of the display sized 5 to 20 inches. Moreover, it is preferable to mass-produce by executing a multiple pattern using a substrate sized 1 ⁇ 1 m to form such sized display section.
  • the range of applying the present invention is extremely wide and is applicable to electronic equipment of all the fields.
  • the electronic equipment of the present invention can be implemented by freely combined with the structures in Embodiments 1 to 5.
  • a semiconductor film that is high in levelness and in orientation rate of crystal is formed for use in an active layer of TFT, whereby a semiconductor device which has a low OFF current value with a reduced variation can be obtained.

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