US20020072159A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
US20020072159A1
US20020072159A1 US10/007,384 US738401A US2002072159A1 US 20020072159 A1 US20020072159 A1 US 20020072159A1 US 738401 A US738401 A US 738401A US 2002072159 A1 US2002072159 A1 US 2002072159A1
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insulating film
gate insulating
region
semiconductor device
body region
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US10/007,384
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English (en)
Inventor
Eiji Nishibe
Shuichi Kikuchi
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Assigned to SANYO ELECTRIC CO., LTD. reassignment SANYO ELECTRIC CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIKUCHI, SHUICHI, NISHIBE, EIJI
Publication of US20020072159A1 publication Critical patent/US20020072159A1/en
Priority to US10/809,011 priority Critical patent/US7217612B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • the present invention is related to a semiconductor device and a method for manufacturing the semiconductor device. More specifically, the present invention is directed to an LD (Lateral Double Diffused) MOS (Metal-Oxide Semiconductor) transistor technique functioning as a high voltage element which is utilized as, for instance, a liquid crystal driving IC.
  • LD Layer Double Diffused
  • MOS Metal-Oxide Semiconductor
  • an LDMOS transistor structure implies such a transistor structure that impurities having different conductive types are diffused with respect to a region formed on the side of a surface of a semiconductor substrate so as to form new regions, and a difference between diffusions of these regions along a lateral direction is utilized as an effective channel length. Since a short channel is formed, the resulting transistor structure may constitute such an element suitably having a lower ON-resistance value.
  • FIG. 9 is a sectional diagram for explaining a conventional LDMOS transistor, as one example thereof, for representing an N-channel type LDMOS transistor structure. It should be noted that while a description as to a P-channel type LDMOS transistor structure is omitted, as is well known in this field, this P-channel type LDMOS transistor owns a similar structure of the N-channel type LDMOS transistor except for the conductive type thereof.
  • reference numeral 51 shows one conductive type semiconductor substrate, for example, a P type semiconductor substrate (P-Sub), and reference numeral 52 represents an N type well region.
  • N well a P type semiconductor substrate
  • PB P type body region
  • N + N type
  • another N type (N + ) region 55 is formed in the N type well region 52 .
  • a gate electrode 58 is formed on a surface of the semiconductor substrate in such a manner that this gate electrode 58 is bridged between a first gate insulating film 56 and a second gate insulating film 57 , the film thickness of which is thinner than that of the first gate insulating film 56 .
  • a channel region 59 is formed in a surface region of the P type body region 53 located just under this gate electrode 58 .
  • N + type region 54 is used as a source region
  • the N + type region 55 is used as a drain region
  • the N type well region 52 is used as a drift region.
  • reference numeral 60 shows a device separation film
  • symbol “S” denotes a source electrode
  • symbol “G” indicates a gate electrode
  • symbol “D” represents a drain electrode.
  • Reference numeral 61 shows a P type (P + ) region which is employed so as to secure a potential of the P type body region 53 .
  • reference numeral 62 shows an interlayer insulating film.
  • the simulation result could reveal such a fact that local current crowding (namely, region “A” shown in FIG. 9) may occur between an edge portion of the P type body region 53 and an edge portion of the first gate insulating film 56 , and thus, a current can very hardly flow between the source of this LDMOS transistor and the drain thereof.
  • local current crowding namely, region “A” shown in FIG. 9
  • the present invention has an object to reduce local current crowding in such a manner that a concave/convex region at a boundary surface between a semiconductor substrate (Si) and a gate insulating film (Sio 2 film) is eliminated so as to distribute equipotential lines.
  • a semiconductor device comprising: for instance, a first gate insulating film which is pattern-formed on a second conductive type well region within a first conductive type semiconductor substrate in such a manner that a side wall portion of the first gate insulating film is made in a taper shape; a second gate insulating film which is formed on the semiconductor substrate except for the first gate insulating film; a gate electrode which is formed in such a manner that the gate electrode is bridged over the first gate insulating film and the second gate insulating film; a first conductive type body region which is formed in such a manner that the first conductive type body region is located adjacent to the gate electrode; a second conductive type source region and a channel region, which are formed within the first conductive type body region; and a second conductive type drain region which is formed at a position separated from the first conductive type body region.
  • the first gate insulating film of the above-described semiconductor device is not formed at a position lower than at least a surface position of the semiconductor substrate.
  • a manufacturing method of this semiconductor device is featured as follows: That is, a second conductive type impurity ion is implanted into a first conductive type semiconductor substrate and then is diffused in the semiconductor substrate so as to form a second conductive type well region, and while a resist film formed on a predetermined region of the second conductive type well region is used as a mask, a first conductive type impurity ion is implanted and then is diffused so as to form a first conductive type body region.
  • the insulating film is patterned so as to form a first insulating film.
  • a second gate insulating film is formed on the semiconductor substrate other than the first gate insulating film, and a gate electrode is formed in such a manner that the gate electrode is bridged over the first gate insulating film and the second gate insulating film.
  • the second conductive type impurity ion is implanted into both a source forming region formed within the first conductive type body region and a drain forming region formed within the second conductive type well region so as to form a source region and a drain region.
  • the step for forming the first gate insulating film is the same step as a step for forming a device separation film.
  • the first gate insulating film is not formed at a position lower than at least a surface position of the semiconductor substrate.
  • FIG. 1 is a sectional view for indicating a manufacturing method of a semiconductor device according to an embodiment of the present invention
  • FIG. 2 is a sectional view for showing the manufacturing method of the semiconductor device according to one embodiment of the present invention
  • FIG. 3 is a sectional view for representing the manufacturing method of the semiconductor device according to one embodiment of the present invention.
  • FIG. 4 is a sectional view for showing the manufacturing method of the semiconductor device according to one embodiment of the present invention.
  • FIG. 5 is a sectional view for representing the manufacturing method of the semiconductor device according to one embodiment of the present invention.
  • FIG. 6 is a sectional view for showing the manufacturing method of the semiconductor device according to one embodiment of the present invention.
  • FIG. 7 is a sectional view for representing the manufacturing method of the semiconductor device according to one embodiment of the present invention.
  • FIG. 8 is a sectional view for showing the manufacturing method of the semiconductor device according to one embodiment of the present invention.
  • FIG. 9 is a sectional view for representing the conventional semiconductor device.
  • FIG. 8 is a sectional view for showing a semiconductor device according to the present invention, more specifically, for explaining an LDMOS transistor, as one example thereof, for representing an N-channel type LDMOS transistor structure. It should be noted that while a description as to a P-channel type LDMOS transistor structure is omitted, as is well known in this field, this P-channel type LDMOS transistor owns a similar structure of the N-channel type LDMOS transistor except for the conductive type thereof.
  • reference numeral 1 shows one conductive type semiconductor substrate, for example, a P type semiconductor substrate (P-Sub), and reference numeral 2 represents an N type well region (N well).
  • N type well region 2 a P type body region (PB) 4 is formed, whereas an N type (N + ) region 11 is formed in the above-explained P type body region 4 , and another N type (N ⁇ ) region 3 is formed in the N type well region 2 .
  • another N type (N + ) region 12 is formed in this N type (N ⁇ ) region 3 .
  • a gate electrode 9 is formed on a surface of the semiconductor substrate in such a manner that this gate electrode 9 is bridged between a first gate insulating film 7 A and a second gate insulating film 8 , the film thickness of which is thinner than that of the first gate insulating film 7 A.
  • a channel region 13 is formed in a surface region of the P type body region 4 located just under this gate electrode 9 .
  • N + type region 11 is used as a source region
  • both the N ⁇ type region 3 and the N + type region 12 are used as a drain region
  • the N type well region 2 is used as a drift region.
  • reference numeral 7 B shows a device separation film
  • symbol “S” denotes a source electrode
  • symbol “G” indicates a gate electrode
  • symbol “D” represents a drain electrode.
  • Reference numeral 14 shows a P type (P+) region which is employed so as to secure a potential of the P type body region 4 .
  • reference numeral 15 shows an interlayer insulating film.
  • the semiconductor device of the present invention has a feature where, as indicated in FIG. 8, the first gate insulating film 7 A is not formed at such a position lower than, at least, the surface position of the semiconductor substrate 1 .
  • the semiconductor device of the present invention owns such a structure that the local current crowding does not occur between the edge portion of the P type body region and the edge portion of the first gate insulating film, as compared with the structure of the conventional semiconductor device (FIG. 9) in which the first gate insulating film 56 is formed under the surface of the substrate.
  • N type impurity is implanted in an ion-implantation manner into a desirable region of the substrate 1 . Since this N type impurity is diffused in a desirable region, the N type well region 2 may be formed. In this case, the above-explained N type well region 2 may constitute the drift region.
  • N type impurity for example, a phosphorus ion is implanted at an acceleration energy of approximately 160 keV and a dose of approximately 5.0 ⁇ 10 12 /cm 2 , and this phosphorus iron is thermally diffused at a temperature of about 1,200° C. and for 13 hours.
  • the phosphorus ion is implanted at the acceleration energy of approximately 100 KeV and the dose of approximately 4.0 ⁇ 10 12 /cm 2 .
  • the boron ion is implanted at the acceleration energy of approximately 80 KeV, and the dose of approximately 1.5 ⁇ 10 13 /cm 2 . Thereafter, these phosphorus and boron ions are thermally diffused at the temperature of approximately 1,050° C. and for 2 hours.
  • an oxidation resistance film for instance, silicon nitride film, not shown
  • a pad oxide film not shown
  • a predetermined region not shown
  • the resulting semiconductor substrate is field-oxidized by way of the LOCOS (local oxidation of silicon) method, so that an insulating film 5 having a film thickness of approximately 1100 nm is formed.
  • this insulating film 5 is patterned to form both the first gate insulating film 7 A and the device separation film 7 B. It should also be noted that in this manufacturing step, since the above-described insulating film 5 is etched away by the isotropic etching method by using hydrofluoric acid, this insulating film 5 is patterned in such a manner that a side wall portion of this insulating film 5 is made in a taper shape. Alternatively, such an isotropic etching treatment that a wet etching process is combined with a dry etching process may be used, and a dry etching treatment using isotropic gas may be employed.
  • the surface of the substrate 1 except for both the first gate insulating film 7 A and the device separation film 7 B are thermally oxidized so as to form such a second gate insulating film 8 having a thickness of approximately 45 nm, and a gate electrode 9 is formed in such a manner that this gate electrode 9 is bridged from this second gate insulating film 8 and over the first gate insulating film 7 A.
  • the gate electrode 9 of the LDMOS transistor according to this embodiment is made of a polysilicon film which is manufactured in such a manner that while POCl 3 is employed as a thermal diffusion source, a phosphorus ion is doped and the ion-doped polysilicon film is made conductive. More specifically, this gate electrode 9 may be constituted by a polycide electrode manufactured in such a manner that a tungsten silicide (WSix) is stacked on this polysilicon film.
  • WSix tungsten silicide
  • a phosphorus ion is implanted at the acceleration energy of approximately 70 keV and the dose of approximately 1.0 ⁇ 10 14 /cm 2 .
  • a side wall spacer film is formed on a side wall portion of the gate electrode 9 .
  • arsenic ion is implanted at the acceleration energy of approximately 70 keV and the dose of approximately 6.0 ⁇ 10 16 /cm 2 .
  • the structures of the source/drain regions are not limited to the above-explained LDD structure.
  • a P type impurity for example, boron difluoride ion
  • a P type impurity for example, boron difluoride ion
  • aborondifluoride ion is implanted at the acceleration energy of 60 kev and the dose of 4 ⁇ 10 16/cm 2 .
  • the interlayer insulating film 15 is formed so that this interlayer insulating film 15 covers an entire surface of the resulting semiconductor device, and contact holes (not shown) are formed in the interlayer insulating film 15 . Then, the source electrode S, the drain electrode D and the gate electrode G are respectively formed via the contact hole. Next, although the description with reference to the drawings is not made, a passivation film is formed on the entire surface of the semiconductor device, so that the semiconductor device may be accomplished.
  • the semiconductor device manufacturing method according to the present invention is different from the conventional manufacturing method for manufacturing the first gate insulating film and the device separation film, and has a feature that the insulating film 5 is formed on the semiconductor substrate 1 by way of the LOCOS method, and then, this formed insulating film 5 is patterned in the desirable shape so as to form both the first gate insulating film 7 A and the device separation film 7 B.
  • the first gate insulating film 7 A is not formed at such a position lower than, at least, the surface position of the substrate.
  • the equipotential lines are no longer distributed by widening the space which is surrounded by both the edge portion (wall) of the first gate insulating film 7 A and the edge portion (wall) of the P type body region 4 .
  • This structure does not disturb, or impede that this semiconductor device is manufactured in very fine manners.
  • the surface of the substrate 1 is field-oxidated by way of the LOCOS method so as to form the insulating film 5 , and the resultant insulating film 5 is patterned, so that the first gate insulating film 7 A and the device separation film 7 B are formed.
  • the present invention is not limited to this manufacturing method.
  • this formed oxide film is patterned in a desirable shape, so that the first gate insulating film 7 A and the device separation film 7 B may be formed.
  • the semiconductor device of the present invention may be accomplished by employing not only the LOCOS method, but also the CVD method. Precisely speaking, when the CVD method is compared with the LOCOS method, this LOCOS method owns the below-mentioned merits.
  • the thermal oxide film which is formed by employing the LOCOS method owns the higher quality than that of the oxide film which is formed by using the CVD method. As a result, the reliability may be improved. Also, there is no increase in the step for forming the CVD oxide film. Furthermore, the better matching characteristic of this oxide film formed by the LOCOS method with respect to another region and another device may be achieved. In other words, for example, as previously explained in this embodiment, the LOCOS device separation film may be used in accordance with the LOCOS method similar to the background art. To the contrary, when the CVD method is employed, such a LOCOS film may not be used also in another region.
  • the local current crowding does not occur between the edge portion of one conductive type body region and the edge portion of the first gate insulating film. This local current crowding occurs in the background art.
  • the reliability can be improved.
  • the insulating film is manufactured by way of the LOCOS method, the better matching characteristic of this insulating film with respect to other regions and also other devices can be realized.
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US6946706B1 (en) * 2003-07-09 2005-09-20 National Semiconductor Corporation LDMOS transistor structure for improving hot carrier reliability
US7214992B1 (en) * 2004-10-27 2007-05-08 National Semiconductor Corporation Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions
US20070181943A1 (en) * 2006-01-14 2007-08-09 Infineon Technologies Austria Ag Lateral power transistor and method for producing same
US20070181941A1 (en) * 2006-02-09 2007-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. High voltage semiconductor devices and methods for fabricating the same
US20080246080A1 (en) * 2006-07-28 2008-10-09 Broadcom Corporation Shallow trench isolation (STI) based laterally diffused metal oxide semiconductor (LDMOS)
US20090273029A1 (en) * 2008-05-02 2009-11-05 William Wei-Yuan Tien High Voltage LDMOS Transistor and Method
US20090321852A1 (en) * 2008-06-27 2009-12-31 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US20100295125A1 (en) * 2009-05-22 2010-11-25 Broadcom Corporation Split gate oxides for a laterally diffused metal oxide semiconductor (LDMOS)
US20110057271A1 (en) * 2006-07-28 2011-03-10 Broadcom Corporation Semiconductor Device with Increased Breakdown Voltage
US8274114B2 (en) 2010-01-14 2012-09-25 Broadcom Corporation Semiconductor device having a modified shallow trench isolation (STI) region and a modified well region
US8283722B2 (en) 2010-06-14 2012-10-09 Broadcom Corporation Semiconductor device having an enhanced well region
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US8698236B2 (en) 2010-11-24 2014-04-15 Semiconductor Components Industries, Llc Semiconductor device and method of manufacturing the same
US9123807B2 (en) 2010-12-28 2015-09-01 Broadcom Corporation Reduction of parasitic capacitance in a semiconductor device
WO2016034043A1 (zh) * 2014-09-02 2016-03-10 无锡华润上华半导体有限公司 Ldmos器件的制作方法
US20160093632A1 (en) * 2014-01-16 2016-03-31 Microchip Technology Incorporated High voltage double-diffused mos (dmos) device and method of manufacture
US20190028098A1 (en) * 2016-07-11 2019-01-24 Magnachip Semiconductor, Ltd. Semiconductor device for display driver ic structure
CN113972265A (zh) * 2020-07-23 2022-01-25 和舰芯片制造(苏州)股份有限公司 一种改善带场板的ldmos制程工艺的方法
US20220028746A1 (en) * 2019-07-17 2022-01-27 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device

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JP3831602B2 (ja) 2006-10-11
JP2002176173A (ja) 2002-06-21

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