US20020024111A1 - Shallow trench isolation type semiconductor device and method of forming the same - Google Patents

Shallow trench isolation type semiconductor device and method of forming the same Download PDF

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Publication number
US20020024111A1
US20020024111A1 US09/819,962 US81996201A US2002024111A1 US 20020024111 A1 US20020024111 A1 US 20020024111A1 US 81996201 A US81996201 A US 81996201A US 2002024111 A1 US2002024111 A1 US 2002024111A1
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Prior art keywords
trench
flexure
layer
gate insulating
oxide layer
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US09/819,962
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You-Cheol Shin
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIN, YOU-CHEOL
Publication of US20020024111A1 publication Critical patent/US20020024111A1/en
Priority to US10/407,115 priority Critical patent/US7144790B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

Definitions

  • the present invention generally relates to a shallow trench isolation type semiconductor device and a method of forming the same. More specifically, the present invention is directed to a shallow trench isolation type semiconductor device in which insulating layers differ in thickness according to regions, and a method of forming the same.
  • a common problem encountered in device isolation in a high-density semiconductor device is a bird's beak effect, which occurs due to a lateral growth of thermal silicon dioxide in the form of a bird's beak under a SiN 4 protective layer.
  • the bird's beak is undesirable since it takes up needed area and has electrical field effects that permit current leakage.
  • a shallow trench isolation (STI) technique for device isolation has been widely used and avoids the problem of the bird's beak effect.
  • STI shallow trench isolation
  • the depth and width of a trench must be increased. Since it is desirable to have semiconductor devices having small footprints for higher integration, the depth must be increased while the width for insulation must be decreased. In a less than ideal scenario, a deep trench cannot be formed due to the decrease in the width.
  • the component at which a high voltage is applied must have a structure that is able to withstand the high voltage.
  • a gate insulating layer formed at the part where the high voltage is applied is made thicker than the gate insulating layer formed at others.
  • FIG. 1 is an exemplary cross-sectional view showing the difference in thickness of a gate insulating layer at a low voltage part of cell and peripheral regions compared to a gate insulating layer at a high voltage part of the peripheral region.
  • FIG. 1 also shows an exemplary formation of a self-aligned trench in each region of a flash memory device in which the gate insulating layers differ in thickness.
  • a trench 17 for device isolation is shallowly formed, which increases the probability that insulation for device isolation will not be sufficient.
  • FIG. 1 includes gate insulating layers 11 and 13 which differ in thickness according to each region of a substrate 10 .
  • the thickness of the gate insulating layer 11 formed at a low voltage part of cell and peripheral regions is about 70 ⁇ to about 80 ⁇ and the thickness of the gate insulating layer 13 formed at a high voltage part of the peripheral region is about 250 ⁇ to about 350 ⁇ .
  • a polysilicon layer 15 for forming a part of a self-aligned floating gate is stacked on the gate insulating layers 11 and 13 .
  • device isolation is then carried out.
  • an etch-stop layer made of silicon nitride is deposited.
  • a high temperature oxide (HTO) layer is then deposited for patterning the etch-stop layer, and an anti-reflection coating (ARC) layer is additionally deposited.
  • HTO high temperature oxide
  • ARC anti-reflection coating
  • a trench pattern for device isolation is formed.
  • upper layers are sequentially etched to be removed.
  • a patterned upper layer can serve as an etching mask to a lower layer.
  • the etch-stop layer is patterned and the photoresist pattern is removed by ashing and stripping techniques.
  • the polysilicon layer 15 , the gate insulating layers 11 and 13 , and the substrate silicon layer 10 are etched to form a trench. In the etching process to form the trench, separately etching the gate insulating layer and the substrate causes problems due to shifting of the etching apparatus.
  • the process is carried out in one etching apparatus (i.e., “in-situ”). It takes a great deal of time to etch a gate insulating layer at a part where the gate insulating layer is thickly formed.
  • a depth difference (A) of about 180 ⁇ to about 500 ⁇ is observed in a substrate trench where the gate insulating layer is thickly formed.
  • the depth difference (A) varies according to the type of etchant used.
  • the trench is filled with a CVD oxide layer.
  • CMP chemical mechanical planarization
  • a wet etching process to remove an etch-stop layer made of silicon nitride, and a cleaning process are then performed.
  • A depth difference
  • a shallow trench isolation type semiconductor device wherein a flexure with a step difference is made at a bottom of a trench.
  • a shallow trench isolation type semiconductor device including at least two regions where gate insulating layers differ in thickness; and a silicon substrate with at least one flexure trench having a step difference.
  • a gate insulating layer is deposited at a thickness of about 200 ⁇ or more.
  • the gate insulating layer has a thin region of about 100 ⁇ or less and a thick region of about 200 ⁇ or more. If a step difference of the gate insulating layer is about 100 ⁇ , the step difference of about 100 ⁇ will remain in an etching process without an etching selectivity with respect to a silicon oxide layer and a silicon layer. The step difference can be expanded to, for example, about 500 ⁇ .
  • the flexure may lean toward the active region.
  • the flexure may be concave and convex.
  • a plurality of flexures may be made therein.
  • a typical example of an aspect of the present invention can be shown in a flash memory that has a thick gate oxide layer of about 300 ⁇ or more in a peripheral region, and a thin gate oxide layer of about 80 ⁇ or less in a low voltage part of cell and peripheral regions.
  • the typical example is shown in a self-aligned flash memory wherein a polysilicon layer to form a part of a floating gate and a trench etching mask are sequentially deposited on a gate insulating layer.
  • the present invention is particularly effective in cases where a width of a trench between one active region and another is 3 micrometers or less at a region having a thick gate oxide layer.
  • a method according to the present invention includes the steps of making a flexure to have a gate oxide layer whose thickness is different from that of an adjacent gate oxide layer, forming an etching mask pattern to expose the gate oxide layer at a trench area including the flexure, and anisotropically etching the gate oxide layer and a silicon substrate to form a trench.
  • a method of forming a shallow trench isolation type semiconductor device comprises the steps of: forming a gate oxide layer, so that a flexure is different from adjacent parts in thickness, the flexure being a part of a trench area on a substrate; forming an etching mask pattern to expose the gate oxide layer in the trench area; and anisotropically and sequentially etching the gate oxide layer and a silicon substrate to form a trench, the gate oxide layer being located on the substrate where the etching mask pattern is formed.
  • the step of anisotropically etching the gate oxide layer and the silicon substrate comprises two steps: etching the gate oxide layer to expose the silicon substrate on the basis of a thin or thick gate oxide area, and etching the silicon substrate.
  • an etchant having a low etching selectivity is used.
  • the silicon substrate is etched in a thin gate oxide area as much as a predetermined thickness according to a kind of etchant.
  • one etchant is used in the two steps.
  • FIG. 1 is an exemplary cross-sectional view showing the difference in thickness of a gate insulating layer at a low voltage part of cell and peripheral regions compared to a gate insulating layer at a high voltage part of the peripheral region.
  • FIG. 2 is an exemplary cross-sectional view showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory according to an aspect of the present invention, wherein gate insulating layers that differ in thickness are formed.
  • FIG. 3 is an exemplary cross-sectional view showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory according to an aspect of the present invention, wherein the gate insulating layers are etched.
  • FIG. 4 is an exemplary cross-sectional view showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory according to an aspect of the present invention, wherein a polysilicon layer is stacked along thin and thick regions of the gate insulating layers.
  • FIG. 5 is an exemplary cross-sectional view showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory according to an aspect of the present invention, wherein an etch-stop layer, an oxide layer and an anti-reflection coating layer are preferably sequentially deposited on the polysilicon layers.
  • FIG. 6 is an exemplary cross-sectional view showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory according to an aspect of the present invention, wherein a photoresist pattern is removed.
  • FIG. 7 is an exemplary cross-sectional view showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory according to an aspect of the present invention, wherein the gate insulating layers and a silicon substrate are preferably sequentially etched.
  • FIG. 8 depicts exemplary cross-sectional views comparing a deep trench without a flexure, and a trench with a flexure made at a bottom thereof according to an aspect of the present invention.
  • a system according to the present invention provides a new and improved shallow trench isolation type semiconductor device and a method of forming the same.
  • a shallow trench isolation type semiconductor device according to the present invention solves the problem of incomplete device isolation caused by a trench isolation layer whose thickness in a silicon substrate is not sufficient due to a thick gate insulating layer.
  • FIG. 2 is an exemplary cross-sectional view showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory according to an aspect of the present invention, wherein gate insulating layers that differ in thickness are formed.
  • a thick gate oxide layer 103 is formed to a thickness of about 300 ⁇ .
  • a photoresist pattern 21 is formed which exposes a region (such as a low voltage part of cell and peripheral regions) where a thin gate oxide layer will be formed.
  • photoresist In the low voltage part of the cell and peripheral regions excluding the regions where the trench is formed, photoresist remains on a middle area (C) of a trench width (B). In the high voltage part of the peripheral region to which a high voltage is applied, the photoresist is removed on a middle area (E) of a trench width (D).
  • a width of a middle area (C) or (E) is about less than half that of a width of a trench which is to be formed later.
  • a suitable value for patterning is about 0.3 to about 0.8 micrometers.
  • FIG. 3 is an exemplary cross-sectional view showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory according to an aspect of the present invention, wherein the gate insulating layers are etched.
  • a thin gate oxide layer 103 ′ is etched. Therefore, in a low voltage area of cell and peripheral regions, a gate insulating layer remains only at a middle area of a trench. On the contrary, in a peripheral high voltage area to which a high voltage is applied, the gate insulating layer is removed only at a middle area. The photoresist pattern 21 is then removed using ashing and stripping techniques. Conventionally, after a cleaning process, a thin gate insulating layer 101 is formed in a region where a substrate silicon layer undergoes exposure. The gate insulating layer 101 is a thermal oxide layer that is formed to a thickness of about 80 ⁇ . A part of the substrate is additionally oxidized in a region where a thick gate insulating layer remains, so that a thick gate insulating layer 103 has a thickness of about 350 ⁇ .
  • FIG. 4 is an exemplary cross-sectional showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory view according to an aspect of the present invention, wherein a polysilicon layer is stacked along thin and thick regions of the gate insulating layers.
  • a polysilicon layer 105 is stacked on an entire surface of a substrate 10 where a thin gate insulating layer 101 and a thick gate insulating layer 103 are formed.
  • a thickness of the polysilicon layer 105 is about 300 ⁇ to about 1000 ⁇ ; preferably about 500 ⁇ .
  • the polysilicon layer 105 is preferably conformally stacked along thin and thick regions of the gate insulating layers.
  • FIG. 5 is an exemplary cross-sectional view showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory according to an aspect of the present invention, wherein an etch-stop layer, an oxide layer and an anti-reflection coating layer are preferably sequentially deposited on the polysilicon layers.
  • an etch-stop layer 131 , an oxide layer 133 of high temperature, and an anti-reflection coating (ARC) layer 135 are preferably sequentially deposited on a polysilicon layer 105 .
  • a photoresist pattern 137 is formed to expose a trench area.
  • the ARC layer 135 , the oxide layer 133 , and the etch-stop layer are preferably sequentially etched to form a pattern thereof.
  • FIG. 6 is an exemplary cross-sectional view showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory according to an aspect of the present invention, wherein a photoresist pattern is removed.
  • the photoresist pattern 137 is removed using ashing and stripping techniques.
  • the polysilicon layer 105 is etched to expose gate insulating layers 101 and 103 that each have a flexure in a trench area. That is, a gate insulating layer having a concave flexure is formed in a trench area of a high voltage part of a peripheral region, and a gate insulating layer having a convex flexure is formed in a trench area of a low voltage part of cell and peripheral regions.
  • an ion implantation process for device isolation In the ion implantation process, impurity ions opposite to substrate ions are complementarily implanted to prevent electrical leakage caused by PN junction at a lower part of a trench. The process is performed not to an entire surface of a substrate, but to a trench area of a high voltage part of a peripheral region or a middle area of the trench. In place of a conventional ion implantation mask for device isolation at a high voltage part of a peripheral region, an ion implantation mask is formed of photoresist in the step of FIG. 6. Then, a trench area of the high voltage part opens up and ion implantation for device isolation is performed.
  • FIG. 7 is an exemplary cross-sectional view showing a step of performing self-aligned trench device isolation at a low voltage part in cell and peripheral regions and a high voltage part of the peripheral region during the formation of a NAND-type flash memory according to an aspect of the present invention, wherein the gate insulating layers and a silicon substrate are preferably sequentially etched.
  • gate insulating layers and the silicon substrate are sequentially etched.
  • the process of etching the thick gate insulating layer 103 and a layer of the silicon substrate 10 are sequentially performed.
  • the thin gate insulating layer 101 is completely removed and, in the process of removing the insulating layer, the silicon substrate is etched to a depth of about 500 ⁇ .
  • the silicon substrate is additionally etched about 2000 ⁇ to about 2500 ⁇ .
  • trenches 141 and 143 are formed having a depth about 2500 ⁇ to about 3000 ⁇ . Since the trench 143 in the peripheral region is wider than the trench 141 , the depth of the trench 143 may be greater due to a Loading Effect, in which an etching rate is increased when a pattern density is decreased.
  • a middle part of the trench width has the same depth in the silicon substrate as the low voltage part of the peripheral region. It is found that a path a charge carrier must pass to cause an electrical leakage between devices is identical to that in the case of a deep trench without a flexure at the bottom thereof.
  • a trench in the low voltage part of the cell and peripheral regions also has a convex flexure at the bottom of the trench. Accordingly, compared with a deep trench without a flexure, the trench of the low voltage part has an effect to make the path of electrical leakage two times longer than a flexure step difference. That is, an effect of the shallow trench isolation is enhanced.
  • a trench depth in a low voltage part of the cell and peripheral regions is relatively sufficient for device isolation compared with the trench depth in a high voltage part of the peripheral region. Accordingly, although it is not necessary to apply a trench having a middle concave flexure in a low voltage part of the cell and peripheral regions, applying such a trench is preferable since device isolation is enhanced.
  • STI processes are conventionally performed.
  • a thermal oxide layer of a sidewall and a nitride liner are formed.
  • the trench is then filled with a CVD oxide layer.
  • Remaining CVD oxide layer is removed using a CMP technique.
  • an oxide layer of high temperature is also removed.
  • an etch-stop layer pattern used as an etching mask is removed as well using a wet etching process.
  • a depth of the trench can be lengthened in a middle area thereof according to an aspect of the present invention. Therefore, it is possible to enhance shallow trench isolation.
  • FIG. 8 depicts exemplary cross-sectional views comparing a deep trench without a flexure 800 , and a trench with a flexure made at a bottom thereof 805 according to an aspect of the present invention.
  • FIG. 8 illustrates the fact that there is no distance difference of a leakage path in a deep trench without a flexure and another trench with a flexure made at a bottom thereof, even though a width of the trench 805 is less than a width of the trench 800 .

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US20040092082A1 (en) * 2002-10-30 2004-05-13 Fujitsu Limited Semiconductor device fabrication method
US6833602B1 (en) * 2002-09-06 2004-12-21 Lattice Semiconductor Corporation Device having electrically isolated low voltage and high voltage regions and process for fabricating the device
CN100461375C (zh) * 2005-12-05 2009-02-11 中芯国际集成电路制造(上海)有限公司 制造用于闪存半导体器件的隔离结构的方法
US20090325360A1 (en) * 2008-06-27 2009-12-31 Hynix Semiconductor Inc. Method of Forming Trench of Semiconductor Device
US20110073933A1 (en) * 2009-09-30 2011-03-31 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
DE10362312B4 (de) * 2003-02-14 2014-10-30 Infineon Technologies Ag Halbleiter-Schaltungsanordnung mit Grabenisolation und mit ladungsspeichernder Schicht und Verfahren zu deren Herstellung
CN110265394A (zh) * 2018-03-12 2019-09-20 三星电子株式会社 集成电路装置及其形成方法
CN110299398A (zh) * 2018-03-22 2019-10-01 联华电子股份有限公司 高电压晶体管及其制造方法
US20230238272A1 (en) * 2019-10-16 2023-07-27 Stmicroelectronics (Rousset) Sas Process for fabricating an integrated circuit comprising a phase of forming trenches in a substrate and corresponding integrated circuit

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JP2010027656A (ja) * 2008-07-15 2010-02-04 Toshiba Corp 半導体装置および半導体装置の製造方法
JP2010056391A (ja) * 2008-08-29 2010-03-11 Toshiba Corp 半導体装置およびその製造方法
US8193067B2 (en) * 2009-12-03 2012-06-05 International Business Machines Corporation Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit
CN101964356A (zh) * 2010-10-25 2011-02-02 上海宏力半导体制造有限公司 半导体器件及其制造方法
US20230230993A1 (en) * 2022-01-20 2023-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Uniform trenches in semiconductor devices and manufacturing method thereof

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US6833602B1 (en) * 2002-09-06 2004-12-21 Lattice Semiconductor Corporation Device having electrically isolated low voltage and high voltage regions and process for fabricating the device
US7078286B1 (en) * 2002-09-06 2006-07-18 Lattice Semiconductor Corporation Process for fabricating a semiconductor device having electrically isolated low voltage and high voltage regions
US20040092082A1 (en) * 2002-10-30 2004-05-13 Fujitsu Limited Semiconductor device fabrication method
US6979610B2 (en) * 2002-10-30 2005-12-27 Fujitsu Limited Semiconductor device fabrication method
DE10362312B4 (de) * 2003-02-14 2014-10-30 Infineon Technologies Ag Halbleiter-Schaltungsanordnung mit Grabenisolation und mit ladungsspeichernder Schicht und Verfahren zu deren Herstellung
CN100461375C (zh) * 2005-12-05 2009-02-11 中芯国际集成电路制造(上海)有限公司 制造用于闪存半导体器件的隔离结构的方法
US20090325360A1 (en) * 2008-06-27 2009-12-31 Hynix Semiconductor Inc. Method of Forming Trench of Semiconductor Device
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CN110265394A (zh) * 2018-03-12 2019-09-20 三星电子株式会社 集成电路装置及其形成方法
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