US20020015351A1 - Method of operating a memory device having a variable data input length - Google Patents

Method of operating a memory device having a variable data input length Download PDF

Info

Publication number
US20020015351A1
US20020015351A1 US09/492,982 US49298200A US2002015351A1 US 20020015351 A1 US20020015351 A1 US 20020015351A1 US 49298200 A US49298200 A US 49298200A US 2002015351 A1 US2002015351 A1 US 2002015351A1
Authority
US
United States
Prior art keywords
bus
semiconductor device
master
semiconductor
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/492,982
Other versions
US6452863B2 (en
Inventor
Michael Farmwald
Mark Horowitz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24032637&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=US20020015351(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Individual filed Critical Individual
Priority to US09/492,982 priority Critical patent/US6452863B2/en
Priority to US09/779,296 priority patent/US6324120B2/en
Priority to US09/796,206 priority patent/US6426916B2/en
Publication of US20020015351A1 publication Critical patent/US20020015351A1/en
Application granted granted Critical
Publication of US6452863B2 publication Critical patent/US6452863B2/en
Adjusted expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/006—Identification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment
    • G06F12/0661—Configuration or reconfiguration with centralised address assignment and decentralised selection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0684—Configuration or reconfiguration with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/376—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a contention resolving method, e.g. collision detection, collision avoidance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Semiconductor computer memories have traditionally been designed and structured to use one memory device for each bit, or small group of bits, of any individual computer word, where the word size is governed by the choice of computer. Typical word sizes range from 4 to 64 bits.
  • Each memory device typically is connected in parallel to a series of address lines and connected to one of a series of data lines. When the computer seeks to read from or write to a specific memory location, an address is put on the address lines and some or all of the memory devices are activated using a separate device select line for each needed device.
  • One or more devices may be connected to each data line but typically only a small number of data lines are connected to a single memory device.
  • data line 0 is connected to device(s) 0
  • data line 1 is connected to device(s) 1
  • data is thus accessed or provided in parallel for each memory read or write operation.
  • every single memory bit in every memory device must operate dependably and correctly.
  • One object of the present invention is to use a new bus interface built into semiconductor devices to support high-speed access to large blocks of data from a single memory device by an external user of the data, such as a microprocessor, in an efficient and cost-effective manner.
  • Another object of this invention is to provide a clocking scheme to permit high speed clock signals to be sent along the bus with minimal clock skew between devices.
  • Another object of this invention is to allow mapping out defective memory devices or portions of memory devices.
  • Another object of this invention is to provide a method for distinguishing otherwise identical devices by assigning a unique identifier to each device.
  • Yet another object of this invention is to provide a method for transferring address, data and control information over a relatively narrow bus and to provide a method of bus arbitration when multiple devices seek to use the bus simultaneously.
  • Another object of this invention is to provide a method of distributing a high-speed memory cache within the DRAM chips of a memory system which is much more effective than previous cache methods.
  • Another object of this invention is to provide devices, especially DRAMs, suitable for use with the bus architecture of the invention.
  • the present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected in parallel to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.
  • a standard DRAM 13 , 14 , ROM (or SRAM) 12 , microprocessor CPU 11 , I/O device, disk controller or other special purpose device such as a high speed switch is modified to use a wholly bus-based interface rather than the prior art combination of point-to-point and bus-based wiring used with conventional versions of these devices.
  • the new bus includes clock signals, power and multiplexed address, data and control signals.
  • 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.
  • 16 bus data lines or other numbers of bus data lines can be used to implement the teaching of this invention.
  • the new bus is used to connect elements such as memory, peripheral, switch and processing units.
  • DRAMs and other devices receive address and control information over the bus and transmit or receive requested data over the same bus.
  • Each memory device contains only a single bus interface with no other signal pins.
  • Other devices that may be included in the system can connect to the bus and other non-bus lines, such as input/output lines.
  • the bus supports large data block transfers and split transactions to allow a user to achieve high bus utilization. This ability to rapidly read or write a large block of data to one single device at a time is an important advantage of this invention.
  • the DRAMs that connect to this bus differ from conventional DRAMs in a number of ways. Registers are provided which may store control information, device identification, device-type and other information appropriate for the chip such as the address range for each independent portion of the device. New bus interface circuits must be added and the internals of prior art DRAM devices need to be modified so they can provide and accept data to and from the bus at the peak data rate of the bus. This requires changes to the column access circuitry in the DRAM, with only a minimal increase in die size. A circuit is provided to generate a low skew internal device clock for devices on the bus, and other circuits provide for demultiplexing input and multiplexing output signals.
  • High bus bandwidth is achieved by running the bus at a very high clock rate (hundreds of MHz), This high clock rate is made possible by the constrained environment of the bus.
  • the bus lines are controlled-impedance, doubly-terminated lines.
  • the maximum bus propagation time is less than 1 ns (the physical bus length is about 10 cm).
  • the pitch of the pins can be very close to the pitch of the pads.
  • the loading on the bus resulting from the individual devices is very small. In a preferred implementation, this generally allows stub capacitances of 1-2 pF and inductances of 0.5-2 nH.
  • Each device 15 , 16 , 17 shown in FIG. 3, only has pins on one side and these pins connect directly to the bus 18 .
  • a transceiver device 19 can be included to interface multiple units to a higher order bus through pins 20 .
  • a primary result of the architecture of this invention is to increase the bandwidth of DRAM access.
  • the invention also reduces manufacturing and production costs, power consumption, and increases packing density and system reliability.
  • FIG. 1 is a diagram which illustrates the basic 2-D organization of memory devices.
  • FIG. 2 is a schematic block diagram which illustrates the parallel connection of all bus lines and the serial Reset line to each device in the system.
  • FIG. 3 is a perspective view of a system of the invention which illustrates the 3-D packaging of semiconductor devices on the primary bus.
  • FIG. 4 shows the format of a request packet.
  • FIG. 5 shows the format of a retry response from a slave.
  • FIG. 6 shows the bus cycles after a request packet collision occurs on the bus and how arbitration is handled.
  • FIG. 7 shows the timing whereby signals from two devices can overlap temporarily and drive the bus at the same time.
  • FIG. 8 shows the connection and timing between bus clocks and devices on the bus.
  • FIG. 9 is a perspective view showing how transceivers can be used to connect a number of bus units to a transceiver bus.
  • FIG. 10 is a block and schematic diagram of input/output circuitry used to connect devices to the bus.
  • FIG. 11 is a schematic diagram of a clocked sense-amplifier used as a bus input receiver.
  • FIG. 12 is a block diagram showing how the internal device clock is generated from two bus clock signals using a set of adjustable delay lines.
  • FIG. 14 is timing diagram of a preferred means of implementing the reset procedure of this invention.
  • FIG. 15 is a diagram illustrating the general organization of a 4 Mbit DRAM divided into 8 subarrays.
  • the present invention is designed to provide a high speed, multiplexed bus for communication between processing devices and memory devices and to provide devices adapted for use in the bus system.
  • the invention can also be used to connect processing devices and other devices, such as I/O interfaces or disk controllers, with or without memory devices on the bus.
  • the bus consists of a relatively small number of lines connected in parallel to each device on the bus.
  • the bus carries substantially all address, data and control information needed by devices for communication with other devices on the bus. In many systems using the present invention, the bus carries almost every signal between every device in the entire system. There is no need for separate device-select lines since device-select information for each device on the bus is carried over the bus. There is no need for separate address and data lines because address and data information can be sent over the same lines.
  • the data from the sense amplifiers is enabled 32 bits at a time onto an internal device bus running at approximately 125 MHz.
  • This internal device bus moves the data to the periphery of the devices where the data is multiplexed into an 8-bit wide external bus interface, running at approximately 500 MHz.
  • the bus architecture of this invention connects master or bus controller devices, such as CPUs, Direct Memory Access devices (DMAs) or Floating Point Units (FPUs), and slave devices, such as DRAM, SRAM or ROM memory devices.
  • a slave device responds to control signals; a master sends control signals.
  • DMAs Direct Memory Access devices
  • FPUs Floating Point Units
  • a slave device responds to control signals; a master sends control signals.
  • a master sends control signals.
  • a master sends control signals.
  • a memory device will typically have only slave functions, while a DMA controller, disk controller or CPU may include both slave and master functions.
  • Many other semiconductor devices, including I/O devices, disk controllers, or other special purpose devices such as high speed switches can be modified for use with the bus of this invention.
  • Each semiconductor device contains a set of internal registers, preferably including a device identification (device ID) register, a device-type descriptor register, control registers and other registers containing other information relevant to that type of device.
  • semiconductor devices connected to the bus contain registers which specify the memory addresses contained within that device and access-time registers which store a set of one or more delay times at which the device can or should be available to send or receive data.
  • registers can be modified and preferably are set as part of an initialization sequence that occurs when the system is powered up or reset.
  • each device on the bus is assigned a unique device ID number, which is stored in the device ID register.
  • a bus master can then use these device ID numbers to access and set appropriate registers in other devices, including access-time registers, control registers, and memory registers, to configure the system.
  • Each slave may have one or several access-time registers (four in a preferred embodiment). In a preferred embodiment, one access-time register in each slave is permanently or semi-permanently programmed with a fixed value to facilitate certain control functions.
  • a preferred implementation of an initialization sequence is described below in more detail.
  • All information sent between master devices and slave devices is sent over the external bus, which, for example, may be 8 bits wide. This is accomplished by defining a protocol whereby a master device, such as a microprocessor, seizes exclusive control of the external bus (i.e., becomes the bus master) and initiates a bus transaction by sending a request packet (a sequence of bytes comprising address and control information) to one or more slave devices on the bus.
  • a request packet a sequence of bytes comprising address and control information
  • An address can consist of 16 to 40 or more bits according to the teachings of this invention.
  • Each slave on the bus must decode the request packet to see if that slave needs to respond to the packet. The slave that the packet is directed to must then begin any internal processes needed to carry out the requested bus transaction at the requested time.
  • the requesting master may also need to transact certain internal processes before the bus transaction begins. After a specified access time the slave(s) respond by returning one or more bytes (8 bits) of data or by storing information made available from the bus. More than one access time can be provided to allow different types of responses to occur at different times.
  • a request packet and the corresponding bus access are separated by a selected number of bus cycles, allowing the bus to be used in the intervening bus cycles by the same or other masters for additional requests or brief bus accesses.
  • multiple, independent accesses are permitted, allowing maximum utilization of the bus for transfer of short blocks of data. Transfers of long blocks of data use the bus efficiently even without overlap because the overhead due to bus address, control and access times is small compared to the total time to request and transfer the block.
  • each memory device is a complete, independent memory subsystem with all the functionality of a prior art memory board in a conventional backplane-bus computer system.
  • Individual memory devices may contain a single memory section or may be subdivided into more than one discrete memory section.
  • Memory devices preferably include memory address registers for each discrete memory section.
  • a failed memory device (or even a subsection of a device) can be “mapped out” with only the loss of a small fraction of the memory, maintaining essentially full system capability. Mapping out bad devices can be accomplished in two ways, both compatible with this invention.
  • the preferred method uses address registers in each memory device (or independent discrete portion thereof) to store information which defines the range of bus addresses to which this memory device will respond. This is similar to prior art schemes used in memory boards in conventional backplane bus systems.
  • the address registers can include a single pointer, usually pointing to a block of known size, a pointer and a fixed or variable block size value or two pointers, one pointing to the beginning and one to the end (or to the “top” and “bottom”) of each memory block.
  • a series of functional memory devices or discrete memory sections can be made to respond to a contiguous range of addresses, giving the system access to a contiguous block of good memory, limited primarily by the number of good devices connected to the bus.
  • a block of memory in a first memory device or memory-section can be assigned a certain range of addresses, then a block of memory in a next memory device or memory section can be assigned addresses starting with an address one higher (or lower, depending on the memory structure) than the last address of the previous block.
  • Preferred devices for use in this invention include device-type register information specifying the type of chip, including how much memory is available in what configuration on that device.
  • a master can perform an appropriate memory test, such as reading and writing each memory cell in one or more selected orders, to test proper functioning of each accessible discrete portion of memory (based in part on information like device ID number and device-type) and write address values (up to 40 bits in the preferred embodiment, 10 12 bytes), preferably contiguous, into device address-space registers.
  • Non-functional or impaired memory sections can be assigned a special address value which the system can interpret to avoid using that memory.
  • TLBs translation look-aside buffers
  • the TLBs can be programmed to use only working memory (data structures describing functional memories are easily generated).
  • a small, simple RAM can be used to map a contiguous range of addresses onto the addresses of the functional memory devices.
  • the preferred bus architecture of this invention comprises 11 signals: BusData[ 0 : 7 ]; AddrValid; Clk 1 and Clk 2 ; plus an input reference level and power and ground lines connected in parallel to each device. Signals are driven onto the bus during conventional bus cycles.
  • the notation “Signal[i:j]” refers to a specific range of signals or lines, for example, BusData[ 0 : 7 ] means BusData 0 , BusData 1 , . . . , BusData 7 .
  • the bus lines for BusData[ 0 : 7 ] signals form a byte-wide, multiplexed data/address/control bus.
  • AddrValid is used to indicate when the bus is holding a valid address request, and instructs a slave to decode the bus data as an address and, if the address is included on that slave, to handle the pending request.
  • the two clocks together provide a synchronized, high speed clock for all the devices on the bus.
  • bus cycles are grouped into pairs of even/odd cycles. Note that all devices connected to a bus should preferably use the same even/odd labeling of bus cycles and preferably should begin operations on even cycles. This is enforced by the clocking scheme.
  • the bus uses a relatively simple, synchronous, split-transaction, block-oriented protocol for bus transactions.
  • One of the goals of the system is to keep the intelligence concentrated in the masters, thus keeping the slaves as simple as possible (since there are typically many more slaves than masters).
  • a slave should preferably respond to a request in a specified time, sufficient to allow the slave to begin or possibly complete a device-internal phase including any internal actions that must precede the subsequent bus access phase.
  • the time for this bus access phase is known to all devices on the bus—each master being responsible for making sure that the bus will be free when the bus access begins.
  • This approach eliminates arbitration in single master systems, and also makes the slave-bus interface simpler.
  • a master to initiate a bus transfer over the bus, a master sends out a request packet, a contiguous series of bytes containing address and control information. It is preferable to use a request packet containing an even number of bytes and also preferable to start each packet on an even bus cycle.
  • the device-select function is handled using the bus data lines.
  • AddrValid is driven, which instructs all slaves to decode the request packet address, determine whether they contain the requested address, and if they do, provide the data back to the master (in the case of a read request) or accept data from the master (in the case of a write request) in a data block transfer.
  • a master can also select a specific device by transmitting a device ID number in a request packet.
  • a special device ID number is chosen to indicate that the packet should be interpreted by all devices on the bus. This allows a master to broadcast a message, for example to set a selected control register of all devices with the same value.
  • the data block transfer occurs later at a time specified in the request packet control information, preferably beginning on an even cycle.
  • a device begins a data block transfer almost immediately with a device-internal phase as the device initiates certain functions, such as setting up memory addressing, before the bus access phase begins.
  • the time after which a data block is driven onto the bus lines is selected from values stored in slave access-time registers.
  • the timing of data for reads and writes is preferably the same; the only difference is which device drives the bus. For reads, the slave drives the bus and the master latches the values from the bus. For writes the master drives the bus and the selected slave latches the values from the bus.
  • a request packet 22 contains 6 bytes of data—4.5 address bytes and 1.5 control bytes.
  • Each request packet uses all nine bits of the multiplexed data/address lines (AddrValid 23 +BusData[ 0 : 7 ] 24 ) for all six bytes of the request packet.
  • AddrValid 27 In a valid request packet, AddrValid 27 must be 0 in the last byte. Asserting this signal in the last byte invalidates the request packet. This is used for the collision detection and arbitration logic (described below).
  • Bytes 25 - 26 contain the first 35 address bits, Address[ 0 : 35 ].
  • the last byte contains AddrValid 27 (the invalidation switch) and 28 , the remaining address bits, Address[ 36 : 39 ], and BlockSize[ 0 : 3 ] (control information).
  • AccessType field specifies whether the requested operation is a read or write and the type of access, for example, whether it is to the control registers or other parts of the device, such as memory.
  • AccessType[ 0 ] is a Read/Write switch: if it is a 1, then the operation calls for a read from the slave (the slave to read the requested memory block and drive the memory contents onto the bus); if it is a 0, the operation calls for a write into the slave (the slave to read data from the bus and write it to memory).
  • AccessType[ 1 : 3 ] provides up to 8 different access types for a slave.
  • AccessType[ 1 : 2 ] preferably indicates the timing of the response, which is stored in an access-time register, AccessRegN.
  • access-time register can be selected directly by having a certain op code select that register, or indirectly by having a slave respond to selected op codes with pre-selected access times (see table below).
  • the remaining bit, AccessType[ 3 ] may be used to send additional information about the request to the slaves.
  • AccessType[ 1 : 3 ] indicates a control register request and the address field of the packet indicates the desired control register.
  • the most significant two bytes can be the device ID number (specifying which slave is being addressed) and the least significant three bytes can specify a register address and may also represent or include data to be loaded into that control register.
  • Control register accesses are used to initialize the access-time registers, so it is preferable to use a fixed response time which can be preprogrammed or even hard wired, for example the value in AccessReg 0 , preferably 8 cycles. Control register access can also be used to initialize or modify other registers, including address registers.
  • the method of this invention provides for access mode control specifically for the DRAMs.
  • One such access mode determines whether the access is page mode or normal RAS access.
  • normal mode in conventional DRAMS and in this invention, the DRAM column sense amps or latches have been precharged to a value intermediate between logical 0 and 1. This precharging allows access to a row in the RAM to begin as soon as the access request for either inputs (writes) or outputs (reads) is received and allows the column sense amps to sense data quickly.
  • page mode both conventional and in this invention
  • the DRAM holds the data in the column sense amps or latches from the previous read or write operation.
  • the DRAM does not need to wait for the data to be sensed (it has been sensed already) and access time for this data is much shorter than the normal access time.
  • Page mode generally allows much faster access to data but to a smaller block of data (equal to the number of sense amps).
  • the access time is longer than the normal access time, since the request must wait for the RAM to precharge before the normal mode access can start.
  • Two access-time registers in each DRAM preferably contain the access times to be used for normal and for page-mode accesses, respectively.
  • the access mode also determines whether the DRAM should precharge the sense amplifiers or should save the contents of the sense amps for a subsequent page mode access. Typical settings are “precharge after normal access” and “save after page mode access” but “precharge after page mode access” or “save after normal access” are allowed, selectable modes of operation.
  • the DRAM can also be set to precharge the sense amps if they are not accessed for a selected period of time.
  • the data stored in the DRAM sense amplifiers may be accessed within much less time than it takes to read out data in normal mode ( ⁇ 10-20 nS vs. 40-100 nS). This data may be kept available for long periods. However, if these sense amps (and hence bit lines) are not precharged after an access, a subsequent access to a different memory word (row) will suffer a precharge time penalty of about 40-100 nS because the sense amps must precharge before latching in a new value.
  • the contents of the sense amps thus may be held and used as a cache, allowing faster, repetitive access to small blocks of data.
  • DRAM-based page-mode caches have been attempted in the prior art using conventional DRAM organizations but they are not very effective because several chips are required per computer word.
  • Such a conventional page-mode cache contains many bits (for example, 32 chips ⁇ 4Kbits) but has very few independent storage entries.
  • the sense amps hold only a few different blocks or memory “locales” (a single block of 4K words, in the example above). Simulations have shown that upwards of 100 blocks are required to achieve high hit rates (>90% of requests find the requested data already in cache memory) regardless of the size of each block. See, for example, Anant Agarwal, et. al., “An Analytic Cache Model,” ACM Transactions on Computer Systems, Vol. 7(2), pp. 184-215 ( May 1989).
  • each DRAM to hold one or more (4 for 4MBit DRAMS) separately-addressed and independent blocks of data.
  • a personal computer or workstation with 100 such DRAMs i.e. 400 blocks or locales
  • the conventional DRAM-based page-mode cache generally has been found to work less well than no cache at all.
  • the access types are preferably used in the following way: AccessType[1:3] Use AccessTime 0 Control Register Fixed, 8[AccessReg0] Access 1 Unused Fixed, 8[AccessReg0] 2-3 Unused AccessReg1 4-5 Page Mode DRAM AccessReg2 access 6-7 Normal DRAM access AccessReg3
  • AccessType[ 2 ] page mode/normal switch
  • AccessType[ 3 ] precharge/save-data switch
  • BlockSize[ 0 : 3 ] specifies the size of the data block transfer. If BlockSize[ 0 ] is 0, the remaining bits are the binary representation of the block size ( 0 - 7 ). If BlockSize[ 0 ] is 1, then the remaining bits give the block size as a binary power of 2, from 8 to 1024.
  • a zero-length block can be interpreted as a special command, for example, to refresh a DRAM without returning any data, or to change the DRAM from page mode to normal access mode or vice-versa.
  • BlockSize[0:2] Number of Bytes in Block 0-7 0-7 respectively 8 8 9 16 10 32 11 64 12 128 13 256 14 512 15 1024
  • a slave will respond at the selected access time by reading or writing data from or to the bus over bus lines BusData[ 0 : 7 ] and AddrValid will be at logical 0.
  • substantially each memory access will involve only a single memory device, that is, a single block will be read from or written to a single memory device.
  • a slave may not be able to respond correctly to a request, e.g., for a read or write.
  • the slave should return an error message, sometimes called a N(o)ACK(nowledge) or retry message.
  • the retry message can include information about the condition requiring a retry, but this increases system requirements for circuitry in both slave and masters. A simple message indicating only that an error has occurred allows for a less complex slave, and 'the master can take whatever action is needed to understand and correct the cause of the error.
  • a slave might not be able to supply the requested data.
  • the DRAM selected must be in page mode and the requested address must match the address of the data held in the sense amps or latches.
  • Each DRAM can check for this match during a page-mode access. If no match is found, the DRAM begins precharging and returns a retry message to the master during the first cycle of the data block (the rest of the returned block is ignored). The master then must wait for the precharge time (which is set to accommodate the type of slave in question, stored in a special register, PreChargeReg), and then resend the request as a normal DRAM access (AccessType 6 or 7 ).
  • a slave signals a retry by driving AddrValid true at the time the slave was supposed to begin reading or writing data.
  • a master which expected to write to that slave must monitor AddrValid during the write and take corrective action if it detects a retry message.
  • All DRAMS and masters can easily recognize such a packet as an invalid request packet, and therefore a retry message.
  • this type of bus transaction all of the fields except for Master[ 0 : 3 ] and AddrValid 23 may be used as information fields, although in the implementation described, the contents are undefined.
  • Another method of signifying a retry message is to add a DataInvalid line and signal to the bus. This signal could be asserted in the case of a NACK.
  • the bus architecture of this invention is also useful in configurations with multiple masters. When two or more masters are on the same bus, each master must keep track of all the pending transactions, so each master knows when it can send a request packet and access the corresponding data block transfer.
  • each master there are many ways for each master to keep track of when the bus is and will be busy.
  • a simple method is for each master to maintain a bus-busy data structure, for example by maintaining two pointers, one to indicate the earliest point in the future when the bus will be busy and the other to indicate the earliest point in the future when the bus will be free, that is, the end of the latest pending data block transfer.
  • each master can determine whether and when there is enough time to send a request packet (as described above under Protocol) before the bus becomes busy with another data block transfer and whether the corresponding data block transfer will interfere with pending bus transactions.
  • each master must read every request packet and update its bus-busy data structure to maintain information about when the bus is and will be free.
  • each device on the bus seeking to write a logical 1 on a BusData or AddrValid line drives that line with a current sufficient to sustain a voltage greater than or equal to the high-logic value for the system.
  • Devices do not drive lines that should have a logical 0; those lines are simply held at a voltage corresponding to a low-logic value.
  • Each master tests the voltage on at least some, preferably all, bus data and the AddrValid lines so the master can detect a logical ‘1’ where the expected level is ‘0’ on a line that it does not drive during a given bus cycle but another master does drive.
  • Another way to detect collisions is to select one or more bus lines for collision signalling.
  • Each master sending a request drives that line or lines and monitors the selected lines for more than the normal drive current (or a logical value of “>1”) indicating requests by more than one master.
  • This can be implemented with a protocol involving BusData and AddrValid lines or could be implemented using an additional bus line.
  • each master detects collisions by monitoring lines which it does not drive to see if another master is driving those lines.
  • each master detecting a collision drives the value of AddrValid 27 in byte 5 of the request packet 22 to 1, which is detected by all masters, including master 11 in the second example above, and forces a bus arbitration cycle, described below.
  • Another collision condition may arise where master A sends a request packet in cycle 0 and master B tries to send a request packet starting in cycle 2 of the first request packet, thereby overlapping the first request packet. This will occur from time to time because the bus operates at high speeds, thus the logic in a second-initiating master may not be fast enough to detect a request initiated by a first master in cycle 0 and to react fast enough by delaying its own request. Master B eventually notices that it wasn't supposed to try to send a request packet (and consequently almost surely destroyed the address that master A was trying to send), and, as in the example above of a simultaneous collision, drives a 1 on AddrValid during byte 5 of the first request packet 27 forcing an arbitration.
  • the logic in the preferred implementation is fast enough that a master should detect a request packet by another master by cycle 3 of the first request packet, so no master is likely to attempt to send a potentially colliding request packet later than cycle 2 .
  • Slave devices not need to detect a collision directly, but they must wait to do anything irrecoverable until the last byte (byte 5 ) is read to ensure that the packet is valid.
  • a request packet with Master[ 0 : 3 ] equal to 0 (a retry signal) is ignored and does not cause a collision. The subsequent bytes of such a packet are ignored.
  • the masters wait a preselected number of cycles after the aborted request packet (4 cycles in a preferred implementation), then use the next free cycle to arbitrate for the bus (the next available even cycle in the preferred implementation).
  • Each colliding master signals to all other colliding masters that it seeks to send a request packet, a priority is assigned to each of the colliding masters, then each master is allowed to make its request in the order of that priority.
  • FIG. 6 illustrates one preferred way of implementing this arbitration.
  • Each colliding master signals its intent to send a request packet by driving a single BusData line during a single bus cycle corresponding to its assigned master number ( 1 - 15 in the present example).
  • master number 1 - 15 in the present example.
  • byte 0 is allocated to requests 1 - 7 from masters 1 - 7 , respectively, (bit 0 is not used) and byte 1 is allocated to requests 8 - 15 from masters 8 - 15 , respectively.
  • At least one device and preferably each colliding master reads the values on the bus during the arbitration cycles to determine and store which masters desire to use the bus.
  • a single byte can be allocated for arbitration requests if the system includes more bus lines than masters. More than 15 masters can be accommodated by using additional bus cycles.
  • a fixed priority scheme (preferably using the master numbers, selecting lowest numbers first) is then used to prioritize, then sequence the requests in a bus arbitration queue which is maintained by at least one device. These requests are queued by each master in the bus-busy data structure and no further requests are allowed until the bus arbitration queue is cleared.
  • priority schemes can be used, including assigning priority according to the physical location of each master.
  • a mechanism is provided to give each device on the bus a unique device identifier (device ID) after power-up or under other conditions as desired or needed by the system.
  • a master can then use this device ID to access a specific device, particularly to set or modify registers of the specified device, including the control and address registers.
  • one master is assigned to carry out the entire system configuration process.
  • the master provides a series of unique device ID numbers for each unique device connected to the bus system.
  • each device connected to the bus contains a special device-type register which specifies the type of device, for instance CPU, 4 MBit memory, 64 MBit memory or disk controller.
  • the configuration master should check each device, determine the device type and set appropriate control registers, including access-time registers.
  • the configuration master should check each memory device and set all appropriate memory address registers.
  • One means to set up unique device ID numbers is to have each device to select a device ID in sequence and store the value in an internal device ID register.
  • a master can pass sequential device ID numbers through shift registers in each of a series of devices, or pass a token from device to device whereby the device with the token reads in device ID information from another line or lines.
  • device ID numbers are assigned to devices according to their physical relationship, for instance, their order along the bus.
  • the device ID setting is accomplished using a pair of pins on each device, ResetIn and ResetOut. These pins handle normal logic signals and are used only during device ID configuration.
  • ResetIn an input
  • ResetOut The output of the reset shift register is connected to ResetOut, which in turn connects to ResetIn for the next sequentially connected device. Substantially all devices on the bus are thereby daisy-chained together.
  • a first reset signal for example, while ResetIn at a device is a logical 1, or when a selected bit of the reset shift register goes from zero to non-zero, causes the device to hard reset, for example by clearing all internal registers and resetting all state machines.
  • a second reset signal for example, the falling edge of ResetIn combined with changeable values on the external bus, causes that device to latch the contents of the external bus into the internal device ID register (Device[ 0 : 7 ]).
  • a master sets the ResetIn line of the first device to a “1” for long enough to ensure that all devices on the bus have been reset (4 cycles times the number of devices—note that the maximum number of devices on the preferred bus configuration is 256 (8 bits), so that 1024 cycles is always enough time to reset all devices.)
  • ResetIn is dropped to “0” and the BusData lines are driven with the first followed by successive device ID numbers, changing after every 4 clock pulses. Successive devices set those device ID numbers into the corresponding device ID register as the falling edge of ResetIn propagates through the shift registers of the daisy-chained devices.
  • the configuration master should choose and set an access time in each access-time register in each slave to a period sufficiently long to allow the slave to perform an actual, desired memory access. For example, for a normal DRAM access, this time must be longer than the row address strobe (RAS) access time. If this condition is not met, the slave may not deliver the correct data.
  • the value stored in a slave access-time register is preferably one-half the number of bus cycles for which the slave device should wait before using the bus in response to a request. Thus an access time value of ‘1’ would indicate that the slave should not access the bus until at least two cycles after the last byte of the request packet has been received.
  • the value of AccessReg 0 is preferably fixed at 8 (cycles) to facilitate access to control registers.
  • the bus architecture of this invention can include more than one master device.
  • the reset or initialization sequence should also include a determination of whether there are multiple masters on the bus, and if so to assign unique master ID numbers to each.
  • the master could poll each device to determine what type of device it is, for example, by reading a special register then, for each master device, write the next available master ID number into a special register.
  • ECC Error detection and correction
  • ECC information is stored separately from the corresponding data, which can then be stored in blocks having integral binary size.
  • ECC information and corresponding data can be stored, for example, in separate DRAM devices. Data can be read without ECC using a single request packet, but to write or read error-corrected data requires two request packets, one for the data and a second for the corresponding ECC information.
  • ECC information may not always be stored permanently and in some situations the ECC information may be available without sending a request packet or without a bus data block transfer.
  • a standard data block size can be selected for use with ECC, and the ECC method will determine the required number of bits of information in a corresponding ECC block.
  • RAMs containing ECC information can be programmed to store an access time that is equal to: (1) the access time of the normal RAM (containing data) plus the time to access a standard data block (for corrected data) minus the time to send a request packet (6 bytes); or (2) the access time of a normal RAM minus the time to access a standard ECC block minus the time to send a request packet.
  • the master To read a data block and the corresponding ECC block, the master simply issues a request for the data immediately followed by a request for the ECC block.
  • the ECC RAM will wait for the selected access time then drive its data onto the bus right after (in case (1) above)) the data RAM has finished driving out the data block.
  • the access time described in case (2) above can be used to drive ECC data before the data is driven onto the bus lines and will recognize that writing data can be done by analogy with the method described for a read.
  • Persons skilled in the art will also recognize the adjustments that must be made in the bus-busy structure and the request packet arbitration methods of this invention in order to accommodate these paired ECC requests.
  • the system designer can choose the size of the data blocks and the number of ECC bits using the memory devices of this invention.
  • the data stream on the bus can be interpreted in various ways. For instance the sequence can be 2 n data bytes followed by 2 m ECC bytes (or vice versa), or the sequence can be 2 k iterations of 8 data bytes plus 1 ECC byte.
  • Other information such as information used by a directory-based cache coherence scheme, can also be managed this way. See, for example, Anant Agarwal, et al., “Scaleable Directory Schemes for Cache Consistency,” 15th International Symposium on Computer Architecture , June 1988, pp. 280-289.
  • Those skilled in the art will recognize alternative methods of implementing ECC schemes that are within the teachings of this invention.
  • Another major advantage of this invention is that it drastically reduces the memory system power consumption. Nearly all the power consumed by a prior art DRAM is dissipated in performing row access. By using a single row access in a single RAM to supply all the bits for a block request (compared to a row-access in each of multiple RAMs in conventional memory systems) the power per bit can be made very small. Since the power dissipated by memory devices using this invention is significantly reduced, the devices potentially can be placed much closer together than with conventional designs.
  • the bus architecture of this invention makes possible an innovative 3-D packaging technology.
  • the pin count for an arbitrarily large memory device can be kept quite small—on the order of 20 pins.
  • this pin count can be kept constant from one generation of DRAM density to the next.
  • the low power dissipation allows each package to be smaller, with narrower pin pitches (spacing between the IC pins).
  • With current surface mount technology supporting pin pitches as low as 20 mils all off-device connections can be implemented on a single edge of the memory device.
  • Semiconductor die useful in this Invention preferably have connections or pads along one edge of the die which can then be wired or otherwise connected to the package pins with wires having similar lengths. This geometry also allows for very short leads, preferably with an effective lead length of less than 4 mm.
  • this invention uses only bused interconnections, i.e., each pad on each device is connected by the bus to the corresponding pad of each other device.
  • the bus can be made quite short, which in turn allows for short propagation times and high data rates.
  • the bus of a preferred embodiment of the present invention consists of a set of resistor-terminated controlled impedance transmission lines which can operate up to a data rate of 500 MHz (2 ns cycles).
  • the characteristics of the transmission lines are strongly affected by the loading caused by the DRAMs (or other slaves) mounted on the bus. These devices add lumped capacitance to the lines which both lowers the impedance of the lines and decreases the transmission speed.
  • the transit time on the bus should preferably be kept under 1 ns, to leave 1 ns for the setup and hold time of the input receivers (described below) plus clock skew.
  • the bus lines must be kept quite short, under about 8 cm for maximum performance.
  • Lower performance systems may have much longer lines, e.g. a 4 ns bus may have 24 cm lines (3 ns transit time, 1 ns setup and hold time).
  • the bus uses current source drivers. Each output must be able to sink 50 mA, which provides an output swing of about 500 mV or more.
  • the bus is active low.
  • the unasserted state (the high value) is preferably considered a logical zero, and the asserted value (low state) is therefore a logical 1.
  • the value of the unasserted state is set by the voltage on the termination resistors, and should be high enough to allow the outputs to act as current sources, while being as low as possible to reduce power dissipation. These constraints may yield a termination voltage about 2V above ground in the preferred implementation.
  • Current source drivers cause the output voltage to be proportional to the sum of the sources driving the bus.
  • the voltage at point 45 goes to logical 0 when device B 42 turns off, then drops at time 47 when the effect of device A 41 turning on is felt. Since the logical 1 driven by current from device A 41 is propagated irrespective of the previous value on the bus, the value on the bus is guaranteed to settle after one time of flight (t,) delay, that is, the time it takes a signal to propagate from one end of the bus to the other.
  • a logical 1 on the bus would prevent the transition put out by device A 41 being felt at the most remote part of the system, e.g., device 43 , until the turnoff waveform from device B 42 reached device A 41 plus one time of flight delay, giving a worst case settling time of twice the time of flight delay.
  • Clocking a high speed bus accurately without introducing error due to propagation delays can be implemented by having each device monitor two bus clock signals and then derive internally a device clock, the true system clock.
  • the bus clock information can be sent on one or two lines to provide a mechanism for each bused device to generate an internal device clock with zero skew relative to all the other device clocks.
  • a bus clock generator 50 at one end of the bus propagates an early bus clock signal in one direction along the bus, for example on line 53 from left to right, to the far end of the bus.
  • the same clock signal then is passed through the direct connection shown to a second line 54 , and returns as a late bus clock signal along the bus from the far end to the origin, propagating from right to left.
  • a single bus clock line can be used if it is left unterminated at the far end of the bus, allowing the early bus clock signal to reflect back along the same line as a late bus clock signal.
  • FIG. 8 b illustrates how each device 51 , 52 receives each of the two bus clock signals at a different time (because of propagation delay along the wires), with constant midpoint in time between the two bus clocks along the bus.
  • the rising edge 55 of Clock 1 53 is followed by the rising edge 56 of Clock 2 54 .
  • the falling edge 57 of Clock 1 53 is followed by the falling edge 58 of Clock 2 54 . This waveform relationship is observed at all other devices along the bus.
  • Clock distribution problems can be further reduced by using a bus clock and device clock rate equal to the bus cycle data rate divided by two, that is, the bus clock period is twice the bus cycle period.
  • a 500 MHz bus preferably uses a 250 MHz clock rate. This reduction in frequency provides two benefits. First it makes all signals on the bus have the same worst case data rates—data on a 500 MHz bus can only change every 2 ns. Second, clocking at half the bus cycle data rate makes the labeling of the odd and even bus cycles trivial, for example, by defining even cycles to be those when the internal device clock is 0 and odd cycles when the internal device clock is 1.
  • bus length The limitation on bus length described above restricts the total number of devices that can be placed on a single bus. Using 2.5 mm spacing between devices, a single 8 cm bus will hold about 32 devices. Persons skilled in the art will recognize certain applications of the present invention wherein the overall data rate on the bus is adequate but memory or processing requirements necessitate a much larger number of devices (many more than 32). Larger systems can easily be built using the teachings of this invention by using one or more memory subsystems, designated primary bus units, each of which consists of two or more devices, typically 32 or close to the maximum allowed by bus design requirements, connected to a transceiver device.
  • each primary bus unit can be mounted on a single circuit board 66 , sometimes called a memory stick.
  • Each transceiver device 19 in turn connects to a transceiver bus 65 , similar or identical in electrical and other respects to the primary bus 18 described at length above.
  • all masters are situated on the transceiver bus so there are no transceiver delays between masters and all memory devices are on primary bus units so that all memory accesses experience an equivalent transceiver delay, but persons skilled in the art will recognize how to implement systems which have masters on more than one bus unit and memory devices on the transceiver bus as well as on primary bus units.
  • each teaching of this invention which refers to a memory device can be practiced using a transceiver device and one or more memory devices on an attached primary bus unit.
  • Other devices generically referred to as peripheral devices, including disk controllers, video controllers or I/O devices can also be attached to either the transceiver bus or a primary bus unit, as desired.
  • Persons skilled in the art will recognize how to use a single primary bus unit or multiple primary bus units as needed with a transceiver bus in certain system designs.
  • the transceivers are quite simple in function. They detect request packets on the transceiver bus and transmit them to their primary bus unit. If the request packet calls for a write to a device on a transceiver's primary bus unit, that transceiver keeps track of the access time and block size and forwards all data from the transceiver bus to the primary bus unit during that time. The transceivers also watch their primary bus unit, forwarding any data that occurs there to the transceiver bus.
  • the high speed of the buses means that the transceivers will need to be pipelined, and will require an additional one or two cycle delay for data to pass through the transceiver in either direction. Access times stored in masters on the transceiver bus must be increased to account for transceiver delay but access times stored in slaves on a primary bus unit should not be modified.
  • TrncvrRW can be bused to all devices on the transceiver bus, using that line in conjunction with the AddrValid line to indicate to all devices on the transceiver bus that the information on the data lines is: 1) a request packet, 2) valid data to a slave, 3) valid data from a slave, or 4) invalid data (or idle bus).
  • Each controller seeking to trite to a slave should drive both AddrValid and TrncvrRW high, indicating valid data for a slave is present on the data lines.
  • Each transceiver device will then transmit all data from the transceiver bus lines to each primary bus unit.
  • Any controller expecting to receive information from a slave should also drive the TrncvrRW line high, but not drive AddrValid, thereby indicating to each transceiver to transmit any data coming from any slave on its primary local bus to the transceiver bus.
  • a still more sophisticated transceiver would recognize signals addressed to or coming from its primary bus unit and transmit signals only at requested times.
  • FIG. 9 An example of the physical mounting of the transceivers is shown in FIG. 9.
  • the transceivers 19 have pins on two sides, and are preferably mounted flat on the primary bus unit with a first set of pins connected to primary bus 16 .
  • a second set of transceiver pins 20 preferably orthogonal to the first set of pins, are oriented to allow the transceiver 19 to be attached to the transceiver bus 65 in much the same way as the DRAMs were attached to the primary bus unit.
  • the transceiver bus can be generally planar and in a different plane, preferably orthogonal to the plane of each primary bus unit.
  • the transceiver bus can also be generally circular with primary bus units mounted perpendicular and tangential to the transceiver bus.
  • Using this two level scheme allows one to easily build a system that contains over 500 slaves (16 buses of 32 DRAMs each).
  • Persons skilled in the art can modify the device ID scheme described above to accommodate more than 256 devices, for example by using a longer device ID or by using additional registers to hold some of the device ID.
  • This scheme can be extended in yet a third dimension to make a second-order transceiver bus, connecting multiple transceiver buses by aligning transceiver bus units parallel to and on top of each other and busing corresponding signal lines through a suitable transceiver. Using such a second-order transceiver bus, one could connect many thousands of slave devices into what is effectively a single bus.
  • the device interface to the high-speed bus can be divided into three main parts.
  • the first part is the electrical interface.
  • This part includes the input receivers, bus drivers and clock generation circuitry.
  • the second part contains the address comparison circuitry and timing registers.
  • This part takes the input request packet and determines if the request in for this device, and if it is, starts the internal access and delivers the data to the pins at the correct time.
  • the final part specifically for memory devices such as DRAMs, is the DRAM column access path. This part needs to provide bandwidth into and out of the DRAM sense amps greater than the bandwidth provided by conventional DRAMS.
  • the implementation of the electrical interface and DRAM column access path are described in more detail in the following sections. Persons skilled in the art recognize how to modify prior-art address comparison circuitry and prior-art register circuitry in order to practice the present invention.
  • FIG. 10 A block diagram of the preferred input/output circuit for address/data/control lines is shown in FIG. 10.
  • This circuitry is particularly well-suited for use in DRAM devices but it can be used or modified by one skilled in the art for use in other devices connected to the bus of this invention. It consists of a set of input receivers 71 , 72 and output driver 76 connected to input/output line 69 and pad 75 and circuitry to use the internal clock 73 and internal clock complement 74 to drive the input interface.
  • the clocked input receivers take advantage of the synchronous nature of the bus. To further reduce the performance requirements for device input receivers, each device pin, and thus each bus line, is connected to two clocked receivers, one to sample the even cycle inputs, the other to sample the odd cycle inputs.
  • each clocked amplifier is given a full 2 ns cycle to amplify the bus low-voltage-swing signal into a full value CMOS logic signal.
  • additional clocked input receivers can be used within the teachings of this invention. For example, four input receivers could be connected to each device pin and clocked by a modified internal device clock to transfer sequential bits from the bus to internal device circuits, allowing still higher external bus speeds or still longer settling times to amplify the bus low-voltage-swing signal into a full value CMOS logic signal.
  • the output drivers are quite simple, and consist of a single RHOS pulldown transistor 76 .
  • This transistor sized so that under worst case conditions it can still sink the 50 mA required by the bus.
  • the transistor will need to be about 200 microns long.
  • Overall bus performance can be improved by using feedback techniques to control output transistor current so that the current through the device is roughly 50 mA under all operating conditions, although this is not absolutely necessary for proper bus operation.
  • An example of one of many methods known to persons skilled in the art for using feedback techniques to control current is described in Bans Schumacher, et al., “CMOS Subnanosecond True-ECL Output Buffer,” J. Solid State Circuits , Vol. 25 (1), pp.
  • This output driver which can be operated at 500 MHz, can in turn be controlled by a suitable multiplexer with two or more (preferably four) inputs connected to other internal chip circuitry, all of which can be designed according to well known prior art.
  • the input receivers of every slave must be able to operate during every cycle to determine whether the signal on the bus is a valid request packet. This requirement leads to a number of constraints on the input circuitry. In addition to requiring small acquisition and resolution delays, the circuits must take little or no DC power, little AC power and inject very little current back into the input or reference lines.
  • the standard clocked DRAM sense amp shown in FIG. 11 satisfies all these requirements except the need for low input currents. When this sense amp goes from sense to sample, the capacitance of the internal nodes 83 and 84 in FIG. 11 is discharged through the reference line 68 and input 69 , respectively. This current in small, but the sum of such currents from all the inputs into the reference lines summed over all devices can be reasonably large.
  • One important part of the input/output circuitry generates an internal device clock based on early and late bus clocks. Controlling clock skew (the difference in clock timing between devices) is important in a system running with 2 ns cycles, thus the internal device clock is generated so the input sampler and the output driver operate as close in time as possible to midway between the two bus clocks.
  • a block diagram of the internal device clock generating circuit is shown in FIG. 12 and the corresponding timing diagram in FIG. 13.
  • the basic idea behind this circuit is relatively simple.
  • a DC amplifier 102 is used to convert the small-swing bus clock into a full-swing CMOS signal. This signal is then fed into a variable delay line 103 .
  • the output of delay line 103 feeds three additional delay lines: 104 having a fixed delay; 105 having the same fixed delay plus a second variable delay; and 106 having the same fixed delay plus one half of the second variable delay.
  • the outputs 107 , 108 of the delay lines 104 and 105 drive clocked input receivers 101 and 111 connected to early and late bus clock inputs 100 and 110 , respectively.
  • variable delay lines 103 and 105 are adjusted via feedback lines 116 , 115 so that input receivers 101 and 111 sample the bus clocks just as they transition.
  • Delay lines 103 and 105 are adjusted so that the falling edge 120 of output 107 precedes the falling edge 121 of the early bus clock, Clock 1 53 , by an amount of time 128 equal to the delay in input sampler 101 .
  • Delay line 108 is adjusted in the same way so that falling edge 122 precedes the falling edge 123 of late bus clock, Clock 2 54 , by the delay 128 in input sampler 111 .
  • output 73 provides an internal device clock midway between the bus clocks.
  • the falling edge 124 of internal device clock 73 precedes the time of actual input sampling 125 by one sampler delay. Note that this circuit organization automatically balances the delay in substantially all device input receivers 71 and 72 (FIG. 10), since outputs 107 and 108 are adjusted so the bus clocks are sampled by input receivers 101 and 111 just as the bus clocks transition.
  • two sets of these delay lines are used, one to generate the true value of the internal device clock 73 , and the other to generate the complement 74 without adding any inverter delay.
  • the dual circuit allows generation of truly complementary clocks, with extremely small skew.
  • the complement internal device clock is used to clock the ‘even’ input receivers to sample at time 127
  • the true internal device clock is used to clock the ‘odd’ input receivers to sample at time 125 .
  • the true and complement internal device clocks are also used to select which data is driven to the output drivers.
  • the gate delay between the internal device clock and output circuits driving the bus is slightly greater than the corresponding delay for the input circuits, which means that the new data always will be driven on the bus slightly after the old data as bee sampled.
  • FIG. 15 A block diagram of a conventional 4 MBit DRAM 130 is shown in FIG. 15.
  • the DRAM memory array is divided into a number of subarrays 150 - 157 , for example, 8. Each subarray is divided into arrays 148 , 149 of memory cells.
  • Row address selection is performed by decoders 146 .
  • Internal I/O lines connect each set of sense-amps, as gated by corresponding column decoders, to input and output circuitry connected ultimately to the device pins.
  • I/O lines are used to drive the data from the selected bit lines to the data pins (some of pins 131 - 145 ), or to take the data from the pins and write the selected bit lines.
  • Such a column access path organized by prior art constraints does not have sufficient bandwidth to interface with a high speed bus.
  • the method of this invention does not require changing the overall method used for column access, but does change implementation details. Many of these details have been implemented selectively in certain fast memory devices, but never in conjunction with the bus architecture of this invention.
  • Running the internal I/O lines in the conventional way at high bus cycle rates is not possible.
  • several (preferably 4) bytes are read or written during each cycle and the column access path is modified to run at a lower rate (the inverse of the number of bytes accessed per cycle, preferably 1 ⁇ 4 of the bus cycle rate).
  • Three different techniques are used to provide the additional internal I/O lines required and to supply data to memory cells at this rate.
  • the number of I/O bit lines in each subarray running through the column decoder 147 is increased, for example, to 16, eight for each of the two columns of column sense amps and the column decoder selects one set of columns from the “top” half 148 of subarray 150 and one set of columns from the “bottom” half 149 during each cycle, where the column decoder selects one column sense amp per I/O bit line.
  • each column I/O line is divided into two halves, carrying data independently over separate internal I/O lines from the left half 147 A and right half 147 B of each subarray (dividing each subarray into quadrants) and the column decoder selects sense amps from each right and left half of the subarray, doubling the number of bits available at each cycle.
  • two different subarrays e.g. 157 and 153 , are accessed.
  • the multiple, gated input receivers described above allow high speed input from the device pins onto the internal I/O lines and ultimately into memory.
  • the multiplexed output driver described above is used to keep up with the data flow available using these techniques.
  • Control means are provided to select whether information at the device pins should be treated as an address, and therefore to be decoded, or input or output data to be driven onto or read from the internal I/O lines.
  • Each subarray can access 32 bits per cycle, 16 bits from the left subarray and 16 from the right subarray. With 8 I/O lines per sense-amplifier column and accessing two subarrays at a time, the DRAM can provide 64 bits per cycle. This extra I/O bandwidth is not needed for reads (and is probably not used), but may be needed for writes. Availability of write bandwidth in a more difficult problem than read bandwidth because over-writing a value in a sense-amplifier may be a slow operation, depending on how the sense amplifier is connected to the bit line. The extra set of internal I/O lines provides some bandwidth margin for write operations.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Information Transfer Systems (AREA)

Abstract

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.
The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

Description

    FIELD OF THE INVENTION
  • An integrated circuit bus interface for computer and video systems is described which allows high speed transfer of blocks of data, particularly to and from memory devices, with reduced power consumption and increased system reliability. A new method of physically implementing the bus architecture is also described. [0001]
    • BACKGROUND OF THE INVENTION
  • Semiconductor computer memories have traditionally been designed and structured to use one memory device for each bit, or small group of bits, of any individual computer word, where the word size is governed by the choice of computer. Typical word sizes range from 4 to 64 bits. Each memory device typically is connected in parallel to a series of address lines and connected to one of a series of data lines. When the computer seeks to read from or write to a specific memory location, an address is put on the address lines and some or all of the memory devices are activated using a separate device select line for each needed device. One or more devices may be connected to each data line but typically only a small number of data lines are connected to a single memory device. Thus [0002] data line 0 is connected to device(s) 0, data line 1 is connected to device(s) 1, and so on. Data is thus accessed or provided in parallel for each memory read or write operation. For the system to operate properly, every single memory bit in every memory device must operate dependably and correctly.
  • To understand the concept of the present invention, it is helpful to review the architecture of conventional memory devices. Internal to nearly all types of memory devices (including the most widely used Dynamic Random Access Memory (DRAM), Static RAM (SRAM) and Read Only Memory (ROM) devices), a large number of bits are accessed in parallel each time the system carries out a memory access cycle. However, only a small percentage of accessed bits which are available internally each time the memory device is cycled ever make it across the device boundary to the external world. [0003]
  • Referring to FIG. 1, all modern DRAM, SRAM and ROM designs have internal architectures with row (word) [0004] lines 5 and column (bit) lines 6 to allow the memory cells to tile a two dimensional area 1. One bit of data is stored at the intersection of each word and bit line. When a particular word line is enabled, all of the corresponding data bits are transferred onto the bit lines. Some prior art DRAMs take advantage of this organization to reduce the number of pins needed to transmit the address. The address of a given memory call is split into two addresses, row and column, each of which can be multiplexed over a bus only half as wide as the memory cell address of the prior art would have required.
    • COMPARISON WITH PRIOR ART
  • Prior art memory systems have attempted to solve the problem of high speed access to memory with limited success. U.S. Pat. No. 3,821,715 (Hoff et. al.), was issued to Intel Corporation for the earliest 4-bit micro-processor. That patent describes a bus connecting a single central processing unit (CPU) with multiple RAMs and ROMs. That bus multiplexes addresses and data over a 4-bit wide bus and uses point-to-point control signals to select particular RAMs or ROMs. The access time is fixed and only a single processing element is permitted. There is no block-mode type of operation, and most important, not all of the interface signals between the devices are bused (the ROM and RAM control lines and the RAM select lines are point-to-point). [0005]
  • In U.S. Pat. No. 4,315,308 (Jackson), a bus connecting a single CPU to a bus interface unit is described. The invention uses multiplexed address, data, and control information over a single 16-bit wide bus. Block-mode operations are defined, with the length of the block sent as part of the control sequence. In addition, variable access-time operations using a “stretch” cycle signal are provided. There are no multiple processing elements and no capability for multiple outstanding requests, and again, not all of the interface signals are bused. [0006]
  • In U.S. Pat. No. 4,449,207 (Kung, et. al.), a DRAM is described which multiplexes address and data on an internal bus. The external interface to this DRAM is conventional, with separate control, address and data connections. [0007]
  • In U.S. Pat. Nos. 4,764,846 and 4,706,166 (Go), a 3-D package arrangement of stacked die with connections along a single edge is described. Such packages are difficult to use because of the point-to-point wiring required to interconnect conventional memory devices with processing elements. Both patents describe complex schemes for solving these problems. No attempt is made to solve the problem by changing the interface. [0008]
  • In U.S. Pat. No. 3,969,706 (Proebsting, et. al.), the current state-of-the-art DRAM interface is described. The address is two-way multiplexed, and there are separate pins for data and control (RAS, CAS, WE, CS). The number of pins grows with the size of the DRAM, and many of the connections must be made point-to-point in a memory system using such DRAMs. [0009]
  • There are many backplane buses described in the prior art, but not in the combination described or having the features of this invention. Many backplane buses multiplex addresses and data on a single bus (e.g., the NU bus). ELXSI and others have implemented split-transaction buses (U.S. Pat. No. 4,595,923 and 4,481,625 (Roberts)). ELXSI has also implemented a relatively low-voltage-swing current-mode ECL driver (approximately 1V swing). Address-space registers are implemented on most backplane buses, as is some form of block mode operation. [0010]
  • Nearly all modern backplane buses implement some type of arbitration scheme, but the arbitration scheme used in this invention differs from each of these. U.S. Pat. Nos. 4,837,682 (Culler), 4,818,985 (Ikeda), 4,779,089 (Theus) and 4,745,548 (Blahut) describe prior art schemes. All involve either log N extra signals, (Theus, Blahut), where N is the number of potential bus requestors, or additional delay to get control of the bus (Ikeda, Culler). None of the buses described in patents or other literature use only bused connections. All contain some point-to-point connections on the backplane. None of the other aspects of this invention such as power reduction by fetching each data block from a single device or compact and low-cost 3-D packaging even apply to backplane buses. [0011]
  • The clocking scheme used in this invention has not been used before and in fact would be difficult to implement in backplane buses due to the signal degradation caused by connector stubs. U.S. Pat. No. 4,247,817 (Heller) describes a clocking scheme using two clock lines, but relies on ramp-shaped clock signals in contrast to the normal rise-time signals used in the present invention. [0012]
  • In U.S. Pat. No. 4,646,279 (Voss), a video RAM is described which implements a parallel-load, serial-out shift register on the output of a DRAM. This generally allows greatly improved bandwidth (and has been extended to 2, 4 and greater width shift-out paths.) The rest of the interfaces to the DRAM (RAS, CAS, multiplexed address, etc.) remain the same as for conventional DRAMS. [0013]
  • One object of the present invention is to use a new bus interface built into semiconductor devices to support high-speed access to large blocks of data from a single memory device by an external user of the data, such as a microprocessor, in an efficient and cost-effective manner. [0014]
  • Another object of this invention is to provide a clocking scheme to permit high speed clock signals to be sent along the bus with minimal clock skew between devices. [0015]
  • Another object of this invention is to allow mapping out defective memory devices or portions of memory devices. [0016]
  • Another object of this invention is to provide a method for distinguishing otherwise identical devices by assigning a unique identifier to each device. [0017]
  • Yet another object of this invention is to provide a method for transferring address, data and control information over a relatively narrow bus and to provide a method of bus arbitration when multiple devices seek to use the bus simultaneously. [0018]
  • Another object of this invention is to provide a method of distributing a high-speed memory cache within the DRAM chips of a memory system which is much more effective than previous cache methods. [0019]
  • Another object of this invention is to provide devices, especially DRAMs, suitable for use with the bus architecture of the invention. [0020]
    • SUMMARY OF INVENTION
  • The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected in parallel to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices. [0021]
  • Referring to FIG. 2, a [0022] standard DRAM 13, 14, ROM (or SRAM) 12, microprocessor CPU 11, I/O device, disk controller or other special purpose device such as a high speed switch is modified to use a wholly bus-based interface rather than the prior art combination of point-to-point and bus-based wiring used with conventional versions of these devices. The new bus includes clock signals, power and multiplexed address, data and control signals. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide. Persons skilled in the art will recognize that 16 bus data lines or other numbers of bus data lines can be used to implement the teaching of this invention. The new bus is used to connect elements such as memory, peripheral, switch and processing units.
  • In the system of this invention, DRAMs and other devices receive address and control information over the bus and transmit or receive requested data over the same bus. Each memory device contains only a single bus interface with no other signal pins. Other devices that may be included in the system can connect to the bus and other non-bus lines, such as input/output lines. The bus supports large data block transfers and split transactions to allow a user to achieve high bus utilization. This ability to rapidly read or write a large block of data to one single device at a time is an important advantage of this invention. [0023]
  • The DRAMs that connect to this bus differ from conventional DRAMs in a number of ways. Registers are provided which may store control information, device identification, device-type and other information appropriate for the chip such as the address range for each independent portion of the device. New bus interface circuits must be added and the internals of prior art DRAM devices need to be modified so they can provide and accept data to and from the bus at the peak data rate of the bus. This requires changes to the column access circuitry in the DRAM, with only a minimal increase in die size. A circuit is provided to generate a low skew internal device clock for devices on the bus, and other circuits provide for demultiplexing input and multiplexing output signals. [0024]
  • High bus bandwidth is achieved by running the bus at a very high clock rate (hundreds of MHz), This high clock rate is made possible by the constrained environment of the bus. The bus lines are controlled-impedance, doubly-terminated lines. For a data rate of 500 MHz, the maximum bus propagation time is less than 1 ns (the physical bus length is about 10 cm). In addition, because of the packaging used, the pitch of the pins can be very close to the pitch of the pads. The loading on the bus resulting from the individual devices is very small. In a preferred implementation, this generally allows stub capacitances of 1-2 pF and inductances of 0.5-2 nH. Each [0025] device 15, 16, 17, shown in FIG. 3, only has pins on one side and these pins connect directly to the bus 18. A transceiver device 19 can be included to interface multiple units to a higher order bus through pins 20.
  • A primary result of the architecture of this invention is to increase the bandwidth of DRAM access. The invention also reduces manufacturing and production costs, power consumption, and increases packing density and system reliability.[0026]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram which illustrates the basic 2-D organization of memory devices. [0027]
  • FIG. 2 is a schematic block diagram which illustrates the parallel connection of all bus lines and the serial Reset line to each device in the system. [0028]
  • FIG. 3 is a perspective view of a system of the invention which illustrates the 3-D packaging of semiconductor devices on the primary bus. [0029]
  • FIG. 4 shows the format of a request packet. [0030]
  • FIG. 5 shows the format of a retry response from a slave. [0031]
  • FIG. 6 shows the bus cycles after a request packet collision occurs on the bus and how arbitration is handled. [0032]
  • FIG. 7 shows the timing whereby signals from two devices can overlap temporarily and drive the bus at the same time. [0033]
  • FIG. 8 shows the connection and timing between bus clocks and devices on the bus. [0034]
  • FIG. 9 is a perspective view showing how transceivers can be used to connect a number of bus units to a transceiver bus. [0035]
  • FIG. 10 is a block and schematic diagram of input/output circuitry used to connect devices to the bus. [0036]
  • FIG. 11 is a schematic diagram of a clocked sense-amplifier used as a bus input receiver. [0037]
  • FIG. 12 is a block diagram showing how the internal device clock is generated from two bus clock signals using a set of adjustable delay lines. [0038]
  • FIG. 13 is a timing diagram showing the relationship of signals in the block diagram of FIG. 12. [0039]
  • FIG. 14 is timing diagram of a preferred means of implementing the reset procedure of this invention. [0040]
  • FIG. 15 is a diagram illustrating the general organization of a 4 Mbit DRAM divided into 8 subarrays.[0041]
    • DETAILED DESCRIPTION
  • The present invention is designed to provide a high speed, multiplexed bus for communication between processing devices and memory devices and to provide devices adapted for use in the bus system. The invention can also be used to connect processing devices and other devices, such as I/O interfaces or disk controllers, with or without memory devices on the bus. The bus consists of a relatively small number of lines connected in parallel to each device on the bus. The bus carries substantially all address, data and control information needed by devices for communication with other devices on the bus. In many systems using the present invention, the bus carries almost every signal between every device in the entire system. There is no need for separate device-select lines since device-select information for each device on the bus is carried over the bus. There is no need for separate address and data lines because address and data information can be sent over the same lines. [0042]
  • Using the organization described herein, very large addresses (40 bits in the preferred implementation) and large data blocks (1024 bytes) can be sent over a small number of bus lines (8 plus one control line in the preferred implementation). [0043]
  • Virtually all of the signals needed by a computer system can be sent over the bus. Persons skilled in the art recognize that certain devices, such as CPUs, may be connected to other signal lines and possibly to independent buses, for example a bus to an independent cache memory, in addition to the bus of this invention. Certain devices, for example cross-point switches, could be connected to multiple, independent buses of this invention. In the preferred implementation, memory devices are provided that have no connections other than the bus connections described herein and CPUs are provided that use the bus of this invention as the principal, if not exclusive, connection to memory and to other devices on the bus. [0044]
  • All modern DRAM, SRAM and ROM designs have internal architectures with row (word) and column (bit) lines to efficiently tile a 2-D area. Referring to FIG. 1, one bit of data is stored at the intersection of each [0045] word line 5 and bit line 6. When a particular word line is enabled, all of the corresponding data bits are transferred onto the bit lines. This data, about 4000 bits at a time in a 4 MBit DRAM, is then loaded into column sense amplifiers 3 and held for use by the I/O circuits.
  • In the invention presented here, the data from the sense amplifiers is enabled 32 bits at a time onto an internal device bus running at approximately 125 MHz. This internal device bus moves the data to the periphery of the devices where the data is multiplexed into an 8-bit wide external bus interface, running at approximately 500 MHz. [0046]
  • The bus architecture of this invention connects master or bus controller devices, such as CPUs, Direct Memory Access devices (DMAs) or Floating Point Units (FPUs), and slave devices, such as DRAM, SRAM or ROM memory devices. A slave device responds to control signals; a master sends control signals. Persons skilled in the art realize that some devices may behave as both master and slave at various times, depending on the mode of operation and the state of the system. For example, a memory device will typically have only slave functions, while a DMA controller, disk controller or CPU may include both slave and master functions. Many other semiconductor devices, including I/O devices, disk controllers, or other special purpose devices such as high speed switches can be modified for use with the bus of this invention. [0047]
  • Each semiconductor device contains a set of internal registers, preferably including a device identification (device ID) register, a device-type descriptor register, control registers and other registers containing other information relevant to that type of device. In a preferred implementation, semiconductor devices connected to the bus contain registers which specify the memory addresses contained within that device and access-time registers which store a set of one or more delay times at which the device can or should be available to send or receive data. [0048]
  • Most of these registers can be modified and preferably are set as part of an initialization sequence that occurs when the system is powered up or reset. During the initialization sequence each device on the bus is assigned a unique device ID number, which is stored in the device ID register. A bus master can then use these device ID numbers to access and set appropriate registers in other devices, including access-time registers, control registers, and memory registers, to configure the system. Each slave may have one or several access-time registers (four in a preferred embodiment). In a preferred embodiment, one access-time register in each slave is permanently or semi-permanently programmed with a fixed value to facilitate certain control functions. A preferred implementation of an initialization sequence is described below in more detail. [0049]
  • All information sent between master devices and slave devices is sent over the external bus, which, for example, may be 8 bits wide. This is accomplished by defining a protocol whereby a master device, such as a microprocessor, seizes exclusive control of the external bus (i.e., becomes the bus master) and initiates a bus transaction by sending a request packet (a sequence of bytes comprising address and control information) to one or more slave devices on the bus. An address can consist of 16 to 40 or more bits according to the teachings of this invention. Each slave on the bus must decode the request packet to see if that slave needs to respond to the packet. The slave that the packet is directed to must then begin any internal processes needed to carry out the requested bus transaction at the requested time. The requesting master may also need to transact certain internal processes before the bus transaction begins. After a specified access time the slave(s) respond by returning one or more bytes (8 bits) of data or by storing information made available from the bus. More than one access time can be provided to allow different types of responses to occur at different times. [0050]
  • A request packet and the corresponding bus access are separated by a selected number of bus cycles, allowing the bus to be used in the intervening bus cycles by the same or other masters for additional requests or brief bus accesses. Thus multiple, independent accesses are permitted, allowing maximum utilization of the bus for transfer of short blocks of data. Transfers of long blocks of data use the bus efficiently even without overlap because the overhead due to bus address, control and access times is small compared to the total time to request and transfer the block. [0051]
  • Device Address Mapping [0052]
  • Another unique aspect of this invention is that each memory device is a complete, independent memory subsystem with all the functionality of a prior art memory board in a conventional backplane-bus computer system. Individual memory devices may contain a single memory section or may be subdivided into more than one discrete memory section. Memory devices preferably include memory address registers for each discrete memory section. A failed memory device (or even a subsection of a device) can be “mapped out” with only the loss of a small fraction of the memory, maintaining essentially full system capability. Mapping out bad devices can be accomplished in two ways, both compatible with this invention. [0053]
  • The preferred method uses address registers in each memory device (or independent discrete portion thereof) to store information which defines the range of bus addresses to which this memory device will respond. This is similar to prior art schemes used in memory boards in conventional backplane bus systems. The address registers can include a single pointer, usually pointing to a block of known size, a pointer and a fixed or variable block size value or two pointers, one pointing to the beginning and one to the end (or to the “top” and “bottom”) of each memory block. By appropriate settings of the address registers, a series of functional memory devices or discrete memory sections can be made to respond to a contiguous range of addresses, giving the system access to a contiguous block of good memory, limited primarily by the number of good devices connected to the bus. A block of memory in a first memory device or memory-section can be assigned a certain range of addresses, then a block of memory in a next memory device or memory section can be assigned addresses starting with an address one higher (or lower, depending on the memory structure) than the last address of the previous block. [0054]
  • Preferred devices for use in this invention include device-type register information specifying the type of chip, including how much memory is available in what configuration on that device. A master can perform an appropriate memory test, such as reading and writing each memory cell in one or more selected orders, to test proper functioning of each accessible discrete portion of memory (based in part on information like device ID number and device-type) and write address values (up to 40 bits in the preferred embodiment, 10[0055] 12 bytes), preferably contiguous, into device address-space registers. Non-functional or impaired memory sections can be assigned a special address value which the system can interpret to avoid using that memory.
  • The second approach puts the burden of avoiding the bad devices on the system master or masters. CPUs and DMA controllers typically have some sort of translation look-aside buffers (TLBs) which map virtual to physical (bus) addresses. With relatively simple software, the TLBs can be programmed to use only working memory (data structures describing functional memories are easily generated). For masters which don't contain TLBs (for example, a video display generator), a small, simple RAM can be used to map a contiguous range of addresses onto the addresses of the functional memory devices. [0056]
  • Either scheme works and permits a system to have a significant percentage of non-functional devices and still continue to operate with the memory which remains. This means that systems built with this invention will have much improved reliability over existing systems, including the ability to build systems with almost no field failures. [0057]
  • Bus [0058]
  • The preferred bus architecture of this invention comprises 11 signals: BusData[[0059] 0:7]; AddrValid; Clk1 and Clk2; plus an input reference level and power and ground lines connected in parallel to each device. Signals are driven onto the bus during conventional bus cycles. The notation “Signal[i:j]” refers to a specific range of signals or lines, for example, BusData[0:7] means BusData0, BusData1, . . . , BusData7.
  • The bus lines for BusData[[0060] 0:7] signals form a byte-wide, multiplexed data/address/control bus. AddrValid is used to indicate when the bus is holding a valid address request, and instructs a slave to decode the bus data as an address and, if the address is included on that slave, to handle the pending request. The two clocks together provide a synchronized, high speed clock for all the devices on the bus. In addition to the bused signals, there is one other line (ResetIn, ResetOut) connecting each device in series for use during initialization to assign every device in the system a unique device ID number (described below in detail).
  • To facilitate the extremely high data rate of this external bus relative to the gate delays of the internal logic, the bus cycles are grouped into pairs of even/odd cycles. Note that all devices connected to a bus should preferably use the same even/odd labeling of bus cycles and preferably should begin operations on even cycles. This is enforced by the clocking scheme. [0061]
  • Protocol and Bus Operation [0062]
  • The bus uses a relatively simple, synchronous, split-transaction, block-oriented protocol for bus transactions. One of the goals of the system is to keep the intelligence concentrated in the masters, thus keeping the slaves as simple as possible (since there are typically many more slaves than masters). To reduce the complexity of the slaves, a slave should preferably respond to a request in a specified time, sufficient to allow the slave to begin or possibly complete a device-internal phase including any internal actions that must precede the subsequent bus access phase. The time for this bus access phase is known to all devices on the bus—each master being responsible for making sure that the bus will be free when the bus access begins. Thus the slaves never worry about arbitrating for the bus. This approach eliminates arbitration in single master systems, and also makes the slave-bus interface simpler. [0063]
  • In a preferred implementation of the invention, to initiate a bus transfer over the bus, a master sends out a request packet, a contiguous series of bytes containing address and control information. It is preferable to use a request packet containing an even number of bytes and also preferable to start each packet on an even bus cycle. [0064]
  • The device-select function is handled using the bus data lines. AddrValid is driven, which instructs all slaves to decode the request packet address, determine whether they contain the requested address, and if they do, provide the data back to the master (in the case of a read request) or accept data from the master (in the case of a write request) in a data block transfer. A master can also select a specific device by transmitting a device ID number in a request packet. In a preferred implementation, a special device ID number is chosen to indicate that the packet should be interpreted by all devices on the bus. This allows a master to broadcast a message, for example to set a selected control register of all devices with the same value. [0065]
  • The data block transfer occurs later at a time specified in the request packet control information, preferably beginning on an even cycle. A device begins a data block transfer almost immediately with a device-internal phase as the device initiates certain functions, such as setting up memory addressing, before the bus access phase begins. The time after which a data block is driven onto the bus lines is selected from values stored in slave access-time registers. The timing of data for reads and writes is preferably the same; the only difference is which device drives the bus. For reads, the slave drives the bus and the master latches the values from the bus. For writes the master drives the bus and the selected slave latches the values from the bus. [0066]
  • In a preferred implementation of this invention shown in FIG. 4, a [0067] request packet 22 contains 6 bytes of data—4.5 address bytes and 1.5 control bytes. Each request packet uses all nine bits of the multiplexed data/address lines (AddrValid 23+BusData[0:7]24) for all six bytes of the request packet. Setting 23 AddrValid=1 in an otherwise unused even cycle indicates the start of an request packet (control information). In a valid request packet, AddrValid 27 must be 0 in the last byte. Asserting this signal in the last byte invalidates the request packet. This is used for the collision detection and arbitration logic (described below). Bytes 25-26 contain the first 35 address bits, Address[0:35]. The last byte contains AddrValid 27 (the invalidation switch) and 28, the remaining address bits, Address[36:39], and BlockSize[0:3] (control information).
  • The first byte contains two 4 bit fields containing control information, AccessType[[0068] 0:3], an op code (operation code) which, for example, specifies the type of access, and Master[0:3], a position reserved for the master sending the packet to include its master ID number. Only master numbers 1 through 15 are allowed—master number 0 is reserved for special system commands. Any packet with Master[0:3]=0 is an invalid or special packet and is treated accordingly.
  • The AccessType field specifies whether the requested operation is a read or write and the type of access, for example, whether it is to the control registers or other parts of the device, such as memory. In a preferred implementation, AccessType[[0069] 0] is a Read/Write switch: if it is a 1, then the operation calls for a read from the slave (the slave to read the requested memory block and drive the memory contents onto the bus); if it is a 0, the operation calls for a write into the slave (the slave to read data from the bus and write it to memory). AccessType[1:3] provides up to 8 different access types for a slave. AccessType[1:2] preferably indicates the timing of the response, which is stored in an access-time register, AccessRegN. The choice of access-time register can be selected directly by having a certain op code select that register, or indirectly by having a slave respond to selected op codes with pre-selected access times (see table below). The remaining bit, AccessType[3] may be used to send additional information about the request to the slaves.
  • One special type of access is control register access, which involves addressing a selected register in a selected slave. In the preferred implementation of this invention, AccessType[[0070] 1:3] equal to zero indicates a control register request and the address field of the packet indicates the desired control register. For example, the most significant two bytes can be the device ID number (specifying which slave is being addressed) and the least significant three bytes can specify a register address and may also represent or include data to be loaded into that control register. Control register accesses are used to initialize the access-time registers, so it is preferable to use a fixed response time which can be preprogrammed or even hard wired, for example the value in AccessReg0, preferably 8 cycles. Control register access can also be used to initialize or modify other registers, including address registers.
  • The method of this invention provides for access mode control specifically for the DRAMs. One such access mode determines whether the access is page mode or normal RAS access. In normal mode (in conventional DRAMS and in this invention), the DRAM column sense amps or latches have been precharged to a value intermediate between logical 0 and 1. This precharging allows access to a row in the RAM to begin as soon as the access request for either inputs (writes) or outputs (reads) is received and allows the column sense amps to sense data quickly. In page mode (both conventional and in this invention), the DRAM holds the data in the column sense amps or latches from the previous read or write operation. If a subsequent request to access data is directed to the same row, the DRAM does not need to wait for the data to be sensed (it has been sensed already) and access time for this data is much shorter than the normal access time. Page mode generally allows much faster access to data but to a smaller block of data (equal to the number of sense amps). However, if the requested data is not in the selected row, the access time is longer than the normal access time, since the request must wait for the RAM to precharge before the normal mode access can start. Two access-time registers in each DRAM preferably contain the access times to be used for normal and for page-mode accesses, respectively. [0071]
  • The access mode also determines whether the DRAM should precharge the sense amplifiers or should save the contents of the sense amps for a subsequent page mode access. Typical settings are “precharge after normal access” and “save after page mode access” but “precharge after page mode access” or “save after normal access” are allowed, selectable modes of operation. The DRAM can also be set to precharge the sense amps if they are not accessed for a selected period of time. [0072]
  • In page mode, the data stored in the DRAM sense amplifiers may be accessed within much less time than it takes to read out data in normal mode ([0073] ˜10-20 nS vs. 40-100 nS). This data may be kept available for long periods. However, if these sense amps (and hence bit lines) are not precharged after an access, a subsequent access to a different memory word (row) will suffer a precharge time penalty of about 40-100 nS because the sense amps must precharge before latching in a new value.
  • The contents of the sense amps thus may be held and used as a cache, allowing faster, repetitive access to small blocks of data. DRAM-based page-mode caches have been attempted in the prior art using conventional DRAM organizations but they are not very effective because several chips are required per computer word. Such a conventional page-mode cache contains many bits (for example, 32 chips×4Kbits) but has very few independent storage entries. In other words, at any given point in time the sense amps hold only a few different blocks or memory “locales” (a single block of 4K words, in the example above). Simulations have shown that upwards of 100 blocks are required to achieve high hit rates (>90% of requests find the requested data already in cache memory) regardless of the size of each block. See, for example, Anant Agarwal, et. al., “An Analytic Cache Model,” [0074] ACM Transactions on Computer Systems, Vol. 7(2), pp. 184-215 (May 1989).
  • The organization of memory in the present invention allows each DRAM to hold one or more (4 for 4MBit DRAMS) separately-addressed and independent blocks of data. A personal computer or workstation with 100 such DRAMs (i.e. 400 blocks or locales) can achieve extremely high, very repeatable hit rates (98-99% on average) as compared to the lower (50-80%), widely varying hit rates using DRAMS organized in the conventional fashion. Further, because of the time penalty associated with the deferred precharge on a “miss” of the page-mode cache, the conventional DRAM-based page-mode cache generally has been found to work less well than no cache at all. [0075]
  • For DRAM slave access, the access types are preferably used in the following way: [0076]
    AccessType[1:3] Use AccessTime
    0 Control Register Fixed, 8[AccessReg0]
    Access
    1 Unused Fixed, 8[AccessReg0]
    2-3 Unused AccessReg1
    4-5 Page Mode DRAM AccessReg2
    access
    6-7 Normal DRAM access AccessReg3
  • Persons skilled in the art will recognize that a series of available bits could be designated as switches for controlling these access modes. For example: [0077]
  • AccessType[[0078] 2]=page mode/normal switch
  • AccessType[[0079] 3]=precharge/save-data switch
  • BlockSize[[0080] 0:3] specifies the size of the data block transfer. If BlockSize[0] is 0, the remaining bits are the binary representation of the block size (0-7). If BlockSize[0] is 1, then the remaining bits give the block size as a binary power of 2, from 8 to 1024. A zero-length block can be interpreted as a special command, for example, to refresh a DRAM without returning any data, or to change the DRAM from page mode to normal access mode or vice-versa.
    BlockSize[0:2] Number of Bytes in Block
    0-7 0-7 respectively
    8 8
    9 16
    10 32
    11 64
    12 128
    13 256
    14 512
    15 1024
  • Persons skilled in the art will recognize that other block size encoding schemes or values can be used. [0081]
  • In most cases, a slave will respond at the selected access time by reading or writing data from or to the bus over bus lines BusData[[0082] 0:7] and AddrValid will be at logical 0. In a preferred embodiment, substantially each memory access will involve only a single memory device, that is, a single block will be read from or written to a single memory device.
  • Retry Format [0083]
  • In some cases, a slave may not be able to respond correctly to a request, e.g., for a read or write. In such a situation, the slave should return an error message, sometimes called a N(o)ACK(nowledge) or retry message. The retry message can include information about the condition requiring a retry, but this increases system requirements for circuitry in both slave and masters. A simple message indicating only that an error has occurred allows for a less complex slave, and 'the master can take whatever action is needed to understand and correct the cause of the error. [0084]
  • For example, under certain conditions a slave might not be able to supply the requested data. During a page-mode access, the DRAM selected must be in page mode and the requested address must match the address of the data held in the sense amps or latches. Each DRAM can check for this match during a page-mode access. If no match is found, the DRAM begins precharging and returns a retry message to the master during the first cycle of the data block (the rest of the returned block is ignored). The master then must wait for the precharge time (which is set to accommodate the type of slave in question, stored in a special register, PreChargeReg), and then resend the request as a normal DRAM access ([0085] AccessType 6 or 7).
  • In the preferred form of the present invention, a slave signals a retry by driving AddrValid true at the time the slave was supposed to begin reading or writing data. A master which expected to write to that slave must monitor AddrValid during the write and take corrective action if it detects a retry message. FIG. 5 illustrates the format of a retry [0086] message 28 which is useful for read requests, consisting of 23 AddrValid=1 with Master[0:3]=0 in the first (even) cycle. Note that AddrValid is normally 0 for data block transfers and that there is no master 0 (only 1 through 15 are allowed). All DRAMS and masters can easily recognize such a packet as an invalid request packet, and therefore a retry message. In this type of bus transaction all of the fields except for Master[0:3] and AddrValid 23 may be used as information fields, although in the implementation described, the contents are undefined. Persons skilled in the art recognize that another method of signifying a retry message is to add a DataInvalid line and signal to the bus. This signal could be asserted in the case of a NACK.
  • Bus Arbitration [0087]
  • In the case of a single master, there are by definition no arbitration problems. The master sends request packets and keeps track of periods when the bus will be busy in response to that packet. The master can schedule multiple requests so that the corresponding data block transfers do not overlap. [0088]
  • The bus architecture of this invention is also useful in configurations with multiple masters. When two or more masters are on the same bus, each master must keep track of all the pending transactions, so each master knows when it can send a request packet and access the corresponding data block transfer. [0089]
  • Situations will arise, however, where two or more masters send a request packet at about the same time and the multiple requests must be detected, then sorted out by some sort of bus arbitration. [0090]
  • There are many ways for each master to keep track of when the bus is and will be busy. A simple method is for each master to maintain a bus-busy data structure, for example by maintaining two pointers, one to indicate the earliest point in the future when the bus will be busy and the other to indicate the earliest point in the future when the bus will be free, that is, the end of the latest pending data block transfer. Using this information, each master can determine whether and when there is enough time to send a request packet (as described above under Protocol) before the bus becomes busy with another data block transfer and whether the corresponding data block transfer will interfere with pending bus transactions. Thus each master must read every request packet and update its bus-busy data structure to maintain information about when the bus is and will be free. [0091]
  • With two or more masters on the bus, masters will occasionally transmit independent request packets during the same bus cycle. Those multiple requests will collide as each such master drives the bus simultaneously with different information, resulting in scrambled request information and neither desired data block transfer. In a preferred form of the invention, each device on the bus seeking to write a logical 1 on a BusData or AddrValid line drives that line with a current sufficient to sustain a voltage greater than or equal to the high-logic value for the system. Devices do not drive lines that should have a logical 0; those lines are simply held at a voltage corresponding to a low-logic value. Each master tests the voltage on at least some, preferably all, bus data and the AddrValid lines so the master can detect a logical ‘1’ where the expected level is ‘0’ on a line that it does not drive during a given bus cycle but another master does drive. [0092]
  • Another way to detect collisions is to select one or more bus lines for collision signalling. Each master sending a request drives that line or lines and monitors the selected lines for more than the normal drive current (or a logical value of “>1”) indicating requests by more than one master. Persons skilled in the art will recognize that this can be implemented with a protocol involving BusData and AddrValid lines or could be implemented using an additional bus line. [0093]
  • In the preferred form of this invention, each master detects collisions by monitoring lines which it does not drive to see if another master is driving those lines. Referring to FIG. 4, the first byte of the request packet includes the number of each master attempting to use the bus (Master[[0094] 0:3]). If two masters send packet requests starting at the same point in time, the master numbers will be logical “or”ed together by at least those masters, and thus one or both of the masters, by monitoring the data on the bus and comparing what it sent, can detect a collision. For instance if requests by masters number 2 (0010) and 5 (0101) collide, the bus will be driven with the value Master[0:3]=7 (0010+0101=0111). Master number 5 will detect that the signal Master[2]=1 and master 2 will detect that Master[1] and Master[3]=1, telling both masters that a collision has occurred. Another example is masters 2 and 11, for which the bus will be driven with the value Master[0:3]=11 (0010+1011=1011), and although master 11 can't readily detect this collision, master 2 can. When any collision is detected, each master detecting a collision drives the value of AddrValid 27 in byte 5 of the request packet 22 to 1, which is detected by all masters, including master 11 in the second example above, and forces a bus arbitration cycle, described below.
  • Another collision condition may arise where master A sends a request packet in [0095] cycle 0 and master B tries to send a request packet starting in cycle 2 of the first request packet, thereby overlapping the first request packet. This will occur from time to time because the bus operates at high speeds, thus the logic in a second-initiating master may not be fast enough to detect a request initiated by a first master in cycle 0 and to react fast enough by delaying its own request. Master B eventually notices that it wasn't supposed to try to send a request packet (and consequently almost surely destroyed the address that master A was trying to send), and, as in the example above of a simultaneous collision, drives a 1 on AddrValid during byte 5 of the first request packet 27 forcing an arbitration. The logic in the preferred implementation is fast enough that a master should detect a request packet by another master by cycle 3 of the first request packet, so no master is likely to attempt to send a potentially colliding request packet later than cycle 2.
  • Slave devices not need to detect a collision directly, but they must wait to do anything irrecoverable until the last byte (byte [0096] 5) is read to ensure that the packet is valid. A request packet with Master[0:3] equal to 0 (a retry signal) is ignored and does not cause a collision. The subsequent bytes of such a packet are ignored.
  • To begin arbitration after a collision, the masters wait a preselected number of cycles after the aborted request packet (4 cycles in a preferred implementation), then use the next free cycle to arbitrate for the bus (the next available even cycle in the preferred implementation). Each colliding master signals to all other colliding masters that it seeks to send a request packet, a priority is assigned to each of the colliding masters, then each master is allowed to make its request in the order of that priority. [0097]
  • FIG. 6 illustrates one preferred way of implementing this arbitration. Each colliding master signals its intent to send a request packet by driving a single BusData line during a single bus cycle corresponding to its assigned master number ([0098] 1-15 in the present example). During two-byte arbitration cycle 29, byte 0 is allocated to requests 1-7 from masters 1-7, respectively, (bit 0 is not used) and byte 1 is allocated to requests 8-15 from masters 8-15, respectively. At least one device and preferably each colliding master reads the values on the bus during the arbitration cycles to determine and store which masters desire to use the bus. Persons skilled in the art will recognize that a single byte can be allocated for arbitration requests if the system includes more bus lines than masters. More than 15 masters can be accommodated by using additional bus cycles.
  • A fixed priority scheme (preferably using the master numbers, selecting lowest numbers first) is then used to prioritize, then sequence the requests in a bus arbitration queue which is maintained by at least one device. These requests are queued by each master in the bus-busy data structure and no further requests are allowed until the bus arbitration queue is cleared. Persons skilled in the art will recognize that other priority schemes can be used, including assigning priority according to the physical location of each master. [0099]
  • System Configuration/Reset [0100]
  • In the bus-based system of this invention, a mechanism is provided to give each device on the bus a unique device identifier (device ID) after power-up or under other conditions as desired or needed by the system. A master can then use this device ID to access a specific device, particularly to set or modify registers of the specified device, including the control and address registers. In the preferred embodiment, one master is assigned to carry out the entire system configuration process. The master provides a series of unique device ID numbers for each unique device connected to the bus system. In the preferred embodiment, each device connected to the bus contains a special device-type register which specifies the type of device, for instance CPU, 4 MBit memory, 64 MBit memory or disk controller. The configuration master should check each device, determine the device type and set appropriate control registers, including access-time registers. The configuration master should check each memory device and set all appropriate memory address registers. [0101]
  • One means to set up unique device ID numbers is to have each device to select a device ID in sequence and store the value in an internal device ID register. For example, a master can pass sequential device ID numbers through shift registers in each of a series of devices, or pass a token from device to device whereby the device with the token reads in device ID information from another line or lines. In a preferred embodiment, device ID numbers are assigned to devices according to their physical relationship, for instance, their order along the bus. [0102]
  • In a preferred embodiment of this invention, the device ID setting is accomplished using a pair of pins on each device, ResetIn and ResetOut. These pins handle normal logic signals and are used only during device ID configuration. On each rising edge of the clock, each device copies ResetIn (an input) into a four-stage reset shift register. The output of the reset shift register is connected to ResetOut, which in turn connects to ResetIn for the next sequentially connected device. Substantially all devices on the bus are thereby daisy-chained together. A first reset signal, for example, while ResetIn at a device is a logical 1, or when a selected bit of the reset shift register goes from zero to non-zero, causes the device to hard reset, for example by clearing all internal registers and resetting all state machines. A second reset signal, for example, the falling edge of ResetIn combined with changeable values on the external bus, causes that device to latch the contents of the external bus into the internal device ID register (Device[[0103] 0:7]).
  • To reset all devices on a bus, a master sets the ResetIn line of the first device to a “1” for long enough to ensure that all devices on the bus have been reset (4 cycles times the number of devices—note that the maximum number of devices on the preferred bus configuration is 256 (8 bits), so that 1024 cycles is always enough time to reset all devices.) Then ResetIn is dropped to “0” and the BusData lines are driven with the first followed by successive device ID numbers, changing after every 4 clock pulses. Successive devices set those device ID numbers into the corresponding device ID register as the falling edge of ResetIn propagates through the shift registers of the daisy-chained devices. FIG. 14 shows ResetIn at a first device going low while a master drives a first device ID onto the bus data lines BusData[[0104] 0:3]. The first device then latches in that first device ID. After four clock cycles, the master changes BusData[0:3] to the next device ID number and ResetOut at the first device goes low, which pulls ResetIn for the next daisy-chained device low, allowing the next device to latch in the next device ID number from BusData[0:3]. In the preferred embodiment, one master is assigned device ID 0 and it is the responsibility of that master to control the ResetIn line and to drive successive device ID numbers onto the bus at the appropriate times. In the preferred embodiment, each device Waits two clock cycles after ResetIn goes low before latching in a device ID number from BusData[0:3].
  • Persons skilled in the art recognize that longer device ID numbers could be distributed to devices by having each device read in multiple bytes from the bus and latch the values into the device ID register. Persons skilled in the art also recognize that there are alternative ways of getting device ID numbers to unique devices. For instance, a series of sequential numbers could be clocked along the ResetIn line and at a certain time each device could be instructed to latch the current reset shift register value into the device ID register. [0105]
  • The configuration master should choose and set an access time in each access-time register in each slave to a period sufficiently long to allow the slave to perform an actual, desired memory access. For example, for a normal DRAM access, this time must be longer than the row address strobe (RAS) access time. If this condition is not met, the slave may not deliver the correct data. The value stored in a slave access-time register is preferably one-half the number of bus cycles for which the slave device should wait before using the bus in response to a request. Thus an access time value of ‘1’ would indicate that the slave should not access the bus until at least two cycles after the last byte of the request packet has been received. The value of AccessReg[0106] 0 is preferably fixed at 8 (cycles) to facilitate access to control registers.
  • The bus architecture of this invention can include more than one master device. The reset or initialization sequence should also include a determination of whether there are multiple masters on the bus, and if so to assign unique master ID numbers to each. Persons skilled in the art will recognize that there are many ways of doing this. For instance, the master could poll each device to determine what type of device it is, for example, by reading a special register then, for each master device, write the next available master ID number into a special register. [0107]
  • ECC [0108]
  • Error detection and correction (“ECC”) methods well known in the art can be implemented in this system. ECC information typically is calculated for a block of data at the time that block of data is first written into memory. The data block usually has an integral binary size, e.g. 256 bits, and the ECC information uses significantly fewer bits. A potential problem arises in that each binary data block in prior art schemes typically is stored with the ECC bits appended, resulting in a block size that is not an integral binary power. [0109]
  • In a preferred embodiment of this invention, ECC information is stored separately from the corresponding data, which can then be stored in blocks having integral binary size. ECC information and corresponding data can be stored, for example, in separate DRAM devices. Data can be read without ECC using a single request packet, but to write or read error-corrected data requires two request packets, one for the data and a second for the corresponding ECC information. ECC information may not always be stored permanently and in some situations the ECC information may be available without sending a request packet or without a bus data block transfer. [0110]
  • In a preferred embodiment, a standard data block size can be selected for use with ECC, and the ECC method will determine the required number of bits of information in a corresponding ECC block. RAMs containing ECC information can be programmed to store an access time that is equal to: (1) the access time of the normal RAM (containing data) plus the time to access a standard data block (for corrected data) minus the time to send a request packet (6 bytes); or (2) the access time of a normal RAM minus the time to access a standard ECC block minus the time to send a request packet. To read a data block and the corresponding ECC block, the master simply issues a request for the data immediately followed by a request for the ECC block. The ECC RAM will wait for the selected access time then drive its data onto the bus right after (in case (1) above)) the data RAM has finished driving out the data block. Persons skilled in the art will recognize that the access time described in case (2) above can be used to drive ECC data before the data is driven onto the bus lines and will recognize that writing data can be done by analogy with the method described for a read. Persons skilled in the art will also recognize the adjustments that must be made in the bus-busy structure and the request packet arbitration methods of this invention in order to accommodate these paired ECC requests. [0111]
  • Since this system is quite flexible, the system designer can choose the size of the data blocks and the number of ECC bits using the memory devices of this invention. Note that the data stream on the bus can be interpreted in various ways. For instance the sequence can be 2[0112] n data bytes followed by 2m ECC bytes (or vice versa), or the sequence can be 2k iterations of 8 data bytes plus 1 ECC byte. Other information, such as information used by a directory-based cache coherence scheme, can also be managed this way. See, for example, Anant Agarwal, et al., “Scaleable Directory Schemes for Cache Consistency,” 15th International Symposium on Computer Architecture, June 1988, pp. 280-289. Those skilled in the art will recognize alternative methods of implementing ECC schemes that are within the teachings of this invention.
  • Low Power 3-D Packaging [0113]
  • Another major advantage of this invention is that it drastically reduces the memory system power consumption. Nearly all the power consumed by a prior art DRAM is dissipated in performing row access. By using a single row access in a single RAM to supply all the bits for a block request (compared to a row-access in each of multiple RAMs in conventional memory systems) the power per bit can be made very small. Since the power dissipated by memory devices using this invention is significantly reduced, the devices potentially can be placed much closer together than with conventional designs. [0114]
  • The bus architecture of this invention makes possible an innovative 3-D packaging technology. By using a narrow, multiplexed (time-shared) bus, the pin count for an arbitrarily large memory device can be kept quite small—on the order of 20 pins. Moreover, this pin count can be kept constant from one generation of DRAM density to the next. The low power dissipation allows each package to be smaller, with narrower pin pitches (spacing between the IC pins). With current surface mount technology supporting pin pitches as low as 20 mils, all off-device connections can be implemented on a single edge of the memory device. Semiconductor die useful in this Invention preferably have connections or pads along one edge of the die which can then be wired or otherwise connected to the package pins with wires having similar lengths. This geometry also allows for very short leads, preferably with an effective lead length of less than 4 mm. Furthermore, this invention uses only bused interconnections, i.e., each pad on each device is connected by the bus to the corresponding pad of each other device. [0115]
  • The use of a low pin count and an edge-connected bus permits a simple 3-D package, whereby the devices are stacked and the bus is connected along a single edge of the stack. The fact that all of the signals are bused is important for the implementation of a simple 3-D structure. Without this, the complexity of the “backplane” would be too difficult to make cost effectively with current technology. The individual devices in a stack of the present invention can be packed quite tightly because of the low power dissipated by the entire memory system, permitting the devices to be stacked bumper-to-bumper or top to bottom. Conventional plastic-injection molded small outline (SO) packages can be used with a pitch of about 2.5 mm (100 mils), but the ultimate limit would be the device die thickness, which is about an order of magnitude smaller, 0.2-0.5 mm using current wafer technology. [0116]
  • Bus Electrical Description [0117]
  • By using devices with very low power dissipation and close physical packing, the bus can be made quite short, which in turn allows for short propagation times and high data rates. The bus of a preferred embodiment of the present invention consists of a set of resistor-terminated controlled impedance transmission lines which can operate up to a data rate of 500 MHz (2 ns cycles). The characteristics of the transmission lines are strongly affected by the loading caused by the DRAMs (or other slaves) mounted on the bus. These devices add lumped capacitance to the lines which both lowers the impedance of the lines and decreases the transmission speed. In the loaded environment, the bus impedance is likely to be on the order of 25 ohms and the propagation velocity about c/4 (c=the speed of light) or 7.5 cm/ns. To operate at a 2 ns data rate, the transit time on the bus should preferably be kept under 1 ns, to leave 1 ns for the setup and hold time of the input receivers (described below) plus clock skew. Thus the bus lines must be kept quite short, under about 8 cm for maximum performance. Lower performance systems may have much longer lines, e.g. a 4 ns bus may have 24 cm lines (3 ns transit time, 1 ns setup and hold time). [0118]
  • In the preferred embodiment, the bus uses current source drivers. Each output must be able to sink 50 mA, which provides an output swing of about 500 mV or more. In the preferred embodiment of this invention, the bus is active low. The unasserted state (the high value) is preferably considered a logical zero, and the asserted value (low state) is therefore a logical 1. Those skilled in the art understand that the method of this invention can also be implemented using the opposite logical relation to voltage. The value of the unasserted state is set by the voltage on the termination resistors, and should be high enough to allow the outputs to act as current sources, while being as low as possible to reduce power dissipation. These constraints may yield a termination voltage about 2V above ground in the preferred implementation. Current source drivers cause the output voltage to be proportional to the sum of the sources driving the bus. [0119]
  • Referring to FIG. 7, although there is no stable condition where two devices drive the bus at the same time, conditions can arise because of propagation delay on the wires where one device, A [0120] 41, can start driving its part of the bus 44 while the bus is still being driven by another device, B 42 (already asserting a logical 1 on the bus). In a system using current drivers, when B 42 is driving the bus (before time 46), the value at points 44 and 45 is logical 1. If B 42 switches off at time 46 just when A 41 switches on, the additional drive by device A 41 causes the voltage at the output 44 of A 41 to briefly below the normal value. The voltage returns to its normal value at time 47 when the effect of device B 42 turning off is felt. The voltage at point 45 goes to logical 0 when device B 42 turns off, then drops at time 47 when the effect of device A 41 turning on is felt. Since the logical 1 driven by current from device A 41 is propagated irrespective of the previous value on the bus, the value on the bus is guaranteed to settle after one time of flight (t,) delay, that is, the time it takes a signal to propagate from one end of the bus to the other. If a voltage drive was used (as in ECL wired-ORing), a logical 1 on the bus (from device B 42 being previously driven) would prevent the transition put out by device A 41 being felt at the most remote part of the system, e.g., device 43, until the turnoff waveform from device B 42 reached device A 41 plus one time of flight delay, giving a worst case settling time of twice the time of flight delay.
  • Clocking [0121]
  • Clocking a high speed bus accurately without introducing error due to propagation delays can be implemented by having each device monitor two bus clock signals and then derive internally a device clock, the true system clock. The bus clock information can be sent on one or two lines to provide a mechanism for each bused device to generate an internal device clock with zero skew relative to all the other device clocks. Referring to FIG. 3, in the preferred implementation, a [0122] bus clock generator 50 at one end of the bus propagates an early bus clock signal in one direction along the bus, for example on line 53 from left to right, to the far end of the bus. The same clock signal then is passed through the direct connection shown to a second line 54, and returns as a late bus clock signal along the bus from the far end to the origin, propagating from right to left. A single bus clock line can be used if it is left unterminated at the far end of the bus, allowing the early bus clock signal to reflect back along the same line as a late bus clock signal.
  • FIG. 8[0123] b illustrates how each device 51, 52 receives each of the two bus clock signals at a different time (because of propagation delay along the wires), with constant midpoint in time between the two bus clocks along the bus. At each device 51, 52, the rising edge 55 of Clock1 53 is followed by the rising edge 56 of Clock2 54. Similarly, the falling edge 57 of Clock1 53 is followed by the falling edge 58 of Clock2 54. This waveform relationship is observed at all other devices along the bus. Devices which are closer to the clock generator have a greater separation between Clock1 and Clock2 relative to devices farther from the generator because of the longer time required for each clock pulse to traverse the bus and return along line 54, but the midpoint in time 59, 60 between corresponding rising or falling edges is fixed because, for any given device, the length of each clock line between the far end of the bus and that device is equal. Each device must sample the two bus clocks and generate its own internal device clock at the midpoint of the two.
  • Clock distribution problems can be further reduced by using a bus clock and device clock rate equal to the bus cycle data rate divided by two, that is, the bus clock period is twice the bus cycle period. Thus a 500 MHz bus preferably uses a 250 MHz clock rate. This reduction in frequency provides two benefits. First it makes all signals on the bus have the same worst case data rates—data on a 500 MHz bus can only change every 2 ns. Second, clocking at half the bus cycle data rate makes the labeling of the odd and even bus cycles trivial, for example, by defining even cycles to be those when the internal device clock is 0 and odd cycles when the internal device clock is 1. [0124]
  • Multiple Buses [0125]
  • The limitation on bus length described above restricts the total number of devices that can be placed on a single bus. Using 2.5 mm spacing between devices, a single 8 cm bus will hold about 32 devices. Persons skilled in the art will recognize certain applications of the present invention wherein the overall data rate on the bus is adequate but memory or processing requirements necessitate a much larger number of devices (many more than 32). Larger systems can easily be built using the teachings of this invention by using one or more memory subsystems, designated primary bus units, each of which consists of two or more devices, typically 32 or close to the maximum allowed by bus design requirements, connected to a transceiver device. [0126]
  • Referring to FIG. 9, each primary bus unit can be mounted on a [0127] single circuit board 66, sometimes called a memory stick. Each transceiver device 19 in turn connects to a transceiver bus 65, similar or identical in electrical and other respects to the primary bus 18 described at length above. In a preferred implementation, all masters are situated on the transceiver bus so there are no transceiver delays between masters and all memory devices are on primary bus units so that all memory accesses experience an equivalent transceiver delay, but persons skilled in the art will recognize how to implement systems which have masters on more than one bus unit and memory devices on the transceiver bus as well as on primary bus units. In general, each teaching of this invention which refers to a memory device can be practiced using a transceiver device and one or more memory devices on an attached primary bus unit. Other devices, generically referred to as peripheral devices, including disk controllers, video controllers or I/O devices can also be attached to either the transceiver bus or a primary bus unit, as desired. Persons skilled in the art will recognize how to use a single primary bus unit or multiple primary bus units as needed with a transceiver bus in certain system designs.
  • The transceivers are quite simple in function. They detect request packets on the transceiver bus and transmit them to their primary bus unit. If the request packet calls for a write to a device on a transceiver's primary bus unit, that transceiver keeps track of the access time and block size and forwards all data from the transceiver bus to the primary bus unit during that time. The transceivers also watch their primary bus unit, forwarding any data that occurs there to the transceiver bus. The high speed of the buses means that the transceivers will need to be pipelined, and will require an additional one or two cycle delay for data to pass through the transceiver in either direction. Access times stored in masters on the transceiver bus must be increased to account for transceiver delay but access times stored in slaves on a primary bus unit should not be modified. [0128]
  • Persons skilled in the art will recognize that a more sophisticated transceiver can control transmissions to and from primary bus units. An additional control line, TrncvrRW can be bused to all devices on the transceiver bus, using that line in conjunction with the AddrValid line to indicate to all devices on the transceiver bus that the information on the data lines is: 1) a request packet, 2) valid data to a slave, 3) valid data from a slave, or 4) invalid data (or idle bus). Using this control line obviates the need for the transceivers to keep track of when data needs to be forwarded from its primary bus to the transceiver bus—all transceivers send all data from their primary bus to the transceiver bus whenever the control signal indicates condition 2) above. In a preferred implementation of this invention, if AddrValid and TrncvrRW are both low, there is no bus activity and the transceivers should remain in an idle state. A controller sending a request packet will drive AddrValid high, indicating to all devices on the transceiver bus that a request packet is being sent which each transceiver should forward to its primary bus unit. Each controller seeking to trite to a slave should drive both AddrValid and TrncvrRW high, indicating valid data for a slave is present on the data lines. Each transceiver device will then transmit all data from the transceiver bus lines to each primary bus unit. Any controller expecting to receive information from a slave should also drive the TrncvrRW line high, but not drive AddrValid, thereby indicating to each transceiver to transmit any data coming from any slave on its primary local bus to the transceiver bus. A still more sophisticated transceiver would recognize signals addressed to or coming from its primary bus unit and transmit signals only at requested times. [0129]
  • An example of the physical mounting of the transceivers is shown in FIG. 9. One important feature of this physical arrangement is to integrate the bus of each [0130] transceiver 19 with the original bus of DRAMs or other devices 15, 16, 17 on the primary bus unit 66. The transceivers 19 have pins on two sides, and are preferably mounted flat on the primary bus unit with a first set of pins connected to primary bus 16. A second set of transceiver pins 20, preferably orthogonal to the first set of pins, are oriented to allow the transceiver 19 to be attached to the transceiver bus 65 in much the same way as the DRAMs were attached to the primary bus unit. The transceiver bus can be generally planar and in a different plane, preferably orthogonal to the plane of each primary bus unit. The transceiver bus can also be generally circular with primary bus units mounted perpendicular and tangential to the transceiver bus.
  • Using this two level scheme allows one to easily build a system that contains over 500 slaves (16 buses of 32 DRAMs each). Persons skilled in the art can modify the device ID scheme described above to accommodate more than 256 devices, for example by using a longer device ID or by using additional registers to hold some of the device ID. This scheme can be extended in yet a third dimension to make a second-order transceiver bus, connecting multiple transceiver buses by aligning transceiver bus units parallel to and on top of each other and busing corresponding signal lines through a suitable transceiver. Using such a second-order transceiver bus, one could connect many thousands of slave devices into what is effectively a single bus. [0131]
  • Device Interface [0132]
  • The device interface to the high-speed bus can be divided into three main parts. The first part is the electrical interface. This part includes the input receivers, bus drivers and clock generation circuitry. The second part contains the address comparison circuitry and timing registers. This part takes the input request packet and determines if the request in for this device, and if it is, starts the internal access and delivers the data to the pins at the correct time. The final part, specifically for memory devices such as DRAMs, is the DRAM column access path. This part needs to provide bandwidth into and out of the DRAM sense amps greater than the bandwidth provided by conventional DRAMS. The implementation of the electrical interface and DRAM column access path are described in more detail in the following sections. Persons skilled in the art recognize how to modify prior-art address comparison circuitry and prior-art register circuitry in order to practice the present invention. [0133]
  • Electrical Interface—Input/Output Circuitry [0134]
  • A block diagram of the preferred input/output circuit for address/data/control lines is shown in FIG. 10. This circuitry is particularly well-suited for use in DRAM devices but it can be used or modified by one skilled in the art for use in other devices connected to the bus of this invention. It consists of a set of [0135] input receivers 71, 72 and output driver 76 connected to input/output line 69 and pad 75 and circuitry to use the internal clock 73 and internal clock complement 74 to drive the input interface. The clocked input receivers take advantage of the synchronous nature of the bus. To further reduce the performance requirements for device input receivers, each device pin, and thus each bus line, is connected to two clocked receivers, one to sample the even cycle inputs, the other to sample the odd cycle inputs. By thus de-multiplexing the input 70 at the pin, each clocked amplifier is given a full 2 ns cycle to amplify the bus low-voltage-swing signal into a full value CMOS logic signal. Persons skilled in the art will recognize that additional clocked input receivers can be used within the teachings of this invention. For example, four input receivers could be connected to each device pin and clocked by a modified internal device clock to transfer sequential bits from the bus to internal device circuits, allowing still higher external bus speeds or still longer settling times to amplify the bus low-voltage-swing signal into a full value CMOS logic signal.
  • The output drivers are quite simple, and consist of a single [0136] RHOS pulldown transistor 76. This transistor sized so that under worst case conditions it can still sink the 50 mA required by the bus. For 0.8 micron CMOS technology, the transistor will need to be about 200 microns long. Overall bus performance can be improved by using feedback techniques to control output transistor current so that the current through the device is roughly 50 mA under all operating conditions, although this is not absolutely necessary for proper bus operation. An example of one of many methods known to persons skilled in the art for using feedback techniques to control current is described in Bans Schumacher, et al., “CMOS Subnanosecond True-ECL Output Buffer,” J. Solid State Circuits, Vol. 25 (1), pp. 150-154 (February 1990). Controlling this current improves performance and reduces power dissipation. This output driver which can be operated at 500 MHz, can in turn be controlled by a suitable multiplexer with two or more (preferably four) inputs connected to other internal chip circuitry, all of which can be designed according to well known prior art.
  • The input receivers of every slave must be able to operate during every cycle to determine whether the signal on the bus is a valid request packet. This requirement leads to a number of constraints on the input circuitry. In addition to requiring small acquisition and resolution delays, the circuits must take little or no DC power, little AC power and inject very little current back into the input or reference lines. The standard clocked DRAM sense amp shown in FIG. 11 satisfies all these requirements except the need for low input currents. When this sense amp goes from sense to sample, the capacitance of the [0137] internal nodes 83 and 84 in FIG. 11 is discharged through the reference line 68 and input 69, respectively. This current in small, but the sum of such currents from all the inputs into the reference lines summed over all devices can be reasonably large.
  • The fact that the sign of the current depends upon on the previous received data makes matters worse. One way to solve this problem is to divide the sample period into two phases. During the first phase, the inputs are shorted to a buffered version of the reference level (which may have an offset). During the second phase, the inputs are connected to the true inputs. This scheme does not remove the input current completely, since the input must still charge [0138] nodes 83 and 84 from the reference value to the current input value, but it does reduce the total charge required by about a factor of 10 (requiring only a 0.25V change rather than a 2.5V change). Persons skilled in the art will recognize that many other methods can be used to provide a clocked amplifier that will operate on very low input currents.
  • One important part of the input/output circuitry generates an internal device clock based on early and late bus clocks. Controlling clock skew (the difference in clock timing between devices) is important in a system running with 2 ns cycles, thus the internal device clock is generated so the input sampler and the output driver operate as close in time as possible to midway between the two bus clocks. [0139]
  • A block diagram of the internal device clock generating circuit is shown in FIG. 12 and the corresponding timing diagram in FIG. 13. The basic idea behind this circuit is relatively simple. A [0140] DC amplifier 102 is used to convert the small-swing bus clock into a full-swing CMOS signal. This signal is then fed into a variable delay line 103. The output of delay line 103 feeds three additional delay lines: 104 having a fixed delay; 105 having the same fixed delay plus a second variable delay; and 106 having the same fixed delay plus one half of the second variable delay. The outputs 107, 108 of the delay lines 104 and 105 drive clocked input receivers 101 and 111 connected to early and late bus clock inputs 100 and 110, respectively. These input receivers 101 and 111 have the same design as the receivers described above and shown in FIG. 11. Variable delay lines 103 and 105 are adjusted via feedback lines 116, 115 so that input receivers 101 and 111 sample the bus clocks just as they transition. Delay lines 103 and 105 are adjusted so that the falling edge 120 of output 107 precedes the falling edge 121 of the early bus clock, Clock1 53, by an amount of time 128 equal to the delay in input sampler 101. Delay line 108 is adjusted in the same way so that falling edge 122 precedes the falling edge 123 of late bus clock, Clock2 54, by the delay 128 in input sampler 111.
  • Since the [0141] outputs 107 and 108 are synchronized with the two bus clocks and the output 73 of the last delay line 106 is between outputs 107 and 108, that is, output 73 follow, output 107 by the same amount of time 129 that output 73 precedes output 108, output 73 provides an internal device clock midway between the bus clocks. The falling edge 124 of internal device clock 73 precedes the time of actual input sampling 125 by one sampler delay. Note that this circuit organization automatically balances the delay in substantially all device input receivers 71 and 72 (FIG. 10), since outputs 107 and 108 are adjusted so the bus clocks are sampled by input receivers 101 and 111 just as the bus clocks transition.
  • In the preferred embodiment, two sets of these delay lines are used, one to generate the true value of the [0142] internal device clock 73, and the other to generate the complement 74 without adding any inverter delay. The dual circuit allows generation of truly complementary clocks, with extremely small skew. The complement internal device clock is used to clock the ‘even’ input receivers to sample at time 127, while the true internal device clock is used to clock the ‘odd’ input receivers to sample at time 125. The true and complement internal device clocks are also used to select which data is driven to the output drivers. The gate delay between the internal device clock and output circuits driving the bus is slightly greater than the corresponding delay for the input circuits, which means that the new data always will be driven on the bus slightly after the old data as bee sampled.
  • DRAM Column Access Modification [0143]
  • A block diagram of a conventional 4 [0144] MBit DRAM 130 is shown in FIG. 15. The DRAM memory array is divided into a number of subarrays 150-157, for example, 8. Each subarray is divided into arrays 148, 149 of memory cells. Row address selection is performed by decoders 146. A column decoder 147A, 147B, including column sense amps on either side of the decoder, runs through the core of each subarray. These column sense amps can be set to precharge or latch the most-recently stored value, as described in detail above. Internal I/O lines connect each set of sense-amps, as gated by corresponding column decoders, to input and output circuitry connected ultimately to the device pins. These internal I/O lines are used to drive the data from the selected bit lines to the data pins (some of pins 131-145), or to take the data from the pins and write the selected bit lines. Such a column access path organized by prior art constraints does not have sufficient bandwidth to interface with a high speed bus. The method of this invention does not require changing the overall method used for column access, but does change implementation details. Many of these details have been implemented selectively in certain fast memory devices, but never in conjunction with the bus architecture of this invention.
  • Running the internal I/O lines in the conventional way at high bus cycle rates is not possible. In the preferred method, several (preferably 4) bytes are read or written during each cycle and the column access path is modified to run at a lower rate (the inverse of the number of bytes accessed per cycle, preferably ¼ of the bus cycle rate). Three different techniques are used to provide the additional internal I/O lines required and to supply data to memory cells at this rate. First, the number of I/O bit lines in each subarray running through the [0145] column decoder 147 is increased, for example, to 16, eight for each of the two columns of column sense amps and the column decoder selects one set of columns from the “top” half 148 of subarray 150 and one set of columns from the “bottom” half 149 during each cycle, where the column decoder selects one column sense amp per I/O bit line. Second, each column I/O line is divided into two halves, carrying data independently over separate internal I/O lines from the left half 147A and right half 147B of each subarray (dividing each subarray into quadrants) and the column decoder selects sense amps from each right and left half of the subarray, doubling the number of bits available at each cycle. Thus each column decode selection turns on a column sense amps, where n equals four (top left and right, bottom left and right quadrants) times the number of I/O lines in the bus to each subarray quadrant (B lines each x 4=32 lines in the preferred implementation). Finally, during each RAS cycle, two different subarrays, e.g. 157 and 153, are accessed. This doubles again the available number of I/O lines containing data. Taken together, these changes increase the internal I/O bandwidth by at least a factor of 8. Your internal buses are used to route these internal I/O lines. Increasing the number of I/O lines and then splitting them in the middle greatly reduces the capacitance of each internal I/O line which in turn reduces the column access time, increasing the column access bandwidth even further.
  • The multiple, gated input receivers described above allow high speed input from the device pins onto the internal I/O lines and ultimately into memory. The multiplexed output driver described above is used to keep up with the data flow available using these techniques. Control means are provided to select whether information at the device pins should be treated as an address, and therefore to be decoded, or input or output data to be driven onto or read from the internal I/O lines. [0146]
  • Each subarray can access 32 bits per cycle, 16 bits from the left subarray and 16 from the right subarray. With 8 I/O lines per sense-amplifier column and accessing two subarrays at a time, the DRAM can provide 64 bits per cycle. This extra I/O bandwidth is not needed for reads (and is probably not used), but may be needed for writes. Availability of write bandwidth in a more difficult problem than read bandwidth because over-writing a value in a sense-amplifier may be a slow operation, depending on how the sense amplifier is connected to the bit line. The extra set of internal I/O lines provides some bandwidth margin for write operations. [0147]
  • Persons skilled in the art will recognize tat my variations of the teachings of this invention can be practiced that still fall within the claims of this invention which follow. [0148]

Claims (147)

What is claimed is:
1. A memory subsystem comprising
two memory devices connected in parallel to a bus,
said bus including a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices,
said control information including device-select information,
said bus containing substantially fewer bus lines than the number of bits in a single address, and
said bus carrying device-select information without the need for separate device-select lines connected directly to individual memory devices.
2. The memory subsystem of claim 1 wherein said bus contains at least 8 bus lines adapted to carry at least 16 address bits and at least 8 data bits.
3. The memory subsystem of claim 1 wherein said bus also includes parallel lines for clock and power.
4. A system comprising
a memory subsystem of claim 1 wherein each bus of said memory subsystem is connected to its own transceiver device,
a transceiver bus connecting said transceiver devices, and
a means for transferring information between each of said buses of said memory subsystems and said transceiver bus, whereby memory subsystems may be integrated into a larger system having more memory than an individual memory subsystem.
5. The system of claim 4 having a plurality of memory subsystems.
6. The system of claim 4 further comprising a master device connected to said transceiver bus.
7. The system of claim 6 wherein said master device is selected from the group consisting of a central processing unit, a floating point unit and a direct memory access unit.
8. The system of claim 4 further comprising a peripheral device connected to the transceiver bust said peripheral device adapted for connection to other devices not on the bus.
9. The system of claim 8 wherein said peripheral device is selected from the group consisting of an I/O interface sort, a video controller and a disk controller.
10. The system of claim 5 wherein said transceiver bus is in a different plane than the plane of the bus of each of said memory subsystems.
11. The system of claim 5 wherein the bus of each memory subsystem lies substantially in a subsystem bus plane and said transceiver bus lies substantially in a plane orthogonal to said subsystem bus plane.
12. The system of claim 4 having at least two transceiver buses, each transceiver bus having a plurality of memory subsystem buses connected through a first transceiver to said transceiver bus,
each of said transceiver buses being further connected to a second transceiver adapted to interface to a second-order transceiver bus, whereby each transceiver bus is connected through said second transceiver to form a second-order transceiver bus unit.
13. A semiconductor subsystem bus for interconnecting semiconductor devices comprising
a plurality of semiconductor devices connected in parallel to a bus, at least one of said semiconductor devices being a memory device or a transceiver device which in turn is connected to a memory subsystem,
said bus including a plurality of bus lines for carrying substantially all address, data and control information needed by said semiconductor devices,
said control information including semiconductor device-select information,
said bus containing substantially fewer bus lines than the number of bits in a single address, and
said bus carrying device-select information without the need for separate device-select lines connected directly to individual semiconductor devices, and
at least one modifiable register in each of the semiconductor devices on said bus, said modifiable registers being accessible from said bus, whereby the subsystem can be configured using signals transmitted on said bus.
14. The semiconductor subsystem bus of claim 13 wherein one type of modifiable register is an access-time register designed to store a time delay after which a device may take some specified action on said bus.
15. The semiconductor subsystem bus of claim 13 further comprising a semiconductor device having at least two access-time registers and
one of said access-time registers is permanently programmed to contain a fixed value and at least one of said access-time registers can be modified by information carried on said bus.
16. The semiconductor subsystem bus of claim 13 further comprising a memory device having at least one discrete memory section and also having a modifiable address register adapted to store memory address information which corresponds to each said discrete memory section.
17. The semiconductor subsystem bus of claim 16 wherein said memory address information comprises a pointer to said discrete memory section.
18. The semiconductor subsystem bus of claim 16 wherein said discrete memory section has a top and a bottom and said memory address information comprises pointers to said top and said bottom.
19. The semiconductor subsystem bus of claim 16 wherein said memory address information comprises
a pointer to said discrete memory section and
a range value indicating the size of said discrete memory section.
20. The semiconductor subsystem bus of claim 16 wherein said address registers of each of said discrete memory sections of each of said memory devices connected to said bus are set to contain memory address information that is different for each discrete memory section and such that the highest memory address in each discrete memory section is one less than the lowest memory address in another discrete memory section,
whereby memory may be organized into one or a small number of contiguous memory blocks.
21. The semiconductor subsystem bus of claim 16 further comprising a means for testing each of said discrete memory sections of each of said memory devices for proper function, and
for each non-functional discrete memory section, a means for setting at least one address register which corresponds to said discrete memory section to indicate that said discrete memory section is non-functional,
for each functional discrete memory section, a means for setting at least one address register which corresponds to said discrete memory section to contain such corresponding address information.
22. The semiconductor subsystem bus of claim 21 wherein said address registers corresponding to said discrete memory sections are set to provide one contiguous memory block within the subsystem.
23. The semiconductor subsystem bus of claim 13 wherein one of said modifiable registers is a device identification register which can be modified to contain a value unique to that semiconductor device.
24. The semiconductor subsystem bus of claim 23 wherein said device identification register is set to contain a unique value which is a function of the physical position of that semiconductor device either along said bus or in relationship to other semiconductor devices or said bus.
25. A bus subsystem comprising
two semiconductor devices connected in parallel to a bus, wherein one of said semiconductor devices is a master device,
said master device including a means for initiating bus transactions,
said bus including a plurality of bus lines for carrying substantially all address, data and control information needed by said devices,
said control information including device-select information,
said bus containing substantially fewer lines than the number of bits in a single address, and
said bus carrying device-select information without the need for separate device-select lines connected directly to individual devices on said bus, whereby said master device initiates bus transactions which transfer information between said semiconductor devices on said bus.
26. The bus subsystem of claim 25 wherein one of said semiconductor devices is a memory device connected to said bus, said memory device having at least one discrete memory section and also having a modifiable address register adapted to store memory address information which corresponds to each said discrete memory section.
27. The bus subsystem of claim 26 wherein one of said semiconductor devices comprises a transceiver device connected in parallel to said bus and connected in parallel to a memory device on a bus other than said bus.
28. The bus subsystem of claim 26 further including a means for said master device to request said memory device to prepare for a bus transaction by sending a request packet along said bus, said memory device and said master device each having a device-internal means to prepare to begin said bus transaction during a device-internal phase and further having a bus access means to effect said bus transaction during a bus access phase, said request packet including
a sequence of bytes containing address and control information,
said control information including information about the requested bus transaction and about the access time, which corresponds to a number of bus cycles, which needs to intervene before beginning said bus-access phase, and
said address information pointing to at least one memory location within one of said discrete memory sections of said memory device.
29. The bus subsystem of claim 28 wherein said memory device includes a means to read said control information and initiate said device-internal means at a time so as to complete said device-internal phase within said access time and begin said bus access phase after said number of bus cycles.
30. The bus subsystem of claim 28 wherein said control information comprises an op code.
31. The bus subsystem of claim 30 wherein said memory device includes sense amplifiers adapted to hold a bit of information or to precharge after a selected time and a means to transfer a data block during a data block transfer either reading data from said memory device or writing data into said memory device, and
wherein said op code instructs said memory device to activate a response means, said response means including a means to
initiate a data block transfer,
select the size of said data block,
select the time to initiate said data block transfer,
access a control register, including reading from or writing to said control register,
precharge said sense amplifiers after each of said data block transfers is complete,
hold a bit of information in each of said sense amplifiers after each of said data block transfers is complete, or
select normal or page-mode access.
32. The bus subsystem of claim 31 wherein said data block transfer comprises a read from or a write to memory within a single memory device.
33. The bus subsystem of claim 28 further comprising a means for said master device to send control information to a specific one of said semiconductor devices on said bus by including in said request packet a device identification number unique to said semiconductor device.
34. The bus subsystem of claim 28 further comprising a means for said master device to send control information to a selected one of said discrete memory portions by including in said request packet a specific memory address.
35. The bus subsystem of claim 28 further comprising a means for said master device to send control information to substantially all semiconductor devices on said bus by including in said request packet a special device identification number which is recognized by said semiconductor devices.
36. The bus subsystem of claim 28 wherein said control information specifies directly or indirectly the number of bus cycles for said master device and said memory device to wait before beginning said bus access phase.
37. The bus subsystem of claim 36 wherein, for a data block transfer, said master device and said memory device use the same access time and same data block size regardless of whether said data block transfer is a read or write operation.
38. The bus subsystem of claim 28 wherein said control information further includes a block-size value that encodes and specifies the size of the block of data to be transferred,
39. The bus subsystem of claim 38 wherein said block-size value is encoded as a linear value for relatively small block sizes values and is encoded as a logarithmic value for relatively larger block sizes.
40. The bus subsystem of claim 38 wherein said block-size value is encoded using four bits, and where the encoded value is
Encoded Value Block Size (Bytes) 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 16 10 32 11 64 12 128 13 256 14 512 15 1024
41. The bus subsystem of claim 26 wherein said memory device is a DRAM device containing
a plurality of sense amplifiers,
a means to hold said sense amplifiers in an unmodified state after a read or write operation, leaving the device in page mode,
a means to precharge said sense amplifiers and
a means for selecting whether to precharge said sense amplifiers or to hold said sense amplifiers in an unmodified state.
42. The bus subsystem of claim 28 wherein said request packet comprises an even number of bytes.
43. The bus subsystem of claim 28 further including a means for generating and controlling a plurality of bus cycles, during which said bus carries said address, data and control information, and wherein alternate said bus cycles are designated odd cycles and even cycles, respectively, and wherein said request packet begins only on an even cycle.
44. The bus subsystem of claim 28 further including a means for generating ECC information corresponding to a block of data and a means for using said ECC information to correct errors in storing or reading said block of data, wherein said ECC information may be stored separately from said block of data.
45. The bus subsystem of claim 44 further comprising at least two of said memory devices wherein said ECC information and said corresponding block of data are stored in a first and a second said memory device, respectively, and said master device includes a means to write or read said block of data with error correction by sending separate ones of said request packets for said ECC information and for said corresponding block of data.
46. A bus subsystem comprising
a memory device and a master device connected in parallel on a bus,
a means for said master device to send a request packet and initiate a bus transaction and
a means for said master device to keep track of current and pending bus transactions,
said bus including a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices,
said bus containing substantially fewer lines than the number of bits in a single address, and said bus carrying device-select information without the need for separate device-select lines connected directly to individual devices on said bus, whereby said master device initiates bus transactions which transfer information between devices on said bus and collisions on said bus are avoided because said master device avoids initiating bus transactions which would conflict with current or pending bus transactions.
47. The bus subsystem of claim 46 having at least two of said master devices and including
a collision detecting means whereby a first said master device sending a first said request packet can detect a second said master device sending one of said colliding request packets, where one of said said colliding request packet may be sent simultaneous with the initial sending of or overlapping the sending of said first request packet, and
an arbitration means whereby said first and said second master devices select a priority order in which each of said master devices will be allowed to access said bus sequentially.
48. The bus subsystem of claim 47 wherein each of said master devices has a master ID number and each of said request packets includes a master ID position which is a predetermined number of bits in a predetermined position in said request packet, and wherein said collision detection means comprises
a means included in each master device for sending a request packet including said master ID number of said master device in said master ID position of said request packet and
a means to detect a collision and invoke said arbitration means if any master device detects any other master ID number in said master ID position.
49. The bus subsystem of claim 47 wherein each of said master devices includes
a means for sending a request packet,
a means for driving a selected bus line or lines during at least one selected bus cycle while said request packet.-is being sent,
a means for monitoring said selected bus line or lines to see if a said master device is sending a colliding request packet and
a means for informing all other master devices that a collision has occurred and for invoking said arbitration means.
50. The bus subsystem of claim 47 wherein each of said master devices includes
a means, when sending a request packet, to drive a selected bus line or lines with a certain current during at least one selected bus cycle,
a means for monitoring said selected bus line or lines for a greater than normal current to see if another master device is driving that line or lines,
a means for detecting said greater than normal current, and
a means for informing all said master devices that a collision has occurred and for invoking said arbitration means.
51. The bus subsystem of claim 47 wherein said arbitration means comprises
a means for initiating an arbitration cycle,
a means for allocating a single bus line to each master device during at least one selected bus cycle relative to the start of said arbitration cycle,
a means for allocating each master device to a single bus line during one of said selected bus cycles if there are more master devices than available bus lines,
a means for each of said master devices which sent a colliding request packet to drive said bus line allocated to said master device during said selected bus cycle, and
a means in at least one of said master devices for storing information about which master devices sent a colliding request packet,
whereby said master devices can monitor selected bus lines during said arbitration cycle and identify each said master device which sent a colliding request packet.
52. The bus subsystem of claim 47 wherein said arbitration means comprises
a means included in a first one of said master devices which sent colliding request packets for identifying each of said master devices which sent colliding request packets,
a means for assigning a priority to each said master device which sent a colliding request-packet, and
a means for allowing each said master device which sent a colliding request packet to access the bus sequentially according to that priority.
53. The bus subsystem of claim 52 wherein said priority is based on the physical location of each of said master devices.
54. The bus subsystem of claim 52 wherein said priority is based on said master ID number of said master devices.
55. The bus subsystem of claim 52 wherein each of said master devices includes a means, when sending a colliding request packet, for deciding which master device can send the next request packet in what order or at what time, whereby no master device may send a new request packet until responses to each pending request packet have been completed or scheduled.
56. A bus subsystem comprising
a plurality of semiconductor devices connected in parallel to a bus,
said bus including a plurality of bus lines for carrying substantially all address, data and control information needed by said semiconductor devices,
said control information including device-select information,
said bus containing substantially fewer lines than the number of bits in a single address, said bus carrying said device-select information without the need for separate device-select lines connected directly to individual semiconductor devices,
said semiconductor devices including a reset means having an input and an output, the output of the reset means of one semiconductor device being connected to the input of the reset means of the next semiconductor device in series.
57. The bus subsystem of claim 56 further including system reset means comprising
a means for generating a first and a second reset signal,
a means for passing said first reset signal to a first of said semiconductor devices and then to subsequent ones of said semiconductor devices in series and
a means for passing a second reset signal to said first semiconductor device and then to said subsequent semiconductor devices in series,
said bus subsystem including one of said semiconductor devices containing
a device identification register adapted to contain a number unique to said semiconductor device within said bus subsystem,
a device identification register setting means, and
a device reset means for resetting said semiconductor device to some desired, known reset state in response to said first reset signal and for setting said device identification register in response to said second reset signal,
whereby said bus subsystem can be reset to a known reset state with a unique device identification value in said device identification register of each of said semiconductor devices.
58. The bus subsystem of claim 57 wherein said desired, known reset state is where all registers in the semiconductor device are cleared and the state machines are reset.
59. The bus subsystem of claim 57 wherein said device identification register setting means comprises
a means for detecting said second reset signal,
a means for reading a device identification number from said bus lines at a specific time relative to said second reset signal and
a means for storing said device identification number in said device identification register of said semiconductor device.
60. The bus subsystem of claim 57 wherein said second reset signal comprises multiple pulse sequences and wherein said device identification setting means includes
a means for interpreting said pulse sequences as a device identification number and
a means for storing said device identification number in said device identification register of said semiconductor device.
61. The bus subsystem of claim 57 wherein said device reset means comprises an A-stage shift register capable of storing n-bit values, wherein said device reset means interprets a specific value in said shift register as said first reset signal and interprets a specific value in said shift register as said second reset signal.
62. The bus subsystem of claim 57 wherein one of said semiconductor devices is a master device, said master device including a means for generating said first and said second reset signals.
63. The bus subsystem of claim 57 wherein one of said semiconductor devices is a master device, said master device including
a master ID register,
a means for assigning a master ID number to said master device and
a means for storing said master ID number in said master ID register.
64. The bus subsystem of claim 63 further comprising a second one of said master devices, and a means for a first one of said master devices to assign a master ID number to substantially all other said master devices, whereby said first master device assigns one of said master ID numbers to each of said master devices on said bus subsystem and each said master device stores said assigned master ID number in said master ID register.
65. The bus subsystem of claim 57 wherein one of said semiconductor devices includes a device-type register adapted to contain an identifier characteristic of that type of semiconductor device, and one or more modifiable registers, at least one of which is an access-time register adapted for storing access times.
66. The bus subsystem of claim 65 wherein one of said semiconductor devices is a master device having
a means for selecting a semiconductor device,
a means for reading said device-type register of said selected semiconductor device,
a means for determining the device type of said selected semiconductor device,
a means for determining access-time values appropriate for said selected semiconductor device and for storing said access-time values in said access-time registers of said selected semiconductor device, and
a means for selecting and storing other values appropriate for said selected semiconductor device in corresponding registers of said selected semiconductor device,
whereby said master device can select a semiconductor device, determine what type it is, and set said access-time and other registers to contain appropriate values.
67. The bus subsystem of claim 66 further comprising a memory device having at least one discrete memory section and at least one modifiable address register adapted to store memory address information which corresponds to each of said discrete memory sections, and
said master device further comprising a means for selecting and testing each of said discrete memory sections and a means for storing address information in said address registers corresponding to each of said discrete memory sections, whereby said master device can test all said discrete memory sections and assign unique address values thereto.
68. A bus subsystem comprising
two semiconductor devices connected in parallel to a bus, one of said semiconductor devices being a master device,
said bus including a plurality of bus data lines for carrying substantially all address, data and control information needed by said semiconductor devices,
said control information including device-select information,
said bus containing substantially fewer of said bus data lines than the number of bits in a single address, and
said bus carrying device-select information without the need for separate device-select lines connected directly to individual semiconductor devices,
wherein all of said bus data lines are terminated transmission lines and all of said address, data and control information is carried on said bus data lines as a sequential series of bits in the form of low-voltage-swing signals.
69. The bus subsystem of claim 68 further comprising a semiconductor device including a current-mode driver connected to drive one of said bus data lines.
70. The bus subsystem of claim 69 further comprising a semiconductor device having a means to measure the voltage of said low-voltage-swing signals on a selected one of said bus data lines, whereby said semiconductor device can determine whether zero, one, or more than one of said current-mode drivers are driving said selected bus data line.
71. The bus subsystem of claim 70 further comprising a semiconductor device having
a plurality of input receivers connected to one of said bus data lines, and
a selection means for selecting said input receivers one by one to sense and store, one at a time, the bits of said sequential series of bits.
72. The bus subsystem of claim 70 further comprising a semiconductor device having two input receivers connected to one of said bus data lines.
73. A bus subsystem comprising
two semiconductor devices connected in parallel to a bus having a first and a second end, said bus including a bus clock line, said bus clock line having first and second ends corresponding to said first and second ends of said bus, respectively,
a clock generator connected to said first end of said bus clock line to generate early bus clock signals with a normal rise time, and
signal return means at said second end of said bus clock line to return said early bus clock signals to said first end of said bus as corresponding late bus clock signals,
whereby each of said early bus clock signals will propagate from said clock generator along said clock line starting from said first end to said second end of said bus and then return at a later time to said first end of said bus as a corresponding late bus clock signal, whereby each semiconductor device on said bus can detect said early bus clock signals and said corresponding late bus clock signals.
74. The bus subsystem of claim 73 further comprising a first and a second said bus clock line having first and second ends at said first and said second ends of said bus, respectively, wherein said signal return means directly connects said second ends of said first and said second bus clock lines whereby each of said early bus clock signals will propagate from said clock generator at said first end of said bus along said first bus clock line to said second end of said bus and then return on said second bus clock line to said first end of said bus as one of said corresponding late bus clock signals.
75. The bus subsystem of claim 73 wherein said signal return means comprises said first bus clock line without a line terminator at said second end thereof whereby each of said early bus clock signals reaching said second end of said first bus clock line will be reflected back along said first bus clock line as said corresponding late bus clock signals.
76. The bus subsystem of claim 73 further comprising
a means for operating said bus in bus cycles timed to have a certain bus cycle frequency and a corresponding bus cycle period and
a means for operating said clock generator with a period of twice the bus cycle period.
77. The bus subsystem of claim 76 wherein said bus cycle frequency is greater than approximately 50 MHz and less than or equal to approximately 500 MHz.
78. The bus subsystem of claim 73 further including a semiconductor device having an internal device clock generating means to derive the midpoint time between said early and corresponding late bus clock signals and to generate an internal device clock synchronized to said midpoint time.
79. The bus subsystem of claim 73 further including a semiconductor device having a low-skew clock generator circuit comprising
a first delay line having an input, an output and a basic delay and means for synchronizing the output of said first delay line with said early bus clock signal,
a second delay line having said basic delay plus a variable delay, said second delay line having an output and a means for synchronizing the output of said second delay line with said late bus clock signal, and
a third delay line having a third delay and a means to set said third delay midway between the delays of said first and second delay lines, said third delay line having an output which provides an internal device clock signal synchronized to a time halfway between said early and said late bus clock signals.
80. The bus subsystem of claim 73 wherein said early and said late bus clock signals are low-voltage-swing signals that transition cyclically between low and high logical values, and further including a semiconductor device having a low-skew clock generator circuit comprising,
a DC amplifier to convert said early and said late bus clock signals into full-swing logic signals,
a first variable delay line having a first variable delay and an input and an output, the input of said first variable delay line being connected to said DC amplifier
a first, a second and a third additional delay line, each having an input and an output, the input of each of said additional delay lines being connected to the output of said first delay line,
said first additional delay line having a fixed delay,
said second additional delay line having said fixed delay plus a second variable delay, and
said third additional delay line having said- fixed delay plus one half of said second variable delay,
a first clocked input receiver connected to sample said early bus clock signal and gated by said output of said first additional delay line,
a means for adjusting said first variable delay so said first clocked input receiver samples said early bus clock signal just as said early bus clock signal transitions,
a second clocked input receiver connected to sample said late bus clock signal and gated by said output of said second additional delay line,
a means for adjusting said second variable delay so said second clocked input receiver samples said late bus clock signal just as said late bus clock signal transitions,
whereby said output of said third additional delay line is synchronized to a time halfway between said outputs of said first and said second additional delay lines, and said output of said third additional delay line provides an internal device clock signal.
81. The bus subsystem of claim 80 further comprising a semiconductor device having
a first one of said low-skew clock generator circuits which generates a “true” internal device clock signal and
a second one of said low-skew clock generator circuits connected to generate a “complement” internal device clock signal synchronized with but opposite in logical value to said “true” internal device clock signal.
82. A DRAM device designed to be connected to an external bus having a plurality of bus lines for carrying substantially all address, data and control information needed by said DRAM device as a sequential series of bits, said control information including device-select information, said external bus containing substantially fewer said bus lines than the number of bits in a single address, and said bus carrying device-select information without the need for separate device-select lines connected directly to said DRAM device, said DRAM device comprising
an array of memory cells connected in rows and columns, each of said memory cells adapted to store one of said bits,
a row address-selection means for selecting one of said rows,
a column sense amp connected to each of said columns, each of said column sense amps adapted to latch one of said bits as a binary logical value or to precharge to a selected state,
a column decoding means connected to each of said column sense amps for selecting a plurality of said column sense amps for inputting one of said bits to or outputting one of said bits from said memory cells,
an internal I/O bus having a plurality of internal I/O lines wherein each of said internal I/O lines is connected to a plurality of said column sense amps, and
a plurality of bus connection means designed to connect said internal I/O lines to said external bus,
whereby a selected bit of said sequential series of bits can be transferred from said external bus to a selected one of said memory cells or said bit contained in a selected one of said memory cells can be transferred to said external bus.
83. The DRAM device of claim 82 further comprising
an output driver connected to one said bus connection means,
an output multiplexer having an output connected to said output driver and a plurality of inputs, each of said inputs being connected to one of said internal I/O lines, and
a control means to select whether said output driver can drive said external bus,
whereby a plurality of memory cells are selected using said row address selection means and said column decoding means and a plurality of bits contained in said plurality of memory cells are output through said column sense amps to said internal I/O bus to said output multiplexer to said output driver to said external bus.
84. The DRAM device of claim 82 further comprising
a plurality of input receivers connected to one of said bus data lines and to said internal I/O bus,
a selection means for selecting said input receivers one by one to sense and store, one at a time, the bits of said sequential series of bits, and
a control means to select whether an input receiver can drive said internal I/O bus, whereby a bit of said sequential series of bits is input from said external bus through one of said input receivers to one of said internal I/O lines to one of said column sense amps to one of said memory cells.
85. The DRAM device of claim 82 further comprising
a first and a second half-array of said memory cells wherein each said row of said array of said memory cells is subdivided into two parts,
a first and a second one of said internal I/O buses connected to said column sense amps in said first and said second half-arrays, respectively, and
a column decoder means to gate selected ones of said column sense amps connected to said memory cells in a selected row of said first and said second half-arrays simultaneously.
86. The DRAM device of claim 85 wherein said column decoder means selects sixteen column sense amps at a time.
87. The DRAM device of claim 82 wherein said external bus operates at a certain speed and wherein said DRAM device includes four of said internal I/O buses, each of which operates at one-fourth the speed of said external bus.
88. The DRAM device of claim 82 further comprising
a means for precharging one of said column sense amps to a precharged state from which a binary logical value can quickly be loaded into said column sense amp,
if said column sense amp contains a binary logical value, a means for latching the logical value currently contained in said column sense amp and
a means for instructing said DRAM device to precharge said column sense amp or latch said binary logical value in said column sense amp.
89. The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction whenever said row address selection means selects a different one of said rows.
90. The DRAM device of claim 88 further comprising a means for instructing said DRAM device to precharge said column sense amp without further instruction at a first or a second preselected time after latching the latest said binary logical value, said first preselected time being long enough for said DRAM to latch said binary logical value into said column sense amp and transfer said binary logical value into memory or onto one of said internal I/O lines, and said second preselected time being a variable which can be stored in said DRAM device whereby said DRAM can latch a binary logical value into said column sense amp for transferring said binary logical value into or out of a selected said memory cell, then precharge to allow a faster subsequent read or write.
91. A package containing
a semiconductor die having a side, circuitry and a plurality of connecting areas positioned along or near said side, spaced at a selected pitch and connected to said circuitry,
said package comprising a plurality of bus connecting means for connecting to a plurality of external bus lines, each of said external bus lines corresponding to one of said connecting areas, each of said bus connecting means being
positioned on a first side of said package,
connected to one said external bus line and to said corresponding connecting area on said semiconductor die, and
spaced at a pitch substantially identical to said selected pitch of said connecting areas,
whereby each of said external bus lines can be connected to said corresponding connecting area on said semiconductor die by bus connection means positioned along a single side of said package.
92. The package of claim 91 further comprising a plurality of said bus connecting means wherein each of said bus connecting means includes
a pin adapted for connection to one of said external bus lines and
a wire connecting said pin to one of said connecting areas on said semiconductor die,
said wire having an effective lead length less than about 4 millimeters and wherein the effective lead length of said wire of each of said bus connection means for said package is approximately equal.
93. A plurality of packages of claim 91 wherein at least two of said semiconductor die are memory devices, each of said packages being generally flat, having a top and a bottom, and wherein
said packages are physically secured adjacent and parallel to each other in a stack,
where a first one of said packages is adjacent to a second one of said packages in said stack, said top of said first package is substantially aligned with said bottom of said second package, and
said bus connecting means of each of said packages are substantially aligned and are lying substantially in a plane.
94. The plurality of packages of claim 93 further comprising a plurality of stacks wherein each of said bus connecting means can be electrically connected to corresponding said bus connecting means in each of said stacks.
95. A semiconductor device capable of use in a semiconductor bus architecture including a plurality of semiconductor devices connected in parallel to a bus wherein said bus includes a plurality of bus lines for carrying substantially all address, data, control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said bus, and has substantially fewer bus lines than the number of bits in a single address, and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device, said semiconductor device comprising
connection means adapted to connect said semiconductor device to said bus, and
at least one modifiable identification register accessible to said bus through said connection means, whereby data may be transmitted to said register via said bus and enable said device thereafter to be uniquely identified.
96. The semiconductor device of claim 95 wherein said semiconductor device is a memory device which connects substantially only to said bus and sends and receives substantially all address, data and control information over said bus.
97. A semiconductor device capable of use in a semiconductor bus architecture including a plurality of semiconductor devices connected in parallel to a bus wherein said bus includes a plurality of bus lines for carrying substantially all address, data, control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said bus, and has substantially fewer bus lines than the number of bits in a single address, and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device, said semiconductor device comprising
connection means adapted to connect said semiconductor device to said bus, and
at least one modifiable register to hold device address information, said modifiable register accessible to said bus through said connection means, whereby data may be transmitted to said register via said bus which enables said device thereafter to respond to a predetermined range of addresses.
98. The semiconductor device of claim 97 wherein said semiconductor device is a memory device which connects substantially only to said bus and sends and receives substantially all address, data and control information over said bus.
99. The semiconductor device of claim 98 wherein said memory device has at least one discrete memory section and also has at least one modifiable address register adapted to store memory address information which corresponds to each said discrete memory section.
100. The semiconductor device of claim 99 wherein said memory address information comprises a pointer to said discrete memory section.
101. The semiconductor device of claim 100 wherein said is discrete memory section has a top and a bottom and said memory address information comprises pointers to said top and said bottom.
102. The semiconductor device of claim 100 wherein said memory address information comprises
a pointer to said discrete memory section and
a range value indicating the size of said discrete memory section.
103. A semiconductor device capable of use in a semiconductor bus architecture including a plurality of semiconductor devices connected in parallel to a bus wherein said bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said bus, and has substantially fewer bus lines than the number of bits in a single address, said semiconductor device comprising
connection means adapted to connect said semiconductor device to said bus, and
at least one modifiable access-time register accessible to said bus through said connection means, whereby data may be transmitted to said register via said bus which establishes a predetermined amount of time that said semiconductor device thereafter must wait before using said bus in response to a request.
104. The semiconductor device of claim 103 wherein said semiconductor device is a memory device which connects substantially only to said bus and sends and receives substantially all address, data and control information over said bus.
105. The semiconductor device of claim 103 further comprising at least two access-time registers and one of said access-time registers is permanently programmed to contain a fixed value and at least one of said access-time registers can be modified by information carried on said bus.
106. A semiconductor device capable of use in a semiconductor bus architecture including a plurality of semiconductor devices connected in parallel to a bus wherein said bus includes a plurality of bus lines for carrying substantially all address, data, control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said bus, and has substantially fewer bus lines than the number of bits in a single address, and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device, and wherein each said bus line is a terminated transmission line, said semiconductor device comprising
connection means adapted to connect said semiconductor device to said bus, and
a bus line driver capable of producing a low-voltage-swing signal on one of said terminated transmission lines.
107. The semiconductor device of claim 106 wherein said semiconductor device is a memory device which connects substantially only to said bus and sends and receives substantially all address, data and control information over said bus.
108. A semiconductor device capable of use in a semiconductor bus architecture including a plurality of semiconductor devices connected in parallel to a bus wherein said bus includes a plurality of bus lines for carrying substantially all address, data, control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said bus, and has substantially fewer bus lines than the number of bits in a single address, and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device, said bus further including at least one bus clock line for carrying early and late bus clock signals, said semiconductor device comprising
connection means adapted to connect said semiconductor device to said bus, and
an internal device clock generating means which generates an internal device clock synchronized to a time halfway between said early and said late bus clock signals.
109. The semiconductor device of claim 108 wherein said bus further includes a first and a second one of said bus clock lines, said first bus clock line carries said early bus clock signal and said second bus clock line carries said late bus clock signal, said semiconductor device further comprising a means to detect said early bus clock signal on said first bus clock line and a means to detect said late bus clock signal on said second bus clock line.
110. The semiconductor device of claim 109 wherein said semiconductor device is a memory device which connects substantially only to said bus and sends and receives substantially all address, data and control information over said bus.
111. A semiconductor device capable of use in a semiconductor bus architecture including a plurality of semiconductor devices connected in parallel to a bus wherein said bus includes a plurality of bus lines for carrying as a sequential series of bits substantially all address, data, control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said bus, and has substantially fewer bus lines than the number of bits in a single address, and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device, said semiconductor device comprising
connection means adapted to connect said semiconductor device to said bus,
a plurality of input receivers connected to one of said bus data lines and
a selection means for selecting said input receivers one by one to sense and store, one at a time, the bits of said sequential series of bits.
112. The semiconductor device of claim 111 wherein said semiconductor device is a memory device which connects substantially only to said bus and sends and receives substantially all address, data and control information over said bus.
113. The semiconductor device of claim 112 wherein two input receivers are connected to one of said bus lines.
114. A semiconductor device capable of use in an architecture for a semiconductor system bus including a plurality of semiconductor devices connected in parallel to a bus wherein said bus system includes a plurality of bus lines for carrying substantially all address, data, control and device-select information needed by said semiconductor device for communication
118. A semiconductor device capable of use in an architecture for a semiconductor system bus including a plurality of semiconductor devices connected in parallel to a bus wherein said system bus includes a plurality of bus lines for carrying substantially all address, data, control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said system bus, and has substantially fewer bus lines than the number of bits in a single address, and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device, said semiconductor device comprising
connection means adapted to connect said semiconductor device to said system bus,
an internal input/output bus within said semiconductor device having more lines than said system bust
a means for multiplexing the lines of said internal bus to the lines of said system bus, whereby said system bus can run at a higher speed than said internal bus, and
at least one modifiable register to hold device address information, said modifiable register accessible to said system bus through said connection means, whereby data may be transmitted to said register via said system bus which enables said device thereafter to respond to a predetermined range of addresses.
119. The semiconductor device of claim 118 wherein said semiconductor device is a memory device which connects substantially only to said system bus and sends and receives substantially all address, data and control information over said system bus.
120. The semiconductor device of claim 119 wherein said memory device has at least one discrete memory section and also has at least one modifiable address register adapted to store memory address information which corresponds to each said discrete memory section.
121. A semiconductor device capable of use in an architecture for a semiconductor system bus including a plurality of semiconductor devices connected in parallel to a bus wherein said system bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said system bus, and has substantially fewer bus lines than the number of bits in a single address, said semiconductor device comprising
connection means adapted to connect said semiconductor device to said system bus,
an internal input/output bus within said semiconductor device having more lines than said system bus,
a means for multiplexing the lines of said internal bus to the lines of said system bus, whereby said system bus can run at a higher speed than said internal bus, and
at least one modifiable access-time register accessible to said system bus through said connection means, whereby data may be transmitted to said register via said system bus which establishes a predetermined amount of time that said semiconductor device thereafter must wait before using said system bus in response to a request.
122. The semiconductor device of claim 121 wherein said semiconductor device is a memory device which connects substantially only to said system bus and sends and receives substantially all address, data and control information over said system bus.
123. The semiconductor device of claim 121 further comprising at least two access-time registers and one of said access-time registers is permanently programmed to contain a fixed value and at least one of said access-time registers can be modified by information carried on said system bus.
124. A semiconductor device capable of use in a semiconductor bus architecture including a plurality of semiconductor devices connected in parallel to a bus wherein said bus includes a plurality of bus lines for carrying substantially all address, data, control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said bus, and has substantially fewer bus lines than the number of bits in a single address, and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device, wherein said address, data, control and device-select information is carried over said bus in the form of request-packets and bus transactions, said semiconductor device comprising
connection means adapted to connect said semiconductor device to said bus,
a means to receive said request packets over said bus,
a means to decode information in said request packets, and
a means to respond to said information in said request packets.
125. The semiconductor device of claim 124 wherein said means to decode information in said request packet further comprises
a means to identify and decode said control information in said request packet,
a means to identify and decode said device-select information in said request packet,
a means to identify and decode said address information in said request packet and
a means to determine whether said control information or said address information instructs said semiconductor device to begin a response.
126. The semiconductor device of claim 124 wherein each of said bus transactions is carried out in response to said address and said control information in one of said request packets, and wherein said means to identify and decode information in said request packets includes a means to identify a sequence of bytes on said bus as one of said request packets containing said address and said control information, said control information including information about the type of said bus transaction being requested and the access time which needs to intervene before beginning said bus transaction over said bus and said address and said control information includes device-select information instructing one or more said semiconductor devices to respond to said address and said control information.
127. The semiconductor device of claim 124 further comprising
a plurality of sense amplifiers adapted to precharge to a selected state or to latch a bit of information,
a means to hold said sense amplifiers in an unmodified state after latching one of said bits of information,
a means to precharge said sense amplifiers and
a means for selecting whether said semiconductor device should precharge said sense amplifiers or should hold said sense amplifiers in an unmodified state.
128. The semiconductor device of claim 124 wherein said means to respond to said information, where said information is control information, further comprises a means to
transfer a data block during a data block transfer, further including a means to
read data from said semiconductor device and
write data into said semiconductor device, and
initiate a data block transfer,
transfer a data block of a selected size,
transfer a data block at a selected time,
access a control register, including a means to read from or write to said control register, or
select normal or page-mode access.
129. The semiconductor device of claim 124 further comprising a means to respond to said information in said request packet if said information includes a device identification number unique to said semiconductor device.
130. The semiconductor device of claim 124 further comprising a means to respond to said information in said request packet if said information includes a special device identification number which calls for said semiconductor device to respond.
131. The semiconductor device of claim 124 further comprising a means to respond to said information in said request packet if said information includes an address unique to said semiconductor device.
132. The semiconductor device of claim 124 further comprising a means to interpret said control information and decode the time to wait before beginning said bus transaction over said bus.
133. The semiconductor device of claim 124 further comprising a means to interpret said control information and decode the size of a data block to transfer during one of said bus transactions.
134. The semiconductor device of claim 124, 125, 126, 127, 128, 129, 130, 131, 132 or 133 wherein said semiconductor device is a memory device which connects substantially only to said bus and sends and receives substantially all address, data and control information over said bus.
135. A semiconductor device capable of use in a semiconductor bus architecture including a plurality of semiconductor devices connected in parallel to a bus wherein said bus includes a plurality of bus lines for carrying substantially all address, data, control and device-select information needed by said semiconductor device for communication with substantially every other semiconductor device connected to said bus, and has substantially fewer bus lines than the number of bits in a single address, and carries device-select information for said semiconductor device without the need for a separate device-select line connected directly to said individual semiconductor device, wherein said address, data, control and device-select information is carried over said bus in the form of request packets and bus transactions, said semiconductor device comprising
connection means adapted to connect said semiconductor device to said bus,
a means to encode address and control information in said request packets and
a means to send said request packets over said bus.
136. The semiconductor device of claim 135 further comprising a means to request a bus transaction wherein each of said bus transactions is carried out in response to said address and said control information in one of said request packets, and wherein said means to encode information in said request packets includes a means to mark a sequence of bytes on said bus as one of said request packets, said control information including information about the type of said bus transaction being requested and the access time which needs to intervene before beginning said bus transaction over said bus and said address and said control information includes device-select information instructing one or more said semiconductor devices to respond to said address and said control information.
137. The semiconductor device of claim 135 wherein one or more of said plurality of semiconductor devices has a unique device identification number, said semiconductor device further comprising a means to send control information to a specific one of said plurality of semiconductor devices by including in said request packet a selected said device identification number.
138. The semiconductor device of claim 135 wherein each of said plurality of semiconductor devices is adapted to respond to a special device identification number, said semiconductor device further comprising a means to send control information to each of said plurality of semiconductor devices by including in said request packet said special device identification number.
139. The semiconductor device of claim 135 wherein one or more of said plurality of semiconductor devices is a memory device having a plurality of addresses, said semiconductor device further comprising a means to send control information to a specific address or range of addresses in one of said plurality of semiconductor devices by including said-specific address or range of addresses in said request packet.
140. The semiconductor device of claim 135 wherein at least one of said request packets is a request packet requesting a bus transaction which is followed by a corresponding one of said bus transactions, said semiconductor device further comprising a means to encode said control information to specify directly or indirectly the time between the end of said request packet requesting a bus transaction and said corresponding bus transaction over said bus.
141. The semiconductor device of claim 140 wherein one type of said bus transactions is a transfer of a data block, said semiconductor device further comprising a means to encode said control information to specify the size of said data block to transfer.
142. The semiconductor device of claim 140 further comprising a means to keep track of current and pending bus transactions, whereby collisions on said bus are avoided because said semiconductor device avoids initiating bus transactions which would conflict with current or pending bus transactions.
143. The semiconductor device of claim 135 wherein said semiconductor device is a first master device and one of said plurality of semiconductor devices is a second master device, further comprising
a collision detecting means whereby said first master device when sending a first one of said request packets can detect said second master device sending a colliding one of said request packets, where said colliding request packet may be sent simultaneous with the initial sending of or overlapping the sending of said first request packet, and
an arbitration means whereby said first and said second master devices select a priority order in which each of said master devices will be allowed to access said bus sequentially.
144. The semiconductor device of claim 143 wherein said semiconductor device is a master device and at least one of said plurality of semiconductor devices is a master device, each of said master devices has a master ID number and each of said request packets includes a master ID position which is a predetermined number of bits in a predetermined position in said request packet, and wherein said collision detection means comprises
a means for said semiconductor device to send its master ID number in said request packet and
a means to detect a collision and invoke said arbitration means if said semiconductor device detects any other master ID number in said master ID position.
145. The semiconductor device of claim 144 wherein said system bus architecture includes a means for carrying information on said bus during bus cycles, said semiconductor device further comprising
a means for driving a selected bus line or lines during at least one selected bus cycle while sending each said request packet,
a means for monitoring said selected bus line or lines to see if another said master device is sending one of said colliding request packets and
a means for informing all said master devices that a collision has occurred and for invoking said arbitration means.
146. The semiconductor device of claim 145 further comprising
a means, when sending a request packet, for driving a selected bus line or lines with a certain current during at least one selected bus cycle,
a means for monitoring said selected bus line or lines for a greater than normal current to see if another said master device is driving that line or lines,
a means for detecting said greater than normal current, and
a means for informing all said master devices that a collision has occurred and for invoking said arbitration means.
147. The semiconductor device of claim 143 wherein said arbitration means comprises
a means for initiating an arbitration cycle,
a means for allocating a single bus line to each said master device during at least one selected bus cycle relative to the start of said arbitration cycle,
a means for allocating each said master device to a single bus line during one of said selected bus cycles if there are more master devices than available bus lines,
a means for each of said master devices which sent one of said colliding request packets to drive said bus line allocated to said master device during said selected bus cycle, and
a means in at least one of said master devices for storing information about which master devices sent one of said colliding request packets,
whereby said master devices can monitor selected bus lines during said arbitration cycle and identify each said master device which sent one of said colliding request packets.
148. The semiconductor device of claim 143 wherein said arbitration means comprises
a means for identifying each of said master devices which sent one of said colliding request packets,
a means for assigning a priority to each said master device which sent one of said colliding request packets, and
a means for allowing each said master device which sent one of said colliding request packets to access the bus sequentially according to that priority.
149. The semiconductor device of claim 143 wherein said priority is based on the physical location of each of said master devices.
150. The semiconductor device of claim 143 wherein said priority is based on said master ID number of said master devices.
US09/492,982 1990-04-18 2000-01-27 Method of operating a memory device having a variable data input length Expired - Fee Related US6452863B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US09/492,982 US6452863B2 (en) 1990-04-18 2000-01-27 Method of operating a memory device having a variable data input length
US09/779,296 US6324120B2 (en) 1990-04-18 2001-02-08 Memory device having a variable data output length
US09/796,206 US6426916B2 (en) 1990-04-18 2001-02-27 Memory device having a variable data output length and a programmable register

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US51089890A 1990-04-18 1990-04-18
US07/954,945 US5319755A (en) 1990-04-18 1992-09-30 Integrated circuit I/O using high performance bus interface
US08/222,646 US5513327A (en) 1990-04-18 1994-03-31 Integrated circuit I/O using a high performance bus interface
US08/448,657 US5638334A (en) 1990-04-18 1995-05-24 Integrated circuit I/O using a high performance bus interface
US08/798,520 US5841580A (en) 1990-04-18 1997-02-10 Integrated circuit I/O using a high performance bus interface
US09/196,199 US6038195A (en) 1990-04-18 1998-11-20 Synchronous memory device having a delay time register and method of operating same
US09/252,997 US6034918A (en) 1990-04-18 1999-02-19 Method of operating a memory having a variable data output length and a programmable register
US09/492,982 US6452863B2 (en) 1990-04-18 2000-01-27 Method of operating a memory device having a variable data input length

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/252,997 Continuation US6034918A (en) 1990-04-18 1999-02-19 Method of operating a memory having a variable data output length and a programmable register

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US09/779,296 Continuation US6324120B2 (en) 1990-04-18 2001-02-08 Memory device having a variable data output length
US09/796,206 Continuation US6426916B2 (en) 1990-04-18 2001-02-27 Memory device having a variable data output length and a programmable register

Publications (2)

Publication Number Publication Date
US20020015351A1 true US20020015351A1 (en) 2002-02-07
US6452863B2 US6452863B2 (en) 2002-09-17

Family

ID=24032637

Family Applications (47)

Application Number Title Priority Date Filing Date
US07/849,212 Expired - Lifetime US5499385A (en) 1990-04-18 1992-03-05 Method for accessing and transmitting data to/from a memory in packets
US07/847,651 Expired - Fee Related US5606717A (en) 1990-04-18 1992-03-05 Memory circuitry having bus interface for receiving information in packets and access time registers
US07/847,532 Expired - Lifetime US5473575A (en) 1990-04-18 1992-03-05 Integrated circuit I/O using a high performance bus interface
US07/954,945 Expired - Lifetime US5319755A (en) 1990-04-18 1992-09-30 Integrated circuit I/O using high performance bus interface
US08/183,573 Expired - Fee Related US5408129A (en) 1990-04-18 1994-01-18 Integrated circuit I/O using a high performance bus interface
US08/222,646 Expired - Lifetime US5513327A (en) 1990-04-18 1994-03-31 Integrated circuit I/O using a high performance bus interface
US08/448,657 Expired - Lifetime US5638334A (en) 1990-04-18 1995-05-24 Integrated circuit I/O using a high performance bus interface
US08/749,729 Expired - Lifetime US5657481A (en) 1990-04-18 1996-11-15 Memory device with a phase locked loop circuitry
US08/762,139 Expired - Lifetime US5809263A (en) 1990-04-18 1996-12-09 Integrated circuit I/O using a high performance bus interface
US08/796,782 Expired - Lifetime US5841715A (en) 1990-04-18 1997-02-10 Integrated circuit I/O using high performance bus interface
US08/798,520 Expired - Lifetime US5841580A (en) 1990-04-18 1997-02-10 Integrated circuit I/O using a high performance bus interface
US08/798,525 Expired - Fee Related US5954804A (en) 1990-04-18 1997-02-10 Synchronous memory device having an internal register
US08/829,459 Expired - Fee Related US6598171B1 (en) 1990-04-18 1997-03-28 Integrated circuit I/O using a high performance bus interface
US08/910,810 Expired - Fee Related US5983320A (en) 1990-04-18 1997-08-13 Method and apparatus for externally configuring and modifying the transaction request response characteristics of a semiconductor device coupled to a bus
US08/979,127 Expired - Fee Related US5915105A (en) 1990-04-18 1997-11-26 Integrated circuit I/O using a high performance bus interface
US09/098,387 Expired - Fee Related US5928343A (en) 1990-04-18 1998-06-16 Memory module having memory devices containing internal device ID registers and method of initializing same
US09/161,090 Expired - Fee Related US6049846A (en) 1990-04-18 1998-09-25 Integrated circuit having memory which synchronously samples information with respect to external clock signals
US09/196,199 Expired - Fee Related US6038195A (en) 1990-04-18 1998-11-20 Synchronous memory device having a delay time register and method of operating same
US09/200,446 Expired - Fee Related US6035365A (en) 1990-04-18 1998-11-27 Dual clocked synchronous memory device having a delay time register and method of operating same
US09/213,243 Expired - Fee Related US6101152A (en) 1990-04-18 1998-12-17 Method of operating a synchronous memory device
US09/221,108 Expired - Fee Related US6415339B1 (en) 1990-04-18 1998-12-28 Memory device having a plurality of programmable internal registers and a delay time register
US09/239,522 Expired - Fee Related US6044426A (en) 1990-04-18 1999-01-29 Memory system having memory devices each including a programmable internal register
US09/252,993 Expired - Fee Related US6085284A (en) 1990-04-18 1999-02-19 Method of operating a memory device having a variable data output length and an identification register
US09/252,998 Expired - Fee Related US6032214A (en) 1990-04-18 1999-02-19 Method of operating a synchronous memory device having a variable data output length
US09/252,997 Expired - Fee Related US6034918A (en) 1990-04-18 1999-02-19 Method of operating a memory having a variable data output length and a programmable register
US09/263,224 Expired - Fee Related US6032215A (en) 1990-04-18 1999-03-05 Synchronous memory device utilizing two external clocks
US09/263,225 Expired - Fee Related US6128696A (en) 1990-04-18 1999-03-05 Synchronous memory device utilizing request protocol and method of operation of same
US09/263,956 Expired - Fee Related US6070222A (en) 1990-04-18 1999-03-08 Synchronous memory device having identification register
US09/357,989 Expired - Fee Related US6067592A (en) 1990-04-18 1999-07-21 System having a synchronous memory device
US09/487,524 Expired - Fee Related US6185644B1 (en) 1990-04-18 2000-01-19 Memory system including a plurality of memory devices and a transceiver device
US09/492,982 Expired - Fee Related US6452863B2 (en) 1990-04-18 2000-01-27 Method of operating a memory device having a variable data input length
US09/510,213 Expired - Fee Related US6182184B1 (en) 1990-04-18 2000-02-22 Method of operating a memory device having a variable data input length
US09/514,872 Expired - Fee Related US6260097B1 (en) 1990-04-18 2000-02-28 Method and apparatus for controlling a synchronous memory device
US09/545,648 Expired - Fee Related US6378020B2 (en) 1990-04-18 2000-04-10 System having double data transfer rate and intergrated circuit therefor
US09/566,551 Expired - Fee Related US6266285B1 (en) 1990-04-18 2000-05-08 Method of operating a memory device having write latency
US09/629,497 Expired - Fee Related US6314051B1 (en) 1990-04-18 2000-07-31 Memory device having write latency
US09/669,295 Expired - Fee Related US6304937B1 (en) 1990-04-18 2000-09-25 Method of operation of a memory controller
US09/801,151 Expired - Fee Related US6697295B2 (en) 1990-04-18 2001-03-07 Memory device having a programmable register
US09/893,836 Expired - Fee Related US6570814B2 (en) 1990-04-18 2001-06-28 Integrated circuit device which outputs data after a latency period transpires
US09/916,493 Expired - Fee Related US6513081B2 (en) 1990-04-18 2001-07-26 Memory device which receives an external reference voltage signal
US09/969,489 Expired - Fee Related US6564281B2 (en) 1990-04-18 2001-10-01 Synchronous memory device having automatic precharge
US10/028,077 Expired - Fee Related US6546446B2 (en) 1990-04-18 2001-12-21 Synchronous memory device having automatic precharge
US10/102,237 Expired - Fee Related US6584037B2 (en) 1990-04-18 2002-02-04 Memory device which samples data after an amount of time transpires
US10/716,595 Abandoned US20040114454A1 (en) 1990-04-18 2003-11-20 Memory device and method for operating same
US10/939,501 Expired - Fee Related US7110322B2 (en) 1990-04-18 2004-09-14 Memory module including an integrated circuit device
US10/939,500 Expired - Fee Related US6975558B2 (en) 1990-04-18 2004-09-14 Integrated circuit device
US10/973,268 Abandoned US20050141332A1 (en) 1990-04-18 2004-10-27 Semiconductor device including a register to store a value that is representative of device type information

Family Applications Before (30)

Application Number Title Priority Date Filing Date
US07/849,212 Expired - Lifetime US5499385A (en) 1990-04-18 1992-03-05 Method for accessing and transmitting data to/from a memory in packets
US07/847,651 Expired - Fee Related US5606717A (en) 1990-04-18 1992-03-05 Memory circuitry having bus interface for receiving information in packets and access time registers
US07/847,532 Expired - Lifetime US5473575A (en) 1990-04-18 1992-03-05 Integrated circuit I/O using a high performance bus interface
US07/954,945 Expired - Lifetime US5319755A (en) 1990-04-18 1992-09-30 Integrated circuit I/O using high performance bus interface
US08/183,573 Expired - Fee Related US5408129A (en) 1990-04-18 1994-01-18 Integrated circuit I/O using a high performance bus interface
US08/222,646 Expired - Lifetime US5513327A (en) 1990-04-18 1994-03-31 Integrated circuit I/O using a high performance bus interface
US08/448,657 Expired - Lifetime US5638334A (en) 1990-04-18 1995-05-24 Integrated circuit I/O using a high performance bus interface
US08/749,729 Expired - Lifetime US5657481A (en) 1990-04-18 1996-11-15 Memory device with a phase locked loop circuitry
US08/762,139 Expired - Lifetime US5809263A (en) 1990-04-18 1996-12-09 Integrated circuit I/O using a high performance bus interface
US08/796,782 Expired - Lifetime US5841715A (en) 1990-04-18 1997-02-10 Integrated circuit I/O using high performance bus interface
US08/798,520 Expired - Lifetime US5841580A (en) 1990-04-18 1997-02-10 Integrated circuit I/O using a high performance bus interface
US08/798,525 Expired - Fee Related US5954804A (en) 1990-04-18 1997-02-10 Synchronous memory device having an internal register
US08/829,459 Expired - Fee Related US6598171B1 (en) 1990-04-18 1997-03-28 Integrated circuit I/O using a high performance bus interface
US08/910,810 Expired - Fee Related US5983320A (en) 1990-04-18 1997-08-13 Method and apparatus for externally configuring and modifying the transaction request response characteristics of a semiconductor device coupled to a bus
US08/979,127 Expired - Fee Related US5915105A (en) 1990-04-18 1997-11-26 Integrated circuit I/O using a high performance bus interface
US09/098,387 Expired - Fee Related US5928343A (en) 1990-04-18 1998-06-16 Memory module having memory devices containing internal device ID registers and method of initializing same
US09/161,090 Expired - Fee Related US6049846A (en) 1990-04-18 1998-09-25 Integrated circuit having memory which synchronously samples information with respect to external clock signals
US09/196,199 Expired - Fee Related US6038195A (en) 1990-04-18 1998-11-20 Synchronous memory device having a delay time register and method of operating same
US09/200,446 Expired - Fee Related US6035365A (en) 1990-04-18 1998-11-27 Dual clocked synchronous memory device having a delay time register and method of operating same
US09/213,243 Expired - Fee Related US6101152A (en) 1990-04-18 1998-12-17 Method of operating a synchronous memory device
US09/221,108 Expired - Fee Related US6415339B1 (en) 1990-04-18 1998-12-28 Memory device having a plurality of programmable internal registers and a delay time register
US09/239,522 Expired - Fee Related US6044426A (en) 1990-04-18 1999-01-29 Memory system having memory devices each including a programmable internal register
US09/252,993 Expired - Fee Related US6085284A (en) 1990-04-18 1999-02-19 Method of operating a memory device having a variable data output length and an identification register
US09/252,998 Expired - Fee Related US6032214A (en) 1990-04-18 1999-02-19 Method of operating a synchronous memory device having a variable data output length
US09/252,997 Expired - Fee Related US6034918A (en) 1990-04-18 1999-02-19 Method of operating a memory having a variable data output length and a programmable register
US09/263,224 Expired - Fee Related US6032215A (en) 1990-04-18 1999-03-05 Synchronous memory device utilizing two external clocks
US09/263,225 Expired - Fee Related US6128696A (en) 1990-04-18 1999-03-05 Synchronous memory device utilizing request protocol and method of operation of same
US09/263,956 Expired - Fee Related US6070222A (en) 1990-04-18 1999-03-08 Synchronous memory device having identification register
US09/357,989 Expired - Fee Related US6067592A (en) 1990-04-18 1999-07-21 System having a synchronous memory device
US09/487,524 Expired - Fee Related US6185644B1 (en) 1990-04-18 2000-01-19 Memory system including a plurality of memory devices and a transceiver device

Family Applications After (16)

Application Number Title Priority Date Filing Date
US09/510,213 Expired - Fee Related US6182184B1 (en) 1990-04-18 2000-02-22 Method of operating a memory device having a variable data input length
US09/514,872 Expired - Fee Related US6260097B1 (en) 1990-04-18 2000-02-28 Method and apparatus for controlling a synchronous memory device
US09/545,648 Expired - Fee Related US6378020B2 (en) 1990-04-18 2000-04-10 System having double data transfer rate and intergrated circuit therefor
US09/566,551 Expired - Fee Related US6266285B1 (en) 1990-04-18 2000-05-08 Method of operating a memory device having write latency
US09/629,497 Expired - Fee Related US6314051B1 (en) 1990-04-18 2000-07-31 Memory device having write latency
US09/669,295 Expired - Fee Related US6304937B1 (en) 1990-04-18 2000-09-25 Method of operation of a memory controller
US09/801,151 Expired - Fee Related US6697295B2 (en) 1990-04-18 2001-03-07 Memory device having a programmable register
US09/893,836 Expired - Fee Related US6570814B2 (en) 1990-04-18 2001-06-28 Integrated circuit device which outputs data after a latency period transpires
US09/916,493 Expired - Fee Related US6513081B2 (en) 1990-04-18 2001-07-26 Memory device which receives an external reference voltage signal
US09/969,489 Expired - Fee Related US6564281B2 (en) 1990-04-18 2001-10-01 Synchronous memory device having automatic precharge
US10/028,077 Expired - Fee Related US6546446B2 (en) 1990-04-18 2001-12-21 Synchronous memory device having automatic precharge
US10/102,237 Expired - Fee Related US6584037B2 (en) 1990-04-18 2002-02-04 Memory device which samples data after an amount of time transpires
US10/716,595 Abandoned US20040114454A1 (en) 1990-04-18 2003-11-20 Memory device and method for operating same
US10/939,501 Expired - Fee Related US7110322B2 (en) 1990-04-18 2004-09-14 Memory module including an integrated circuit device
US10/939,500 Expired - Fee Related US6975558B2 (en) 1990-04-18 2004-09-14 Integrated circuit device
US10/973,268 Abandoned US20050141332A1 (en) 1990-04-18 2004-10-27 Semiconductor device including a register to store a value that is representative of device type information

Country Status (7)

Country Link
US (47) US5499385A (en)
EP (7) EP1640847B1 (en)
JP (3) JP3414393B2 (en)
KR (1) KR100201057B1 (en)
DE (15) DE69133598D1 (en)
IL (4) IL96808A (en)
WO (1) WO1991016680A1 (en)

Families Citing this family (744)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (en) 1992-10-02 1996-03-14 삼성전자주식회사 Semiconductor memory device
US5587962A (en) * 1987-12-23 1996-12-24 Texas Instruments Incorporated Memory circuit accommodating both serial and random access including an alternate address buffer register
US5093807A (en) * 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
USRE40552E1 (en) 1990-04-06 2008-10-28 Mosaid Technologies, Inc. Dynamic random access memory using imperfect isolating transistors
GB9007791D0 (en) * 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
GB9007790D0 (en) * 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
US6324120B2 (en) * 1990-04-18 2001-11-27 Rambus Inc. Memory device having a variable data output length
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
US6751696B2 (en) * 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
EP1004956B2 (en) 1990-04-18 2009-02-11 Rambus Inc. Method of operating a synchronous memory having a variable data output length
US6249481B1 (en) 1991-10-15 2001-06-19 Kabushiki Kaisha Toshiba Semiconductor memory device
US6223264B1 (en) * 1991-10-24 2001-04-24 Texas Instruments Incorporated Synchronous dynamic random access memory and data processing system using an address select signal
US5498990A (en) * 1991-11-05 1996-03-12 Monolithic System Technology, Inc. Reduced CMOS-swing clamping circuit for bus lines
US5471632A (en) * 1992-01-10 1995-11-28 Digital Equipment Corporation System for transferring data between a processor and a system bus including a device which packs, unpacks, or buffers data blocks being transferred
USRE39879E1 (en) * 1992-03-06 2007-10-09 Rambus, Inc. Method of transferring data by transmitting lower order and upper order memory address bits in separate words with respective op codes and start information
US5715407A (en) * 1992-03-06 1998-02-03 Rambus, Inc. Process and apparatus for collision detection on a parallel bus by monitoring a first line of the bus during even bus cycles for indications of overlapping packets
JP3517237B2 (en) * 1992-03-06 2004-04-12 ラムバス・インコーポレーテッド Synchronous bus system and memory device therefor
JP2868141B2 (en) * 1992-03-16 1999-03-10 株式会社日立製作所 Disk array device
US5254883A (en) * 1992-04-22 1993-10-19 Rambus, Inc. Electrical current source circuitry for a bus
US5485490A (en) * 1992-05-28 1996-01-16 Rambus, Inc. Method and circuitry for clock synchronization
USRE38482E1 (en) * 1992-05-28 2004-03-30 Rambus Inc. Delay stage circuitry for a ring oscillator
AU4798793A (en) * 1992-08-10 1994-03-03 Monolithic System Technology, Inc. Fault-tolerant, high-speed bus system and bus interface for wafer-scale integration
DE69316955T2 (en) * 1992-09-18 1998-07-30 Hitachi Ltd Computer system with synchronous, dynamic memory
US6279116B1 (en) 1992-10-02 2001-08-21 Samsung Electronics Co., Ltd. Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation
US5511024A (en) * 1993-06-02 1996-04-23 Rambus, Inc. Dynamic random access memory system
US5420987A (en) * 1993-07-19 1995-05-30 3 Com Corporation Method and apparatus for configuring a selected adapter unit on a common bus in the presence of other adapter units
JP3579461B2 (en) * 1993-10-15 2004-10-20 株式会社ルネサステクノロジ Data processing system and data processing device
US5469435A (en) * 1994-01-25 1995-11-21 Apple Computer, Inc. Bus deadlock avoidance during master split-transactions
US5631734A (en) 1994-02-10 1997-05-20 Affymetrix, Inc. Method and apparatus for detection of fluorescently labeled materials
EP1005010A3 (en) 1994-03-16 2001-10-24 Brooktree Corporation Method for processing data in a multimedia graphics system
GB9406477D0 (en) * 1994-03-31 1994-05-25 D2B Systems Co Ltd Interconnection of local communication bus systems
US5655113A (en) 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
US5508968A (en) * 1994-08-12 1996-04-16 International Business Machines Corporation Dynamic random access memory persistent page implemented as processor register sets
US5796673A (en) 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
US5568651A (en) * 1994-11-03 1996-10-22 Digital Equipment Corporation Method for detection of configuration types and addressing modes of a dynamic RAM
US5715437A (en) 1994-11-10 1998-02-03 Brooktree Corporation System for, and method of, processing in hardware commands received from software without polling of the hardware by the software
JPH08278916A (en) * 1994-11-30 1996-10-22 Hitachi Ltd Multichannel memory system, transfer information synchronizing method, and signal transfer circuit
US5606710A (en) * 1994-12-20 1997-02-25 National Semiconductor Corporation Multiple chip package processor having feed through paths on one die
US5717931A (en) * 1994-12-20 1998-02-10 Motorola, Inc. Method and apparatus for communicating between master and slave electronic devices where the slave device may be hazardous
US5699516A (en) * 1994-12-22 1997-12-16 Motorola, Inc. Method and apparatus for implementing a in-order termination bus protocol within a data processing system
KR100566464B1 (en) 1995-01-31 2006-03-31 가부시끼가이샤 히다치 세이사꾸쇼 Semiconductor memory device
JP4341043B2 (en) * 1995-03-06 2009-10-07 真彦 久野 I / O expansion device, external storage device, method and apparatus for accessing this external storage device
US5592123A (en) * 1995-03-07 1997-01-07 Linfinity Microelectronics, Inc. Frequency stability bootstrapped current mirror
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
DE69622079T2 (en) * 1995-03-31 2002-10-31 Sun Microsystems, Inc. Method and device for the rapid initiation of memory accesses in a cache-coherent multiprocessor system
US5822341A (en) * 1995-04-06 1998-10-13 Advanced Hardware Architectures, Inc. Multiport RAM for use within a viterbi decoder
US5635852A (en) * 1995-04-17 1997-06-03 Linfinity Microelectronics, Inc. Controllable actice terminator for a computer bus
US5608312A (en) * 1995-04-17 1997-03-04 Linfinity Microelectronics, Inc. Source and sink voltage regulator for terminators
US5787267A (en) * 1995-06-07 1998-07-28 Monolithic System Technology, Inc. Caching method and circuit for a memory system with circuit module architecture
JP2630311B2 (en) * 1995-06-15 1997-07-16 日本電気株式会社 Semiconductor integrated circuit device
US5748920A (en) * 1995-06-23 1998-05-05 Cirrus Logic, Inc. Transaction queue in a graphics controller chip
EP0752666A3 (en) 1995-07-06 2004-04-28 Sun Microsystems, Inc. Method and apparatus for fast-forwarding slave requests in a packet-switched computer system
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
US5752076A (en) * 1995-08-31 1998-05-12 Intel Corporation Dynamic programming of bus master channels by intelligent peripheral devices using communication packets
US5537353A (en) * 1995-08-31 1996-07-16 Cirrus Logic, Inc. Low pin count-wide memory devices and systems and methods using the same
US6025840A (en) * 1995-09-27 2000-02-15 Cirrus Logic, Inc. Circuits, systems and methods for memory mapping and display control systems using the same
US5895480A (en) * 1995-10-10 1999-04-20 Holtek Microelectronics, Inc. Method of and means for accessing an address by respectively substracting base addresses of memory integrated circuits from an access address
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6035369A (en) * 1995-10-19 2000-03-07 Rambus Inc. Method and apparatus for providing a memory with write enable information
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US5748914A (en) † 1995-10-19 1998-05-05 Rambus, Inc. Protocol for communication with dynamic memory
US5636174A (en) * 1996-01-11 1997-06-03 Cirrus Logic, Inc. Fast cycle time-low latency dynamic random access memories and systems and methods using the same
US5944807A (en) 1996-02-06 1999-08-31 Opti Inc. Compact ISA-bus interface
US5815673A (en) * 1996-03-01 1998-09-29 Samsung Electronics Co., Ltd. Method and apparatus for reducing latency time on an interface by overlapping transmitted packets
DE69625327D1 (en) * 1996-03-20 2003-01-23 St Microelectronics Srl Time-allocating internal bus, especially for non-volatile memories
US5911051A (en) * 1996-03-29 1999-06-08 Intel Corporation High-throughput interconnect allowing bus transactions based on partial access requests
US6317803B1 (en) 1996-03-29 2001-11-13 Intel Corporation High-throughput interconnect having pipelined and non-pipelined bus transaction modes
US5872940A (en) * 1996-04-01 1999-02-16 Motorola, Inc. Programmable read/write access signal and method therefor
US5906003A (en) * 1996-04-17 1999-05-18 Cirrus Logic, Inc. Memory device with an externally selectable-width I/O port and systems and methods using the same
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US5829016A (en) * 1996-04-24 1998-10-27 Cirrus Logic, Inc. Memory system with multiplexed input-output port and systems and methods using the same
US5835965A (en) * 1996-04-24 1998-11-10 Cirrus Logic, Inc. Memory system with multiplexed input-output port and memory mapping capability
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US6009487A (en) * 1996-05-31 1999-12-28 Rambus Inc. Method and apparatus for setting a current of an output driver for the high speed bus
US5857083A (en) * 1996-06-07 1999-01-05 Yamaha Corporation Bus interfacing device for interfacing a secondary peripheral bus with a system having a host CPU and a primary peripheral bus
US5815456A (en) * 1996-06-19 1998-09-29 Cirrus Logic, Inc. Multibank -- multiport memories and systems and methods using the same
US5845098A (en) * 1996-06-24 1998-12-01 Motorola Inc. Address lines load reduction
US5901293A (en) * 1996-06-25 1999-05-04 Claxton; Daniel Dean Bus interface controller for serially-accessed variable-access-time memory device
US5734661A (en) * 1996-09-20 1998-03-31 Micron Technology, Inc. Method and apparatus for providing external access to internal integrated circuit test circuits
US5870616A (en) * 1996-10-04 1999-02-09 International Business Machines Corporation System and method for reducing power consumption in an electronic circuit
DE19758672B4 (en) * 1996-10-09 2004-07-15 Fujitsu Ltd., Kawasaki Signal transmission system for LSI chips
US5872736A (en) * 1996-10-28 1999-02-16 Micron Technology, Inc. High speed input buffer
US5917758A (en) 1996-11-04 1999-06-29 Micron Technology, Inc. Adjustable output driver circuit
US5774135A (en) * 1996-11-05 1998-06-30 Vlsi, Technology, Inc. Non-contiguous memory location addressing scheme
US6076127A (en) * 1996-11-06 2000-06-13 International Business Machines Corporation Configuration of a single point bus arbitration scheme using on-chip arbiters
US5915102A (en) * 1996-11-06 1999-06-22 International Business Machines Corporation Common arbiter interface device with arbitration configuration for centralized common bus arbitration
US5949254A (en) * 1996-11-26 1999-09-07 Micron Technology, Inc. Adjustable output driver circuit
US6115318A (en) * 1996-12-03 2000-09-05 Micron Technology, Inc. Clock vernier adjustment
JP3177464B2 (en) * 1996-12-12 2001-06-18 株式会社日立製作所 Input / output circuit cell and semiconductor integrated circuit device
US5838177A (en) * 1997-01-06 1998-11-17 Micron Technology, Inc. Adjustable output driver circuit having parallel pull-up and pull-down elements
US5894586A (en) * 1997-01-23 1999-04-13 Xionics Document Technologies, Inc. System for providing access to memory in which a second processing unit is allowed to access memory during a time slot assigned to a first processing unit
US6125157A (en) * 1997-02-06 2000-09-26 Rambus, Inc. Delay-locked loop circuitry for clock delay adjustment
US5953263A (en) * 1997-02-10 1999-09-14 Rambus Inc. Synchronous memory device having a programmable register and method of controlling same
US5920518A (en) * 1997-02-11 1999-07-06 Micron Technology, Inc. Synchronous clock generator including delay-locked loop
US6230245B1 (en) 1997-02-11 2001-05-08 Micron Technology, Inc. Method and apparatus for generating a variable sequence of memory device command signals
US6104209A (en) * 1998-08-27 2000-08-15 Micron Technology, Inc. Low skew differential receiver with disable feature
US5940608A (en) 1997-02-11 1999-08-17 Micron Technology, Inc. Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal
US5987576A (en) * 1997-02-27 1999-11-16 Hewlett-Packard Company Method and apparatus for generating and distributing clock signals with minimal skew
US5977798A (en) * 1997-02-28 1999-11-02 Rambus Incorporated Low-latency small-swing clocked receiver
US6175894B1 (en) 1997-03-05 2001-01-16 Micron Technology, Inc. Memory device command buffer apparatus and method and memory devices and computer systems using same
US5956502A (en) * 1997-03-05 1999-09-21 Micron Technology, Inc. Method and circuit for producing high-speed counts
US5946244A (en) 1997-03-05 1999-08-31 Micron Technology, Inc. Delay-locked loop with binary-coupled capacitor
US5870347A (en) * 1997-03-11 1999-02-09 Micron Technology, Inc. Multi-bank memory input/output line selection
US5898638A (en) * 1997-03-11 1999-04-27 Micron Technology, Inc. Latching wordline driver for multi-bank memory
US6088761A (en) * 1997-03-31 2000-07-11 Sun Microsystems, Inc. Reduced pin system interface
US5831929A (en) * 1997-04-04 1998-11-03 Micron Technology, Inc. Memory device with staggered data paths
US5896404A (en) * 1997-04-04 1999-04-20 International Business Machines Corporation Programmable burst length DRAM
JP3189727B2 (en) 1997-04-15 2001-07-16 日本電気株式会社 Packet-type memory LSI with built-in coprocessor, memory system using the same, and control method therefor
AU7706198A (en) * 1997-05-30 1998-12-30 Micron Technology, Inc. 256 meg dynamic random access memory
TW378330B (en) 1997-06-03 2000-01-01 Fujitsu Ltd Semiconductor memory device
US6215192B1 (en) 1997-06-12 2001-04-10 Matsushita Electric Industrial Co., Ltd. Integrated circuit package and integrated circuit package control system
US6014759A (en) 1997-06-13 2000-01-11 Micron Technology, Inc. Method and apparatus for transferring test data from a memory array
US5996043A (en) 1997-06-13 1999-11-30 Micron Technology, Inc. Two step memory device command buffer apparatus and method and memory devices and computer systems using same
US5987614A (en) * 1997-06-17 1999-11-16 Vadem Distributed power management system and method for computer
US6484244B1 (en) 1997-06-17 2002-11-19 Micron Technology, Inc. Method and system for storing and processing multiple memory commands
US6115823A (en) * 1997-06-17 2000-09-05 Amphus, Inc. System and method for task performance based dynamic distributed power management in a computer system and design method therefor
US6173432B1 (en) 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US6266379B1 (en) 1997-06-20 2001-07-24 Massachusetts Institute Of Technology Digital transmitter with equalization
KR100213241B1 (en) * 1997-06-23 1999-08-02 윤종용 Data input output circuit and method
US6286062B1 (en) 1997-07-01 2001-09-04 Micron Technology, Inc. Pipelined packet-oriented memory system having a unidirectional command and address bus and a bidirectional data bus
US5953284A (en) * 1997-07-09 1999-09-14 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
US6044429A (en) 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
US5978869A (en) * 1997-07-21 1999-11-02 International Business Machines Corporation Enhanced dual speed bus computer system
US6011732A (en) * 1997-08-20 2000-01-04 Micron Technology, Inc. Synchronous clock generator including a compound delay-locked loop
US6044413A (en) * 1997-08-22 2000-03-28 Hewlett-Packard Company Method of concurrent bus operation for bus controlled devices operating in different contexts
US5926047A (en) * 1997-08-29 1999-07-20 Micron Technology, Inc. Synchronous clock generator including a delay-locked loop signal loss detector
US5940609A (en) * 1997-08-29 1999-08-17 Micorn Technology, Inc. Synchronous clock generator including a false lock detector
US6101197A (en) * 1997-09-18 2000-08-08 Micron Technology, Inc. Method and apparatus for adjusting the timing of signals over fine and coarse ranges
US5991841A (en) * 1997-09-24 1999-11-23 Intel Corporation Memory transactions on a low pin count bus
US6131127A (en) * 1997-09-24 2000-10-10 Intel Corporation I/O transactions on a low pin count bus
US6157970A (en) * 1997-09-24 2000-12-05 Intel Corporation Direct memory access system using time-multiplexing for transferring address, data, and control and a separate control line for serially transmitting encoded DMA channel number
US6119189A (en) * 1997-09-24 2000-09-12 Intel Corporation Bus master transactions on a low pin count bus
US6067594A (en) * 1997-09-26 2000-05-23 Rambus, Inc. High frequency bus system
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
WO1999019875A2 (en) * 1997-10-10 1999-04-22 Rambus Incorporated Apparatus and method for pipelined memory operations
AU9604698A (en) * 1997-10-10 1999-05-03 Rambus Incorporated Method and apparatus for two step memory write operations
JP4578676B2 (en) * 1997-10-10 2010-11-10 ラムバス・インコーポレーテッド Apparatus and method for compensating device timing
US6347354B1 (en) 1997-10-10 2002-02-12 Rambus Incorporated Apparatus and method for maximizing information transfers over limited interconnect resources
US6401167B1 (en) 1997-10-10 2002-06-04 Rambus Incorporated High performance cost optimized memory
US6133773A (en) * 1997-10-10 2000-10-17 Rambus Inc Variable delay element
US6513103B1 (en) 1997-10-10 2003-01-28 Rambus Inc. Method and apparatus for adjusting the performance of a synchronous memory system
KR100278650B1 (en) * 1997-11-07 2001-03-02 윤종용 Semiconductor memory device using a packet command
US6009488A (en) * 1997-11-07 1999-12-28 Microlinc, Llc Computer having packet-based interconnect channel
US6098114A (en) * 1997-11-14 2000-08-01 3Ware Disk array system for processing and tracking the completion of I/O requests
US6134630A (en) 1997-11-14 2000-10-17 3Ware High-performance bus architecture for disk array system
US6138176A (en) * 1997-11-14 2000-10-24 3Ware Disk array controller with automated processor which routes I/O data according to addresses and commands received from disk drive controllers
US6965974B1 (en) * 1997-11-14 2005-11-15 Agere Systems Inc. Dynamic partitioning of memory banks among multiple agents
US6078891A (en) * 1997-11-24 2000-06-20 Riordan; John Method and system for collecting and processing marketing data
CA2223119A1 (en) * 1997-11-28 1999-05-28 Mosaid Technologies Incorporated Address counter cell
KR100261218B1 (en) * 1997-12-08 2000-07-01 윤종용 Pin assignment method of semiconductor memory device & semiconductor memory device inputing packet signal
US6202119B1 (en) 1997-12-19 2001-03-13 Micron Technology, Inc. Method and system for processing pipelined memory commands
KR100252057B1 (en) * 1997-12-30 2000-05-01 윤종용 Semiconductor memory device usable in SDR and DDR
KR100272503B1 (en) 1998-01-26 2000-11-15 김영환 Rambus asic having high speed testing function and testing method thereof
GB9801654D0 (en) * 1998-01-26 1998-03-25 Memory Corp Plc Memory system
US6047346A (en) * 1998-02-02 2000-04-04 Rambus Inc. System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers
US5936877A (en) 1998-02-13 1999-08-10 Micron Technology, Inc. Die architecture accommodating high-speed semiconductor devices
US5923594A (en) * 1998-02-17 1999-07-13 Micron Technology, Inc. Method and apparatus for coupling data from a memory device using a single ended read data path
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
DE69941502D1 (en) * 1998-02-25 2009-11-19 Nxp Bv CONNECTING PERIPHERAL DEVICES TO A BUS VIA A SLAVE INTERFACE DEVICE
US6269451B1 (en) 1998-02-27 2001-07-31 Micron Technology, Inc. Method and apparatus for adjusting data timing by delaying clock signal
US6314527B1 (en) 1998-03-05 2001-11-06 Micron Technology, Inc. Recovery of useful areas of partially defective synchronous memory components
US6212482B1 (en) 1998-03-06 2001-04-03 Micron Technology, Inc. Circuit and method for specifying performance parameters in integrated circuits
US6154821A (en) * 1998-03-10 2000-11-28 Rambus Inc. Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain
US6327205B1 (en) 1998-03-16 2001-12-04 Jazio, Inc. Signal latching of high bandwidth DRAM arrays when skew between different components is higher than signal rate
TR200002649T2 (en) 1998-03-16 2000-11-21 Jazio Inc. High-speed signal generation for VLSI CMOS interface circuits.
US6160423A (en) * 1998-03-16 2000-12-12 Jazio, Inc. High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines
JP3259679B2 (en) * 1998-03-23 2002-02-25 日本電気株式会社 Semiconductor memory burn-in test circuit
US6122698A (en) * 1998-04-16 2000-09-19 Samsung Electronics Co., Ltd Data bus having conducting lines driven at multiple adjustable current levels to transfer multiple-bit data on each conducting line
US6456628B1 (en) * 1998-04-17 2002-09-24 Intelect Communications, Inc. DSP intercommunication network
US6381707B1 (en) 1998-04-28 2002-04-30 Micron Technology, Inc. System for decoding addresses for a defective memory array
US6381708B1 (en) 1998-04-28 2002-04-30 Micron Technology, Inc. Method for decoding addresses for a defective memory array
JPH11316617A (en) 1998-05-01 1999-11-16 Mitsubishi Electric Corp Semiconductor circuit device
US6216185B1 (en) 1998-05-01 2001-04-10 Acqis Technology, Inc. Personal computer peripheral console with attached computer module
US6345330B2 (en) 1998-05-01 2002-02-05 Acqis Technology, Inc. Communication channel and interface devices for bridging computer interface buses
US6275782B1 (en) * 1998-05-05 2001-08-14 Advanced Micro Devices, Inc. Non-intrusive performance monitoring
JP3727778B2 (en) * 1998-05-07 2005-12-14 株式会社東芝 Data high-speed transfer synchronization system and data high-speed transfer synchronization method
JP4226686B2 (en) * 1998-05-07 2009-02-18 株式会社東芝 Semiconductor memory system, semiconductor memory access control method, and semiconductor memory
US6016282A (en) * 1998-05-28 2000-01-18 Micron Technology, Inc. Clock vernier adjustment
US6496945B2 (en) * 1998-06-04 2002-12-17 Compaq Information Technologies Group, L.P. Computer system implementing fault detection and isolation using unique identification codes stored in non-volatile memory
US6405280B1 (en) 1998-06-05 2002-06-11 Micron Technology, Inc. Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence
US6453377B1 (en) 1998-06-16 2002-09-17 Micron Technology, Inc. Computer including optical interconnect, memory unit, and method of assembling a computer
US6615189B1 (en) * 1998-06-22 2003-09-02 Bank One, Delaware, National Association Debit purchasing of stored value card for use by and/or delivery to others
US6505276B1 (en) 1998-06-26 2003-01-07 Nec Corporation Processing-function-provided packet-type memory system and method for controlling the same
KR100292625B1 (en) * 1998-06-29 2001-07-12 박종섭 High speed interface device
US20010026533A1 (en) * 1998-07-06 2001-10-04 Andreas Schwager Method to perform a scheduled action of network devices
US6510503B2 (en) * 1998-07-27 2003-01-21 Mosaid Technologies Incorporated High bandwidth memory interface
US6175905B1 (en) 1998-07-30 2001-01-16 Micron Technology, Inc. Method and system for bypassing pipelines in a pipelined memory command generator
KR100306965B1 (en) * 1998-08-07 2001-11-30 윤종용 Data Transmission Circuit of Synchronous Semiconductor Memory Device
US6282210B1 (en) 1998-08-12 2001-08-28 Staktek Group L.P. Clock driver with instantaneously selectable phase and method for use in data communication systems
KR100295051B1 (en) * 1998-08-20 2001-07-12 윤종용 Input buffer for semiconductor memory device and input buffring method
US6285962B1 (en) * 1998-08-26 2001-09-04 Tanisys Technology, Inc. Method and system for testing rambus memory modules
US6338127B1 (en) 1998-08-28 2002-01-08 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same
US6424034B1 (en) 1998-08-31 2002-07-23 Micron Technology, Inc. High performance packaging for microprocessors and DRAM chips which minimizes timing skews
US6392296B1 (en) 1998-08-31 2002-05-21 Micron Technology, Inc. Silicon interposer with optical connections
US6219237B1 (en) 1998-08-31 2001-04-17 Micron Technology, Inc. Structure and method for an electronic assembly
US6586835B1 (en) 1998-08-31 2003-07-01 Micron Technology, Inc. Compact system module with built-in thermoelectric cooling
US6281042B1 (en) 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6374376B1 (en) * 1998-09-03 2002-04-16 Micron Technology, Inc. Circuit, system and method for arranging data output by semiconductor testers to packet-based devices under test
US6279090B1 (en) 1998-09-03 2001-08-21 Micron Technology, Inc. Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device
US6349399B1 (en) 1998-09-03 2002-02-19 Micron Technology, Inc. Method and apparatus for generating expect data from a captured bit pattern, and memory device using same
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6633947B1 (en) * 1998-09-16 2003-10-14 Intel Corporation Memory expansion channel for propagation of control and request packets
US6587912B2 (en) * 1998-09-30 2003-07-01 Intel Corporation Method and apparatus for implementing multiple memory buses on a memory module
US6321335B1 (en) 1998-10-30 2001-11-20 Acqis Technology, Inc. Password protected modular computer method and device
KR100275751B1 (en) * 1998-11-09 2000-12-15 윤종용 Semiconductor memory device having simple architecture
US6430696B1 (en) 1998-11-30 2002-08-06 Micron Technology, Inc. Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same
US6041016A (en) * 1998-12-04 2000-03-21 Intel Corporation Optimizing page size in mixed memory array using address multiplexing
US6374360B1 (en) 1998-12-11 2002-04-16 Micron Technology, Inc. Method and apparatus for bit-to-bit timing correction of a high speed memory bus
KR100327330B1 (en) 1998-12-17 2002-05-09 윤종용 Rambus DRAM semiconductor device
US6496876B1 (en) 1998-12-21 2002-12-17 Micron Technology, Inc. System and method for storing a tag to identify a functional storage location in a memory device
US6347350B1 (en) 1998-12-22 2002-02-12 Intel Corporation Driving the last inbound signal on a line in a bus with a termination
US6738844B2 (en) * 1998-12-23 2004-05-18 Intel Corporation Implementing termination with a default signal on a bus line
US6463494B1 (en) * 1998-12-30 2002-10-08 Intel Corporation Method and system for implementing control signals on a low pin count bus
US6457094B2 (en) * 1999-01-22 2002-09-24 Winbond Electronics Corporation Memory array architecture supporting block write operation
US6078532A (en) * 1999-02-01 2000-06-20 Cisco Technology Inc. Method and apparatus for improving performance of DRAM subsystems with SRAM overlays
US6255852B1 (en) 1999-02-09 2001-07-03 Micron Technology, Inc. Current mode signal interconnects and CMOS amplifier
GB2346990B (en) 1999-02-20 2003-07-09 Ibm Client/server transaction data processing system with automatic distributed coordinator set up into a linear chain for use of linear commit optimization
US6470060B1 (en) 1999-03-01 2002-10-22 Micron Technology, Inc. Method and apparatus for generating a phase dependent control signal
US6334163B1 (en) 1999-03-05 2001-12-25 International Business Machines Corp. Elastic interface apparatus and method therefor
US6330635B1 (en) 1999-04-16 2001-12-11 Intel Corporation Multiple user interfaces for an integrated flash device
US6381684B1 (en) 1999-04-26 2002-04-30 Integrated Device Technology, Inc. Quad data rate RAM
US6889299B1 (en) * 1999-04-27 2005-05-03 Seiko Epson Corporation Semiconductor integrated circuit
US6426984B1 (en) * 1999-05-07 2002-07-30 Rambus Incorporated Apparatus and method for reducing clock signal phase skew in a master-slave system with multiple latent clock cycles
US6643777B1 (en) 1999-05-14 2003-11-04 Acquis Technology, Inc. Data security method and device for computer modules
KR100594198B1 (en) * 1999-05-14 2006-07-03 삼성전자주식회사 Multichannel RAMBUS system
US6718415B1 (en) 1999-05-14 2004-04-06 Acqis Technology, Inc. Computer system and method including console housing multiple computer modules having independent processing units, mass storage devices, and graphics controllers
GB9912129D0 (en) * 1999-05-26 1999-07-28 3Com Corp Communication device with forwarding database having having a trie search facility
US6150845A (en) * 1999-06-01 2000-11-21 Fairchild Semiconductor Corp. Bus hold circuit with overvoltage tolerance
DE10081643D2 (en) 1999-06-10 2002-05-29 Pact Inf Tech Gmbh Sequence partitioning on cell structures
US6433786B1 (en) * 1999-06-10 2002-08-13 Intel Corporation Memory architecture for video graphics environment
US6211698B1 (en) 1999-06-29 2001-04-03 Hyundai Electronics Industries Co., Ltd. High speed interface apparatus
US7069406B2 (en) 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
US6442636B1 (en) * 1999-07-09 2002-08-27 Princeton Technology Corporation Parallel bus system capable of expanding peripheral devices
KR100297735B1 (en) 1999-07-13 2001-11-01 윤종용 Semiconductor memory device having effective arrangement of fuction blocks
KR100304707B1 (en) 1999-07-13 2001-11-01 윤종용 Reference voltage regulator capable of compensating drop of reference voltage and semiconductor memory device including the same
US6839393B1 (en) * 1999-07-14 2005-01-04 Rambus Inc. Apparatus and method for controlling a master/slave system via master device synchronization
US6370668B1 (en) 1999-07-23 2002-04-09 Rambus Inc High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes
US6813251B1 (en) 1999-07-27 2004-11-02 Intel Corporation Split Transaction protocol for a bus system
US7554829B2 (en) 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
US6477592B1 (en) 1999-08-06 2002-11-05 Integrated Memory Logic, Inc. System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream
US6467013B1 (en) 1999-09-30 2002-10-15 Intel Corporation Memory transceiver to couple an additional memory channel to an existing memory channel
US6851047B1 (en) 1999-10-15 2005-02-01 Xilinx, Inc. Configuration in a configurable system on a chip
US6396329B1 (en) * 1999-10-19 2002-05-28 Rambus, Inc Method and apparatus for receiving high speed signals with low latency
US7124221B1 (en) * 1999-10-19 2006-10-17 Rambus Inc. Low latency multi-level communication interface
US6643787B1 (en) * 1999-10-19 2003-11-04 Rambus Inc. Bus system optimization
US7161513B2 (en) * 1999-10-19 2007-01-09 Rambus Inc. Apparatus and method for improving resolution of a current mode driver
US7269212B1 (en) 2000-09-05 2007-09-11 Rambus Inc. Low-latency equalization in multi-level, multi-line communication systems
US6646953B1 (en) 2000-07-06 2003-11-11 Rambus Inc. Single-clock, strobeless signaling system
US6842789B1 (en) * 1999-10-21 2005-01-11 Sun Microsystems, Inc. Method and apparatus for assigning unique device identifiers across a distributed computing system
US7039047B1 (en) * 1999-11-03 2006-05-02 Intel Corporation Virtual wire signaling
US6643752B1 (en) * 1999-12-09 2003-11-04 Rambus Inc. Transceiver with latency alignment circuitry
US6557065B1 (en) 1999-12-20 2003-04-29 Intel Corporation CPU expandability bus
US6404660B1 (en) 1999-12-23 2002-06-11 Rambus, Inc. Semiconductor package with a controlled impedance bus and method of forming same
KR100316719B1 (en) * 1999-12-29 2001-12-13 윤종용 Output driver preventing degradation of channel bus line and memory module mounted semiconductor devices having thereof
US6516384B1 (en) * 1999-12-30 2003-02-04 Intel Corporation Method and apparatus to perform a round robin and locking cache replacement scheme
US6910146B2 (en) * 1999-12-31 2005-06-21 Intel Corporation Method and apparatus for improving timing margin in an integrated circuit as determined from recorded pass/fail indications for relative phase settings
US6647507B1 (en) 1999-12-31 2003-11-11 Intel Corporation Method for improving a timing margin in an integrated circuit by setting a relative phase of receive/transmit and distributed clock signals
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US20050010737A1 (en) * 2000-01-05 2005-01-13 Fred Ware Configurable width buffered module having splitter elements
US7010642B2 (en) * 2000-01-05 2006-03-07 Rambus Inc. System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
US7363422B2 (en) * 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US7266634B2 (en) * 2000-01-05 2007-09-04 Rambus Inc. Configurable width buffered module having flyby elements
US7404032B2 (en) * 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US6502161B1 (en) * 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
DE10002130A1 (en) 2000-01-19 2001-08-02 Infineon Technologies Ag Method and device for alternately operating a read-write memory in the one-memory operating mode and in the entangled multi-memory operating mode
US6600959B1 (en) * 2000-02-04 2003-07-29 International Business Machines Corporation Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays
US6987823B1 (en) * 2000-02-07 2006-01-17 Rambus Inc. System and method for aligning internal transmit and receive clocks
US6847644B1 (en) 2000-02-23 2005-01-25 Cypress Semiconductor Corp. Hybrid data transport scheme over optical networks
US7006525B1 (en) 2000-02-23 2006-02-28 Cypress Semiconductor Corp. Hybrid data transport scheme over optical networks
US6999479B1 (en) 2000-02-23 2006-02-14 Cypress Semiconductor Corp. Hybrid data transport scheme over optical networks
US6778561B1 (en) 2000-02-23 2004-08-17 Cypress Semiconductor Corp. Hybrid data transport scheme over optical networks
US6973084B1 (en) 2000-02-23 2005-12-06 Cypress Semiconductor Corp. Hybrid data transport scheme over optical networks
JP3663106B2 (en) * 2000-02-28 2005-06-22 東芝機械株式会社 Data input / output device
US6198666B1 (en) * 2000-02-29 2001-03-06 International Business Machines Corporation Control input timing-independent dynamic multiplexer circuit
EP1130516A1 (en) * 2000-03-01 2001-09-05 Hewlett-Packard Company, A Delaware Corporation Address mapping in solid state storage device
US6578157B1 (en) 2000-03-06 2003-06-10 Micron Technology, Inc. Method and apparatus for recovery of useful areas of partially defective direct rambus rimm components
JP3980807B2 (en) * 2000-03-27 2007-09-26 株式会社東芝 Semiconductor device and semiconductor module
US6980314B1 (en) * 2000-04-03 2005-12-27 Hewlett-Packard Development Company, L.P. Method and device for improving utilization of a bus
US7269765B1 (en) * 2000-04-13 2007-09-11 Micron Technology, Inc. Method and apparatus for storing failing part locations in a module
US6556952B1 (en) 2000-05-04 2003-04-29 Advanced Micro Devices, Inc. Performance monitoring and optimizing of controller parameters
US6606041B1 (en) 2000-05-10 2003-08-12 Micron Technology, Inc. Predictive timing calibration for memory devices
US6889357B1 (en) * 2000-05-10 2005-05-03 Micron Technology, Inc. Timing calibration pattern for SLDRAM
US6434081B1 (en) 2000-05-12 2002-08-13 Micron Technology, Inc. Calibration technique for memory devices
US6369652B1 (en) 2000-05-15 2002-04-09 Rambus Inc. Differential amplifiers with current and resistance compensation elements for balanced output
US6535966B1 (en) * 2000-05-17 2003-03-18 Sun Microsystems, Inc. System and method for using a page tracking buffer to reduce main memory latency in a computer system
US6791555B1 (en) * 2000-06-23 2004-09-14 Micron Technology, Inc. Apparatus and method for distributed memory control in a graphics processing system
US6937664B1 (en) 2000-07-18 2005-08-30 Integrated Memory Logic, Inc. System and method for multi-symbol interfacing
DE10036643B4 (en) 2000-07-26 2005-12-22 Robert Bosch Gmbh Method and device for selecting peripheral elements
US6587804B1 (en) 2000-08-14 2003-07-01 Micron Technology, Inc. Method and apparatus providing improved data path calibration for memory devices
US6535450B1 (en) 2000-08-18 2003-03-18 Micron Technology, Inc. Method for selecting one or a bank of memory devices
KR100389916B1 (en) * 2000-08-28 2003-07-04 삼성전자주식회사 Memory module and memory controller
US6704881B1 (en) * 2000-08-31 2004-03-09 Micron Technology, Inc. Method and apparatus for providing symmetrical output data for a double data rate DRAM
US6862653B1 (en) 2000-09-18 2005-03-01 Intel Corporation System and method for controlling data flow direction in a memory system
US6530006B1 (en) 2000-09-18 2003-03-04 Intel Corporation System and method for providing reliable transmission in a buffered memory system
US6625685B1 (en) * 2000-09-20 2003-09-23 Broadcom Corporation Memory controller with programmable configuration
US6772352B1 (en) 2000-09-29 2004-08-03 Intel Corporation Method and apparatus for reducing the rate of commands being issued if the rate exceeds a threshold which is based upon a temperature curve
US6385094B1 (en) 2000-09-29 2002-05-07 Intel Corporation Method and apparatus for achieving efficient memory subsystem write-to-read turnaround through read posting
US6553449B1 (en) 2000-09-29 2003-04-22 Intel Corporation System and method for providing concurrent row and column commands
US6735709B1 (en) * 2000-11-09 2004-05-11 Micron Technology, Inc. Method of timing calibration using slower data rate pattern
US20020107943A1 (en) * 2000-11-10 2002-08-08 Heath Chester A. Reset control in modular network computers
US6628528B2 (en) 2000-11-30 2003-09-30 Theodore Zale Schoenborn Current sharing in memory packages
US6580619B2 (en) * 2000-11-30 2003-06-17 Intel Corporation Multilayer reference plane in package devices
JPWO2002050910A1 (en) * 2000-12-01 2004-04-22 株式会社日立製作所 Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device
US6925086B2 (en) * 2000-12-12 2005-08-02 International Business Machines Corporation Packet memory system
FR2818774B1 (en) * 2000-12-22 2003-03-21 Wany Engineering Sas PARALLEL ELECTRONIC ARCHITECTURE CONTAINING A PLURALITY OF PROCESSING UNITS CONNECTED TO A COMMUNICATION BUS, AND ADDRESSABLE BY THEIR FUNCTIONALITIES
GB2382899B (en) * 2000-12-29 2003-12-17 Zarlink Semiconductor Ltd A data queue system
US6889336B2 (en) 2001-01-05 2005-05-03 Micron Technology, Inc. Apparatus for improving output skew for synchronous integrate circuits has delay circuit for generating unique clock signal by applying programmable delay to delayed clock signal
DE10101553C1 (en) * 2001-01-15 2002-07-25 Infineon Technologies Ag Semiconductor memory with delay control loop
US6700827B2 (en) 2001-02-08 2004-03-02 Integrated Device Technology, Inc. Cam circuit with error correction
US6587936B1 (en) 2001-02-21 2003-07-01 Cisco Technology, Inc. Multi-bank memory access method and apparatus
US7123660B2 (en) * 2001-02-27 2006-10-17 Jazio, Inc. Method and system for deskewing parallel bus channels to increase data transfer rates
US6788593B2 (en) 2001-02-28 2004-09-07 Rambus, Inc. Asynchronous, high-bandwidth memory component using calibrated timing elements
US7610447B2 (en) 2001-02-28 2009-10-27 Rambus Inc. Upgradable memory system with reconfigurable interconnect
US6889304B2 (en) 2001-02-28 2005-05-03 Rambus Inc. Memory device supporting a dynamically configurable core organization
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US9141390B2 (en) 2001-03-05 2015-09-22 Pact Xpp Technologies Ag Method of processing data with an array of data processors according to application ID
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
DE60227498D1 (en) * 2001-03-23 2008-08-21 Advanced Bionutrition Corp DISTRIBUTION OF AGENTS FOR THE CONTROL OF AFFECTS IN AQUACULTURE USING BIOACTIVE PROTEINS CONTAINING YEAST
US6934823B2 (en) * 2001-03-29 2005-08-23 Intel Corporation Method and apparatus for handling memory read return data from different time domains
US7500075B1 (en) 2001-04-17 2009-03-03 Rambus Inc. Mechanism for enabling full data bus utilization without increasing data granularity
US7263148B2 (en) * 2001-04-20 2007-08-28 Mastek International Source synchronous CDMA bus interface
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US8391039B2 (en) * 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
KR100412130B1 (en) 2001-05-25 2003-12-31 주식회사 하이닉스반도체 Circuit for control output current of rambus dram
US6532162B2 (en) 2001-05-26 2003-03-11 Intel Corporation Reference plane of integrated circuit packages
ITMI20011150A1 (en) * 2001-05-30 2002-11-30 St Microelectronics Srl COLUMN MULTIPLATOR FOR SEMICONDUCTOR MEMORIES
KR100434270B1 (en) * 2001-05-30 2004-06-04 엘지전자 주식회사 Control System for Home Appliance Network
DE10126610B4 (en) * 2001-05-31 2007-11-29 Infineon Technologies Ag Memory module and method for testing a semiconductor chip
US20020191621A1 (en) * 2001-06-14 2002-12-19 Cypress Semiconductor Corp. Programmable protocol processing engine for network packet devices
US20020194363A1 (en) * 2001-06-14 2002-12-19 Cypress Semiconductor Corp. Programmable protocol processing engine for network packet devices
US20030023492A1 (en) * 2001-06-20 2003-01-30 John Riordan Method and system for collecting and processing marketing data
US10031733B2 (en) 2001-06-20 2018-07-24 Scientia Sol Mentis Ag Method for processing data
US6801989B2 (en) 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US6710616B1 (en) * 2001-07-30 2004-03-23 Lsi Logic Corporation Wafer level dynamic burn-in
KR100422585B1 (en) * 2001-08-08 2004-03-12 주식회사 하이닉스반도체 Ring - register controlled DLL and its method
US6806728B2 (en) * 2001-08-15 2004-10-19 Rambus, Inc. Circuit and method for interfacing to a bus channel
US7941056B2 (en) * 2001-08-30 2011-05-10 Micron Technology, Inc. Optical interconnect in high-speed memory systems
US6724665B2 (en) * 2001-08-31 2004-04-20 Matrix Semiconductor, Inc. Memory device and method for selectable sub-array activation
US6735546B2 (en) 2001-08-31 2004-05-11 Matrix Semiconductor, Inc. Memory device and method for temperature-based control over write and/or read operations
US7107374B1 (en) 2001-09-05 2006-09-12 Xilinx, Inc. Method for bus mastering for devices resident in configurable system logic
JP4000028B2 (en) * 2001-09-18 2007-10-31 株式会社東芝 Synchronous semiconductor memory device
DE10147138B4 (en) * 2001-09-25 2009-01-22 Qimonda Ag Method for integrating imperfect semiconductor memory devices in data processing devices
JP3959264B2 (en) * 2001-09-29 2007-08-15 株式会社東芝 Multilayer semiconductor device
JP4308461B2 (en) * 2001-10-05 2009-08-05 ラムバス・インコーポレーテッド Semiconductor memory device
US20030074434A1 (en) * 2001-10-11 2003-04-17 Jason James L. Determination of message source in network communications
EP1446910B1 (en) 2001-10-22 2010-08-11 Rambus Inc. Phase adjustment apparatus and method for a memory device signaling system
US6542416B1 (en) 2001-11-02 2003-04-01 Rambus Inc. Methods and arrangements for conditionally enforcing CAS latencies in memory devices
US6838712B2 (en) * 2001-11-26 2005-01-04 Micron Technology, Inc. Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
US20030101312A1 (en) * 2001-11-26 2003-05-29 Doan Trung T. Machine state storage apparatus and method
KR100557550B1 (en) 2001-12-21 2006-03-03 주식회사 하이닉스반도체 Clock synchronization circuit
JP4204226B2 (en) * 2001-12-28 2009-01-07 日本テキサス・インスツルメンツ株式会社 Device identification method, data transmission method, device identifier assigning apparatus, and device
US7099922B2 (en) * 2002-01-23 2006-08-29 International Business Machines Corporation Method and system for simultaneous management of multiple tokens on a communication ring
US7101770B2 (en) 2002-01-30 2006-09-05 Micron Technology, Inc. Capacitive techniques to reduce noise in high speed interconnections
US7698230B1 (en) * 2002-02-15 2010-04-13 ContractPal, Inc. Transaction architecture utilizing transaction policy statements
KR100412142B1 (en) * 2002-02-26 2003-12-31 주식회사 하이닉스반도체 Circuit for implementing a special mode in a semiconductor memory device of packet transmission method
US7174401B2 (en) 2002-02-28 2007-02-06 Lsi Logic Corporation Look ahead split release for a data bus
TWI235919B (en) * 2002-03-05 2005-07-11 Via Tech Inc Data-transmission control method
US6751113B2 (en) * 2002-03-07 2004-06-15 Netlist, Inc. Arrangement of integrated circuits in a memory module
US7235457B2 (en) 2002-03-13 2007-06-26 Micron Technology, Inc. High permeability layered films to reduce noise in high speed interconnects
US7689022B2 (en) 2002-03-15 2010-03-30 Affymetrix, Inc. System, method, and product for scanning of biological materials
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US7135903B2 (en) * 2002-09-03 2006-11-14 Rambus Inc. Phase jumping locked loop circuit
US6911853B2 (en) * 2002-03-22 2005-06-28 Rambus Inc. Locked loop with dual rail regulation
US6952123B2 (en) 2002-03-22 2005-10-04 Rambus Inc. System with dual rail regulated locked loop
US6759881B2 (en) * 2002-03-22 2004-07-06 Rambus Inc. System with phase jumping locked loop circuit
US6922091B2 (en) 2002-09-03 2005-07-26 Rambus Inc. Locked loop circuit with clock hold function
FR2838006B1 (en) * 2002-04-02 2004-11-12 St Microelectronics Sa DEVICE AND METHOD FOR SYNCHRONIZING A DATA EXCHANGE WITH A REMOTE MEMBER
US6563730B1 (en) 2002-04-09 2003-05-13 National Semiconductor Corporation Low power static RAM architecture
US6762961B2 (en) * 2002-04-16 2004-07-13 Sun Microsystems, Inc. Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier
US6948019B2 (en) * 2002-04-30 2005-09-20 Lsi Logic Corporation Apparatus for arbitrating non-queued split master devices on a data bus
US7231306B1 (en) * 2002-04-30 2007-06-12 Rambus Inc. Method and apparatus for calibrating static timing offsets across multiple outputs
US7020208B1 (en) 2002-05-03 2006-03-28 Pericom Semiconductor Corp. Differential clock signals encoded with data
US7133972B2 (en) 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
KR100437467B1 (en) * 2002-07-03 2004-06-23 삼성전자주식회사 Multi-chip system having continuous burst read mode of operation
US6944091B2 (en) * 2002-07-10 2005-09-13 Samsung Electronics Co., Ltd. Latency control circuit and method of latency control
US7149824B2 (en) 2002-07-10 2006-12-12 Micron Technology, Inc. Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction
US7298667B2 (en) * 2002-07-10 2007-11-20 Samsung Electronic Co., Ltd. Latency control circuit and method of latency control
KR100486250B1 (en) * 2002-07-10 2005-05-03 삼성전자주식회사 Latency control circuit and Method there-of for high frequency operation in synchronous semiconductor device
US7362800B1 (en) 2002-07-12 2008-04-22 Rambus Inc. Auto-configured equalizer
US8861667B1 (en) 2002-07-12 2014-10-14 Rambus Inc. Clock data recovery circuit with equalizer clock calibration
US7292629B2 (en) 2002-07-12 2007-11-06 Rambus Inc. Selectable-tap equalizer
US7200024B2 (en) * 2002-08-02 2007-04-03 Micron Technology, Inc. System and method for optically interconnecting memory devices
US7117316B2 (en) * 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US7254331B2 (en) * 2002-08-09 2007-08-07 Micron Technology, Inc. System and method for multiple bit optical data transmission in memory systems
US7149874B2 (en) * 2002-08-16 2006-12-12 Micron Technology, Inc. Memory hub bypass circuit and method
US7124260B2 (en) * 2002-08-26 2006-10-17 Micron Technology, Inc. Modified persistent auto precharge command protocol system and method for memory devices
US7081896B1 (en) * 2002-08-27 2006-07-25 Nvidia Corporation Memory request timing randomizer
US6820181B2 (en) * 2002-08-29 2004-11-16 Micron Technology, Inc. Method and system for controlling memory accesses to memory modules having a memory hub architecture
US7836252B2 (en) 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US6711051B1 (en) 2002-09-05 2004-03-23 National Semiconductor Corporation Static RAM architecture with bit line partitioning
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7102907B2 (en) * 2002-09-09 2006-09-05 Micron Technology, Inc. Wavelength division multiplexed memory module, memory system and method
US20040054864A1 (en) * 2002-09-13 2004-03-18 Jameson Neil Andrew Memory controller
US20040064686A1 (en) * 2002-09-30 2004-04-01 Miller Gregory L. Method and apparatus for marking current memory configuration
US6859434B2 (en) 2002-10-01 2005-02-22 Comsys Communication & Signal Processing Ltd. Data transfer scheme in a communications system incorporating multiple processing elements
US6982926B2 (en) * 2002-10-04 2006-01-03 Pgs Americas, Inc. Apparatus and method for bubble shielding towed marine cable
US20040081179A1 (en) * 2002-10-23 2004-04-29 Gregorcyk Arthur J. Method and system for selecting between serial storage buses using data signals of the buses
JP3773195B2 (en) * 2002-10-25 2006-05-10 インターナショナル・ビジネス・マシーンズ・コーポレーション Memory module, information processing apparatus, initial setting method for memory module, and program
US6879526B2 (en) * 2002-10-31 2005-04-12 Ring Technology Enterprises Llc Methods and apparatus for improved memory access
US7707351B2 (en) * 2002-10-31 2010-04-27 Ring Technology Enterprises Of Texas, Llc Methods and systems for an identifier-based memory section
US7197662B2 (en) * 2002-10-31 2007-03-27 Ring Technology Enterprises, Llc Methods and systems for a storage system
US7415565B2 (en) * 2002-10-31 2008-08-19 Ring Technology Enterprises, Llc Methods and systems for a storage system with a program-controlled switch for routing data
US6954394B2 (en) * 2002-11-27 2005-10-11 Matrix Semiconductor, Inc. Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions
US7051229B2 (en) * 2002-12-03 2006-05-23 Alcatel Canada Inc. Logical bus overlay for increasing the existing system bus data rate
KR100506062B1 (en) * 2002-12-18 2005-08-05 주식회사 하이닉스반도체 Composite Memory Device
KR100506448B1 (en) * 2002-12-27 2005-08-08 주식회사 하이닉스반도체 Device for controlling interleave using non-volatile ferroelectric memory
US7362697B2 (en) * 2003-01-09 2008-04-22 International Business Machines Corporation Self-healing chip-to-chip interface
US6826663B2 (en) * 2003-01-13 2004-11-30 Rambus Inc. Coded write masking
WO2004063906A2 (en) * 2003-01-13 2004-07-29 Rambus Inc. Coded write masking
DE10302128B3 (en) * 2003-01-21 2004-09-09 Infineon Technologies Ag Buffer amplifier system for buffer storage of signals runs several DRAM chips in parallel and has two output buffer amplifiers in parallel feeding reference and signal networks with capacitors and DRAMs
KR100507367B1 (en) * 2003-01-24 2005-08-05 주식회사 하이닉스반도체 Device for controlling serial bus using non-volatile ferroelectric memory
US6967896B2 (en) * 2003-01-30 2005-11-22 Saifun Semiconductors Ltd Address scramble
DE10307548A1 (en) * 2003-02-21 2004-09-09 Infineon Technologies Ag Synchronous memory system for computer, has memory ranks with one-to-one correspondence with elements of select command segment
JP2004259318A (en) * 2003-02-24 2004-09-16 Renesas Technology Corp Synchronous semiconductor memory device
JP2004265265A (en) * 2003-03-04 2004-09-24 Matsushita Electric Ind Co Ltd Data transfer control device
CN100337269C (en) * 2003-04-08 2007-09-12 华为技术有限公司 Method for matching speech packet collection retransmission entity with coding and decoding entity
US20050044174A1 (en) * 2003-04-11 2005-02-24 Sun Microsystems, Inc. Multi-node computer system where active devices selectively initiate certain transactions using remote-type address packets
US7234099B2 (en) * 2003-04-14 2007-06-19 International Business Machines Corporation High reliability memory module with a fault tolerant address and command bus
US6741111B1 (en) 2003-04-21 2004-05-25 Pericom Semiconductor Corp. Data register for buffering double-data-rate DRAMs with reduced data-input-path power consumption
US7028155B2 (en) * 2003-04-22 2006-04-11 Hewlett-Packard Development Company, L.P. Master-slave data management system and method
US6996785B1 (en) 2003-04-25 2006-02-07 Universal Network Machines, Inc . On-chip packet-based interconnections using repeaters/routers
US7287143B2 (en) * 2003-04-30 2007-10-23 Hynix Semiconductor Inc. Synchronous memory device having advanced data align circuit
US7266679B2 (en) * 2003-05-01 2007-09-04 Dell Products L.P. System and method for reducing instability in an information handling system
US20040225944A1 (en) * 2003-05-09 2004-11-11 Brueggen Christopher M. Systems and methods for processing an error correction code word for storage in memory components
US7392347B2 (en) * 2003-05-10 2008-06-24 Hewlett-Packard Development Company, L.P. Systems and methods for buffering data between a coherency cache controller and memory
US20050166006A1 (en) * 2003-05-13 2005-07-28 Advanced Micro Devices, Inc. System including a host connected serially in a chain to one or more memory modules that include a cache
US20040232956A1 (en) * 2003-05-22 2004-11-25 Rambus Inc Synchronized clocking
DE10323415A1 (en) * 2003-05-23 2004-12-30 Infineon Technologies Ag Data storage arrangement with control device and memory unit for computers and processors
US6838902B1 (en) * 2003-05-28 2005-01-04 Actel Corporation Synchronous first-in/first-out block memory for a field programmable gate array
US7194581B2 (en) * 2003-06-03 2007-03-20 Intel Corporation Memory channel with hot add/remove
US7200787B2 (en) * 2003-06-03 2007-04-03 Intel Corporation Memory channel utilizing permuting status patterns
US7127629B2 (en) * 2003-06-03 2006-10-24 Intel Corporation Redriving a data signal responsive to either a sampling clock signal or stable clock signal dependent on a mode signal
US8171331B2 (en) * 2003-06-04 2012-05-01 Intel Corporation Memory channel having deskew separate from redrive
US7340537B2 (en) * 2003-06-04 2008-03-04 Intel Corporation Memory channel with redundant presence detect
US7165153B2 (en) 2003-06-04 2007-01-16 Intel Corporation Memory channel with unidirectional links
US7386768B2 (en) 2003-06-05 2008-06-10 Intel Corporation Memory channel with bit lane fail-over
US7245145B2 (en) * 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US7168027B2 (en) 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7047385B1 (en) * 2003-06-16 2006-05-16 Cisco Technology, Inc. High-speed memory for use in networking systems
US7120727B2 (en) * 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7260685B2 (en) * 2003-06-20 2007-08-21 Micron Technology, Inc. Memory hub and access method having internal prefetch buffers
US7107415B2 (en) * 2003-06-20 2006-09-12 Micron Technology, Inc. Posted write buffers and methods of posting write requests in memory modules
US7428644B2 (en) * 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
DE10328658A1 (en) 2003-06-26 2005-02-10 Infineon Technologies Ag Hub module for one or more memory modules
DE10330593B4 (en) * 2003-07-07 2010-11-04 Qimonda Ag Integrated clock supply module for a memory module, memory module, which includes the integrated clock supply module, as well as methods for operating the memory module under test conditions
US7356627B2 (en) * 2003-07-10 2008-04-08 Nokia Corporation Device identification
US6987684B1 (en) 2003-07-15 2006-01-17 Integrated Device Technology, Inc. Content addressable memory (CAM) devices having multi-block error detection logic and entry selective error correction logic therein
US6870749B1 (en) 2003-07-15 2005-03-22 Integrated Device Technology, Inc. Content addressable memory (CAM) devices with dual-function check bit cells that support column redundancy and check bit cells with reduced susceptibility to soft errors
US7193876B1 (en) 2003-07-15 2007-03-20 Kee Park Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors
US7389364B2 (en) * 2003-07-22 2008-06-17 Micron Technology, Inc. Apparatus and method for direct memory access in a hub-based memory system
US7428245B1 (en) * 2003-08-01 2008-09-23 Staccato Communications, Inc. Split medium access and control layer communications system
US6861884B1 (en) * 2003-08-04 2005-03-01 Rambus Inc. Phase synchronization for wide area integrated circuits
US7317415B2 (en) 2003-08-08 2008-01-08 Affymetrix, Inc. System, method, and product for scanning of biological materials employing dual analog integrators
US7210059B2 (en) * 2003-08-19 2007-04-24 Micron Technology, Inc. System and method for on-board diagnostics of memory modules
US7133991B2 (en) 2003-08-20 2006-11-07 Micron Technology, Inc. Method and system for capturing and bypassing memory transactions in a hub-based memory system
US7136958B2 (en) * 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
US20050050237A1 (en) * 2003-08-28 2005-03-03 Jeddeloh Joseph M. Memory module and method having on-board data search capabilities and processor-based system using such memory modules
US7084894B2 (en) * 2003-09-12 2006-08-01 Hewlett-Packard Development Company, L.P. Optical disc drive focusing apparatus
US7310752B2 (en) * 2003-09-12 2007-12-18 Micron Technology, Inc. System and method for on-board timing margin testing of memory modules
US6961276B2 (en) * 2003-09-17 2005-11-01 International Business Machines Corporation Random access memory having an adaptable latency
US7177201B1 (en) 2003-09-17 2007-02-13 Sun Microsystems, Inc. Negative bias temperature instability (NBTI) preconditioning of matched devices
US7194593B2 (en) 2003-09-18 2007-03-20 Micron Technology, Inc. Memory hub with integrated non-volatile memory
US20050063506A1 (en) * 2003-09-23 2005-03-24 Sony Corporation Method and system for jitter correction
US7057958B2 (en) * 2003-09-30 2006-06-06 Sandisk Corporation Method and system for temperature compensation for memory cells with temperature-dependent behavior
US7164612B1 (en) 2003-10-10 2007-01-16 Sun Microsystems, Inc. Test circuit for measuring sense amplifier and memory mismatches
US7020035B1 (en) 2003-10-10 2006-03-28 Sun Microsystems, Inc. Measuring and correcting sense amplifier and memory mismatches using NBTI
US7120743B2 (en) * 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7234070B2 (en) * 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
US7237042B2 (en) * 2003-10-29 2007-06-26 Intel Corporation Mechanism for generating a virtual identifier
US7243205B2 (en) * 2003-11-13 2007-07-10 Intel Corporation Buffered memory module with implicit to explicit memory command expansion
US7177211B2 (en) * 2003-11-13 2007-02-13 Intel Corporation Memory channel test fixture and method
US7065666B2 (en) * 2003-11-13 2006-06-20 Micron Technology, Inc. Apparatus and method for generating a delayed clock signal
US7143207B2 (en) * 2003-11-14 2006-11-28 Intel Corporation Data accumulation between data path having redrive circuit and memory device
US7447953B2 (en) 2003-11-14 2008-11-04 Intel Corporation Lane testing with variable mapping
US7219294B2 (en) * 2003-11-14 2007-05-15 Intel Corporation Early CRC delivery for partial frame
JP2005182872A (en) * 2003-12-17 2005-07-07 Toshiba Corp Nonvolatile semiconductor memory device
US7304875B1 (en) 2003-12-17 2007-12-04 Integrated Device Technology. Inc. Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same
JP2005190036A (en) * 2003-12-25 2005-07-14 Hitachi Ltd Storage controller and control method for storage controller
JP4741226B2 (en) * 2003-12-25 2011-08-03 株式会社日立製作所 Semiconductor memory module and memory system
US7330992B2 (en) 2003-12-29 2008-02-12 Micron Technology, Inc. System and method for read synchronization of memory modules
US7631138B2 (en) * 2003-12-30 2009-12-08 Sandisk Corporation Adaptive mode switching of flash memory address mapping based on host usage characteristics
US8504798B2 (en) * 2003-12-30 2013-08-06 Sandisk Technologies Inc. Management of non-volatile memory systems having large erase blocks
US8250295B2 (en) 2004-01-05 2012-08-21 Smart Modular Technologies, Inc. Multi-rank memory module that emulates a memory module having a different number of ranks
KR100558557B1 (en) * 2004-01-20 2006-03-10 삼성전자주식회사 Method for data sampling for ues in semiconductor memory device and circuits thereof
US7042777B2 (en) * 2004-01-28 2006-05-09 Infineon Technologies Ag Memory device with non-variable write latency
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module
US7188219B2 (en) 2004-01-30 2007-03-06 Micron Technology, Inc. Buffer control system and method for a memory system having outstanding read and write request buffers
US7412574B2 (en) * 2004-02-05 2008-08-12 Micron Technology, Inc. System and method for arbitration of memory responses in a hub-based memory system
US7181584B2 (en) * 2004-02-05 2007-02-20 Micron Technology, Inc. Dynamic command and/or address mirroring system and method for memory modules
US7788451B2 (en) * 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
KR100604836B1 (en) 2004-02-26 2006-07-26 삼성전자주식회사 Memory system employing simultaneous bi-directional input/output circuit on address bus line
US7916574B1 (en) 2004-03-05 2011-03-29 Netlist, Inc. Circuit providing load isolation and memory domain translation for memory module
US7289386B2 (en) 2004-03-05 2007-10-30 Netlist, Inc. Memory module decoder
US7366864B2 (en) 2004-03-08 2008-04-29 Micron Technology, Inc. Memory hub architecture having programmable lane widths
US7257683B2 (en) * 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
US7120723B2 (en) 2004-03-25 2006-10-10 Micron Technology, Inc. System and method for memory hub-based expansion bus
US7447240B2 (en) * 2004-03-29 2008-11-04 Micron Technology, Inc. Method and system for synchronizing communications links in a hub-based memory system
US7902938B2 (en) 2004-03-29 2011-03-08 Nec Corporation Data transmitter, data transmission line, and data transmission method
US7213082B2 (en) 2004-03-29 2007-05-01 Micron Technology, Inc. Memory hub and method for providing memory sequencing hints
US6980042B2 (en) * 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US7590797B2 (en) * 2004-04-08 2009-09-15 Micron Technology, Inc. System and method for optimizing interconnections of components in a multichip memory module
US7142479B2 (en) 2004-04-19 2006-11-28 Nokia Corporation Addressing data within dynamic random access memory
TWI252409B (en) * 2004-04-26 2006-04-01 Sunplus Technology Co Ltd Enhanced expandable time-sharing bus device
US7162567B2 (en) * 2004-05-14 2007-01-09 Micron Technology, Inc. Memory hub and method for memory sequencing
US7222213B2 (en) * 2004-05-17 2007-05-22 Micron Technology, Inc. System and method for communicating the synchronization status of memory modules during initialization of the memory modules
US20050259692A1 (en) * 2004-05-19 2005-11-24 Zerbe Jared L Crosstalk minimization in serial link systems
DE102004025984A1 (en) * 2004-05-26 2005-12-15 Sms Demag Ag Method and device for assembly and functional testing of rolling fittings in rolling mills or in rolling mills, such as tandem rolling mills
US7363419B2 (en) * 2004-05-28 2008-04-22 Micron Technology, Inc. Method and system for terminating write commands in a hub-based memory system
US7212423B2 (en) * 2004-05-31 2007-05-01 Intel Corporation Memory agent core clock aligned to lane
US7519788B2 (en) * 2004-06-04 2009-04-14 Micron Technology, Inc. System and method for an asynchronous data buffer having buffer write and read pointers
US7310748B2 (en) * 2004-06-04 2007-12-18 Micron Technology, Inc. Memory hub tester interface and method for use thereof
JP4610235B2 (en) * 2004-06-07 2011-01-12 ルネサスエレクトロニクス株式会社 Hierarchical module
US20060004953A1 (en) * 2004-06-30 2006-01-05 Vogt Pete D Method and apparatus for increased memory bandwidth
US7383399B2 (en) * 2004-06-30 2008-06-03 Intel Corporation Method and apparatus for memory compression
DE102004031715B4 (en) * 2004-06-30 2013-05-29 Globalfoundries Inc. Combined on-chip command and response data interface
DE102004032943A1 (en) * 2004-07-07 2006-02-02 Siemens Ag Central processing unit access time point controlling method for micro controller, involves executing access action, with which cycle time is allocated to access category, for availability release of availability control on external circuit
US7254659B2 (en) * 2004-07-26 2007-08-07 Motorola, Inc. Method of VMEbus split-read transaction
US7224595B2 (en) 2004-07-30 2007-05-29 International Business Machines Corporation 276-Pin buffered memory module with enhanced fault tolerance
US7389375B2 (en) 2004-07-30 2008-06-17 International Business Machines Corporation System, method and storage medium for a multi-mode memory buffer device
US7296129B2 (en) * 2004-07-30 2007-11-13 International Business Machines Corporation System, method and storage medium for providing a serialized memory interface with a bus repeater
US7539800B2 (en) * 2004-07-30 2009-05-26 International Business Machines Corporation System, method and storage medium for providing segment level sparing
US20060036826A1 (en) * 2004-07-30 2006-02-16 International Business Machines Corporation System, method and storage medium for providing a bus speed multiplier
US7287235B1 (en) * 2004-08-06 2007-10-23 Calypto Design Systems, Inc. Method of simplifying a circuit for equivalence checking
US7366942B2 (en) * 2004-08-12 2008-04-29 Micron Technology, Inc. Method and apparatus for high-speed input sampling
US8190808B2 (en) 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7392331B2 (en) * 2004-08-31 2008-06-24 Micron Technology, Inc. System and method for transmitting data packets in a computer system having a memory hub architecture
US7301831B2 (en) * 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
US7324403B2 (en) * 2004-09-24 2008-01-29 Intel Corporation Latency normalization by balancing early and late clocks
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US7254075B2 (en) 2004-09-30 2007-08-07 Rambus Inc. Integrated circuit memory system having dynamic memory bank count and page size
EP1647989A1 (en) * 2004-10-18 2006-04-19 Dialog Semiconductor GmbH Dynamical adaption of memory sense electronics
US7299313B2 (en) * 2004-10-29 2007-11-20 International Business Machines Corporation System, method and storage medium for a memory subsystem command interface
US7356737B2 (en) * 2004-10-29 2008-04-08 International Business Machines Corporation System, method and storage medium for testing a memory module
US7395476B2 (en) * 2004-10-29 2008-07-01 International Business Machines Corporation System, method and storage medium for providing a high speed test interface to a memory subsystem
US7305574B2 (en) * 2004-10-29 2007-12-04 International Business Machines Corporation System, method and storage medium for bus calibration in a memory subsystem
US7441060B2 (en) 2004-10-29 2008-10-21 International Business Machines Corporation System, method and storage medium for providing a service interface to a memory system
US7277988B2 (en) 2004-10-29 2007-10-02 International Business Machines Corporation System, method and storage medium for providing data caching and data compression in a memory subsystem
US7331010B2 (en) * 2004-10-29 2008-02-12 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
US7512762B2 (en) 2004-10-29 2009-03-31 International Business Machines Corporation System, method and storage medium for a memory subsystem with positional read data latency
US7310704B1 (en) * 2004-11-02 2007-12-18 Symantec Operating Corporation System and method for performing online backup and restore of volume configuration information
JP4419074B2 (en) * 2004-11-15 2010-02-24 エルピーダメモリ株式会社 Semiconductor memory device
US7536666B1 (en) * 2004-11-19 2009-05-19 Xilinx, Inc. Integrated circuit and method of routing a clock signal in an integrated circuit
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US7301838B2 (en) * 2004-12-13 2007-11-27 Innovative Silicon S.A. Sense amplifier circuitry and architecture to write data into and/or read from memory cells
US7218570B2 (en) * 2004-12-17 2007-05-15 Sandisk 3D Llc Apparatus and method for memory operations using address-dependent conditions
US20060164909A1 (en) * 2005-01-24 2006-07-27 International Business Machines Corporation System, method and storage medium for providing programmable delay chains for a memory system
US20060168407A1 (en) * 2005-01-26 2006-07-27 Micron Technology, Inc. Memory hub system and method having large virtual page size
US20060179191A1 (en) * 2005-02-10 2006-08-10 Young David W Covert channel firewall
JP2006285602A (en) * 2005-03-31 2006-10-19 Nec Corp Memory system, information processing apparatus, data transfer method, program, and recording medium
US7702839B2 (en) * 2005-04-12 2010-04-20 Nokia Corporation Memory interface for volatile and non-volatile memory devices
US20060248305A1 (en) * 2005-04-13 2006-11-02 Wayne Fang Memory device having width-dependent output latency
US7184327B2 (en) * 2005-04-14 2007-02-27 Micron Technology, Inc. System and method for enhanced mode register definitions
KR100670656B1 (en) * 2005-06-09 2007-01-17 주식회사 하이닉스반도체 Semiconductor memory deivce
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US20080082763A1 (en) * 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8619452B2 (en) 2005-09-02 2013-12-31 Google Inc. Methods and apparatus of stacking DRAMs
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US9542352B2 (en) * 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US7580312B2 (en) 2006-07-31 2009-08-25 Metaram, Inc. Power saving system and method for use with a plurality of memory circuits
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US20080126690A1 (en) * 2006-02-09 2008-05-29 Rajan Suresh N Memory module with memory stack
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US7590796B2 (en) 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8041881B2 (en) * 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US20070014168A1 (en) * 2005-06-24 2007-01-18 Rajan Suresh N Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US20080028136A1 (en) * 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
KR100674978B1 (en) * 2005-06-27 2007-01-29 삼성전자주식회사 Method of adjusting termination values of some address pins of semiconductor device and semiconductor device using same
US7872892B2 (en) * 2005-07-05 2011-01-18 Intel Corporation Identifying and accessing individual memory devices in a memory channel
KR100615580B1 (en) * 2005-07-05 2006-08-25 삼성전자주식회사 Semiconductor memory device and data input and output method of the same, and memory system comprising the same
US7660183B2 (en) 2005-08-01 2010-02-09 Rambus Inc. Low power memory device
US7519888B2 (en) 2005-09-12 2009-04-14 Virage Logic Corporation Input-output device testing
US7616036B1 (en) 2005-09-12 2009-11-10 Virage Logic Corporation Programmable strobe and clock generator
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US7464225B2 (en) * 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US7403446B1 (en) * 2005-09-27 2008-07-22 Cypress Semiconductor Corporation Single late-write for standard synchronous SRAMs
KR101293365B1 (en) 2005-09-30 2013-08-05 모사이드 테크놀로지스 인코퍼레이티드 Memory with output control
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US7478259B2 (en) 2005-10-31 2009-01-13 International Business Machines Corporation System, method and storage medium for deriving clocks in a memory system
KR100668498B1 (en) 2005-11-09 2007-01-12 주식회사 하이닉스반도체 Apparatus and method for outputting data of semiconductor memory
US7685392B2 (en) 2005-11-28 2010-03-23 International Business Machines Corporation Providing indeterminate read data latency in a memory system
US7679401B1 (en) * 2005-12-01 2010-03-16 Tabula, Inc. User registers implemented with routing circuits in a configurable IC
JP4799157B2 (en) * 2005-12-06 2011-10-26 エルピーダメモリ株式会社 Multilayer semiconductor device
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
WO2007099447A2 (en) * 2006-03-02 2007-09-07 Nokia Corporation Method and system for flexible burst length control
US8335868B2 (en) * 2006-03-28 2012-12-18 Mosaid Technologies Incorporated Apparatus and method for establishing device identifiers for serially interconnected devices
US7404055B2 (en) 2006-03-28 2008-07-22 Intel Corporation Memory transfer with early access to critical portion
US7681102B2 (en) * 2006-04-03 2010-03-16 Qlogic, Corporation Byte level protection in PCI-Express devices
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
JP5065618B2 (en) * 2006-05-16 2012-11-07 株式会社日立製作所 Memory module
US7636813B2 (en) 2006-05-22 2009-12-22 International Business Machines Corporation Systems and methods for providing remote pre-fetch buffers
US7283414B1 (en) 2006-05-24 2007-10-16 Sandisk 3D Llc Method for improving the precision of a temperature-sensor circuit
US7594055B2 (en) * 2006-05-24 2009-09-22 International Business Machines Corporation Systems and methods for providing distributed technology independent memory controllers
US7640386B2 (en) 2006-05-24 2009-12-29 International Business Machines Corporation Systems and methods for providing memory modules with multiple hub devices
US7584336B2 (en) 2006-06-08 2009-09-01 International Business Machines Corporation Systems and methods for providing data modification operations in memory subsystems
US20070300077A1 (en) * 2006-06-26 2007-12-27 Seshadri Mani Method and apparatus for biometric verification of secondary authentications
US7617367B2 (en) * 2006-06-27 2009-11-10 International Business Machines Corporation Memory system including a two-on-one link memory subsystem interconnection
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US20080025136A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation
US20080028137A1 (en) * 2006-07-31 2008-01-31 Schakel Keith R Method and Apparatus For Refresh Management of Memory Modules
US20080028135A1 (en) * 2006-07-31 2008-01-31 Metaram, Inc. Multiple-component memory interface system and method
US7493439B2 (en) 2006-08-01 2009-02-17 International Business Machines Corporation Systems and methods for providing performance monitoring in a memory system
US7669086B2 (en) 2006-08-02 2010-02-23 International Business Machines Corporation Systems and methods for providing collision detection in a memory system
US7581073B2 (en) 2006-08-09 2009-08-25 International Business Machines Corporation Systems and methods for providing distributed autonomous power management in a memory system
US7587559B2 (en) * 2006-08-10 2009-09-08 International Business Machines Corporation Systems and methods for memory module power management
US7490217B2 (en) 2006-08-15 2009-02-10 International Business Machines Corporation Design structure for selecting memory busses according to physical memory organization information stored in virtual address translation tables
US7539842B2 (en) 2006-08-15 2009-05-26 International Business Machines Corporation Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tables
US20080059748A1 (en) * 2006-08-31 2008-03-06 Nokia Corporation Method, mobile device, system and software for a write method with burst stop and data masks
US7613265B2 (en) * 2006-09-05 2009-11-03 International Business Machines Corporation Systems, methods and computer program products for high speed data transfer using an external clock signal
US8098784B2 (en) * 2006-09-05 2012-01-17 International Business Machines Corporation Systems, methods and computer program products for high speed data transfer using a plurality of external clock signals
US7757064B2 (en) * 2006-09-07 2010-07-13 Infineon Technologies Ag Method and apparatus for sending data from a memory
JP4328790B2 (en) * 2006-09-13 2009-09-09 Ｏｋｉセミコンダクタ株式会社 Semiconductor integrated circuit
US7483334B2 (en) 2006-09-26 2009-01-27 Micron Technology, Inc. Interleaved input signal path for multiplexed input
JP4823009B2 (en) * 2006-09-29 2011-11-24 株式会社東芝 Memory card and host device
US7870459B2 (en) 2006-10-23 2011-01-11 International Business Machines Corporation High density high reliability memory module with power gating and a fault tolerant address and command bus
US7477522B2 (en) * 2006-10-23 2009-01-13 International Business Machines Corporation High density high reliability memory module with a fault tolerant address and command bus
US7546397B2 (en) * 2006-10-24 2009-06-09 Intersil Americas Inc. Systems and methods for allowing multiple devices to share the same serial lines
US7715251B2 (en) * 2006-10-25 2010-05-11 Hewlett-Packard Development Company, L.P. Memory access strobe configuration system and process
US8010709B2 (en) * 2006-12-06 2011-08-30 Mosaid Technologies Incorporated Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
US8331361B2 (en) * 2006-12-06 2012-12-11 Mosaid Technologies Incorporated Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
US8433874B2 (en) * 2006-12-06 2013-04-30 Mosaid Technologies Incorporated Address assignment and type recognition of serially interconnected memory devices of mixed type
US7853727B2 (en) * 2006-12-06 2010-12-14 Mosaid Technologies Incorporated Apparatus and method for producing identifiers regardless of mixed device type in a serial interconnection
US8271758B2 (en) 2006-12-06 2012-09-18 Mosaid Technologies Incorporated Apparatus and method for producing IDS for interconnected devices of mixed type
KR101441280B1 (en) * 2006-12-06 2014-09-17 컨버전트 인텔렉츄얼 프로퍼티 매니지먼트 인코포레이티드 System and method of operating memory devices of mixed type
US7925854B2 (en) * 2006-12-06 2011-04-12 Mosaid Technologies Incorporated System and method of operating memory devices of mixed type
US20080137470A1 (en) * 2006-12-07 2008-06-12 Josef Schnell Memory with data clock receiver and command/address clock receiver
US7990724B2 (en) 2006-12-19 2011-08-02 Juhasz Paul R Mobile motherboard
US7721140B2 (en) 2007-01-02 2010-05-18 International Business Machines Corporation Systems and methods for improving serviceability of a memory system
US7603526B2 (en) * 2007-01-29 2009-10-13 International Business Machines Corporation Systems and methods for providing dynamic memory pre-fetch
US7606988B2 (en) 2007-01-29 2009-10-20 International Business Machines Corporation Systems and methods for providing a dynamic memory bank page policy
US7609562B2 (en) * 2007-01-31 2009-10-27 Intel Corporation Configurable device ID in non-volatile memory
US8010710B2 (en) * 2007-02-13 2011-08-30 Mosaid Technologies Incorporated Apparatus and method for identifying device type of serially interconnected devices
US7639557B1 (en) 2007-03-05 2009-12-29 Altera Corporation Configurable random-access-memory circuitry
US7778074B2 (en) * 2007-03-23 2010-08-17 Sigmatel, Inc. System and method to control one time programmable memory
ES2883587T3 (en) 2007-04-12 2021-12-09 Rambus Inc Memory system with peer-to-peer request interconnect
CA2687120A1 (en) * 2007-05-08 2008-11-13 Scanimetrics Inc. Ultra high speed signal transmission/reception
WO2008154625A2 (en) 2007-06-12 2008-12-18 Rambus Inc. In-dram cycle-based levelization
US20080320192A1 (en) * 2007-06-19 2008-12-25 Sundaram Chinthamani Front side bus performance using an early defer-reply mechanism
JP4890369B2 (en) * 2007-07-10 2012-03-07 エルピーダメモリ株式会社 Duty detection circuit, DLL circuit using the same, semiconductor memory device, and data processing system
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
WO2009015086A2 (en) 2007-07-20 2009-01-29 Blue Danube Labs Inc Method and system for multi-point signal generation with phase synchronized local carriers
US8068357B2 (en) * 2007-09-05 2011-11-29 Rambus Inc. Memory controller with multi-modal reference pad
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US7567473B2 (en) 2007-09-18 2009-07-28 International Business Machines Corporation Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition
US7602631B2 (en) * 2007-09-18 2009-10-13 International Business Machines Corporation Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition
US7764533B2 (en) * 2007-09-18 2010-07-27 International Business Machines Corporation Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition
US7602632B2 (en) * 2007-09-18 2009-10-13 International Business Machines Corporation Multi-level memory cell utilizing measurement time delay as the characteristic parameter for level definition
US8898368B2 (en) * 2007-11-07 2014-11-25 Inphi Corporation Redriven/retimed registered dual inline memory module
US8332932B2 (en) * 2007-12-07 2012-12-11 Scout Analytics, Inc. Keystroke dynamics authentication techniques
US7523379B1 (en) * 2008-03-31 2009-04-21 International Business Machines Corporation Method for time-delayed data protection
TWI373714B (en) * 2008-04-02 2012-10-01 Novatek Microelectronics Corp Electronic device for contention detection of bidirectional bus and related method
US8154901B1 (en) 2008-04-14 2012-04-10 Netlist, Inc. Circuit providing load isolation and noise reduction
US8516185B2 (en) 2009-07-16 2013-08-20 Netlist, Inc. System and method utilizing distributed byte-wise buffers on a memory module
WO2010064292A1 (en) * 2008-12-01 2010-06-10 パイオニア株式会社 Data processing device, its system, its method, its program and recording medium in which its program is recorded
US8122159B2 (en) 2009-01-16 2012-02-21 Allegro Microsystems, Inc. Determining addresses of electrical components arranged in a daisy chain
US9105323B2 (en) * 2009-01-23 2015-08-11 Micron Technology, Inc. Memory device power managers and methods
US8264903B1 (en) 2009-05-05 2012-09-11 Netlist, Inc. Systems and methods for refreshing a memory module
KR101003150B1 (en) * 2009-05-14 2010-12-21 주식회사 하이닉스반도체 Circuit and method for shifting address
JP2010271841A (en) * 2009-05-20 2010-12-02 Mitsubishi Electric Corp Clock signal synchronization circuit
US9767342B2 (en) 2009-05-22 2017-09-19 Affymetrix, Inc. Methods and devices for reading microarrays
JP5449032B2 (en) 2009-05-28 2014-03-19 パナソニック株式会社 Memory system
US8046628B2 (en) * 2009-06-05 2011-10-25 Micron Technology, Inc. Failure recovery memory devices and methods
WO2010144624A1 (en) 2009-06-09 2010-12-16 Google Inc. Programming of dimm termination resistance values
US9128632B2 (en) 2009-07-16 2015-09-08 Netlist, Inc. Memory module with distributed data buffers and method of operation
US20110019760A1 (en) * 2009-07-21 2011-01-27 Rambus Inc. Methods and Systems for Reducing Supply and Termination Noise
US8461782B2 (en) * 2009-08-27 2013-06-11 Allegro Microsystems, Llc Linear or rotational motor driver identification
US7893739B1 (en) * 2009-08-27 2011-02-22 Altera Corporation Techniques for providing multiple delay paths in a delay circuit
US8130016B2 (en) * 2009-08-27 2012-03-06 Altera Corporation Techniques for providing reduced duty cycle distortion
US20110161428A1 (en) * 2009-12-28 2011-06-30 Ezpnp Technologies Corp. Two-way data and resources sharing method
EP2341445B1 (en) * 2009-12-30 2017-09-06 Intel Deutschland GmbH Method for high speed data transfer
US8938589B2 (en) 2010-01-28 2015-01-20 Hewlett-Packard Development Company, L. P. Interface methods and apparatus for memory devices using arbitration
CN102812518B (en) 2010-01-28 2015-10-21 惠普发展公司，有限责任合伙企业 Access method of storage and device
US8335879B2 (en) * 2010-04-29 2012-12-18 Hewlett-Packard Development Company, L.P. Node differentiation in multi-node electronic systems
US8495327B2 (en) 2010-06-04 2013-07-23 Nvidia Corporation Memory device synchronization
US8625320B1 (en) 2010-08-31 2014-01-07 Netlogic Microsystems, Inc. Quaternary content addressable memory cell having one transistor pull-down stack
US8582338B1 (en) 2010-08-31 2013-11-12 Netlogic Microsystems, Inc. Ternary content addressable memory cell having single transistor pull-down stack
US8553441B1 (en) 2010-08-31 2013-10-08 Netlogic Microsystems, Inc. Ternary content addressable memory cell having two transistor pull-down stack
US8462532B1 (en) 2010-08-31 2013-06-11 Netlogic Microsystems, Inc. Fast quaternary content addressable memory cell
US8848438B2 (en) * 2010-10-05 2014-09-30 Stec, Inc. Asymmetric log-likelihood ratio for MLC flash channel
KR101796116B1 (en) 2010-10-20 2017-11-10 삼성전자 주식회사 Semiconductor device, memory module and memory system having the same and operating method thereof
WO2012061633A2 (en) * 2010-11-03 2012-05-10 Netlist, Inc. Method and apparatus for optimizing driver load in a memory package
US8773880B2 (en) 2011-06-23 2014-07-08 Netlogic Microsystems, Inc. Content addressable memory array having virtual ground nodes
US8837188B1 (en) 2011-06-23 2014-09-16 Netlogic Microsystems, Inc. Content addressable memory row having virtual ground and charge sharing
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US9146867B2 (en) 2011-10-31 2015-09-29 Hewlett-Packard Development Company, L.P. Methods and apparatus to access memory using runtime characteristics
US9712453B1 (en) * 2012-03-26 2017-07-18 Amazon Technologies, Inc. Adaptive throttling for shared resources
JP2013222364A (en) * 2012-04-18 2013-10-28 Renesas Electronics Corp Signal processing circuit
US9129071B2 (en) * 2012-10-24 2015-09-08 Texas Instruments Incorporated Coherence controller slot architecture allowing zero latency write commit
US9582451B2 (en) * 2013-02-01 2017-02-28 Infineon Technologies Ag Receiver architecture
US8723329B1 (en) * 2013-03-15 2014-05-13 Invensas Corporation In-package fly-by signaling
US10324841B2 (en) 2013-07-27 2019-06-18 Netlist, Inc. Memory module with local synchronization
CN107041146A (en) 2013-09-24 2017-08-11 华盛顿大学商业化中心 Desmoglein2 (DSG2) conjugated protein and application thereof
KR101816944B1 (en) * 2013-10-02 2018-01-09 엘에스산전 주식회사 Method for automatically setting ID in UART Ring communication
US9172565B2 (en) 2014-02-18 2015-10-27 Allegro Microsystems, Llc Signaling between master and slave components using a shared communication node of the master component
US9787495B2 (en) 2014-02-18 2017-10-10 Allegro Microsystems, Llc Signaling between master and slave components using a shared communication node of the master component
WO2015167449A1 (en) * 2014-04-29 2015-11-05 Hewlett-Packard Development Company, L.P. Switches coupling volatile memory devices to a power source
KR102204391B1 (en) 2014-08-18 2021-01-18 삼성전자주식회사 Memory device having sharable ECC (Error Correction Code) cell array
GB201603589D0 (en) * 2016-03-01 2016-04-13 Surecore Ltd Memory unit
CA3031328C (en) * 2016-07-27 2023-04-25 Hubbell Incorporated Systems, apparatuses and methods for dual line inbound detection on a data communication bus
US10402110B2 (en) 2016-08-04 2019-09-03 Rambus Inc. Adjustable access energy and access latency memory system and devices
US10679722B2 (en) 2016-08-26 2020-06-09 Sandisk Technologies Llc Storage system with several integrated components and method for use therewith
US9721675B1 (en) * 2016-11-09 2017-08-01 Winbond Electronics Corporation Memory device having input circuit and operating method of same
FR3061383B1 (en) 2016-12-26 2019-05-24 Stmicroelectronics (Grenoble 2) Sas SYNCHRONIZATION OF A SENSOR NETWORK
US10057523B1 (en) 2017-02-13 2018-08-21 Alexander Krymski Image sensors and methods with multiple phase-locked loops and serializers
US10210918B2 (en) 2017-02-28 2019-02-19 Micron Technology, Inc. Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal
US10090026B2 (en) 2017-02-28 2018-10-02 Micron Technology, Inc. Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories
KR20180106017A (en) * 2017-03-17 2018-10-01 에스케이하이닉스 주식회사 Memory system and operating method of memory system
US10269397B2 (en) * 2017-08-31 2019-04-23 Micron Technology, Inc. Apparatuses and methods for providing active and inactive clock signals
US10170166B1 (en) * 2017-09-08 2019-01-01 Winbond Electronics Corp. Data transmission apparatus for memory and data transmission method thereof
KR20190030923A (en) * 2017-09-15 2019-03-25 에스케이하이닉스 주식회사 Error correction circuit, operating method thereof and data storage device incuding the same
US10747708B2 (en) 2018-03-08 2020-08-18 Allegro Microsystems, Llc Communication system between electronic devices
US10747470B2 (en) * 2018-05-10 2020-08-18 Micron Technology, Inc. Semiconductor device with pseudo flow through scheme for power savings
TWI666638B (en) * 2018-08-21 2019-07-21 華邦電子股份有限公司 Memory circuit and data bit status detector thereof
US10861564B2 (en) 2018-10-17 2020-12-08 Winbond Electronics Corp. Memory circuit and data bit status detector thereof
JP6894459B2 (en) 2019-02-25 2021-06-30 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． Pseudo-static random access memory and how it works
US10714163B2 (en) 2019-05-13 2020-07-14 Intel Corporation Methods for mitigating transistor aging to improve timing margins for memory interface signals
JP6748760B1 (en) 2019-05-13 2020-09-02 ウィンボンド エレクトロニクス コーポレーション Semiconductor memory device
DE102019125493A1 (en) * 2019-09-23 2021-03-25 Infineon Technologies Ag Slave device, bus system and method
US11442494B2 (en) 2020-06-08 2022-09-13 Analog Devices, Inc. Apparatus and methods for controlling a clock signal
US12056394B2 (en) 2020-08-13 2024-08-06 Cadence Design Systems, Inc. Memory interface training
KR20220086785A (en) * 2020-12-16 2022-06-24 삼성전자주식회사 Operating method of transaction accelerator, operating method of computing device including transaction accelerator, and computing device including transaction accelerator
US11768060B2 (en) * 2021-02-18 2023-09-26 Kirsch Llc Arrow or bolt having an advanced crossbow pin and pin nock
CN113377438B (en) * 2021-08-13 2021-11-30 沐曦集成电路(上海)有限公司 Processor and data reading and writing method thereof

Family Cites Families (475)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE627616A (en) * 1962-01-26
US3562432A (en) * 1966-11-16 1971-02-09 Communications Satellite Corp Synchronizer for time division multiple access satellite communication system
GB1262691A (en) * 1968-11-12 1972-02-02 Burroughs Corp Data processing system having current drive for transmission line
FR2044650B1 (en) * 1969-05-16 1974-06-14 Ibm France
US3713025A (en) * 1969-12-04 1973-01-23 Avco Corp Phase slip corrector means and method for synchronization of pseudorandom generating means in multistation networks
US3691534A (en) * 1970-11-04 1972-09-12 Gen Instrument Corp Read only memory system having increased data rate with alternate data readout
US3721838A (en) * 1970-12-21 1973-03-20 Ibm Repairable semiconductor circuit element and method of manufacture
US3740723A (en) * 1970-12-28 1973-06-19 Ibm Integral hierarchical binary storage element
US3771145B1 (en) * 1971-02-01 1994-11-01 Wiener Patricia P. Integrated circuit read-only memory
US3924241A (en) * 1971-03-15 1975-12-02 Burroughs Corp Memory cycle initiation in response to the presence of the memory address
US3758761A (en) * 1971-08-17 1973-09-11 Texas Instruments Inc Self-interconnecting/self-repairable electronic systems on a slice
US3753244A (en) * 1971-08-18 1973-08-14 Ibm Yield enhancement redundancy technique
US3803562A (en) * 1972-11-21 1974-04-09 Honeywell Inf Systems Semiconductor mass memory
US3821715A (en) 1973-01-22 1974-06-28 Intel Corp Memory system for a multi chip digital computer
GB1461245A (en) * 1973-01-28 1977-01-13 Hawker Siddeley Dynamics Ltd Reliability of random access memory systems
DE2364408C3 (en) * 1973-12-22 1979-06-07 Olympia Werke Ag, 2940 Wilhelmshaven Circuit arrangement for addressing the memory locations of a memory consisting of several chips
DE2364254B2 (en) * 1973-12-22 1976-03-18 CIRCUIT ARRANGEMENT FOR DATA PROCESSING DEVICES
US3950735A (en) 1974-01-04 1976-04-13 Honeywell Information Systems, Inc. Method and apparatus for dynamically controlling read/write operations in a peripheral subsystem
US3846763A (en) 1974-01-04 1974-11-05 Honeywell Inf Systems Method and apparatus for automatic selection of translators in a data processing system
US3882470A (en) * 1974-02-04 1975-05-06 Honeywell Inf Systems Multiple register variably addressable semiconductor mass memory
US3900837A (en) * 1974-02-04 1975-08-19 Honeywell Inf Systems Variably addressable semiconductor mass memory
US4038648A (en) * 1974-06-03 1977-07-26 Chesley Gilman D Self-configurable circuit structure for achieving wafer scale integration
US3969706A (en) * 1974-10-08 1976-07-13 Mostek Corporation Dynamic random access memory misfet integrated circuit
US4263650B1 (en) * 1974-10-30 1994-11-29 Motorola Inc Digital data processing system with interface adaptor having programmable monitorable control register therein
US4079448A (en) * 1975-04-07 1978-03-14 Compagnie Honeywell Bull Apparatus for synchronizing tasks on peripheral devices
US4084154A (en) 1975-05-01 1978-04-11 Burroughs Corporation Charge coupled device memory system with burst mode
US4007452A (en) * 1975-07-28 1977-02-08 Intel Corporation Wafer scale integration system
US4099231A (en) * 1975-10-01 1978-07-04 Digital Equipment Corporation Memory control system for transferring selected words in a multiple memory word exchange during one memory cycle
US4048673A (en) 1976-02-27 1977-09-13 Data General Corporation Cpu - i/o bus interface for a data processing system
US4206833A (en) 1976-07-15 1980-06-10 Clark Equipment Company Mobile aerial tower
US4250570B1 (en) * 1976-07-15 1996-01-02 Intel Corp Redundant memory circuit
JPS60816B2 (en) 1976-12-18 1985-01-10 三洋電機株式会社 Radio receiver digital value setting device
GB1574468A (en) * 1976-09-30 1980-09-10 Burroughs Corp Input-output subsystem in a digital data processing system
US4494186A (en) * 1976-11-11 1985-01-15 Honeywell Information Systems Inc. Automatic data steering and data formatting mechanism
US4092665A (en) * 1976-12-29 1978-05-30 Xerox Corporation Method and means for extracting variable length data from fixed length bytes
US4047246A (en) 1977-01-10 1977-09-06 Data General Corporation I/O bus transceiver for a data processing system
US4142069A (en) * 1977-06-20 1979-02-27 The United States Of America As Represented By The Secretary Of The Army Time reference distribution technique
US4255814A (en) * 1977-07-15 1981-03-10 Motorola, Inc. Simulcast transmission system
US4191996A (en) * 1977-07-22 1980-03-04 Chesley Gilman D Self-configurable computer and memory system
US4333142A (en) * 1977-07-22 1982-06-01 Chesley Gilman D Self-configurable computer and memory system
US4398248A (en) * 1980-10-20 1983-08-09 Mcdonnell Douglas Corporation Adaptive WSI/MNOS solid state memory system
JPS5714922Y2 (en) 1977-09-22 1982-03-27
US4426685A (en) 1978-03-20 1984-01-17 The United States Of America As Represented By The Secretary Of The Navy Solid state delay device
US4375665A (en) * 1978-04-24 1983-03-01 Texas Instruments Incorporated Eight bit standard connector bus for sixteen bit microcomputer using mirrored memory boards
US4231104A (en) 1978-04-26 1980-10-28 Teradyne, Inc. Generating timing signals
US4247817A (en) * 1978-05-15 1981-01-27 Teradyne, Inc. Transmitting electrical signals with a transmission time independent of distance between transmitter and receiver
US4205373A (en) * 1978-05-22 1980-05-27 Ncr Corporation System and method for accessing memory connected to different bus and requesting subsystem
US4183095A (en) * 1978-09-01 1980-01-08 Ncr Corporation High density memory device
US4222122A (en) 1978-11-15 1980-09-16 Everlast World's Boxing Headquarters Corp. Boxing headguard
US4234934A (en) * 1978-11-30 1980-11-18 Sperry Rand Corporation Apparatus for scaling memory addresses
US4257097A (en) 1978-12-11 1981-03-17 Bell Telephone Laboratories, Incorporated Multiprocessor system with demand assignable program paging stores
US4315308A (en) 1978-12-21 1982-02-09 Intel Corporation Interface between a microprocessor chip and peripheral subsystems
US4249247A (en) * 1979-01-08 1981-02-03 Ncr Corporation Refresh system for dynamic RAM memory
US4222112A (en) * 1979-02-09 1980-09-09 Bell Telephone Laboratories, Incorporated Dynamic RAM organization for reducing peak current
JPS55110355A (en) * 1979-02-16 1980-08-25 Toshiba Corp Memory board and selection system for it
US4253147A (en) 1979-04-09 1981-02-24 Rockwell International Corporation Memory unit with pipelined cycle of operations
DE2915488C2 (en) * 1979-04-17 1982-05-19 Nixdorf Computer Ag, 4790 Paderborn Circuit arrangement for controlling the transmission of digital signals, in particular PCM signals, between connection points of a time division multiplex telecommunications network, in particular a PCM time division multiplex telecommunications network
US4250352A (en) * 1979-05-10 1981-02-10 Workman William S Sr Remote station monitoring system
US4286321A (en) * 1979-06-18 1981-08-25 International Business Machines Corporation Common bus communication system in which the width of the address field is greater than the number of lines on the bus
US4320505A (en) * 1979-07-23 1982-03-16 Bell Telephone Laboratories, Incorporated Processing apparatus for data rate reduction
JPS5634186A (en) * 1979-08-29 1981-04-06 Hitachi Ltd Bipolar memory circuit
JPS5636628A (en) 1979-09-03 1981-04-09 Asahi Optical Co Ltd Memory device in phase synchronizing type automatic exposure control mechanism
US4443864A (en) * 1979-10-09 1984-04-17 Texas Instruments Incorporated Memory system for microprocessor with multiplexed address/data bus
US4306298A (en) * 1979-10-09 1981-12-15 Texas Instruments Incorporated Memory system for microprocessor with multiplexed address/data bus
JPS5669056A (en) 1979-11-08 1981-06-10 Fanuc Ltd Robot-equipped machining center
US4330852A (en) 1979-11-23 1982-05-18 Texas Instruments Incorporated Semiconductor read/write memory array having serial access
US4322635A (en) 1979-11-23 1982-03-30 Texas Instruments Incorporated High speed serial shift register for MOS integrated circuit
DE2948159C2 (en) 1979-11-29 1983-10-27 Siemens AG, 1000 Berlin und 8000 München Integrated memory module with selectable operating functions
JPS5682961U (en) 1979-12-01 1981-07-04
JPS5682961A (en) 1979-12-11 1981-07-07 Fujitsu Ltd Memory control system
DE2952056C2 (en) * 1979-12-22 1981-11-26 Hewlett-Packard GmbH, 7030 Böblingen Write and read circuit for a memory with random access
US4338569A (en) 1980-03-11 1982-07-06 Control Data Corporation Delay lock loop
US4348754A (en) * 1980-05-15 1982-09-07 Ampex Corporation Digital delay for high quality audio use
GB2077468B (en) 1980-06-04 1984-10-24 Hitachi Ltd Multi-computer system with plural serial bus loops
JPS5714922A (en) 1980-07-02 1982-01-26 Hitachi Ltd Storage device
US4468738A (en) * 1980-07-16 1984-08-28 Ford Aerospace & Communications Corporation Bus access arbitration using unitary arithmetic resolution logic and unique logical addresses of competing processors
US4385350A (en) * 1980-07-16 1983-05-24 Ford Aerospace & Communications Corporation Multiprocessor system having distributed priority resolution circuitry
US4360870A (en) * 1980-07-30 1982-11-23 International Business Machines Corporation Programmable I/O device identification
US4373183A (en) * 1980-08-20 1983-02-08 Ibm Corporation Bus interface units sharing a common bus using distributed control for allocation of the bus
US4379222A (en) * 1980-08-21 1983-04-05 Ncr Corporation High speed shift register
US4355376A (en) * 1980-09-30 1982-10-19 Burroughs Corporation Apparatus and method for utilizing partially defective memory devices
JPS5764895U (en) * 1980-10-03 1982-04-17
US4408272A (en) 1980-11-03 1983-10-04 Bell Telephone Laboratories, Incorporated Data control circuit
EP0054077B1 (en) 1980-12-08 1984-11-21 International Business Machines Corporation Method of transmitting information between stations attached to a unidirectional transmission ring
JPS57101957A (en) 1980-12-17 1982-06-24 Hitachi Ltd Storage control device
US4435762A (en) 1981-03-06 1984-03-06 International Business Machines Corporation Buffered peripheral subsystems
US4945471A (en) * 1981-04-01 1990-07-31 Teradata Corporation Message transmission system for selectively transmitting one of two colliding messages based on contents thereof
US4493021A (en) * 1981-04-03 1985-01-08 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Multicomputer communication system
US4583161A (en) * 1981-04-16 1986-04-15 Ncr Corporation Data processing system wherein all subsystems check for message errors
US4630193A (en) * 1981-04-27 1986-12-16 Textron, Inc. Time multiplexed processor bus
JPS57186289A (en) * 1981-05-13 1982-11-16 Hitachi Ltd Semiconductor memory
JPS6030898B2 (en) * 1981-05-15 1985-07-19 テクトロニクス・インコ−ポレイテツド Logic analyzer input device
JPS589285A (en) * 1981-07-08 1983-01-19 Toshiba Corp Semiconductor device
US4458357A (en) * 1981-08-17 1984-07-03 Basic Four Corporation Circuit board identity generator
JPS5831637A (en) 1981-08-20 1983-02-24 Nec Corp Multiplex processor
US4438494A (en) * 1981-08-25 1984-03-20 Intel Corporation Apparatus of fault-handling in a multiprocessing system
US4419747A (en) * 1981-09-14 1983-12-06 Seeq Technology, Inc. Method and device for providing process and test information in semiconductors
US4513374A (en) * 1981-09-25 1985-04-23 Ltv Aerospace And Defense Memory system
US4500905A (en) * 1981-09-30 1985-02-19 Tokyo Shibaura Denki Kabushiki Kaisha Stacked semiconductor device with sloping sides
US4811202A (en) * 1981-10-01 1989-03-07 Texas Instruments Incorporated Quadruply extended time multiplexed information bus for reducing the `pin out` configuration of a semiconductor chip package
US4421996A (en) * 1981-10-09 1983-12-20 Advanced Micro Devices, Inc. Sense amplification scheme for random access memory
US4637365A (en) 1981-10-19 1987-01-20 Motortech, Inc. Fuel conditioning apparatus and method
US4481625A (en) * 1981-10-21 1984-11-06 Elxsi High speed data bus system
US4595923A (en) 1981-10-21 1986-06-17 Elxsi Improved terminator for high speed data bus
US4462088A (en) 1981-11-03 1984-07-24 International Business Machines Corporation Array design using a four state cell for double density
JPS5880193A (en) 1981-11-06 1983-05-14 Mitsubishi Electric Corp Erasing device for storage contents of memory
US4480307A (en) * 1982-01-04 1984-10-30 Intel Corporation Interface for use between a memory and components of a module switching apparatus
US4488218A (en) * 1982-01-07 1984-12-11 At&T Bell Laboratories Dynamic priority queue occupancy scheme for access to a demand-shared bus
FR2520910B1 (en) 1982-02-04 1987-07-10 Victor Company Of Japan VIDEO MEMORY DEVICE
US4470114A (en) * 1982-03-01 1984-09-04 Burroughs Corporation High speed interconnection network for a cluster of processors
JPS58155596A (en) * 1982-03-10 1983-09-16 Hitachi Ltd Dynamic type mos ram
JPS58159360A (en) * 1982-03-17 1983-09-21 Fujitsu Ltd Semiconductor device
JPS58184626A (en) 1982-04-22 1983-10-28 Toshiba Corp Bus clock synchronization system
US4449207A (en) 1982-04-29 1984-05-15 Intel Corporation Byte-wide dynamic RAM with multiplexed internal buses
FR2526250B1 (en) * 1982-04-30 1988-05-13 Labo Electronique Physique METHOD FOR AUTOMATIC TIME SETTING OF STATIONS IN A MULTIPLEX TRANSMISSION AND DATA PROCESSING SYSTEM
JPS58192154A (en) 1982-05-07 1983-11-09 Casio Comput Co Ltd Memory device having automatic data processing function
US4506348A (en) * 1982-06-14 1985-03-19 Allied Corporation Variable digital delay circuit
US4519034A (en) * 1982-06-30 1985-05-21 Elxsi I/O Bus clock
US4667305A (en) * 1982-06-30 1987-05-19 International Business Machines Corporation Circuits for accessing a variable width data bus with a variable width data field
JPS595478A (en) 1982-07-02 1984-01-12 Toshiba Corp Addressing device of electronic computer
NO157998C (en) 1982-07-13 1988-06-29 Siemens Ag SYNCHRON RATE GENERATOR FOR DIGITAL SIGNAL MULTIPLE DEVICES.
US4513370A (en) * 1982-07-19 1985-04-23 Amdahl Corporation Data transfer control system and method for a plurality of linked stations
US4608700A (en) * 1982-07-29 1986-08-26 Massachusetts Institute Of Technology Serial multi-drop data link
US4433934A (en) * 1982-08-19 1984-02-28 Rockwell International Corporation Push-pull yoke-power takeoff coupling
US4494021A (en) * 1982-08-30 1985-01-15 Xerox Corporation Self-calibrated clock and timing signal generator for MOS/VLSI circuitry
EP0106121B1 (en) * 1982-09-20 1989-08-23 Kabushiki Kaisha Toshiba Video ram write control apparatus
US4476560A (en) * 1982-09-21 1984-10-09 Advanced Micro Devices, Inc. Diagnostic circuit for digital systems
US4562435A (en) * 1982-09-29 1985-12-31 Texas Instruments Incorporated Video display system using serial/parallel access memories
US4513372A (en) 1982-11-15 1985-04-23 Data General Corporation Universal memory
US4496861A (en) * 1982-12-06 1985-01-29 Intel Corporation Integrated circuit synchronous delay line
US4509142A (en) 1982-12-15 1985-04-02 Texas Instruments Incorporated Semiconductor memory device with pipeline access
JPS59111561A (en) * 1982-12-17 1984-06-27 Hitachi Ltd Access controlling system of composite processor system
US4586167A (en) * 1983-01-24 1986-04-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
US4528661A (en) 1983-02-14 1985-07-09 Prime Computer, Inc. Ring communications system
JPS59165285A (en) 1983-03-11 1984-09-18 Hitachi Ltd Semiconductor storage element
JPS59172897A (en) 1983-03-22 1984-09-29 Victor Co Of Japan Ltd Clock pulse generating circuit in color video signal reproducing device
EP0120172B1 (en) 1983-03-29 1988-02-03 International Business Machines Corporation Bus interface device for a data processing system
GB2138230B (en) * 1983-04-12 1986-12-03 Sony Corp Dynamic random access memory arrangements
FR2545670B1 (en) 1983-05-04 1985-07-05 Billy Jean Claude MULTIPLEXER, DEMULTIPLEXER AND MULTIPLEXING-DEMULTIPLEXING EQUIPMENT WITH RECONFIGURABLE FRAMES
US4520465A (en) 1983-05-05 1985-05-28 Motorola, Inc. Method and apparatus for selectively precharging column lines of a memory
US4616310A (en) 1983-05-20 1986-10-07 International Business Machines Corporation Communicating random access memory
US4513355A (en) * 1983-06-15 1985-04-23 Motorola, Inc. Metallization and bonding means and method for VLSI packages
JPS603268A (en) 1983-06-20 1985-01-09 Dainippon Screen Mfg Co Ltd Method for writing and reading picture data to storage device in picture scanning recorder
US4770640A (en) * 1983-06-24 1988-09-13 Walter Howard F Electrical interconnection device for integrated circuits
JPS6011993A (en) * 1983-06-30 1985-01-22 シャープ株式会社 Electronic cash register
US4649511A (en) * 1983-07-25 1987-03-10 General Electric Company Dynamic memory controller for single-chip microprocessor
US4656605A (en) * 1983-09-02 1987-04-07 Wang Laboratories, Inc. Single in-line memory module
JPS6055459A (en) 1983-09-07 1985-03-30 Hitachi Ltd Control method of block data transfer and storage
US4646270A (en) * 1983-09-15 1987-02-24 Motorola, Inc. Video graphic dynamic RAM
US4763249A (en) 1983-09-22 1988-08-09 Digital Equipment Corporation Bus device for use in a computer system having a synchronous bus
US4628489A (en) 1983-10-03 1986-12-09 Honeywell Information Systems Inc. Dual address RAM
JPS6080193A (en) 1983-10-07 1985-05-08 Hitachi Micro Comput Eng Ltd Memory system
FR2553609B1 (en) 1983-10-14 1985-12-27 Chomel Denis ASYNCHRONOUS DIGITAL BUS MULTIPLEXING SYSTEM WITH DISTRIBUTED BUS
GB8329511D0 (en) 1983-11-04 1983-12-07 Inmos Ltd Timing apparatus
US4570220A (en) * 1983-11-25 1986-02-11 Intel Corporation High speed parallel bus and data transfer method
US4882669A (en) * 1983-11-28 1989-11-21 Canon Kabushiki Kaisha Multi computer fail safe control apparatus
US4635192A (en) * 1983-12-06 1987-01-06 Tri Sigma Corporation Self configuring bus structure for computer network
US4660141A (en) * 1983-12-06 1987-04-21 Tri Sigma Corporation Self configuring computer network with automatic bus exchange of module identification numbers and processor assigned module numbers
JPS60136086A (en) 1983-12-23 1985-07-19 Hitachi Ltd Semiconductor memory device
JPS60140993A (en) 1983-12-27 1985-07-25 Matsushita Electric Ind Co Ltd Recording/reproducing device
US4639890A (en) 1983-12-30 1987-01-27 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing selectable cascaded serial shift registers
US4688197A (en) 1983-12-30 1987-08-18 Texas Instruments Incorporated Control of data access to memory for improved video system
US4747081A (en) 1983-12-30 1988-05-24 Texas Instruments Incorporated Video display system using memory with parallel and serial access employing serial shift registers selected by column address
US4663735A (en) 1983-12-30 1987-05-05 Texas Instruments Incorporated Random/serial access mode selection circuit for a video memory system
US4745548A (en) * 1984-02-17 1988-05-17 American Telephone And Telegraph Company, At&T Bell Laboratories Decentralized bus arbitration using distributed arbiters having circuitry for latching lockout signals gated from higher priority arbiters
US4584672A (en) * 1984-02-22 1986-04-22 Intel Corporation CMOS dynamic random-access memory with active cycle one half power supply potential bit line precharge
US4654655A (en) * 1984-03-02 1987-03-31 Motorola, Inc. Multi-user serial data bus
US4631659A (en) 1984-03-08 1986-12-23 Texas Instruments Incorporated Memory interface with automatic delay state
US4766536A (en) * 1984-04-19 1988-08-23 Rational Computer bus apparatus with distributed arbitration
US4775931A (en) * 1984-05-11 1988-10-04 Hewlett-Packard Company Dynamically configured computing device
US4566098A (en) * 1984-05-14 1986-01-21 Northern Telecom Limited Control mechanism for a ring communication system
US4727475A (en) * 1984-05-18 1988-02-23 Frederick Kiremidjian Self-configuring modular computer system with automatic address initialization
US4649516A (en) * 1984-06-01 1987-03-10 International Business Machines Corp. Dynamic row buffer circuit for DRAM
JPS60261095A (en) 1984-06-06 1985-12-24 Mitsubishi Electric Corp Semiconductor storage device
US4712194A (en) * 1984-06-08 1987-12-08 Matsushita Electric Industrial Co., Ltd. Static random access memory
EP0166192B1 (en) 1984-06-29 1991-10-09 International Business Machines Corporation High-speed buffer store arrangement for fast transfer of data
USH696H (en) 1984-07-03 1989-10-03 Cpt Corporation System for accessing shared resource device by intelligent user devices
JPS6154098A (en) * 1984-08-23 1986-03-18 Fujitsu Ltd Semiconductor memory device
US4637018A (en) 1984-08-29 1987-01-13 Burroughs Corporation Automatic signal delay adjustment method
JPH0799616B2 (en) * 1984-08-30 1995-10-25 三菱電機株式会社 Semiconductor memory device
US4773005A (en) * 1984-09-07 1988-09-20 Tektronix, Inc. Dynamic address assignment system
JPS6172350A (en) 1984-09-14 1986-04-14 Fujitsu Ltd Data transfer control system
US4646269A (en) 1984-09-18 1987-02-24 Monolithic Memories, Inc. Multiple programmable initialize words in a programmable read only memory
JPS6172350U (en) 1984-10-12 1986-05-16
US4629909A (en) 1984-10-19 1986-12-16 American Microsystems, Inc. Flip-flop for storing data on both leading and trailing edges of clock signal
US4641276A (en) 1984-10-22 1987-02-03 General Electric Company Serial-parallel data transfer system for VLSI data paths
JPS61102333A (en) * 1984-10-24 1986-05-21 Nippon Denso Co Ltd Differential gear for automobile
JPS61107453A (en) 1984-10-30 1986-05-26 Nec Corp Module address setting circuit
US4758993A (en) * 1984-11-19 1988-07-19 Fujitsu Limited Random access memory device formed on a semiconductor substrate having an array of memory cells divided into sub-arrays
US4625307A (en) 1984-12-13 1986-11-25 United Technologies Corporation Apparatus for interfacing between at least one channel and at least one bus
DE3543911A1 (en) 1984-12-14 1986-06-26 Mitsubishi Denki K.K., Tokio/Tokyo DIGITAL DELAY UNIT
US4633440A (en) 1984-12-31 1986-12-30 International Business Machines Multi-port memory chip in a hierarchical memory
US4675813A (en) * 1985-01-03 1987-06-23 Northern Telecom Limited Program assignable I/O addresses for a computer
DE3588156T2 (en) 1985-01-22 1998-01-08 Texas Instruments Inc., Dallas, Tex. Semiconductor memory with serial access
US4683555A (en) * 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
US4636986B1 (en) 1985-01-22 1999-12-07 Texas Instruments Inc Separately addressable memory arrays in a multiple array semiconductor chip
US4984217A (en) * 1985-01-23 1991-01-08 Hitachi, Ltd. Semiconductor memory
US4712190A (en) 1985-01-25 1987-12-08 Digital Equipment Corporation Self-timed random access memory chip
JPS61175845A (en) * 1985-01-31 1986-08-07 Toshiba Corp Microprocessor system
US4719602A (en) * 1985-02-07 1988-01-12 Visic, Inc. Memory with improved column access
DE3504992A1 (en) * 1985-02-14 1986-08-14 Brown, Boveri & Cie Ag, 6800 Mannheim PERFORMANCE SEMICONDUCTOR MODULE WITH INTEGRATED HEAT PIPE
US4933835A (en) * 1985-02-22 1990-06-12 Intergraph Corporation Apparatus for maintaining consistency of a cache memory with a primary memory
JPS61195015A (en) 1985-02-25 1986-08-29 シーメンス、アクチエンゲゼルシヤフト Digital filtering circuit apparatus for image signal
US4740924A (en) 1985-02-25 1988-04-26 Siemens Aktiengesellschaft Circuit arrangement comprising a matrix-shaped memory arrangement for variably adjustable time delay of digital signals
EP0194939B1 (en) * 1985-03-14 1992-02-05 Fujitsu Limited Semiconductor memory device
US4685088A (en) 1985-04-15 1987-08-04 International Business Machines Corporation High performance memory system utilizing pipelining techniques
US4726021A (en) 1985-04-17 1988-02-16 Hitachi, Ltd. Semiconductor memory having error correcting means
EP0198932B1 (en) * 1985-04-23 1990-07-25 International Business Machines Corporation Extension arrangement and station connecting method for a ring communication system
US4744062A (en) 1985-04-23 1988-05-10 Hitachi, Ltd. Semiconductor integrated circuit with nonvolatile memory
JPS61267148A (en) * 1985-05-22 1986-11-26 Hitachi Ltd Memory circuit
US4644532A (en) * 1985-06-10 1987-02-17 International Business Machines Corporation Automatic update of topology in a hybrid network
US4951251A (en) * 1985-06-17 1990-08-21 Hitachi, Ltd. Semiconductor memory device
US4703418A (en) 1985-06-28 1987-10-27 Hewlett-Packard Company Method and apparatus for performing variable length data read transactions
US4893174A (en) * 1985-07-08 1990-01-09 Hitachi, Ltd. High density integration of semiconductor circuit
JPS6216289A (en) 1985-07-16 1987-01-24 Nec Corp Read only memory
US4680738A (en) * 1985-07-30 1987-07-14 Advanced Micro Devices, Inc. Memory with sequential mode
US4658381A (en) * 1985-08-05 1987-04-14 Motorola, Inc. Bit line precharge on a column address change
US4750839A (en) * 1985-08-07 1988-06-14 Texas Instruments Incorporated Semiconductor memory with static column decode and page mode addressing capability
JPS6238593A (en) * 1985-08-14 1987-02-19 Fujitsu Ltd Dynamic semiconductor storage device
JPS6240693A (en) * 1985-08-16 1987-02-21 Fujitsu Ltd Semiconductor memory device with nibbling mode function
JPS6251509A (en) 1985-08-27 1987-03-06 Nec Home Electronics Ltd Transferring device
JPH0736269B2 (en) * 1985-08-30 1995-04-19 株式会社日立製作所 Semiconductor memory device
JPS6265298A (en) * 1985-09-17 1987-03-24 Fujitsu Ltd Write system of eprom
JPH0638696B2 (en) 1985-09-20 1994-05-18 株式会社東芝 Power converter
US4835733A (en) 1985-09-30 1989-05-30 Sgs-Thomson Microelectronics, Inc. Programmable access memory
JP2664137B2 (en) * 1985-10-29 1997-10-15 凸版印刷株式会社 IC card
US4920483A (en) * 1985-11-15 1990-04-24 Data General Corporation A computer memory for accessing any word-sized group of contiguous bits
US4740923A (en) * 1985-11-19 1988-04-26 Hitachi, Ltd Memory circuit and method of controlling the same
US4779089A (en) * 1985-11-27 1988-10-18 Tektronix, Inc. Bus arbitration controller
US4792926A (en) * 1985-12-09 1988-12-20 Kabushiki Kaisha Toshiba High speed memory system for use with a control bus bearing contiguous segmentially intermixed data read and data write request signals
US4858112A (en) * 1985-12-17 1989-08-15 General Electric Company Interface comprising message and protocol processors for interfacing digital data with a bus network
US4748617A (en) 1985-12-20 1988-05-31 Network Systems Corporation Very high-speed digital data bus
GB2187367B (en) * 1986-01-09 1990-03-28 Ricoh Kk Control system for local area network
US4785396A (en) * 1986-01-28 1988-11-15 Intel Corporation Push-pull serial bus coupled to a plurality of devices each having collision detection circuit and arbitration circuit
US4755937A (en) 1986-02-14 1988-07-05 Prime Computer, Inc. Method and apparatus for high bandwidth shared memory
DE3604966C1 (en) * 1986-02-17 1987-04-09 Nixdorf Computer Ag Circuit arrangement for switching binary signals, in particular PCM signals
JPH0754638B2 (en) * 1986-02-18 1995-06-07 松下電子工業株式会社 Shift register
JPS62202537A (en) 1986-02-19 1987-09-07 Hitachi Ltd Semiconductor integrated circuit device
US4719627A (en) * 1986-03-03 1988-01-12 Unisys Corporation Memory system employing a low DC power gate array for error correction
US4949301A (en) 1986-03-06 1990-08-14 Advanced Micro Devices, Inc. Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs
DE3752017T2 (en) 1986-03-20 1997-08-28 Nippon Electric Co Microcomputer with accessibility to an internal memory with the desired variable access time
US4706166A (en) 1986-04-25 1987-11-10 Irvine Sensors Corporation High-density electronic modules--process and product
CA1293565C (en) 1986-04-28 1991-12-24 Norio Ebihara Semiconductor memory
US4979145A (en) 1986-05-01 1990-12-18 Motorola, Inc. Structure and method for improving high speed data rate in a DRAM
US4825416A (en) * 1986-05-07 1989-04-25 Advanced Micro Devices, Inc. Integrated electronic memory circuit with internal timing and operable in both latch-based and register-based systems
JPS62287499A (en) * 1986-06-06 1987-12-14 Fujitsu Ltd Semiconductor memory device
JPH081754B2 (en) * 1986-06-10 1996-01-10 日本電気株式会社 Memory circuit
DE3789731T2 (en) 1986-06-20 1994-08-18 Hitachi Ltd Digital video signal processor.
JPS634492A (en) * 1986-06-23 1988-01-09 Mitsubishi Electric Corp Semiconductor storage device
US4803621A (en) * 1986-07-24 1989-02-07 Sun Microsystems, Inc. Memory access system
US4835674A (en) 1986-07-28 1989-05-30 Bull Hn Information Systems Inc. Computer network system for multiple processing elements
JPS6334795A (en) 1986-07-29 1988-02-15 Mitsubishi Electric Corp Semiconductor storage device
US5031072A (en) * 1986-08-01 1991-07-09 Texas Instruments Incorporated Baseboard for orthogonal chip mount
US4747100A (en) 1986-08-11 1988-05-24 Allen-Bradley Company, Inc. Token passing network utilizing active node table
JPS6346864A (en) 1986-08-14 1988-02-27 Nec Corp Facsimile equipment
US4845664A (en) * 1986-09-15 1989-07-04 International Business Machines Corp. On-chip bit reordering structure
US5276846A (en) 1986-09-15 1994-01-04 International Business Machines Corporation Fast access memory structure
US4754433A (en) 1986-09-16 1988-06-28 Ibm Corporation Dynamic ram having multiplexed twin I/O line pairs
US4799199A (en) * 1986-09-18 1989-01-17 Motorola, Inc. Bus master having burst transfer mode
US4785394A (en) * 1986-09-19 1988-11-15 Datapoint Corporation Fair arbitration technique for a split transaction bus in a multiprocessor computer system
US4719505A (en) 1986-09-19 1988-01-12 M/A-Com Government Systems, Inc. Color burst regeneration
JPS6391766A (en) 1986-10-06 1988-04-22 Fujitsu Ltd Control system for accessing memory device
US4922141A (en) 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
GB2197553A (en) 1986-10-07 1988-05-18 Western Digital Corp Phase-locked loop delay line
DE3685114D1 (en) * 1986-10-30 1992-06-04 Ibm "DAISY-CHAIN" CONFIGURATION FOR BUS ACCESS.
US4839801A (en) 1986-11-03 1989-06-13 Saxpy Computer Corporation Architecture for block processing computer system
US5140688A (en) 1986-11-10 1992-08-18 Texas Instruments Incorporated GaAs integrated circuit programmable delay line element
JPH01130240A (en) * 1987-11-16 1989-05-23 Yokogawa Hewlett Packard Ltd Data train generating device
CA1258912A (en) * 1986-11-20 1989-08-29 Stephen J. King Interactive real-time video processor with zoom, pan and scroll capability
JPS63132365A (en) * 1986-11-22 1988-06-04 Nec Corp Bus adjustment control system
JPS63142445A (en) 1986-12-05 1988-06-14 Agency Of Ind Science & Technol Memory device
JPS63146298A (en) 1986-12-10 1988-06-18 Mitsubishi Electric Corp Variable work length shift register
JPS63276795A (en) 1986-12-16 1988-11-15 Mitsubishi Electric Corp Variable length shift register
DE3786539T2 (en) * 1986-12-19 1993-10-28 Fujitsu Ltd Semiconductor memory with double access device for realizing a reading operation at high speed.
US4764846A (en) * 1987-01-05 1988-08-16 Irvine Sensors Corporation High density electronic package comprising stacked sub-modules
JPS63175287A (en) * 1987-01-16 1988-07-19 Hitachi Ltd Storage device
US5018109A (en) 1987-01-16 1991-05-21 Hitachi, Ltd. Memory including address registers for increasing access speed to the memory
US4789960A (en) 1987-01-30 1988-12-06 Rca Licensing Corporation Dual port video memory system having semi-synchronous data input and data output
US4821226A (en) 1987-01-30 1989-04-11 Rca Licensing Corporation Dual port video memory system having a bit-serial address input port
US4851990A (en) 1987-02-09 1989-07-25 Advanced Micro Devices, Inc. High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure
US4782439A (en) 1987-02-17 1988-11-01 Intel Corporation Direct memory access system for microcontroller
GB8704315D0 (en) * 1987-02-24 1987-04-01 Int Computers Ltd Data display apparatus
JPS63142445U (en) 1987-03-10 1988-09-20
US5038320A (en) * 1987-03-13 1991-08-06 International Business Machines Corp. Computer system with automatic initialization of pluggable option cards
US5056060A (en) * 1987-03-13 1991-10-08 Apple Computer, Inc. Printed circuit card with self-configuring memory system for non-contentious allocation of reserved memory space among expansion cards
EP0282735B1 (en) 1987-03-20 1992-05-06 Hitachi, Ltd. Clock signal supply system
US5184027A (en) 1987-03-20 1993-02-02 Hitachi, Ltd. Clock signal supply system
US4837682A (en) * 1987-04-07 1989-06-06 Glen Culler & Associates Bus arbitration system and method
US4858113A (en) 1987-04-10 1989-08-15 The United States Of America As Represented By The Director Of The National Security Agency Reconfigurable pipelined processor
KR960009249B1 (en) * 1987-04-24 1996-07-16 미다 가쓰시게 Semiconductor memory
US5133064A (en) 1987-04-27 1992-07-21 Hitachi, Ltd. Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices
JPS63271679A (en) * 1987-04-30 1988-11-09 Toshiba Corp Data writing system
US4937733A (en) * 1987-05-01 1990-06-26 Digital Equipment Corporation Method and apparatus for assuring adequate access to system resources by processors in a multiprocessor computer system
JPS63281519A (en) * 1987-05-13 1988-11-18 Noboru Yamaguchi Synchronizing clock signal generating device
US4805198A (en) * 1987-05-19 1989-02-14 Crystal Semiconductor Corporation Clock multiplier/jitter attenuator
US4761567A (en) 1987-05-20 1988-08-02 Advanced Micro Devices, Inc. Clock scheme for VLSI systems
US4817058A (en) * 1987-05-21 1989-03-28 Texas Instruments Incorporated Multiple input/output read/write memory having a multiple-cycle write mask
JPS63296292A (en) * 1987-05-27 1988-12-02 Mitsubishi Electric Corp Semiconductor device
JPS63304491A (en) * 1987-06-04 1988-12-12 Mitsubishi Electric Corp Semiconductor memory
US4785428A (en) 1987-06-18 1988-11-15 Intel Corporation Programmable memory array control signals
JPS6429951A (en) 1987-07-24 1989-01-31 Hitachi Ltd Storage system
US4807189A (en) * 1987-08-05 1989-02-21 Texas Instruments Incorporated Read/write memory having a multiple column select mode
JP2714944B2 (en) 1987-08-05 1998-02-16 三菱電機株式会社 Semiconductor storage device
JP2590122B2 (en) * 1987-08-07 1997-03-12 富士通株式会社 Semiconductor memory
JP2679994B2 (en) * 1987-08-14 1997-11-19 株式会社日立製作所 Vector processing equipment
US4845677A (en) 1987-08-17 1989-07-04 International Business Machines Corporation Pipelined memory chip structure having improved cycle time
JPS6429951U (en) 1987-08-17 1989-02-22
US4930065A (en) 1987-08-20 1990-05-29 David Computer Corporation Automatic data channels for a computer system
JPH0671241B2 (en) 1987-09-10 1994-09-07 株式会社ケンウッド Initial synchronization method for spread spectrum communication
US5179687A (en) * 1987-09-26 1993-01-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device containing a cache and an operation method thereof
JPS6488662A (en) 1987-09-29 1989-04-03 Fujitsu Ltd Semiconductor memory
JP2701030B2 (en) * 1987-10-09 1998-01-21 株式会社日立製作所 Write control circuit for high-speed storage device
US5051889A (en) * 1987-10-23 1991-09-24 Chips And Technologies, Incorporated Page interleaved memory access
US5040153A (en) * 1987-10-23 1991-08-13 Chips And Technologies, Incorporated Addressing multiple types of memory devices
US4964038A (en) * 1987-10-28 1990-10-16 International Business Machines Corp. Data processing system having automatic address allocation arrangements for addressing interface cards
KR970008786B1 (en) 1987-11-02 1997-05-29 가부시기가이샤 히다찌세이사꾸쇼 Semiconductor integrated circuit
US5226147A (en) * 1987-11-06 1993-07-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device for simple cache system
US4947484A (en) * 1987-11-10 1990-08-07 Echelon Systems Corporation Protocol for network having a plurality of intelligent cells
US4920486A (en) * 1987-11-23 1990-04-24 Digital Equipment Corporation Distributed arbitration apparatus and method for shared bus
US4855809A (en) * 1987-11-24 1989-08-08 Texas Instruments Incorporated Orthogonal chip mount system module and method
JPH01146187A (en) 1987-12-02 1989-06-08 Mitsubishi Electric Corp Semiconductor memory device built-in cache memory
US5014242A (en) * 1987-12-10 1991-05-07 Hitachi, Ltd. Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit
JPH01236494A (en) 1988-03-17 1989-09-21 Hitachi Ltd Semiconductor integrated circuit device
US6112287A (en) 1993-03-01 2000-08-29 Busless Computers Sarl Shared memory multiprocessor system using a set of serial links as processors-memory switch
US4878166A (en) 1987-12-15 1989-10-31 Advanced Micro Devices, Inc. Direct memory access apparatus and methods for transferring data between buses having different performance characteristics
JPH01166545A (en) * 1987-12-22 1989-06-30 Nec Corp Zigzag type ic
US5093807A (en) 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
US4954992A (en) * 1987-12-24 1990-09-04 Mitsubishi Denki Kabushiki Kaisha Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor
US4959816A (en) * 1987-12-28 1990-09-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US5200926A (en) * 1987-12-28 1993-04-06 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
US5157776A (en) 1987-12-30 1992-10-20 Zenith Data Systems Corporation High speed memory for microcomputer systems
JPH0821234B2 (en) * 1988-01-14 1996-03-04 三菱電機株式会社 Dynamic semiconductor memory device and control method thereof
US4873671A (en) 1988-01-28 1989-10-10 National Semiconductor Corporation Sequential read access of serial memories with a user defined starting address
US4916670A (en) * 1988-02-02 1990-04-10 Fujitsu Limited Semiconductor memory device having function of generating write signal internally
IL89120A (en) 1988-02-17 1992-08-18 Mips Computer Systems Inc Circuit synchronization system
US5101117A (en) 1988-02-17 1992-03-31 Mips Computer Systems Variable delay line phase-locked loop circuit synchronization system
JPH0786853B2 (en) * 1988-02-29 1995-09-20 株式会社ピーエフユー Bus transfer control method
US4975763A (en) * 1988-03-14 1990-12-04 Texas Instruments Incorporated Edge-mounted, surface-mount package for semiconductor integrated circuit devices
JPH021671A (en) * 1988-03-17 1990-01-05 Toshiba Corp Load control system for packet switchboard
JP2923786B2 (en) 1988-03-18 1999-07-26 日立マクセル株式会社 Semiconductor file memory and storage system using the same
US4811364A (en) * 1988-04-01 1989-03-07 Digital Equipment Corporation Method and apparatus for stabilized data transmission
US5193199A (en) * 1988-04-14 1993-03-09 Zilog, Inc. Device and method for programming critical hardware parameters
US5220673A (en) * 1988-04-14 1993-06-15 Zilog, Inc. Device and method for programming critical hardware parameters
CA1301261C (en) * 1988-04-27 1992-05-19 Wayne D. Grover Method and apparatus for clock distribution and for distributed clock synchronization
JPH0212541A (en) * 1988-04-29 1990-01-17 Internatl Business Mach Corp <Ibm> Computing system and operation thereof
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
US5029124A (en) 1988-05-17 1991-07-02 Digital Equipment Corporation Method and apparatus for providing high speed parallel transfer of bursts of data
JP2818415B2 (en) * 1988-05-18 1998-10-30 日本電気株式会社 Buffer storage device
US5254880A (en) * 1988-05-25 1993-10-19 Hitachi, Ltd. Large scale integrated circuit having low internal operating voltage
US5034917A (en) * 1988-05-26 1991-07-23 Bland Patrick M Computer system including a page mode memory with decreased access time and method of operation thereof
US4870622A (en) 1988-06-24 1989-09-26 Advanced Micro Devices, Inc. DRAM controller cache
US5134699A (en) 1988-06-24 1992-07-28 Advanced Micro Devices, Inc. Programmable burst data transfer apparatus and technique
DK163397C (en) 1988-06-24 1992-07-13 Nordiske Kabel Traad PROCEDURE FOR REGULATING A PHASE GENERATOR'S PHASE IN RELATION TO A DATA SIGNAL
US4953130A (en) * 1988-06-27 1990-08-28 Texas Instruments, Incorporated Memory circuit with extended valid data output time
US5210715A (en) * 1988-06-27 1993-05-11 Texas Instruments Incorporated Memory circuit with extended valid data output time
US5404327A (en) * 1988-06-30 1995-04-04 Texas Instruments Incorporated Memory device with end of cycle precharge utilizing write signal and data transition detectors
JP2534757B2 (en) * 1988-07-06 1996-09-18 株式会社東芝 Refresh circuit
US5111423A (en) * 1988-07-21 1992-05-05 Altera Corporation Programmable interface for computer system peripheral circuit card
US5038317A (en) * 1988-07-25 1991-08-06 Allen-Bradley Company, Inc. Programmable controller module rack with a relative rack slot addressing mechanism
US4912630A (en) 1988-07-29 1990-03-27 Ncr Corporation Cache address comparator with sram having burst addressing control
US4939510A (en) * 1988-08-22 1990-07-03 E-Systems, Inc. Broadband communications RF packet collision detection
JP2574474B2 (en) 1988-08-23 1997-01-22 富士通株式会社 Optical module
JPH0697614B2 (en) 1988-08-26 1994-11-30 エヌ・イーケムキャット株式会社 Supported platinum alloy electrocatalyst
US5247518A (en) * 1988-09-02 1993-09-21 Hitachi, Ltd. High-speed ring lan system
US5206833A (en) * 1988-09-12 1993-04-27 Acer Incorporated Pipelined dual port RAM
JP2633645B2 (en) * 1988-09-13 1997-07-23 株式会社東芝 Semiconductor memory device
US5193193A (en) 1988-09-14 1993-03-09 Silicon Graphics, Inc. Bus control system for arbitrating requests with predetermined on/off time limitations
US5179667A (en) 1988-09-14 1993-01-12 Silicon Graphics, Inc. Synchronized DRAM control apparatus using two different clock rates
JPH0283891A (en) * 1988-09-20 1990-03-23 Fujitsu Ltd Semiconductor memory
US5138434A (en) * 1991-01-22 1992-08-11 Micron Technology, Inc. Packaging for semiconductor logic devices
US4932002A (en) * 1988-09-30 1990-06-05 Texas Instruments, Incorporated Bit line latch sense amp
FI81225C (en) 1988-09-30 1990-09-10 Kone Oy FOERFARANDE OCH ANORDNING FOER ATT SAENDA MEDDELANDE I BINAERFORM I EN SERIETRAFIKBUSS.
US4975877A (en) * 1988-10-20 1990-12-04 Logic Devices Incorporated Static semiconductor memory with improved write recovery and column address circuitry
US5006982A (en) 1988-10-21 1991-04-09 Siemens Ak. Method of increasing the bandwidth of a packet bus by reordering reply packets
US4956694A (en) * 1988-11-04 1990-09-11 Dense-Pac Microsystems, Inc. Integrated circuit chip stacking
JP2674809B2 (en) * 1988-11-07 1997-11-12 日本電気株式会社 Information processing device
US5034964A (en) 1988-11-08 1991-07-23 Tandem Computers Incorporated N:1 time-voltage matrix encoded I/O transmission system
US4975872A (en) * 1988-11-17 1990-12-04 Matsushita Electric Industrial Co., Ltd. Dual port memory device with tag bit marking
US5148523A (en) * 1988-11-29 1992-09-15 Solbourne Computer, Inc. Dynamic video RAM incorporationg on chip line modification
US5142637A (en) * 1988-11-29 1992-08-25 Solbourne Computer, Inc. Dynamic video RAM incorporating single clock random port control
US5023838A (en) 1988-12-02 1991-06-11 Ncr Corporation Random access memory device with integral logic capability
US5142376A (en) 1988-12-16 1992-08-25 Canon Kabushiki Kaisha Image signal recording and reproducing system with pilot signal phase-locked with a synchronizing signal
US5018111A (en) 1988-12-27 1991-05-21 Intel Corporation Timing circuit for memory employing reset function
US4982400A (en) * 1988-12-29 1991-01-01 Intel Corporation Ring bus hub for a star local area network
US4864563A (en) 1989-01-09 1989-09-05 E-Systems, Inc. Method for establishing and maintaining a nodal network in a communication system
US5123100A (en) 1989-01-13 1992-06-16 Nec Corporation Timing control method in a common bus system having delay and phase correcting circuits for transferring data in synchronization and time division slot among a plurality of transferring units
US5129069A (en) * 1989-01-24 1992-07-07 Zenith Data Systems Corporation Method and apparatus for automatic memory configuration by a computer
JPH02210685A (en) * 1989-02-10 1990-08-22 Tokyo Electric Co Ltd Dram controller
US4937734A (en) * 1989-02-21 1990-06-26 Sun Microsystems, Inc. High speed bus with virtual memory data transfer and rerun cycle capability
US5099481A (en) 1989-02-28 1992-03-24 Integrated Device Technology, Inc. Registered RAM array with parallel and serial interface
US5111486A (en) 1989-03-15 1992-05-05 Motorola, Inc. Bit synchronizer
JPH02246151A (en) * 1989-03-20 1990-10-01 Hitachi Ltd Resistance means, logic circuit, input circuit, fuse-blowing circuit, drive circuit, power-supply circuit and electrostatic protective circuit; semiconductor storage device containing them, and its layout system and test system
US4998069A (en) * 1989-03-31 1991-03-05 Tandem Computers Incorporated Loopback tester for testing field replaceable units
CA2011935A1 (en) * 1989-04-07 1990-10-07 Desiree A. Awiszio Dual-path computer interconnect system with four-ported packet memory control
US4940909A (en) * 1989-05-12 1990-07-10 Plus Logic, Inc. Configuration control circuit for programmable logic devices
US5114423A (en) * 1989-05-15 1992-05-19 Advanced Cardiovascular Systems, Inc. Dilatation catheter assembly with heated balloon
US5001672A (en) 1989-05-16 1991-03-19 International Business Machines Corporation Video ram with external select of active serial access register
US5175822A (en) * 1989-06-19 1992-12-29 International Business Machines Corporation Apparatus and method for assigning addresses to scsi supported peripheral devices
DE69023556T2 (en) * 1989-06-26 1996-07-18 Nippon Electric Co Semiconductor memory with an improved data reading scheme.
US4901036A (en) 1989-06-29 1990-02-13 Motorola, Inc. Frequency synthesizer with an interface controller and buffer memory
US4954987A (en) * 1989-07-17 1990-09-04 Advanced Micro Devices, Inc. Interleaved sensing system for FIFO and burst-mode memories
CA2017458C (en) * 1989-07-24 2000-10-10 Jonathan R. Engdahl Intelligent network interface circuit
KR940008295B1 (en) * 1989-08-28 1994-09-10 가부시기가이샤 히다찌세이사꾸쇼 Semiconductor memory
JPH0394350A (en) * 1989-09-07 1991-04-19 Nec Corp Semiconductor storage device
US5163131A (en) * 1989-09-08 1992-11-10 Auspex Systems, Inc. Parallel i/o network file server architecture
US5107465A (en) 1989-09-13 1992-04-21 Advanced Micro Devices, Inc. Asynchronous/synchronous pipeline dual mode memory access circuit and method
US4970418A (en) * 1989-09-26 1990-11-13 Apple Computer, Inc. Programmable memory state machine for providing variable clocking to a multimode memory
JP2982905B2 (en) * 1989-10-02 1999-11-29 三菱電機株式会社 Dynamic semiconductor memory device
US4998262A (en) * 1989-10-10 1991-03-05 Hewlett-Packard Company Generation of topology independent reference signals
US5121382A (en) * 1989-10-11 1992-06-09 Digital Equipment Corporation Station-to-station full duplex communication in a communications network
US5058132A (en) 1989-10-26 1991-10-15 National Semiconductor Corporation Clock distribution system and technique
US5448744A (en) * 1989-11-06 1995-09-05 Motorola, Inc. Integrated circuit microprocessor with programmable chip select logic
GB8925723D0 (en) 1989-11-14 1990-01-04 Amt Holdings Processor array system
EP0429252B1 (en) * 1989-11-17 1998-01-14 Digital Equipment Corporation System and method for storing firmware in relocatable format
US5111464A (en) * 1989-12-01 1992-05-05 Mips Computer Systems, Inc. Interrupt reporting for single-bit memory errors
US5179670A (en) * 1989-12-01 1993-01-12 Mips Computer Systems, Inc. Slot determination mechanism using pulse counting
US4998222A (en) 1989-12-04 1991-03-05 Nec Electronics Inc. Dynamic random access memory with internally gated RAS
US5278974A (en) * 1989-12-04 1994-01-11 Digital Equipment Corporation Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths
US5175831A (en) * 1989-12-05 1992-12-29 Zilog, Inc. System register initialization technique employing a non-volatile/read only memory
DE69032758T2 (en) * 1989-12-19 1999-06-24 3Com Corp., Santa Clara, Calif. Configuration procedure for a computer bus adapter card without bridges or switches
US5036495A (en) 1989-12-28 1991-07-30 International Business Machines Corp. Multiple mode-set for IC chip
US5175835A (en) * 1990-01-10 1992-12-29 Unisys Corporation Multi-mode DRAM controller
US5021985A (en) 1990-01-19 1991-06-04 Weitek Corporation Variable latency method and apparatus for floating-point coprocessor
US5107491A (en) 1990-02-20 1992-04-21 Advanced Micro Devices, Inc. Collision filter
US5012408A (en) * 1990-03-15 1991-04-30 Digital Equipment Corporation Memory array addressing system for computer systems with multiple memory arrays
US5301155A (en) * 1990-03-20 1994-04-05 Mitsubishi Denki Kabushiki Kaisha Multiblock semiconduction storage device including simultaneous operation of a plurality of block defect determination circuits
KR100236876B1 (en) * 1990-03-28 2000-01-15 가나이 쓰도무 Cmos circuit with reduced signal swing
EP0449052A3 (en) 1990-03-29 1993-02-24 National Semiconductor Corporation Parity test method and apparatus for a memory chip
US5023488A (en) * 1990-03-30 1991-06-11 Xerox Corporation Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines
JP2938511B2 (en) * 1990-03-30 1999-08-23 三菱電機株式会社 Semiconductor storage device
US5181205A (en) * 1990-04-10 1993-01-19 National Semiconductor Corporation Short circuit detector circuit for memory arrays
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
US6324120B2 (en) * 1990-04-18 2001-11-27 Rambus Inc. Memory device having a variable data output length
US5243703A (en) * 1990-04-18 1993-09-07 Rambus, Inc. Apparatus for synchronously generating clock signals in a data processing system
US5384501A (en) * 1990-06-15 1995-01-24 Kabushiki Kaisha Toshiba Integration circuit including a differential amplifier having a variable transconductance
US5270973A (en) * 1990-08-06 1993-12-14 Texas Instruments Incorporated Video random access memory having a split register and a multiplexer
US5077693A (en) * 1990-08-06 1991-12-31 Motorola, Inc. Dynamic random access memory
US6249481B1 (en) * 1991-10-15 2001-06-19 Kabushiki Kaisha Toshiba Semiconductor memory device
US5198995A (en) * 1990-10-30 1993-03-30 International Business Machines Corporation Trench-capacitor-one-transistor storage cell and array for dynamic random access memories
JP3992757B2 (en) 1991-04-23 2007-10-17 テキサス インスツルメンツ インコーポレイテツド A system that includes a memory synchronized with a microprocessor, and a data processor, a synchronous memory, a peripheral device and a system clock
US5392292A (en) * 1991-06-27 1995-02-21 Cray Research, Inc. Configurable spare memory chips
GB2260631B (en) * 1991-10-17 1995-06-28 Intel Corp Microprocessor 2X core design
US5297091A (en) * 1991-10-31 1994-03-22 International Business Machines Corporation Early row address strobe (RAS) precharge
US5276641A (en) * 1991-12-12 1994-01-04 International Business Machines Corporation Hybrid open folded sense amplifier architecture for a memory device
JP3481263B2 (en) * 1992-02-19 2003-12-22 株式会社リコー Serial storage device
US5257232A (en) * 1992-03-05 1993-10-26 International Business Machines Corporation Sensing circuit for semiconductor memory with limited bitline voltage swing
US5325516A (en) * 1992-03-09 1994-06-28 Chips And Technologies Inc. Processor system with dual clock
JPH05274879A (en) * 1992-03-26 1993-10-22 Nec Corp Semiconductor device
US5254883A (en) * 1992-04-22 1993-10-19 Rambus, Inc. Electrical current source circuitry for a bus
US5384745A (en) * 1992-04-27 1995-01-24 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
JP2892216B2 (en) * 1992-05-22 1999-05-17 株式会社東芝 Semiconductor memory
FR2694121B1 (en) * 1992-07-24 1995-09-22 Sgs Thomson Microelectronics MEMORY IN INTEGRATED CIRCUIT WITH PRELOADING PRIOR TO OUTPUT.
KR960001859B1 (en) * 1993-04-16 1996-02-06 삼성전자주식회사 Decoding circuit and the decoding method of semiconductor
US5511024A (en) * 1993-06-02 1996-04-23 Rambus, Inc. Dynamic random access memory system
KR960006271B1 (en) * 1993-08-14 1996-05-13 삼성전자주식회사 Semiconductor memory device with input/output line driving method for high speed operating
US5497347A (en) * 1994-06-21 1996-03-05 Motorola Inc. BICMOS cache TAG comparator having redundancy and separate read an compare paths
US5594937A (en) * 1994-09-02 1997-01-14 Ghz Equipment Company System for the transmission and reception of directional radio signals utilizing a gigahertz implosion concept
JP2630277B2 (en) * 1994-10-24 1997-07-16 日本電気株式会社 Semiconductor storage device
JP3739104B2 (en) * 1995-02-27 2006-01-25 株式会社ルネサステクノロジ Nonvolatile semiconductor memory device
US5636173A (en) * 1995-06-07 1997-06-03 Micron Technology, Inc. Auto-precharge during bank selection
US5873114A (en) * 1995-08-18 1999-02-16 Advanced Micro Devices, Inc. Integrated processor and memory control unit including refresh queue logic for refreshing DRAM during idle cycles
US5604705A (en) * 1995-08-22 1997-02-18 Lucent Technologies Inc. Static random access memory sense amplifier
JPH09171486A (en) * 1995-10-16 1997-06-30 Seiko Epson Corp Pc card
US5860125A (en) * 1995-11-08 1999-01-12 Advanced Micro Devices, Inc. Integrated circuit including a real time clock, configuration RAM, and memory controller in a core section which receives an asynchronous partial reset and an asynchronous master reset
US5841707A (en) * 1995-11-29 1998-11-24 Texas Instruments Incorporated Apparatus and method for a programmable interval timing generator in a semiconductor memory
US5712882A (en) * 1996-01-03 1998-01-27 Credence Systems Corporation Signal distribution system
US5657841A (en) * 1996-03-04 1997-08-19 Morvan; Jacques Extension cord reel assembly with ground fault interrupt outlets
US5742798A (en) * 1996-08-09 1998-04-21 International Business Machines Corporation Compensation of chip to chip clock skew
KR100204810B1 (en) * 1996-09-13 1999-06-15 윤종용 Semiconductor memory device having variable erasing block size
US5953263A (en) * 1997-02-10 1999-09-14 Rambus Inc. Synchronous memory device having a programmable register and method of controlling same
US5825710A (en) * 1997-02-26 1998-10-20 Powerchip Semiconductor Corp. Synchronous semiconductor memory device
JP3504104B2 (en) * 1997-04-03 2004-03-08 富士通株式会社 Synchronous DRAM
US5881016A (en) * 1997-06-13 1999-03-09 Cirrus Logic, Inc. Method and apparatus for optimizing power consumption and memory bandwidth in a video controller using SGRAM and SDRAM power reduction modes
JP3247639B2 (en) * 1997-08-07 2002-01-21 インターナショナル・ビジネス・マシーンズ・コーポレーション Semiconductor memory, data reading method and writing method for semiconductor memory
KR100281898B1 (en) * 1998-07-21 2001-02-15 윤종용 Duty cycle correction circuit and method for correcting duty cycle of data

Also Published As

Publication number Publication date
US5606717A (en) 1997-02-25
US6067592A (en) 2000-05-23
US6584037B2 (en) 2003-06-24
US6038195A (en) 2000-03-14
DE69132501T2 (en) 2001-08-23
US20010030904A1 (en) 2001-10-18
US20020141281A1 (en) 2002-10-03
US20020091890A1 (en) 2002-07-11
DE69132501D1 (en) 2001-02-08
DE69132721D1 (en) 2001-10-11
US6513081B2 (en) 2003-01-28
DE69133572T2 (en) 2008-02-14
US20050141332A1 (en) 2005-06-30
US6032215A (en) 2000-02-29
EP1022642A1 (en) 2000-07-26
DE69133550D1 (en) 2006-11-16
US6314051B1 (en) 2001-11-06
US6101152A (en) 2000-08-08
EP1640847A3 (en) 2006-05-31
WO1991016680A1 (en) 1991-10-31
EP1816570A2 (en) 2007-08-08
EP1816570A3 (en) 2007-08-15
US6546446B2 (en) 2003-04-08
US6032214A (en) 2000-02-29
US5954804A (en) 1999-09-21
DE00100018T1 (en) 2005-12-29
US6128696A (en) 2000-10-03
DE06125946T1 (en) 2007-11-22
DE69132121D1 (en) 2000-05-25
EP0525068A1 (en) 1993-02-03
EP1816569A2 (en) 2007-08-08
US6452863B2 (en) 2002-09-17
JP3414393B2 (en) 2003-06-09
JPH05507374A (en) 1993-10-21
US6035365A (en) 2000-03-07
US6598171B1 (en) 2003-07-22
US6570814B2 (en) 2003-05-27
US6185644B1 (en) 2001-02-06
US5513327A (en) 1996-04-30
DE69133500T2 (en) 2006-07-27
JP2003203008A (en) 2003-07-18
DE69133550T2 (en) 2007-01-11
DE69133611D1 (en) 2009-02-26
DE69133500D1 (en) 2006-03-30
DE69132501T3 (en) 2009-09-03
US5473575A (en) 1995-12-05
DE69133565D1 (en) 2007-04-19
US20020001253A1 (en) 2002-01-03
US5408129A (en) 1995-04-18
US6564281B2 (en) 2003-05-13
DE69133565T3 (en) 2015-10-08
US6049846A (en) 2000-04-11
EP1640847A2 (en) 2006-03-29
EP1830241B1 (en) 2008-06-25
US5499385A (en) 1996-03-12
US5928343A (en) 1999-07-27
EP0525068B1 (en) 2000-04-19
US6070222A (en) 2000-05-30
EP1022642B1 (en) 2001-09-05
DE06125954T1 (en) 2007-11-22
US6266285B1 (en) 2001-07-24
EP1640847B1 (en) 2007-06-13
US5841715A (en) 1998-11-24
DE69132121T2 (en) 2000-09-21
DE69132721T2 (en) 2002-05-29
IL96808A0 (en) 1991-09-16
US6415339B1 (en) 2002-07-02
US5841580A (en) 1998-11-24
JP3550143B2 (en) 2004-08-04
US6044426A (en) 2000-03-28
US6260097B1 (en) 2001-07-10
US5983320A (en) 1999-11-09
EP1816569B1 (en) 2009-01-07
US20040114454A1 (en) 2004-06-17
EP0525068A4 (en) 1995-09-20
US6378020B2 (en) 2002-04-23
DE69133565T2 (en) 2007-07-05
IL96808A (en) 1996-03-31
JP3404383B2 (en) 2003-05-06
IL110648A0 (en) 1994-11-11
US7110322B2 (en) 2006-09-19
IL110650A0 (en) 1994-11-11
EP1197830A2 (en) 2002-04-17
US5915105A (en) 1999-06-22
US20050033903A1 (en) 2005-02-10
JP2001273765A (en) 2001-10-05
DE69133598D1 (en) 2008-08-07
US5319755A (en) 1994-06-07
US6085284A (en) 2000-07-04
EP1816569A3 (en) 2007-09-26
EP1197830B1 (en) 2006-10-04
DE02000378T1 (en) 2005-12-29
DE1022642T1 (en) 2001-01-11
US20020004867A1 (en) 2002-01-10
US5809263A (en) 1998-09-15
US20020046314A1 (en) 2002-04-18
DE06125958T1 (en) 2007-11-22
US5638334A (en) 1997-06-10
US6182184B1 (en) 2001-01-30
US6034918A (en) 2000-03-07
IL110649A0 (en) 1994-11-11
US6975558B2 (en) 2005-12-13
KR100201057B1 (en) 1999-06-15
DE69133572D1 (en) 2007-07-26
US6304937B1 (en) 2001-10-16
EP1830241A1 (en) 2007-09-05
US20020016876A1 (en) 2002-02-07
US5657481A (en) 1997-08-12
US6697295B2 (en) 2004-02-24
EP1197830A3 (en) 2005-09-21
US20050030802A1 (en) 2005-02-10

Similar Documents

Publication Publication Date Title
EP1640847B1 (en) Dynamic random access memory (DRAM) semiconductor device
US6684285B2 (en) Synchronous integrated circuit device
US6324120B2 (en) Memory device having a variable data output length
EP1022641A1 (en) Integrated circuit i/o using a high performance bus interface

Legal Events

Date Code Title Description
CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

RR Request for reexamination filed

Effective date: 20070404

RR Request for reexamination filed

Effective date: 20081124

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20140917

LIMR Reexamination decision: claims changed and/or cancelled

Free format text: THE PATENTABILITY OF CLAIMS 29-35 IS CONFIRMED. CLAIMS 1-28 ARE CANCELLED.

Filing date: 20070628

Effective date: 20151027