JPS60261095A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the processing time when a data with a consecutive address is read continuously by controlling automatically increment or decrement of a content of an address register. CONSTITUTION:An initial address is written in an address register 2 and a complement of a number of times incrementing or decrementing the address is written in a control register 9. Then an increment/decrement 8 increments/decrements the content of the register 2 by 1 each and a memory cell group 4 is read continuously by the consecutive address until the content of the register 9 reaches ''0''. The processing time in reading the data of the consecutive address continuously is reduced in comparison with the use of an address counter by controlling automatically the increment or decrement of the content of the address register.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor memory device, and particularly to speeding up the readout thereof.

[Prior art]

FIG. 1 is a block diagram showing a conventional semiconductor memory device constituting a RAM (random access memory). In the figure, (1) is an external address line, (2) is an address register, and (3) is an internal address. Line (4) is a memory cell group, and (5) is an external output data line.

When reading data stored in the memory cell group (41), an address signal indicating the address within the memory cell group (4:) of the data is written to the address register (2) via the external address line (1). .This address register (2
) is input to the memory cell group (41) via the internal address line (31), and the data specified by the address is output to the output data line (5).However, the contents of the address register (2) may vary. A circuit for selecting output data at the correct timing between the memory cell group (41) and the output data line (5) or after the output data line (5) so as not to mistakenly use the data in the transient period during which the is necessary.

Next, when reading data at another address within the memory cell group (41), write that address from the external address line (1) to the address register (2) and write it to the internal address line (3).
) to access the memory cell group (41).

Conventional RAM is configured as described above, so each time one piece of data is read, it is necessary to input the address of that data from the external address line (11) and write it to the address register (21). Even when address data is read out sequentially, input from the external address line (1) is required for each piece of data, which has the drawback of increasing the time required for reading.

[Summary of the invention]

This invention was made in order to eliminate the drawbacks of the conventional devices as described above.In this invention, an incrementer/decrementer and an output data register are built into a semiconductor memory device, and data at consecutive addresses are sequentially stored. When reading data, input only the first address of the data group to be read from the external address line and set it in the address register, and then use the incrementer/decrementer to increment the contents of the address register at predetermined clock intervals. The address is sequentially changed by adding or subtracting 1, and the data read at the time when the changing address is settled is stored in the output data register, and then the contents of the address register are added to the numerical value at the next clock point. 1
It is designed to add or subtract. Also, in this invention, a control register is provided, and each time a value 1 is added or subtracted from the contents of the address register from the incrementer/decrementer, the value 1 is added to the control register, and the cumulative value indicated by the contents of the control register is By stopping the operation of the incrementer/decrementer when the total number of data to be read continuously is reached, the incrementer/decrementer
The operation of the decrementer was automatically controlled.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.
The same reference numerals as in the figure indicate the same or equivalent parts, (6) is the internal output data line, 17) is the output data register, (81 is the incrementer/decrementer, (9) is the control register, (101 is the data line) , u1+ is the input line of the signal state (read control signal), (1z is the control signal set. When the content of the control register (9) is the value O, the signal logic on the signal line (Iz becomes "0" and increment is performed. ta/decrementer 1
The operation of 81 is stopped.

The operation of the circuit shown in FIG. 2 will be explained below using numerical examples.

Memory cell group (41, for example, address r30.J
Consider the case where 20HJ pieces of data are read out continuously (in ascending order) from the address (the suffix H indicates hexadecimal display) to the address r4F□.In this case,
Incrementer/decrementer: The number of times 81 should add the number 1 to address register (2) is r 4F J −
r 30HJ'= r IFHJ = (r20HJ-r
oIHJ)H. That is, this is because the data at the first address "30H" among the r20)I J data is set from the external address line (1).

At the same time, write the numerical value r 30HJ from the external address line (1) to the address register (2), and at the same time write the numerical value representing -rlFHJ (the complement of the numerical value r IFHJ to the numerical value r 100g J, that is, the numerical value "EIH") to the data line (101 is written into the control register (9).The data at the address "-" is output onto the internal output data line (6).Signal R
At the time when D becomes active (that is, at the rising point of the pulse), the data on the internal output data line (61) is written to the output data register (7) and sent onto the external output data line (51).

Since the signal logic on the control signal line u21 is "1", the next time the signal RD becomes inactive (that is, at the falling point of the pulse), the incrementer/decrementer (8) is triggered and the address register (2 ) and control register (9)
Add the value 1 to the contents of and convert each contents to r 31H
J, "E2u J." Data at address "31H" is output to the internal output data line (6), and then written to the output data register (7) when the signal plane becomes active.

In this way, the data at consecutive addresses are read out one after another, but the contents of the address register (2) are "4EH".
” to r 4FHJ, control register (9)
The content changes from “FFH” to “00H”, and the signal line (
The signal logic on 121 becomes "0" and the operation of incrementer/decrementer 18) is stopped.

In the above embodiment, the complement of the numerical value "IFH" is set as the initial value of the control register (9), but the numerical value "IFH"
Set the incrementer/decrementer (8
) by subtracting the value 1. In that case, the contents of address register (2) are changed from r 4 EHJ to “4
FH”, the content of the control register (9) becomes “0”.
1” to “OOH”.

To read r20HJ pieces of data consecutively in descending order from address number r 4PHJ, use the address register (2).
When writing the numerical value “4FHJtl-control register (9
), write rIFHJ, and use the incrementer/decrementer (81) to sequentially subtract the numerical value 1 from both registers +21 and +91.

The contents of the control register (9) are set to a reset state (numerical value "0").
If it is turned ON (the state in which " is written), the circuit in FIG. 2 operates in the same way as the circuit in FIG. 1.

Note that in the above embodiment, incrementer/decrementer 1
Although the nine falling points of the signal RD are used as the trigger in step 8), other suitable lock signals may also be used.

Further, in the above embodiment, the control register (9) is provided separately from the memory cell group (41), but a part of the memory cell group (41) may be used as a register.

Further, the circuit shown in FIG. 2 may be configured on the same substrate as the CPU or other peripheral circuits connected thereto.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to shorten the processing time when data at consecutive addresses are successively read.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional device, and FIG. 2 is a block diagram showing an embodiment of the present invention. (1)...External address line, (2)...Address register, (41...Memory cell group, (7)...Output data register, 181...Incrementer/Decrementer, (9) ... Control register. In addition, the same reference numerals in each figure indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 2 11 Section χ Procedure Amendment (Voluntary) #'t-ff!tJI s l , Indication of the case Japanese Patent Application No. 59-116904 2 'Issue 1') Name Semiconductor storage device 3, relationship to the amended person case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name
(601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 4, Agent Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo (all above)

Claims (2)

[Claims] (1) A memory cell group in which memory cells each storing a predetermined number of bits of data are arranged in each memory location determined by an address, and an address register in which an address signal specifying the data to be accessed in this memory cell group is stored. , means for writing an address signal into this address register from an external address line; an incrementer/decrementer that adds or subtracts a numerical value of 1 to the contents of the address register at every predetermined clock; operating this incrementer/decrementer; A control register that outputs a control signal to stop the operation. At the time of writing an address signal to the above address register,
A numerical value related to the total number of data to be continuously read from the memory cell group is written in the control register, and the incrementer/decrementer adds or subtracts a numerical value 1 to the contents of the address register at every predetermined clock. At each point in time, the incrementer/decrementer adds or subtracts a value 1 to the contents of the control register, and when the contents of the control register reach a predetermined value, the incrementer/decrementer adds or subtracts 1 from the control register to the control register. means for outputting a signal to stop the operation of the address register; an output data register to which data accessed by the contents of the address register and read from the memory cell group is input; A semiconductor memory device comprising means for writing an input signal to the output data register into the output data register at the time when the process of changing the contents of the address register by the /decrementer is completed. (2) The memory cell group, address register, incrementer/decrementer, control register, and output data register are formed on the same substrate as other related circuits. Semiconductor storage device.