DE19758672B4 - Signal transmission system for LSI chips - Google Patents

Abstract

The system is used for signal transmission between LSI chips and has a signal transmission line with a response time equal to, or longer than, the length of a transmission symbol. The terminal resistance (51,53) for one or both ends of the transmission line is greater than the characteristic impedance of the transmission line (2). A driver output resistance is set to a higher value, or a damping resistance (7) is connected in series with the transmission line.

Description

The present invention relates on a transfer device of a signal and a receiver circuit for use in the device for transmitting a signal, and more specifically to a device for the transmission of signals between LSI chips, and a receiver circuit to use the system according to claims 1 and 99th

Lately the performance of DRAMs (Dynamic Random Access Memory) and processors greatly increased, and more specifically, processor performance was speed greatly improved while the improvement in DRAM performance especially in terms of the storage capacity took place. Meanwhile, the improvement in the operating speed was the DRAM is not as significant as the improvement in memory capacity, which makes the speed difference between the DRAM and the processor has further increased and this speed difference in recent years has been the bottleneck with the increase computer performance has been.

They are signal transmission systems for signal transmission between processors and DRAMs (DRAM modules) known in the next Years great Widespread, including the SSTL (Series-Stub Terminated Logic) and other low-amplitude signal standards. In which SSTL or a comparable signaling system with lower Amplitude becomes a signal transmission line (in the following transmission line called) completed by a resistor that is about the typical Transmission line impedance, thereby suppressing reflections at the end ends and high signal transmission speeds can be achieved. Furthermore, by using the signaling with low amplitude the power required to charge and discharge the transmission line decreased, causing a transmission can be done at high speed and low power.

In a bus system (signal transmission system), The SSTL uses high-speed signal transmission through a balanced termination (end resistance) and a reactive resistance allows and the power consumption is based on compared to known systems reduced signal using low amplitude. Meanwhile, the total power consumption of the device on the same Hold level or push it below that level while simultaneously the signal transmission bandwidth between the DRAM and the processor, there is a need for a device to transfer a signal with a lower power requirement.

Furthermore, for example, in a DRAM controller and several DRAM chips through a RAM bus channel a common signal transmission line (Bus) connected to each other. For transmission and recording the high speed signals must have an exact timing between the signal transmitter and the receiver be created. Correct clocking can be carried out in the RAM bus channel as well as the reception as well as for transmission are provided, provided that a clock line and a Signal transmission line both in terms of their routing as well as their electrical properties are identical. That is, the RAM bus channel requires that the Clock line and the signal transmission line along the same Wegs are formed and have the same electrical properties.

However, the load characteristics differ between the clock line and the signal transmission line inevitable. The reason for this is, that the Signal transmission line the use of a latch circuit that is synchronous with the Receiving clock operated to create a highly sensitive reception will while the clock line the use of a differential amplifier, etc. needed since no latch circuit can be used. Because the load property a latch circuit and that of a differential amplifier and the same is different, are the electrical conduction properties (e.g. the delay per unit length) between the clock line and the signal transmission line inevitable different.

WO 91/16680 A1 describes a high-speed bus system presented. The high data transmission bandwidth the bus system is of the order of magnitude due to a high clock rate a few hundred MHz, through a controlled line impedance and achieved by bus line ends sealed on both sides. This high data transmission bandwidth of the high-speed bus system has some difficulties connected. The high clock rate in connection with the due to the longitudinal extension delays that are not negligible leads to undesirable Inter-symbol interference, which is a misinterpretation of the transmission data can cause by the receiving unit. It also requires a high Data transfer rate exact clock synchronization between transmitter and receiver unit, which is particularly the case in distributed systems due to the longitudinal extension the bus lines is difficult to implement.

The state of the art and the same problems will arise later described in detail with reference to the accompanying drawings.

It is an object of the present invention Transfer device to create a signal in which the response time of a signal transmission line approximately equal to or more than the length one transferred Symbol. It is another object of the present invention, a Transfer device to create a signal that can generate clocks without losing symmetry exist between the clock line and the signal transmission line (bus) must, and the the gap can decrease when switching from a transmission device to another is done.

According to the present invention is a device for transmission a signal is provided in which the response time of a signal transmission line approximately equal to or more than the length one transferred Symbol.

The task is characterized by the characteristics of claim 1 or 49 solved. The subclaims contain advantageous further training.

A terminating resistor on one or both ends of the signal transmission line provided a higher Have value as a typical impedance of the signal transmission line. At least one resistor can be in series with the signal transmission line be switched or the signal transmission line can be constructed so that it itself has a resistance.

Signals can be transferred between several circuit blocks become. At least one of the multiple circuit blocks can a receiver circuit for receiving a signal which is transmitted by the signal transmission line, and the receiver circuit can be a circuit for combining signals from earlier times Signal components, and have a signal logic decision circuit, to make a logical decision regarding the signal. The circuit for cleaning up past signal components can use an intersymbol interference estimation unit to estimate Inter-symbol interference based on a previously received one Signals and a subtraction unit for subtracting the estimated intersymbol interference of a signal that is actually at the current sampling time is obtained.

The intersymbol interference estimation unit can be constructed so that it a sum of linear weights from previously estimated values determined. The intersymbol interference estimation unit can be a shift register, previous bit information to obtain, and have a weighting unit by which in the Weight data contained in the shift register. The weighting unit can consist of several resistors be constructed. The weighting unit can consist of several capacitors and switches.

The intersymbol interference estimation unit can be constructed so that it non-linear weights of previously estimated values determined. Inter-symbol interference estimator may have a shift register for holding previously obtained bit information and have a storage unit to store estimates corresponding to those shown in to store data held in the shift register.

The intersymbol interference estimation unit can have an accumulation unit in order to obtain an analog value of the back in time received signal to accumulate and an intersymbol interference generating unit, to generate inter-symbol interference from the analog value. The inter-symbol interference estimation unit can be constructed in this way be them a linearly weighted sum of an analog value one in front of one Clock received signal and a fixed analog reference value determined. The inter-symbol interference estimation unit can have multiple switching units and capacitor units.

The multiple circuit blocks can be integrated Be semiconductor circuit chips, and the signal transmission system can be as a bus system can be formed which has a plurality of integrated semiconductor circuit chips combines. The signal transmission line can be used as a bidirectional data bus or a data signal line accomplished his. The signal transmission line can be implemented as a unidirectional address bus or an address signal line. The multiple semiconductor integrated circuit chips can with a processor or a controller and several memory modules be trained.

Furthermore, according to the present invention a device for transmission a signal between a plurality of circuit blocks by means of the signal transmission line provided that a clock distribution unit for distributing a Clocks to each of the circuit blocks by means of a clock line, a common clock generation unit to create a common beat based on the beat for everyone of the circuit blocks with an accuracy equal to a time shorter than the period, which the signal needs to traverse the wiring between the signal blocks, and a unit for transmitting and receiving the signal synchronously has the common beat.

Each of the circuit blocks can an integrated circuit module, an integrated circuit chip or be a circuit component within a single chip. The maximum length the signal transmission line can't be bigger than is the distance that the signal is along in a bit time period Signal transmission line travels. The maximum length the signal transmission line can't be bigger than half of the distance that the signal is along in a bit period Signal transmission line travels.

A buffer can be located in the signal transmission line added to delay the signal with a time duration that is the same or an integer multiple is a bit duration of the signal, and around the delayed signal back to transfer what the buffer the transfer the signal over a Distance allows which is the maximum length of the Signal transmission line exceeds. The buffer can connect to other circuit blocks connected to the buffer output a clock that the other circuit blocks for Generate a common clock.

The signal transmission line can be a Bus of the type with a common signal transmission line, and it can be terminated at one end or both ends of the bus with a terminating resistor be provided with a resistance value of approximately equal or more than the typical impedance of the bus. A driver circuit for Driving the signal transmission line may have an output impedance that is greater than the typical impedance the signal transmission line. The driver circuit can have a DC drive output produce.

The signal generation unit for the common Clock can record bars that run lengthways a clock line that run between a clock segment forward moving clock and a clock segment with backward moving Clock is folded, and can generate the common clock by they have a clock value midway between the rising edges of the clock going forward and backward, that of the circuit block is obtained. The generation unit for one common clock can have a linear sum generating unit, around a linear sum of sinusoidal Clocking the clock segments for the forward and moving backwards To generate clock of the folded clock line, and a waveform shaping unit for waveform shaping of the sine signals by the linear sum generating unit be preserved. The common clock generating unit can a phase interpolator have the clocks running backwards and forwards in the folded clock line, and around a clock with a Phase in the middle between the forward and the back generate running clock.

The signal generation unit for one common clock can be along generate a standing wave of the clock line, and each of the circuit blocks can take a beat from the standing wave along the Clock line is generated. A generation unit for generating the standing wave along The clock line may have a unit to actively reflect it Signal of the clock either in the clock drive circuit or in the clock termination circuit or both, creating an electrical length of Clock line can be set.

The cycle of the clock that is used to generate the common clock used can be more than twice the length of a bit duration of the signal that is along the Signal transmission line transmitted becomes. The clock line can have transmission properties have significantly different from those of the signal transmission line differ, and they can be improved with an electrical Shielding against the external environment in the Comparison to the signal transmission line be provided.

At least one of the circuit blocks can be provided with a receiver circuit on the receiving side, to eliminate inter-symbol interference of the signal, and it can transmit that transmitted by means of the signal transmission line Receive signal.

Furthermore, according to the present invention a receiver circuit intended for use in a device for transmitting a signal, to an over a signal transmission line transmitted Receive signal, the receiver circuit being a circuit for signal cleansing of earlier signal components of the Signal and a signal logic decision circuit, to make a logical decision regarding the signal.

The circuit for signal cleansing of past An inter-symbol interference estimator can share signals for assessment inter-symbol interference based on one previously received Signal and a subtraction circuit to the estimated intersymbol interference subtract from a signal that is actually at the current time Will be received. The intersymbol interference estimation unit can be constructed so that it a sum of linear weights from previous decision values determined. The intersymbol interference estimation unit can be a shift register for holding previous bit information and a weighting unit to weight the data held in the shift register. The weighting unit can be constructed from several resistors. The weighting unit can be made up of several capacitors and circuits.

The intersymbol interference estimation unit can be constructed so that it nonlinear weights of previous decision values determined. The Inter-symbol interference estimator can have a shift register for holding previous bit information and a storage unit for storing estimated values according to the in data held in the shift register.

The inter-symbol interference estimation unit may have an accumulation unit for accumulating an analog value of the previously received signal and inter-symbol interference generation unit for an inter-symbol interference limit from the analog value. The inter-symbol interference estimator may be constructed to determine a linearly weighted sum of an analog value of a signal received a clock and a fixed analog reference value. The inter-symbol interference estimation unit can have a plurality of switching units and capacitor units.

The signal generation unit for one common beat can move you forward directed clock and a backward Measure the lengthways Clock line for the forward or moving backwards Clock run, and can find the common clock by identifying a Clock value in the middle between the rising or the falling Flanks of the forward or backward (running) Clock that is picked up by each circuit block. At least a pair of the clock generating circuits that constitute a generating circuit for one forward directed clock and a backward generating circuit Can have clock for every couple on clock lines including the clock line for the forward or moving backwards Clock be provided, and the generating circuits for the after forward directed clock and the backward clock can the Phases of the rising or falling edges of the forward or adjust backward clock to set the phases to one bring predetermined value. The generation circuit for the after Front-facing clock can have a clock synchronization unit of an interphase signal obtained by extracting a Intermediate point between the rising or falling edge of the forward and backward measures received on the rising or falling edge of a reference clock, a unit for detecting a phase difference between the intermediate phase signal and the common clock and a unit for setting the phase of the forward clock so that the detected phase difference becomes zero.

Multiple clock generation circuits can for each Clock line section for the backwards or forward moving generation clock may be provided, the clock generation circuit, which is at each end of the clock line sections, only a circuit for forward or moving backwards Clock, and each of the clock generating circuits that along at intermediate positions the clock line section for the forward or moving backwards Clock can be a backward clock generation circuit have a common clock and a backward Clock based on the forward Clock generated by the clock generating circuit on the previous one Stage is received, and a forward clock generating circuit, which is a new forward beat for the clock generation circuit the following stage. Each of the clock generation circuits can furthermore have a buffer for controlling a signal, which is supplied by means of a signal line. The signal line, the the circuit blocks connects can be a point-to-point connection, and the clock generating circuits can each for one or for several of the circuit blocks be provided.

The generating circuit for the backward moving Clock can consist of a feedback loop, which carries out a phase adjustment, by a constant phase difference between the received forward clock and the backward clock maintain. The backward clock generation circuit can with a variable delay unit be provided, a feedback loop to synchronize a delay value in the variable delay unit on one clock cycle and one unit around the forward clock by a value proportional to the clock cycle through a delay stage to delay, subordinate to the feedback loop is controlled. The variable delay unit can have several variable delay units in a cascade, the feedback loop may have the delay value in each of the variable delay circuits control with the same value and the backward moving clock can stop along a designated node of the multiple variable delay circuits be removed.

The phase of the backward moving clock can do so be controlled that the Phase difference between the advancing clock and an inverted one Version of the backward moving clock on each of the circuit blocks, the forward and backward facing Clock received, is within ± 180 ° or ± 90 °.

The backward moving clock can inverted version of the forward moving clocks. The forward one and the backward one Can beat each have a waveform, its rise and fall times form an essential portion of a clock cycle. The forward and backward moving Clock can be a sinusoidal, triangular or trapezoidal waveform exhibit. The common clock generating circuit can be a difference comparator, for whose difference inputs the forward and moving backwards Be given tact.

The termination ends of the forward and backward clocks can each be terminated with an impedance that is greater than the typical impedance for the forward or backward clock. At least one forward or backward moving clock can be transmitted using a differential signal transmission method. The advancing clock can be transmitted as a complementary signal and the backward clock can be generated from a signal created by differential amplification of the complementary forward clock.

The forward and backward moving clock can by Introduce of a delay value a feedback controlled variable delay circuit be introduced into a reference clock in an idle state. If the forward and backward moving Clock can be removed, a once issued outside a chip Signal in turn latched into the chip as a clock moving forward on the basis of which the common clock is generated.

According to the present invention is a device for transmission a signal with a signal transmission line, which is designed so that it Data without subpoena for transmits each bit by an intersymbol interference component by the previous Data is introduced is eliminated, and a unit for eliminating an intersymbol interference component a signal is provided which is transmitted by means of the signal transmission line becomes.

The signal transmission line can with be formed at one end. The signal transmission line can be in Form complementary Buses running be and the device for transmission a signal can be a bus driver of the complementary type and a bus amplifier of the complementary type exhibit.

The device for transmission a signal can also have a precharge circuit, the the signal transmission line not for everyone Bit during precharges a data transfer period, and the the signal transmission line outside the duration of the data transfer precharges to a predetermined potential level. The precharge circuit the signal transmission line can only while a predetermined period before and after the data transmission period subpoena. The precharge circuit can be the signal transmission line while preload all time periods except the data transfer period. The precharge circuit can be used in any signal transmission line Charge way externally.

The complementary type bus amplifier can be an amplifier with an intersymbol interference cancellation function for a single-ended line corresponding to each of the complementary buses and having a complementary type differential amplifier, the downstream of the amplifier with inter-symbol interference elimination is provided. The complementary type differential amplifier can as a differential amplifier of the Latch-type. The latch type differential amplifier can be used as a differential amplifier be formed with a gate receptacle. The differential amplifier of the complementary type can be designed as a current mirror differential amplifier.

The complementary type bus amplifier can a differential amplifier with a first and a second complementary gate input, an amplifier precharge circuit, provided at each of the first and second inputs of the differential amplifier is to precharge in such a way that the sensitivity of the differential amplifier is increased, and have two groups of first and second capacitors, which are provided at the first and second inputs of the differential amplifier, the first and the second input of the differential amplifier with the complementary buses be connected by means of the first and second capacitors can, and in each group of capacitors the first capacitor always with one of the complementary ones Busses can be connected, whereas the second capacitor is selective through a switching device with one or the other of the complementary buses can be connected.

In each group of capacitors, the second capacitor may be coupled to the bus opposite the bus coupled to the first capacitor connected to the same differential input during an inter-symbol interference estimation and may be connected to the same bus during a data decision process connected to the first capacitor connected to the same differential input, thereby eliminating the complementary intersymbol interference components. The complementary type bus amplifier may have a first and a second amplifier block that have more than one intersymbol interference cancellation function, and may be constructed so that the second amplifier block performs a data decision process while the first amplifier block has an intersymbol interference estimation process and at the next sampling time executes an inter-symbol interference estimation process while the first amplifier block is executing a data decision process, and wherein the first and the second amplifier block each have a differential amplifier, a first and a second complementary gate input, an amplifier precharge circuit which are provided at the first and the second input of the differential amplifier to precharge it in such a way as to improve the sensitivity of the differential amplifier and to have two groups of first and second capacitors connected to the first and the second input of the differential amplifier are provided, the first and the second input of the differential amplifier being able to be connected to the complementary buses by means of the first and second capacitors, and in each group of capacitors the first capacitor can always be connected to one of the complementary buses , whereas the second capacitor se can be selectively connected to one or the other of the complementary buses by a switching unit.

The complementary type bus amplifier can a differential amplifier with a first and a second gate receiving complementary input, an amplifier precharge circuit, which is provided at a first input of the differential amplifier to it to precharge in such a way that the sensitivity of the differential amplifier is increased, an auto zero switch to control the electrical conductivity between the second input of the differential amplifier and an output of the Differential amplifier and have two groups of first and second capacitors, which are provided at the first and the second input of the differential amplifier are, the first and the second input of the differential amplifier with the complementary buses by means of the first and second capacitors can and in each group of capacitors the first capacitor always with one of the complementary ones Buses can be connected, whereas the second capacitor can be selectively connected a switching device connected to one or the other of the complementary buses can be. In each group of capacitors, the second capacitor can while an intersymbol interference estimation on the bus of the bus connected to the first capacitor which is connected to the same differential input and can be used during a Data decision process connected to the same bus, which is connected to the first capacitor, the one with the same differential input is connected, thereby eliminating complementary intersymbol interference components can be achieved.

The complementary type bus amplifier can have a first and a second amplifier block, each have an intersymbol interference cancellation function, and can be constructed so that the second amplifier block executes a data decision process while the first amplifier block performs an intersymbol interference estimation process and at the next time executes an intersymbol interference estimation process during the first amplifier block one Executes data decision process, and wherein the first and the second amplifier block each have a differential amplifier a first and a second gate receiving complementary input, one Amplifier precharge circuit, which is provided in a first input of the differential amplifier to it so that the sensitivity of the differential amplifier elevated an auto-zero circuit to control the electrical conductivity between the second input of the differential amplifier and an output of the Differential amplifier and have two groups of first and second capacitors, which are provided at the first and the second input of the differential amplifier are, the first and the second input of the differential amplifier with the complementary Buses connected by means of the first and second capacitors could be, and in each group of capacitors the first capacitor always with one of the complementary ones Busses can be coupled, whereas the second capacitor is selective through a switching device with one or the other of the complementary Buses can be connected.

In each group of capacitors can the second capacitor during opposite the intersymbol interference estimator on the bus be coupled to the bus, which is connected to the first capacitor which is connected to the same differential input and can during of the data decision process are connected to the same bus, connected to the first capacitor, the same one Differential input is connected, eliminating the complementary intersymbol interference components can be done. If the value of the first capacitor is labeled C 10 and the value of the second capacitor is denoted by C20 is, can the values of the first and second capacitors are chosen so that she essentially satisfy the equation C10 / (C10 + C20) = (1 + exp (-T / τ)) / 2, where τ is the time constant of the bus and T is the cycle of one bit or the length of time while of the 1-bit data in the bus.

The differential amplifier can as a differential amplifier of the latch type his. With the exception of a data readout period, the differential amplifier can be one Set the output node to a high level when a data acquisition transistor is of the N channel type, or a low level if the data acquisition transistor is from P channel type is which increases the operating speed. During a preload for the differential amplifier input node and an inter-symbol interference component estimation process within a data readout period and with the exception of a data transfer period can the differential amplifier an output node to a high level when a data acquisition transistor from N channel type is or set to a low level when the data acquisition transistor is of the P-channel type, which increases the operating speed. The differential amplifier can be designed as a current mirror differential amplifier. The differential amplifier can so executed be that he only during the data transfer period is operated.

The complementary type bus amplifier may be a data bus amplifier, the complementary type bus driver may be a sense amplifier, and the complementary buses may each be data buses, the data bus amplifier transmitting an inter-symbol interference component into that of the sense amplifier by means of the data buses can eliminate the data and can therefore perform an uninterrupted data readout without pre-loading the data bus during data transmission.

The semiconductor memory device can be a DRAM. Data buses can be hierarchically structured. The data buses can be a local data bus, around data from the sense amplifier are output using a selected column transfer gate transferred to, and have a global data bus to transfer data transmitted from the local data bus be chosen by means of a local data bus switch.

The data bus amplifier can process data of two amplifier blocks in in a nested manner in sync with the rising and falling Clocking a clock or the increasing clocks of complementary clocks Read out, which are provided in parallel and with an intersymbol interference elimination function are provided. The semiconductor memory device can continue a generation unit for have a first column selection signal having a column decoder and has a column selection signal generating circuit, a column selection signal from the increasing clocking of the clock to generate, and a second column selection signal generation unit with a column decoder and a column selection signal generating circuit, a column selection signal from the falling timing of the clock or to generate the rising clock of an inverted clock, the first and second column selection signal generation units being nested Way can be operated to switch between the column selection signals with a high Speed. The first and second column selection signal generating units can Column selection signals in overlapping Generate wise.

The data bus amplifier can use the data of a single amplifier block read out that with an intersymbol interference removal function is provided. The amplifier block that with the intersymbol interference removal function an intersymbol interference estimation process can be synchronous with the increasing one or falling timing of a clock, as well as a data decision process synchronous with the rising or falling timing of the clock To run.

The semiconductor device can be one Load included for the data bus is provided. For the In case the Data buses are gradually moving towards a low without the load Level shift, the load can be from a P-channel MOS transistor built with a size be that exactly for oppression the drift of the data buses is sufficient, and the complementary Buses can each pulled to a high level by the P-channel MOS transistor, with Except for data transmission the P-channel MOS transistor can be turned off to stop the effect of the load. In cases that the data buses without the load to drift towards a low level the load can be built up from an N-channel MOS transistor of a size which is exactly for oppression the drift of the data buses is sufficient, and the complementary Buses can each pulled to a high level by the N-channel MOS transistor be, with the exception of data transmission of the N-channel MOS transistor can be turned off to stop the effect of the load.

In cases where the data buses are without the load tend to drift towards a low level side Load can be formed from a resistor, and the resistor can can be connected to a high level by means of a transistor, wherein with the exception of data transmission the transistor to stop the effect of the load can be turned off can. In cases that the Data buses without the load drift towards the low level the load may cross-coupled P-channel MOS transistors be constructed, and the cross-coupled P-channel MOS transistors can connected to a high level by means of a control transistor be so that a Bus that transfers high level data towards of a higher one Level than the other bus that carries low level data, where with the exception of data transmission the control transistor is turned off to stop the effect of the load can be. In cases that the Data buses without the load drifting towards the high level side can tend the load from an N-channel MOS transistor with a Size built up be that exactly for oppression the drift of the data buses is sufficient, and the complementary Buses can each toward a low level through the N-channel MOS transistor be pulled, except during data transfer the N-channel MOS transistor turned off to stop the effect of the load can be.

In the event that the data buses tend to drift toward a high level side without the load, the load can be constructed with a P-channel MOS transistor of a size sufficient to suppress the data bus drift, and the complementary ones Buses can each be pulled low by the P-channel MOS transistor, with the exception of data transmission, the P-channel MOS transistor can be turned off to stop the effect of the load. In cases where the data buses tend to drift towards a high level side without the load, the load can consist of a resistor and the resistor can be connected by means of a transistor with a low voltage level, with the exception of data transmission the transistor for stopping the Effect of the load can be switched off. In cases where the data buses are without the When the load tends to drift toward a high level side, the load may be composed of cross-coupled N-channel MOS transistors, and the cross-coupled N-channel MOS transistors may be connected to a low level by means of a control transistor so that a bus which transmits low level data is pulled to a lower level than the other bus which transmits high level data, except for the data transmission, the control transistor can be turned off to stop the effect of the load.

The load can only be in one place be provided on the global data bus. Multiple loads can be different from each other spaced at multiple locations along the global data bus his. The load can only be provided on the local data bus. Multiple loads can spaced apart at multiple locations along the global data bus and of the local data bus can be provided. The sense amplifier can be designed as a cross-coupled CMOS transistor pair. The sense amplifier can have a differential potential on a bit line through a gate record, and can transfer data to the data buses before the bit line Completely open which prevents data from being transmitted through the sense amplifier the differential potential of the data buses are inverted.

The sense amplifier can be used as a gate pickup amplifier a P-channel or N-channel MOS transistor accomplished his. The sense amplifier can be used as a gate pickup amplifier executed with a CMOS transistor his. The semiconductor memory device can have a time offset, from a time of generation of a column selection signal Choice of a sense amplifier until a time of arrival of data is determined from the chosen one sense amplifier on the bus amplifier are compensated based on a position of the selected sense amplifier, and can determine control signals from the data bus amplifier be used at an appropriate time when the arrived Data take effect, the time offset by a difference between a first length from a column selection signal generation circuit to the selected sense amplifier and a second length of the chosen one sense amplifier to the data bus amplifier is caused by means of the data bus.

The semiconductor memory device can generate the column selection signal for the sense amplifiers at a later time, the closer on the column selection signal generating circuit and the data bus amplifier and at an earlier time for the sense amplifier generate that are further away from the column selection signal generating circuit and the data bus amplifier which means the timing at which the data arrive at the bus amplifier essentially independent of the position of each of the sense amplifiers are kept constant can. The semiconductor memory device can be divided into several memory blocks be that a longitudinal direction cross the data bus that is directly connected to the data bus amplifier is, a block selection address for selecting the memory block can be in the Column selection signal generation circuit can be input, a delay value in the column selection signal generating circuit can by the block selection address are controlled, whereby the timing at which the data arrive at the bus amplifier essentially independent be kept constant from the position of each of the sense amplifiers can.

The semiconductor memory device may a row block selection address to a column selection signal generating circuit give, and a delay value in the column selection signal generating circuit can by the block selection address be controlled so that the Generation clocking for the column selection signal for blocks forward, which are further away from the bus amplifier, and for blocks delayed will that closer to the bus amplifier are located. The delay value in the column selection signal generating circuit can be by a transfer gate and an additional capacitor are formed, the capacitance of the additional capacitor being larger for the blocks, the closer on the bus amplifier are located. The delay value in the column selection signal generating circuit can be through a delay line consisting of several cascades arranged delay stages are formed, the delay line a larger number of delay stages provides that must be traversed for a block that is closer to the repeaters located. Each of the delay levels can have first and second NAND gates and an inverter exhibit.

The semiconductor memory device can control signals used in the data bus amplifier to a earlier Time for sense amplifier generate that closer on the column selection signal generation circuit and the data bus amplifier, and to a later one Time for sense amplifier generate that are further away from the column selection signal generating circuit and the data bus amplifier and can control signals used in the data bus amplifier generate at a convenient time when the arrived Data take effect.

Furthermore, according to the present invention there is provided a receiver circuit for use in an apparatus for transmitting a signal which transmits data by means of complementary buses and which detects the data by eliminating an inter-symbol interference component introduced by the preceding data, comprising a differential amplifier a first and a second gate pick-up complementary input, an amplifier precharge circuit which each of the first and second inputs of the differential amplifier is provided to precharge it such that the sensitivity of the differential amplifier is increased, and two groups of first and second capacitors are provided at the first and second inputs of the differential amplifier, the first and second inputs of the differential amplifier are coupled to the complementary buses by means of the first and second capacitors, and in each group of capacitors the first capacitor is always coupled to one of the complementary buses, whereas the second capacitor is selectively connected to one by a switching unit or the other of the complementary buses is coupled.

The present invention is made from referring to the following description of preferred embodiments on the accompanying drawings. Show it:

1 2 shows a block diagram of the basic functional arrangement of a device according to the invention for transmitting a signal,

2 1 shows a schematic block diagram of an example of a device for transmitting a signal according to the prior art,

3 the relationship between the symbol length and the response time in a device for transmitting a signal according to the prior art,

4A and 4B graphically the relationship between the symbol length and the response time in a device for transmitting a signal according to the invention,

5A 2 shows a block diagram of an example arrangement of a receiver circuit in the device according to the invention for transmitting a signal,

5B schematically the structure of a self-calibration comparator in the receiver circuit of 5A .

6A and 6B schematically the operation of the receiver circuit of 5A .

7 2 shows a block diagram of an exemplary embodiment of a device according to the invention for transmitting a signal,

8th a graph of a waveform in each memory block in the device for transmitting a signal from 7 .

9 2 shows a block diagram of a first mode of a device according to the invention for transmitting a signal,

10 2 shows a block diagram of a second mode of a device according to the invention for transmitting a signal,

11 2 shows a block diagram of a third mode of the device according to the invention for transmitting a signal,

12 2 shows a block diagram of a first exemplary embodiment of the receiver circuit in the device according to the invention for transmitting a signal according to the second mode,

13 2 shows a block diagram of a second exemplary embodiment of the receiver circuit in the device for transmitting a signal according to the second mode of the present invention,

14 2 shows a block diagram of a third exemplary embodiment of the receiver circuit in the device according to the invention for transmitting a signal according to the second mode,

15 2 shows a block diagram of a fourth exemplary embodiment of the receiver circuit in the device according to the invention for transmitting a signal according to the second mode,

16 a block diagram of an example of the self-calibration comparator in the receiver circuit of FIG 5A .

17 a circuit diagram of another example of the self-calibration comparator in the receiver circuit of FIG 5A .

18 a circuit diagram of another example of a self-calibration comparator in the receiver circuit of 5A .

19 2 shows a block diagram of a first example of a device according to the invention for transmitting a signal,

20 2 shows a block diagram of a second example of a device according to the invention for transmitting a signal,

21 2 shows a block diagram of a third example of a device according to the invention for transmitting a signal,

22 2 shows a block diagram of a fourth example of a device according to the invention for transmitting a signal,

23 2 shows a block diagram of a fifth example of a device according to the invention for transmitting a signal,

24 2 shows a block diagram of a sixth example of a device according to the invention for transmitting a signal,

25 2 shows a block diagram which schematically represents a known device for transmitting a signal,

26 2 shows a block diagram of the basic functional structure of a device for transmitting a signal according to a third mode of the present invention,

27 a graph (first part) for explaining the operation of the device for transmitting a signal from 26 .

28A and 28B Graphics (second part) for explaining the operation of the device for transmitting a signal from 26 .

29 2 shows a block diagram of a first exemplary embodiment of the signal transmission system according to a third mode of the present invention,

30 a block diagram of a modified example of the device for transmitting a signal from 29 .

31 FIG. 2 is a block diagram showing a configuration example of an essential portion of each device in the signal transmission device according to the third mode of the present invention;

32 1 is a block diagram showing another structural example of an essential portion of each device in the signal transmission device according to the third mode of the present invention;

33 2 shows a block diagram of a second exemplary embodiment of the device for transmitting a signal according to the third mode of the present invention,

34 2 shows a block diagram of a third exemplary embodiment of the device for transmitting a signal according to the third mode of the present invention,

35 a block diagram showing a modified example of the device for transmitting a signal s from 34 shows,

36 2 shows a block diagram of a fourth exemplary embodiment of the device for transmitting a signal according to the third mode of the present invention,

37 1 is a circuit diagram showing an example of a driver circuit in the signal transmission apparatus according to the third mode of the present invention.

38 2 shows a block diagram of a fifth exemplary embodiment of the S device for transmitting a signal according to the third mode of the present invention,

39A and 39B Block diagrams of a sixth embodiment of the S device for transmitting a signal according to the third mode of the present invention,

40A and 40B Block diagrams of a seventh embodiment of the device for transmitting a signal according to the third mode of the present invention,

41 FIG. 2 is a circuit diagram showing an example of a common clock generation circuit in the S signal transmission apparatus according to the third mode of the present invention;

42 FIG. 2 is a circuit diagram of another example of the common clock generation circuit in the signal transmission device according to the third mode of the present invention; FIG.

43 a circuit diagram of another example of a comparator in the common clock generating circuit of 42 .

44 FIG. 2 is a circuit diagram of another example of the signal generation circuit for a common clock in the device for transmitting a signal according to the third mode of the present invention;

45 2 shows a block diagram of an eighth exemplary embodiment of the device for transmitting a signal according to the third mode of the present invention,

46 4 is a graph showing an example of a clock distribution transmission line in the signal transmission apparatus according to the third mode of the present invention;

47 1 is a block diagram showing the basic functional structure of an apparatus for transmitting a signal according to a fourth mode of the present invention.

48 Fig. 10 is a timing chart for explaining the operation of the signal transmission device of 47 .

49 Fig. 4 is a block diagram of a first embodiment of the S device for transmitting a signal according to the fourth mode of the present invention;

50 Fig. 10 is a block diagram of an example of a common clock generating circuit for use in the device for transmitting a signal from 49 .

51 a block diagram of an example of a forward clock generating circuit for use in the apparatus for transmitting a signal from 49 .

52 a block diagram (first part) of another example of the common clock generating circuit for use in the apparatus for transmitting a signal from 49 .

53 a block diagram (second part) of another example of the common clock generating circuit for use in the apparatus for transmitting a signal from 49 .

54 a block diagram of an example of a reverse clock generating circuit for use in the apparatus for transmitting a signal from 49 .

55 a circuit diagram of an example of a phase comparator for use in the common clock generating circuit in the apparatus for transmitting a signal from 49 .

56 a block diagram of an example of a control circuit for use in the common clock generating circuit in the apparatus for transmitting a signal from 49 .

57 a circuit diagram of an example of a variable delay circuit for use in the common clock generating circuit in the apparatus for transmitting a signal from 49 .

58 2 shows a block diagram of a second exemplary embodiment of the device for transmitting a signal according to the fourth mode of the present invention,

59 a block diagram of a third off exemplary embodiment of the device for transmitting a signal according to the fourth mode of the present invention,

60 1 is a block diagram showing an example of a forward clocking circuit for use in the signal transmission apparatus according to a fourth embodiment of a fourth mode of the present invention;

61 FIG. 3 is a block diagram showing an example of a backward clock generation circuit for use in the signal transmission apparatus according to the fifth embodiment according to the fourth mode of the present invention;

62 FIG. 3 is a block diagram of another example of the backward clock generation circuit for use in the signal transmission apparatus according to a sixth embodiment according to the fourth mode of the present invention;

63 FIG. 5 is a graph for explaining the operation of the backward clock generation circuit for use in the signal transmission device according to a seventh embodiment according to the fourth mode of the present invention; FIG.

64 FIG. 2 is a block diagram of another example of the backward clock generation circuit for use in the signal transmission apparatus according to an eighth embodiment according to the fourth mode of the present invention;

65 1 is a block diagram showing an example of a sine wave generating circuit for use in the signal transmission device according to a ninth embodiment according to the fourth mode of the present invention;

66 a circuit diagram of an example of a nonlinear amplifier in the sine wave generating circuit of FIG 65 .

67 1 is a block diagram showing an example of a common clock generation circuit for use in the signal transmission apparatus according to the tenth embodiment according to the fourth mode of the present invention;

68 a circuit diagram of an example of a differential comparator in the common clock generating circuit of 67 .

69 1 is a block diagram showing an example of a terminating resistor in the signal transmission device according to the eleventh embodiment according to the fourth mode of the present invention.

70 2 shows a block diagram for explaining a method for providing a forward clock in the device for transmitting a signal according to a twelfth exemplary embodiment according to the fourth mode of the present invention,

71 1 is a block diagram of an essential portion of an apparatus for transmitting a signal which is implemented on a printed circuit board according to a 13th embodiment according to the fourth mode of the present invention;

72 1 is a block diagram of an essential portion of an apparatus for transmitting a signal implemented in a semiconductor integrated circuit according to a 14th embodiment according to the fourth mode of the present invention;

73 2 is a block diagram showing in schematic form an example of a known semiconductor memory device relevant to the fifth mode of the present invention;

74 FIG. 11 is a circuit diagram of an example of a sense amplifier in the semiconductor memory device of FIG 73 .

75 FIG. 4 is a circuit diagram of an example of a data bus amplifier in the semiconductor memory device of FIG 73 .

76 10 is a circuit diagram of an example of a data bus short circuit / precharge circuit in the semiconductor memory device of FIG 73 .

77 a waveform diagram for explaining an example of a data readout sequence in the semiconductor memory device of FIG 73 .

78 2 shows a block diagram of the arrangement according to a first principle of the device for transmitting a signal according to the fifth mode of the present invention,

79 a waveform diagram for explaining the operation of the device for transmitting a signal from 78 .

80 2 shows a block diagram of the arrangement of a second principle of the device for transmitting a signal according to the fifth mode of the present invention,

81 a waveform diagram for explaining the operation of the device for transmitting a signal from 80 .

82 2 shows a block diagram of the arrangement according to a third principle of the device for transmitting a signal according to the fifth mode of the present invention,

83 a waveform diagram (first part) for explaining the operation of the device for transmitting a signal from 82 .

84 a waveform diagram (second part) for explaining the operation of the device for transmitting a signal from 82 .

85 3 is a block diagram schematically showing an example of a semiconductor memory device using the signal transmission device according to the fifth embodiment of the present invention;

86 a block diagram that in schemati Scher form shows an essential portion of a first embodiment of the device for transmitting a signal according to the fifth mode of the present invention,

87A and 87B Circuit diagrams of examples of an arrangement of a driver in the device for transmitting a signal from 86 .

87C a schematic representation of an example of a bus amplifier in the device for transmitting a signal from 86 .

88 a schematic representation of an example of a signal curve for operating the bus amplifier of 87C .

89 is a schematic representation of an example of the operating waveform of a bus in the device for transmitting a signal from 86 .

90 2 shows a block diagram which shows in schematic form an essential section of a second exemplary embodiment of the S device for transmitting a signal according to the fifth mode of the present invention,

91 a circuit diagram of an example of a precharge circuit in the device for transmitting a signal from 90 .

92 a schematic representation of an example of a signal curve for driving a bus and a bus amplifier in the device for transmitting a signal from 90 .

93 is a schematic representation of an example of the operating waveform of the bus in the device for transmitting a signal from 90 .

94 FIG. 2 is a block diagram schematically showing an essential portion of a third embodiment of the signal transmission device according to the fifth mode of the present invention;

95A and 95B Circuit diagrams, the arrangement examples of a driver in the device for transmitting a signal from 94 demonstrate,

95C a schematic representation of an example of a bus amplifier in the device for transmitting a signal from 94 .

96A a circuit diagram of an example of a PRD amplifier in the bus amplifier of 95C .

96B 3 is a circuit diagram of an example of a latch type amplifier in the bus amplifier of FIG 95C .

97 a schematic representation of an example of a signal curve for operating the bus amplifier of 95C .

98 a circuit diagram of an example of the operating waveform of the bus and the bus amplifier in the device for transmitting a signal from 94 .

99 2 is a block diagram schematically showing an essential portion according to a fourth embodiment of the device for transmitting a signal according to the fifth mode of the present invention;

100A a circuit diagram of an example of a precharge circuit in the device for transmitting a signal from 99 .

100B a circuit diagram of an example of a bus amplifier in the signal transmission system of 99 .

101A a circuit diagram of an example of a PRD amplifier in the bus amplifier of 100B .

101B a circuit diagram of an example of a current mirror amplifier in the bus amplifier of 100B .

102 a schematic representation of an example of a signal curve for operating the bus amplifier of 100B .

103 a circuit diagram of an example of the operating waveform of the bus and the bus amplifier in the device for transmitting a signal from 99 .

104 2 shows a block diagram which shows in schematic form essential sections of a fifth exemplary embodiment of the device for transmitting a signal according to the fifth mode of the present invention,

105 a block diagram of an example of a bus amplifier in the device for transmitting a signal from 104 .

106A . 106B and 106C Waveforms showing the relationship between the bus time constant and a 1-bit cycle,

107A and 107B Circuit diagrams to explain the operation of the bus amplifier from 105 .

108 a circuit diagram of another example of the bus amplifier in the device for transmitting a signal from 104 .

109 a circuit diagram of an example of a PRD amplifier arrangement in the bus amplifier of 108 .

110 a circuit diagram of an example of a multiplexer in the bus amplifier of 108 .

111 a schematic representation of an example of a signal curve for operating the bus amplifier of 108 .

112 a schematic representation of an example of the signal curve of the bus and the bus amplifier in the device for transmitting a signal from 104 .

113 1 shows a schematic illustration of an example of a bus amplifier in the device for transmitting a signal according to a sixth exemplary embodiment of the device for transmitting signal according to the fifth mode of the present invention,

114 a circuit diagram of an example of a PRD amplifier arrangement in the bus amplifier of 113 .

115 a circuit diagram of another example of the PRD amplifier arrangement in the bus amplifier of 113 .

116 a circuit diagram of an example of a multiplexer in the bus amplifier of 113 .

117 1 shows a schematic illustration of an example of the operating signal curve of the bus and the bus amplifier in the sixth exemplary embodiment of the S device for transmitting a signal according to the fifth mode of the present invention,

118 1 shows a schematic illustration of an example of a bus amplifier in the device for transmitting a signal according to the seventh embodiment of the device for transmitting signal according to the fifth mode of the present invention.

119 a circuit diagram of an example of a PRD amplifier arrangement in the bus amplifier of 118 .

120 a circuit diagram of an example of a multiplexer in the bus amplifier of 118 .

121 a schematic representation of a signal curve for the operation of the bus amplifier of 118 .

122 2 shows a schematic illustration of an example of the operating signal curve of the bus and the bus amplifier in the seventh exemplary embodiment of the device for transmitting a signal according to the fifth mode of the present invention,

123 1 shows a schematic illustration of a bus amplifier in the device for transmitting a signal as an eighth exemplary embodiment of the device for transmitting a signal in accordance with the fifth mode of the present invention.

124 a circuit diagram of an example of a PRD amplifier arrangement in the bus amplifier of 123 .

125A and 125B schematic representations for explaining the operation of the bus amplifier of 124 .

126 a circuit diagram of an example of a multiplexer in the bus amplifier of 123 .

127 a circuit diagram of an example of a signal curve for the operation of the bus amplifier of 123 .

128 1 shows a schematic illustration of an example of the operating signal curve of the bus and the bus amplifier in the eighth exemplary embodiment of the device for transmitting a signal according to the fifth mode of the present invention,

129 1 is a circuit diagram showing an example of a bus amplifier in the signal transmission device as a ninth embodiment of the signal transmission device according to the fifth mode of the present invention.

130 a circuit diagram of an example of a PRD amplifier arrangement in the bus amplifier of 129 .

131 a circuit diagram of an example of a latch circuit in the bus amplifier of 129 .

132 a schematic representation of an example of a signal curve for operating the bus amplifier of 129 .

133 1 shows a schematic illustration of an example of the operating signal curve of the bus and the bus amplifier in the ninth exemplary embodiment of the device for transmitting a signal according to the fifth mode of the present invention,

134 1 shows a schematic illustration of an example of a bus amplifier in the device for transmitting a signal as a tenth exemplary embodiment of the device for transmitting a signal in accordance with the fifth mode of the present invention.

135A a circuit diagram of an example of a PRD amplifier arrangement in the bus amplifier of 134 .

135B a circuit diagram of another example of a PRD amplifier arrangement in the bus amplifier of 134 .

136 a circuit diagram of yet another example of the PRD amplifier arrangement in the bus amplifier of FIG 134 .

137 a circuit diagram of an example of a multiplexer in the bus amplifier of 134 .

138 a schematic representation of an example of a signal curve for operating the bus amplifier of 134 .

139 1 shows a schematic illustration of an example of the operating signal curve of the bus and the bus amplifier in the tenth exemplary embodiment of the device for transmitting a signal according to the fifth mode of the present invention,

140 3 is a block diagram schematically showing an example of a semiconductor memory device as an eleventh embodiment, the device for transmitting a signal according to the fifth mode of the present invention being used;

141 is a schematic representation of an example of a bus amplifier in the semiconductor memory device of 140 .

142 a circuit diagram of an example of a PRD amplifier arrangement in the bus amplifier of 141 .

143 a circuit diagram of an example of a multiplexer in the bus amplifier of 141 .

144 6 is a circuit diagram of an example of a sense amplifier in the semiconductor memory device of FIG 140 .

145 is a schematic representation of the example of the operating waveform of the bus and the bus amplifier in the semiconductor memory device of 140 .

146 a block diagram showing in schematic form an example of a semiconductor memory device as a twelfth embodiment, the device for transferring a Signal according to the fifth mode of the present invention is used

147 a block diagram showing the arrangement of a column decoder system in the semiconductor memory device of 146 shows,

148 is a schematic representation of an example of the operating waveform of a bus and a bus amplifier in the semiconductor memory device of 146 .

149 4 is a block diagram schematically showing an example of a semiconductor memory device as the 13th embodiment, the device for transmitting a signal according to the fifth mode of the present invention being used;

150 4 is a schematic illustration for explaining how the data bus waveform changes depending on the presence or absence of a load in the semiconductor memory device of FIG 149 changed

151A to 151i schematic diagrams showing examples of the load in the semiconductor memory device of FIG 149 demonstrate,

152 4 is a schematic diagram showing an example of the mounting positions of the load in the semiconductor memory device of the 13th embodiment, the device for transmitting a signal according to the fifth mode of the present invention being used;

153 FIG. 2 is a schematic illustration of still another example of the attachment positions of the load in the semiconductor memory device of the 13th embodiment, the device being used for transmitting a signal according to the fifth mode of the present invention;

154 4 is a diagram showing still another example of the attachment positions of the load in the semiconductor memory device of the 13th embodiment, the device for transmitting a signal according to the fifth mode of the present invention being used;

155 FIG. 2 is a block diagram schematically showing an example of a semiconductor memory device as a 14th embodiment using the signal transmission device according to the fifth mode of the present invention; FIG.

156 2 is a schematic illustration showing a comparison of the data bus signal waveforms when the load is provided according to the 13th or the 14th exemplary embodiment, the device for transmitting a signal according to the fifth mode of the present invention being used,

157 FIG. 10 is a schematic diagram showing a modified example of the load to be used in the semiconductor memory device of FIG 155 Is used,

158 2 is a block diagram schematically showing an example of a semiconductor memory device as a 15th embodiment, the device for transmitting a signal according to the fifth mode of the present invention being used;

159 14 is a circuit diagram showing an example of a sense amplifier used in the semiconductor memory device of FIG 158 is usable.

160 FIG. 10 is a waveform diagram for explaining an example of the operation of the semiconductor memory device of FIG 158 .

161 FIG. 10 is a waveform diagram for explaining another example of the operation of the semiconductor memory device of FIG 158 .

162 FIG. 14 is a circuit diagram showing the arrangement of an essential portion of a semiconductor memory device as a 16th embodiment using the signal transmission device according to the fifth mode of the present invention.

163 FIG. 2 is a block diagram schematically showing an example of a semiconductor memory device as a 17th embodiment using the signal transmission device according to the fifth mode of the present invention;

164 is a schematic diagram showing an example of the operation waveform of a bus and a bus amplifier in the semiconductor memory device of 163 shows,

165 is a schematic diagram showing another example of an operation waveform of the bus and the bus amplifier in the semiconductor memory device of FIG 163 shows,

166 2 is a block diagram schematically showing the arrangement of an essential portion of a semiconductor memory device as an 18th embodiment, the device for transmitting a signal according to the fifth mode of the present invention being used;

167 is a schematic diagram showing an example of a bus amplifier in the semiconductor memory device of 166 shows,

168 a circuit diagram of an example of a PRD amplifier arrangement in the bus amplifier of 167 .

169 a circuit diagram of an example of a multiplexer in the bus amplifier of 167 .

170 1 is a block diagram showing an example of an arrangement of a column decoder system in the semiconductor memory device of the 18th embodiment using the signal transmission device according to the fifth mode of the present invention.

171 is a schematic representation of an example of a CL pulse generation circuit in 170 .

172 a waveform diagram for Er Purification of the Operation of the CL Pulse Generation Circuit from 171 .

173 is a schematic representation of another example of the bus amplifier in the semiconductor memory device of 166 .

174 a circuit diagram of an example of a PRD amplifier arrangement in the bus amplifier of 173 .

175 a circuit diagram of an example of a latch circuit in the bus amplifier of 173 .

176 2 shows a block diagram of another example of an arrangement of the column decoder system in the semiconductor memory device of the 18th embodiment, the device for transmitting a signal according to the fifth mode of the present invention being used,

177 FIG. 12 is a block diagram schematically showing the arrangement of an essential portion in the semiconductor memory device as a 19th embodiment using the signal transmission device according to the fifth mode of the present invention, and

178 4 is a schematic illustration of an example of a CL pulse generation circuit used in the semiconductor memory device of FIG 177 Is used.

More preferred than the description embodiments the transmission device a signal and the receiver circuit in the transmission device a signal according to the present Invention first becomes the problem underlying the invention explained with reference to the relevant drawings.

2 Fig. 12 is a block diagram schematically showing an example of a known signal transmission device. An example of a bus system using an SSTL is shown. In 2 is the reference symbol 101 a driver 102 is a signal transmission line, 103 and 104 are terminating resistors (R _T ), 151 to 153 are reactive resistors (R _S ), 161 is a processor (a controller) and 162 and 163 are DRAM modules. Furthermore, the reference symbol V _TT denotes an intermediate potential (voltage supply line) between the supply voltage V _CC and the ground voltage V _SS .

As in 2 the terminating resistors are shown in the prior art bus system 103 and 104 each provided at the ends (terminating ends) of the transmission line and connected to the voltage supply line V _{TT of} an intermediate potential. On the other hand, the processor 161 and the DRAM modules 162 . 163 with the transmission line 102 using the dummy resistors 151 respectively. 152 . 153 connected at intermediate points along the transmission line 102 are provided.

The typical impedance of the transmission line and the resistance values of the terminating resistors 103 and 104 are each set to approximately 50 Ω and thus equal to the typical impedance Z _{0 of} the line. That is, when the terminating resistors 103 and 104 set in this way, this arrangement creates a total parallel resistance of 25 Ω at both ends, and the driver drives this resistor to generate a signal voltage. Here is the driver's output impedance 101 chosen very small to create a large drive capability, ie the transistor that drives the driver 101 is a very large transistor.

More specifically, if a bus system considered using the SSTL must have a minimal signal amplitude of 400 mV is required the driver provide a current of approximately 15 mA, and if the system is to have a safety margin, the needed Current at about 32 mA doubled.

As described above, in the bus system (device for transmitting a signal) using SSTL, high-speed transmission is enabled due to the matched termination (terminating resistors R _T ) and dummy resistors (R _S ), and the power consumption becomes compared to known systems also reduced because small amplitude signaling is used. Meanwhile, it is required that the signal transmission bandwidth between the DRAM and the processor be increased further in the future, and therefore the total power consumption of the device at the same level or in the current level is reduced, and therefore there is a need for a device for Transmission of a signal with lower energy consumption. That means, for example, a current consumption of 32 mA per bit will become unacceptable if the bus bandwidth is increased to 24 bits or 128 bits in the future.

The preferred embodiments the transmission device a signal and the receiver circuit for use in the device for transmitting a signal Described below with reference to the accompanying drawings.

1 Fig. 12 is a block diagram showing the basic arrangement of a signal transmission (bus system) apparatus to which a first mode of the present invention is applied. In 1 denotes the reference symbol 1 a driver 2 is a signal transmission line, 3 and 4 are terminating resistors (R _T ), 51 to 53 are reactive resistors (R _S ), 61 is a processor (a controller), 62 and 63 are DRAM modules and 7 is a damping resistor (R _D ). Furthermore, the reference symbol V _TT denotes an intermediate potential (voltage supply line) between the supply voltage V _CC and the ground voltage V _SS .

As in 1 are shown at the Bussys the termination resistors according to the first mode of the present invention 3 and 4 each provided at one end (terminating end) of the transmission line and connected to the voltage supply line V _{TT of} an intermediate potential. The resistance values R _{T are} the terminating resistors 3 and 4 each to a larger value than the typical impedance Z _{0 of} the transmission line 2 set (R _T > Z ₀ ). Furthermore, the driver's output impedance 1 chosen very large, that is, the transistor that drives the driver 1 is a small transistor.

On the other hand, the processor 61 and the DRAM modules 62 . 63 with the transmission line 2 using the dummy resistors 51 respectively. 52 . 53 connected at intermediate points along the transmission line 2 are provided. There are also several damping resistors 7 in the transmission line 2 intended.

More specifically, the bus system (signal transmission device) according to the first mode of the present invention is constructed so that the power consumption is reduced (low-consumption arrangement) by (1) the terminating resistances R _T to a value larger than the typical one Impedance Z _{0 of} the transmission line are set, (2) the output impedance of the driver is increased, and / or (3) one or more damping resistors R _{D are used} in series with the transmission line as required. When the terminating resistor R _{T is made} large, the energy consumed at the terminating end for the same signal amplitude decreases, and when the driver's output impedance is increased, the signal current decreases while achieving a reduction in the energy required to drive the driver , Instead of using the damping resistors R _D in series with the transmission line, the transmission line itself can be formed from a material with a corresponding resistance value.

In the low energy arrangement described above however, the frequency characteristic of the transmission line deteriorates, and the inherent Response time with which a voltage signal on the transmission line answers, gets big. As a result, not only can the case occur that the signal voltage does not assume its expected full amplitude value during the period of symbol length T, but there can also be intersymbol interference, what the detection of the signal by a known method makes impossible.

According to a second mode of the present In view of this problem, the invention becomes a device for Prediction of intersymbol interference from previous signals in the receiver (the receiver circuit in the transmission device of a signal) is used, and the signal is constructed in such a way that time past Signal portions by subtracting the predicted intersymbol interference value is detected from the signal voltage currently received.

3 Fig. 4 is a schematic diagram showing the relationship between the symbol length and the response time in a typical known device for transmitting a signal.

As in 3 is shown, in the typical known bus system (device for transmitting a signal), for example due to multiple reflections of the signal in the transmission line (bus), a predetermined period of time is required for the signal to assume its expected full amplitude. The response time τ is defined as the time it takes for the signal voltage to rise to 90% of its full amplitude value. In the typical known bus system, in order to ensure reliable signal transmission along the transmission line, the response time τ is chosen to be sufficiently shorter than the length (one data cycle) T of the transmitted symbol, ie the symbol length T is chosen to be sufficiently longer than the response time τ (T> r) , More specifically, in the typical known bus system, the symbol length T is selected, for example, as two or three times the length of the response time τ (T = 2 to 3 τ), and if the response time r is long, high-speed signal transmission is not possible.

In contrast, it is according to the second Mode of the present invention, the response time τ is approximately equal or longer than the length (one data cycle) T of the transmitted Symbol selected, i.e. the symbol length T is approximate selected equal to or less than the response time τ of the signal transmission line (T ≤ τ: for example T = 0.3 τ), and back in time Signal components that the transmitted Signal during the duration of the symbol length T shows is detected. In the second mode of the present invention, therefore, one signal transmission executed at high speed become.

4A and 4B are schematic diagrams showing the relationship between the symbol length and the response time in the signal transmission apparatus of the present invention.

For example, if the transmitted symbol is "0" in the periods P _n-2 , P _n-1 , and P _{n + 1} , and the data changes to "1" during the periods P _n and P _n + ₂ , as in 4A and 4B is shown, according to the present invention, the transmission symbol length T is chosen, for example, shorter than the response time τ. Accordingly, the signal of the data "1" in the period P _{n is} not detected after the response time τ when the signal voltage has increased significantly, but is detected during the time T during which the signal voltage is still changing (rising). As from 4A and 4B it can be seen that the change in the signal voltage (in the time period P _n ) when the data changes from 0 to "1" after a sequence is different from the change in the signal voltage (in the time period) P _{n + 2} ) when the data changes to "1" after changing from a 1 to a 0, but according to the present invention, the actual change in the signal voltage (data signal) in the transmission line (bus) by eliminating the effects from previous data changes regardless of continuous changes in data.

Thus, according to the second mode of the present Invention the signal transmission speed elevated be made approximately equal by the transmission symbol length T or less than the response time τ (T ≤ τ) is selected and the past Signal components detected be the transmitted Symbol in the duration of a symbol length T shows.

If the circuit response is linear, as will be described later, the intersymbol interference prediction (eliminating the impact of previous data changes using a past signal component detector (PRD)) can be accomplished by weighted addition of "1" or "0" bit decision results of previously received signals can be achieved (linear decision feedback using a decision feedback equalizer (DFE)) (see 12 and 13 ). On the other hand, when there is nonlinear intersymbol interference, the prediction of the interference terms can be done by pre-recording the amount of interference in a memory by reading out the memory using the previously received signal sequence as an address (see 14 and 15 ) can be achieved.

The above-mentioned intersymbol interference prediction can also use an analog value of the signal voltage accomplished received one bar before. This technique achieved the best prediction when the signal voltage response by one System with a delay expressed first order can be.

That is, in the system with a first order lag, when n = 0, ± 1, ± 2, ..., the signal voltage V (nT) is expressed as: V (nT) = xV TT + (1 - x) V (n (n - 1) T) + x (V inf - V TT ) (1)

The relationship x = 1 - exp (-T / τ) is used.

In the above equation, τ is the time constant (response time) of the circuit, V _inf is the signal voltage (full amplitude) when data "1" or "0" is transmitted for a sufficiently long period of time, and V _TT is the reference voltage. If a symmetrical CMOS driver is used, the reference voltage V _TT is V _CC / 2.

Show in equation (1) above the first and second terms of intersymbol interference on and the the third term represents the actual signal. That is, equation (1) shows that the Inter-symbol interference by storing the signal voltage a clock and by determining a linear sum of the signal voltage before a clock and the fixed reference voltage is obtained. The linear sum the stored analog voltage and the fixed voltage can easily generated by a circuit using capacitors as described below.

5A FIG. 12 is a block diagram showing an example of the structure of the receiver circuit (detection circuit for past signal portions) in the signal transmission device according to the present invention, and FIG 5B is a schematic representation of the structure of a self-calibration comparator in the receiver circuit of FIG 5A , Furthermore are 6A and 6B schematic representations to explain the operation of the receiver circuit (detection circuit for past signal components) of 5A : 6A is a schematic representation of the timing of each signal used in the detection circuit for past signal components, and 6B Fig. 4 is a schematic diagram showing, for example, how a voltage (signal voltage) changes on the transmission line with changing data.

As in 5A shown has the detection circuit for temporal portions of the signal 8th Autocalibration comparators 81 and 82 , a DLL (Delay Locked Loop) circuit 83 and a selector circuit (MUX) 84 on. The self-calibration comparators 81 and 82 are each supplied with the reference voltage V _TT (V _CC / 2), the input voltage (signal voltage) V _in and the control signals ϕ1 and ϕ2, which are generated by the DLL circuit 83 be issued. The voting circuit 84 selects an output signal of the self-calibration comparator 81 or 82 with a predetermined timing and outputs the selected signal (data output).

As in 5B shown the self-calibration comparator 81 ( 82 ) two capacitors 815 and 816 , a CMOS inverter 818 and switch 811 to 814 and 817 on. Using the control signals ϕ1 and ϕ2 the switches 811 to 814 to control the applied voltage (reference voltage V _TT or signal voltage V _in ) for the capacitors 815 and 816 and to connect the capacitors 815 and 816 controlled. The desk 817 is parallel to the inverter 818 switched and is switched on or off by the control signal ϕ1. How out 6A can be seen the control signals ϕ1 and 2 signals that rise immediately in synchronism with the falling and rising of the clock CLK. The switches 811 to 814 and 817 For example, each can be constructed from a transfer gate consisting of two transistors or a single switching transistor.

The self-calibration comparator performs in operation 81 ( 82 ) a self-calibration process by storing the signal voltage V ((n - 1) T) and V _TT in the capacitors 815 and 816 through the tax ersignal ϕ1 (with the timing with which the signal ϕ1 goes high), while at the same time the input and the output of the inverter 818 get connected. This self-calibration process becomes the input node of the inverter 818 set to V _on , which represents the voltage obtained when the input and the output of the inverter are short-circuited and which represents the threshold voltage at which the output signal of the inverter changes from "0" to "1"). Therefore, the charges Q1 and Q2 are in the capacitors 815 and 816 are saved, given by: Q1 = (V ((n - 1) T) - V on ) C1 Q2 = (V TT - V on ) C2 where C1 and C2 are the capacitors 815 respectively. 816 are.

Next, after the control signal ϕ1 goes low, the capacitors 815 and 816 connected in parallel by the control signal ϕ2 (with the timing with which the signal ϕ2 is brought to a high value) around the input V (nT) with the input node of the inverter 818 connect to. The voltage V at the input node of the inverter 818 at this point in time is given by the cargo maintenance law by: V = V (nT) - (Q 1 + Q2) / (C1 + C2) = V (nT) - (1 - x) V ((n - 1) T) - xV TT + V on ) = x (V inf - V TT ) + V on (2)

The right side of equation (2) is equal to the equation presented above (1), wherein the inter-symbol interference terms are subtracted from this term (whereby only the actual signal remains), and the voltage V _is added. This means that the output signal of the inverter 818 depending on whether the actual signal is positive or negative, and therefore that only the actual signal has to be examined in order to make a correct decision. More specifically, even if the data looks like in 6B shown, the data signal can be correctly obtained using the analog value of the signal voltage obtained one clock before and by eliminating (estimating) the effect of the previous data changes.

In the detection circuit for past signal components 8th of 5A are the output signals (OUTc) of the two self-calibration comparators 81 and 82 alternatively through the dial circuit 84 is selected, the reason for this is that the above decision processing of the input signal (V _in ) will be carried out at intervals of 2T, and therefore the two self-calibration comparators will be operated in an interleaved manner so that the decision processing can be carried out in periods of 1T , The operation (processing), which is carried out on the basis of the control signal Grundlage1 and on the basis of the control signal ϕ2, is between the one self-calibration comparator 81 and the other self-calibration comparator 82 changed.

7 Fig. 10 is a block diagram showing an example of the construction of the signal transmission apparatus according to the invention, and 8th Fig. 10 is a schematic illustration showing the result of simulation of a waveform in each of the memory blocks in the device for transmitting a signal from 7 represents.

In 7 is the reference symbol 201 a driver 202 ( 221 to 226 ) is a signal transmission line, 250 to 254 are reactive resistors (R _S ), 261 to 264 are memories (DRAM modules) and 207 is a damping resistor (R _D ). The transmission lines 221 and 226 each have a typical impedance of 70 Ω and a length of 10 mm, and the transmission lines 222 to 225 each have a typical impedance of 70 Ω and a length of 12.5 mm. The dummy resistors 250 to 254 each have a resistance value of 225 Ω, while the damping resistance 207 has a resistance value of 7 Ω. Here is the typical impedance of each of the transmission lines 222 to 225 ( 215 ) set to 70 Ω because different circuits (memory 216 to 264 , etc.) are connected to the transmission lines and the effective typical impedance is approximately 50 Ω due to the effects of parasitic capacitances on the transmission line and other effects.

The driver 201 consists of a P-channel MOS transistor 211 , an N-channel MOS transistor 212 , a capacitor 213 , an inductance 214 and a transmission line 215 , The capacitance of the capacitor 213 4 pF, the inductance of the inductance 214 is 2.5 nH, and the transmission line 215 has a typical impedance of 70 Ω and a length of 15 mm. The fact that the gate width of each of the transistors 211 and 212 only several 10 μm (e.g. 60 μm for the transistor 211 and 30 μm for the transistor 212 ), the circuit response can be approximated by a system with a first-order delay so that the intersymbol interference can be eliminated using the aforementioned equation (1). Furthermore, by inserting a resistor (damping resistor 207 ) suppresses the oscillation behavior of the signal voltage parallel to the transmission line and the intersymbol interference can be eliminated (estimated) more precisely.

8th shows the result of the simulation performed with the above ratios. As can be seen from the result, the change in the signal voltage (data “1”) in the memory “2” ( 262 ) and in memory "4" ( 264 ) can be approximated by the equation V = p0exp (0 - td).

Termination resistors can also be used 203 and 204 (R _T ) at each end of the signal transmission line 202 as in parentheses in 7 shown to be provided. The impedance of the transmission line is preferably set to 70 Ω, the terminating resistance R _T is within a range from ∞ R R _T 200 200 Ω, the damping resistance R _D is within a range from 7 Ω ≥ R _D > 0 Ω and the reactance R _S is set to approximately 25 Ω.

As described above, the Transfer device a signal according to the first Mode of the present invention by adjusting the termination resistance to a value greater than the typical impedance of the signal transmission line, Increase the output resistance of the driver or inserting a damping resistor in parallel to the signal transmission line the signal power can be significantly reduced. More specifically can according to the circuit simulation for example, energy consumption by a factor of approximately 4 im Be reduced compared to the SSTL. In the receiver circuit in the transmission device a signal according to the second Mode of the present invention is the intersymbol interference, which occurs in the device for transmitting a signal described above, predicted from the previous signal and eliminated, causing a precise data reception (transmission) is made possible at high speed.

9 Fig. 4 is a block diagram of a first embodiment of the signal transmission apparatus according to the first mode of the present invention. In 9 denotes the reference symbol 301 a driver, 302 ( 321 to 325 ) is a signal transmission line, 303 and 304 are terminating resistors (R _T ), 351 to 354 are reactive resistors (R _S ), 361 to 364 are memory modules (DRAM modules) and 310 is a processor or controller (DRAM controller).

The termination resistors 303 and 304 to connect (terminate) the ends of the transmission line 302 with the voltage supply line V _TT , for example, are each set to a resistance value of 200 Ω, which is much more than the typical impedance (approximately 50 Ω) of the transmission line 302 is. Furthermore, the memory modules 361 to 364 with the transmission line 302 using the dummy resistors 351 to 354 connected. The potential of the voltage supply line V _{TT is set,} for example, to a mean value (V _CC / 2) between the voltage supply voltage V _CC and the ground voltage V _SS .

The driver 301 is a CMOS inverter consisting of a P-channel MOS transistor 311 and an N-channel MOS transistor 312 built up. The gate width of the transistor 311 for example set to 60 microns, and the gate width of the transistor 312 is set to 30 μm, for example. That is, the gate width of each driver transistor in this embodiment is reduced by a factor of approximately 7 to 8 compared to the transistor used in the prior art driver with the low output impedance. In this way, the output impedance of the driver circuit is increased.

According to the result of a special Simulation for the first embodiment accomplished is the energy consumption per bit even at a transfer rate of approximately 533 MHz 12 mW, reducing energy consumption per bit by a factor of 4 or more compared to the 50 mW or more at which SSTL is achieved.

10 10 is a block diagram of a second embodiment of the signal transmission apparatus according to the first mode of the present invention.

The second embodiment of the in 10 Device shown for transmitting a signal differs from the first embodiment of 9 in that the terminating resistors 303 and 304 are omitted and that a damping resistor 307 (R _D ) in series between each of the transmission lines 321 to 325 ( 302 ) is inserted. Here are the damping resistors 307 in series with the transmission line 302 inserted and chosen so that they create a total resistance of about 70 Ω. By providing the damping resistors 307 For example, the response of a device for transmitting a signal with high accuracy can be approximated by a system with a first order delay, and accurate signal reception is possible by eliminating intersymbol interference by a receiver circuit using capacitive coupling.

This novel effect of the second embodiment is based on the fact that there no terminating resistor is provided (open), the DC energy consumption is zero, so the energy consumption for a Signal that only has data values of "1" or "0" most of the time is practical can be reduced to zero.

11 Fig. 4 is a block diagram of a third embodiment of the signal transmission apparatus according to the first mode of the present invention.

The third embodiment of the in 11 Device for transmitting a signal shown differs from the first embodiment, which is shown in 9 is shown in that a damping resistor 307 (R _D ) in series between each of the transmission lines 321 to 325 ( 302 ) is switched. Here are the damping resistors 307 that are in series with the transmission line 302 are used so that they create a total resistance of approximately 30 Ω, and the terminating resistors 303 and 304 are each set to a resistance value of approximately 300 Ω.

That is, according to the third embodiment are both the termination resistances of approximately 300 Ω as well the damping resistors of a total of 30 Ω is provided. With this arrangement, the vibration behavior of waveforms can be almost perfectly suppressed be, if at the same time the attenuation of signals that are characterized by the transmission line spread, is avoided, and thus the stability of the signal transmission can be improved.

12 Fig. 4 is a block diagram of a first embodiment of the receiver circuit in the signal transmission apparatus according to the second mode of the present invention. In 12 is the reference symbol 41 a differential amplifier, 42 is a decision circuit 43 is a shift register, 44 is a resistance and 45 is a resistor ladder circuit.

The first embodiment of the in 12 The receiver circuit shown is provided with a prediction unit for predicting intersymbol interference, and the prediction output signal (reference voltage V _ref ) becomes the reference voltage side (-) of the differential amplifier 41 given, the signal input side is coupled to the signal voltage V _in . A so-called feedback decision (decision feedback equalizer (DFE)) is used as the prediction unit, in which the previous 4 bits of a digital signal (d4 to d1) in the shift register 43 are held and the intersymbol interference terms by the resistor ladder circuit 45 are generated (non-linearly weighted A / D converter).

More specifically, the shift register holds 43 Data d4, which travels 4 bits, data d3, which travels 3 bits, data d2, which travels 2 bits, and the immediately preceding data d1 (1 bit back) and gives the data to the reference voltage side of the differential amplifier 41 by means of the resistors 454 to 451 , the resistance values according to the effects of the previous bits (the data 4 Bits back to the immediately preceding data). The resistance shows 454 has a large resistance value because the effect of the data 4 bits beforehand is very small, whereas the resistance 451 has a small resistance value because the impact of the immediately preceding data is large.

The differential amplifier 41 differentially amplifies the signal voltage V _in with the reference voltage V _ref , and the output signal of the differential amplifier 41 is in the decision circuit 42 judged to make a decision regarding the data to be transmitted (signal voltage V _in ).

According to the first embodiment of the in 12 A correct inter-symbol interference prediction can be performed by storing a sufficiently long sequence of previously received signals (thereby eliminating the effects of previous data changes), not only for a first order delay system, but for various responses, and thus correct circuitry Data are output.

13 Fig. 10 is a block diagram of a second embodiment of the receiver circuit in the signal transmission apparatus according to the second mode of the present invention.

The receiver circuit of the second in 13 The embodiment shown differs from the previous first embodiment in that the resistance 44 and the resistor ladder circuit 45 through capacitive coupling using the capacitors 44 ' and 45 ' are replaced. That is, according to the second embodiment, the non-linearly weighted A / D converter is implemented by a capacitive coupling, which has the advantage of reducing power consumption compared to the first embodiment using the resistance conductors. The capacitors 451 ' to 454 ' are with switches 461 to 464 to select between the ground potential (V _SS ) and the 4 bit data traversed up to the immediately preceding data connected in the shift register 43 are held. A switch 47 is with the reference voltage side (-) of the differential amplifier 41 connected.

In the receiver circuit from 13 are the switches during initialization 461 to 464 connected to the ground potential while the switch 47 remains in the ON state. After that, after the switch 47 has been turned off, the switches 461 to 464 to the output side of the shift register 43 switched so that the immediately preceding data up to the data that cover 4 bits (d1 to d4) and in the shift register 43 are held to the respective plates of the corresponding capacitors 451 ' to 454 ' are given. The other plates of the capacitors 451 ' to 454 ' are together with the reference voltage side of the differential amplifier 41 connected. The condenser 454 ' according to the data 4 bits before is chosen so that it has a small capacitance value, since the effect of the data 4 bits before is very small, whereas the capacitor 451 ' has a large capacity value because the impact of the immediately preceding data is large.

14 Fig. 10 is a block diagram of a third embodiment of the receiver circuit in the signal transmission apparatus according to the second mode of the present invention. In 14 is the reference symbol 48 a memory and 49 is a D / A converter.

In the third embodiment of the in 14 As in the first exemplary embodiment, the receiver circuit shown is 4 previous bits of a digital signal (d4 to dl) in the shift register 43 kept and the contents of memory 48 is read out using the previously received digital signal sequence as an address. That is, an output signal corresponding to the signal in the shift register 43 is held by the memory 48 read. The output signal from the memory 48 becomes the reference voltage V _ref to the reference voltage side of the differential amplifier 41 using the D / A converter 49 given, and differentially amplified with the signal voltage V _in , which is on the signal input side (+) of the differential amplifier 41 is applied, and then the output signal of the differential amplifier 41 in the decision circuit 42 evaluated to make a decision regarding the transmitted data (signal voltage V _in ).

In this way, according to the third in 14 Embodiment shown, even if the intersymbol interference becomes non-linear due to the effects of a transistor, diode, etc., by storing a value that is a non-linear component in the memory 48 contains a correct prediction value (a correct decision can be made regarding the transmitted data), which is an advantage of the third embodiment.

15 Fig. 4 is a block diagram of a fourth embodiment of the receiver circuit in the signal transmission apparatus according to the second mode of the present invention.

The fourth embodiment of the in 15 Receiver circuit shown consists essentially of the arrangement of 5A using capacitor / switch combinations and eliminating the effects of previous data changes using the analog value of the signal voltage received one clock before and the arrangement of the decision feedback prediction of 13 who used capacitors. In the capacitor / switch combination circuit, the intersymbol interference shown in equation (1) given above is subtracted from the input signal, and in the decision feedback prediction unit, the residual error is eliminated using the input signal to the reference side of the Differential amplifier is given. The fourth embodiment has the advantage that intersymbol interference can be eliminated with high accuracy using fewer memory levels than in known decision feedback prediction units.

More specifically, in the receiver circuit of 15 first the switch 511 switched to the OFF state and the switches 512 and 513 switched to the ON state by a differential voltage between the voltage V _b and a signal voltage (V _in ) through a capacitor 514 and a differential voltage between the voltage V _b and the voltage V _TT across a capacitor 515 create (save). At this point the switches 561 to 564 connected to the ground potential V _SS . The voltage V _{b is} a bias voltage that is applied to ensure reliable operation of the differential amplifier 541 to ensure. Furthermore, when the switch 545 is switched on, a self-calibration process for the differential amplifier 541 executed.

Next up are the switches 512 to 514 turned off, and the switch 511 is turned on, causing the capacitors 514 and 515 parallel to the connection of a node on the signal input side (+) of the differential amplifier 541 get connected. At this point the switches 561 to 564 so driven that they select the previous bit information (the data 4 bits before to the immediately preceding data) contained in the shift register 543 are held. In this state, the potential (V _ref ) changes at the node on the reference voltage side (-) of the differential amplifier 541 according to the previous bit information. A capacitor 544 is between the reference voltage side of the differential amplifier 541 and the voltage (power supply line) V _TT provided. In this arrangement, as in the arrangement of 13 the predicted intermediate symbol interference based on the previous 4 bits as an example as reference voltage V _ref to the differential amplifier 541 given, the signal which is applied to the signal input side is differentially amplified using the reference voltage V _ref . Then the output signal of the differential amplifier 541 in the decision circuit 542 evaluated to make a decision regarding the transmitted data (signal voltage V _in ).

Here is the capacitor 544 according to the data 4 Bits previously selected to have a small capacitance, and the capacitor 551 corresponding to the immediately preceding bit data is chosen to have a large capacity, the reasons for which are described above. The prediction unit for predicting the intersymbol interference is not limited to the arrangement with capacitors and switches shown above, but it will be apparent to those skilled in the art that the prediction unit uses the resistance conductors of FIG 12 or for example the memory of 14 can be built.

16 FIG. 11 is a circuit diagram of an example of the self-calibration comparator in the receiver circuit of FIG 5A , and 17 FIG. 10 is a circuit diagram of another example of the self-calibration comparator in the receiver circuit of FIG 5A ,

More specifically, in the self-calibration comparator of 16 the switches 811 to 814 and 817 in the circuit of 5B constructed from N-channel MOS transistors. On the other hand, in the self-calibration comparator of 17 the switches 811 to 814 and 817 in the circuit of 5B built up of transfer gates, each consist of an N-channel and a P-channel MOS transistor. In 17 are inverters 810 and 820 are provided to generate the control signals ϕ2 and ϕ1, respectively, and each transfer gate can thus be driven by complementary signals.

18 FIG. 10 is a circuit diagram of another example of the self-calibration comparator in the receiver circuit of FIG 5A ,

In the self-calibration comparator from 18 is the inverter 818 in the circuit of 17 through a circuit ( 818 ' ) consisting of a differential amplifier 8181 and an inverter 8182 replaced. As in 18 the switch (transfer gate) is shown 817 between the signal input side of the differential amplifier 8181 and the output of the inverter 8182 is inserted, and a self-calibration process is performed using this switch. The reference voltage side of the differential amplifier 8181 is supplied to the reference voltage V _r . Furthermore, the operating state of the differential amplifier 8181 controlled by an enable signal CMe, the differential amplifier 8181 is activated for operation when the enable signal CMe is at the high level.

19 to 24 Fig. 14 are block diagrams each showing an example in which a signal transmission apparatus according to the present invention is applied.

In 19 is the reference symbol 601 a controller (memory controller or processor) and 602 is a memory (DRAM). The controller 601 has a multi-phase delay locked line (MP-DLL) 611 on, which can output several control signals (clock signals) with different phases, a detector for past signal components (PRD) 613 and drivers 612 and 614 , The memory 602 assigns an MP-DLL 621 , PRD 622 and 623 and a driver 624 on.

The controller 601 and the memory 602 are provided by an ni-bit unidirectional address signal line (signal transmission line, address bus), which goes from the controller to the memory, and an nj-bit bidirectional data signal line (signal transmission line, data bus) 616 connected with each other. The drivers 612 . 614 and 624 have high output impedance as described above, and the outputs of these drivers 612 . 614 and 624 are with the appropriate PRD 622 . 623 respectively. 613 connected to the detection of the signal components in the past. The arrangement and operation of the PRD 622 . 623 and 613 the same as referring to above 5A . 5B . 6A . 6B . 12 to 15 , etc. described, and the arrangement of the signal transmission lines 615 and 616 is the same as referring to 2 . 7 to 11 , etc. described. In 20 to 24 described below, the arrangements described with reference to the above figures can be applied to the signal transmission lines (address bus and data bus), drivers, receiver circuit (PRDs), etc.

How out 19 can be seen in the controller 601 the control signals (clocks) from the synchronously controlled MP-DLL 611 to the PRD 613 and the drivers 612 and 614 given while in the store 602 the control signals from the synchronously controlled MP-DLL 621 to the PRDs 622 and 623 and the driver 624 are given. In the application example shown, the clock CLK is given to each switching block (controller and memory) using a known transmission line (for example SSTL: "Series-Stub Terminal Logic", serial blind termination logic).

In 20 is the reference symbol 603 a controller (or a processor or a chip group), 604a to 604d are memory and 651 and 652 are logic chips. The controllers 603 assign an MP-DLL 631 , PRDs 632 and 633 and drivers 634 . 635 and 636 on. The stores 604a to 604d have an identical structure, for example the memory 604a an MP-DLL 641 , PRDs 642 and 643 and a driver 644 on. Furthermore, the logic chip 651 a DLL 6511 and a driver 6512 on while the logic chip 652 a DLL 6521 and a PRD 6522 having.

The controller 603 and the stores 604a to 604d are through a ni-bit unidirectional address bus 637 , which leads from the controller to the memories, and an nj-bit bidirectional data bus 638 connected with each other. These buses 637 and 638 are each constructed as a 1: 4 bus, but it can be seen that the number of memories is not limited to 4, but can be changed in any way.

The controller 603 and the logic chip 651 are unidirectional data signal line (data bus A) 653 from the logic chip 651 to the controller 603 and an nq-bit unidirectional data signal line (data bus B) 654 from the controller 603 down to the logic chip 652 connected with each other. That is, the arrangement of the signal transmission line in the device for transmitting a signal according to the invention (the signal transmission line according to the present invention) is applied to the unidirectional signal transmission lines 637 . 653 and 654 and the bidirectional signal transmission line 638 applied.

The drivers 634 . 635 . 636 . 644 and 6512 have a high output impedance and the output signals of these drivers 634 . 635 . 636 . 644 and 6512 are with the appropriate PRDs 6522 . 642 . 643 . 633 respectively. 632 connected to the detection of past signal components. That is, the arrangement of the receiver circuit in the signal transmission apparatus according to the present invention (the receiver circuit according to the invention) is applied to the PRDs 6522 . 642 . 643 . 633 and 632 applied. On the other hand, the arrangement of the drivers in the device for transmission a signal according to the present invention (the drivers according to the invention) to the drivers 634 . 635 . 636 . 644 and 6512 applied.

How out 20 can be seen in the controller 603 the control signals from the synchronously controlled MP-DLL 631 to the PRDs 632 and 633 and the drivers 634 to 636 given while in the store 604a ( 604a to 604d ) the control signals from the MP-DLL 641 to the PRDs 642 and 643 and the driver 644 are given. Furthermore, in the logic chip 651 the control signal from the DLL 6511 to the driver 6512 given, and in the logic chip 652 the control signal from the DLL 6521 to the PRD 6522 given.

In the 21 The signal transmission device shown is a modified example of the signal transmission device from 20 where the logic chips 651 and 652 by a processor (or a graphic engine) 605 are replaced. The reference number 603 ' denotes a controller (or one of the logic chips).

The processor 605 assigns an MP-DLL 6051 , a PRD 6052 and drivers 6053 and 6054 on. As from the comparison between 20 and 21 can be seen, is the unidirectional data signal line in this application example 654 in 20 as a bidirectional data signal line 654 ' trained, and accordingly is a PRD 632 ' in the controller 603 ' are provided. That is, the arrangement of the signal transmission line of the present invention is applied to the unidirectional signal transmission lines 637 and 653 and the bidirectional signal transmission lines 638 and 654 ' applied, the arrangement of the receiver circuit of the present invention is applied to the PRDs 6052 . 642 . 643 . 633 . 632 and 632 ' applied and the arrangement of the drivers according to the present invention is applied to the drivers 634 . 635 . 636 . 644 . 6053 and 6054 applied.

The device for transmitting a signal from 22 again is a modified example of the device for transmitting a signal from 21 by the processor 605 through a logic chip 605 ' is replaced and the signal transmission line 654 ' when the present invention is applied to the device for transmitting a signal from 21 is used, is replaced by a known SSTL signal line.

More specifically, the nq-bit is bidirectional signal line, which is the logic chip 605 ' and the controller 603 '' connects, from an SSTL signal line and drivers 6054 ' and 634 '' built, and receiver 6052 ' and 632 '' are designed for use with SSTL. In this way, the arrangement of the signal transmission line according to the present invention on the unidirectional signal transmission lines 637 and 653 and the bidirectional device for transmitting a signal 638 applied, the arrangement of the receiver circuit according to the invention is applied to the PRDs 642 . 643 . 633 and 632 applied and the arrangement of the drivers according to the present invention is applied to the drivers 635 . 636 . 644 and 6053 applied.

In 23 is the reference symbol 606 a controller (or a processor), 607 is a memory, and 664 and 674 are differential amplifiers. In the 23 S device shown for transmitting a signal is constructed so that the clock CLK in the form of complementary signals CLK / CLK by the differential amplifier 664 and 674 to the DLLs 661 and 671 is given.

More specifically, the complementary clocks CLK / CLK become the controller 606 and the memory 607 given where they are before being passed through the respective differential amplifiers 664 and 674 to the respective DLLs 661 and 671 be differentially amplified. The output signal (control signal) of the DLL 661 becomes a driver 662 and a PRD 663 given while the output signal of the DLL 671 to a driver 672 and a PRD 673 is given. With this arrangement, the application example shown achieves clock transmission at high speed and with low energy consumption. The arrangement of the signal transmission line according to the invention is on a bidirectional signal transmission line 665 applied, the arrangement of the receiver circuit according to the invention is on the PRDs 663 and 673 applied and the arrangement of the drivers of the present invention is on the drivers 662 and 672 applied.

In 24 is the reference symbol 608 a controller (or a processor), 609 is a memory 684 and 694 are differential amplifiers and 685 . 686 . 695 and 696 are drivers. In the in 24 In the device for transmitting a signal shown, the clock CLK is provided using a known signal line, and for this are the DLL 681 and and 691 designed to output complementary strobe signals ST-B / ST-B and ST-A / ST-A in synchronism with the data output clock. These strobe signals ST-B / ST-B and ST-A / ST-A become the differential amplifiers 694 and 684 given at the respective signal receiving sides and the PRDs 692 and 682 are through the respective DLLs 691 and 681 controlled.

With this arrangement in the above application example, the same delay as the delay through the signal transmission line is generated by the delay of the strobe signals ST-B / ST-B and ST-A / ST-A, whereby accurate synchronization of the signals can be achieved , Here, the arrangement of the signal transmission line according to the present invention on a bidirectional signal transmission line 687 applied, the arrangement of the receiver circuit according to the invention is applied to the PRDs 683 and 693 applied and the arrangement of the drivers according to the invention is applied to the drivers 682 and 692 applied.

As described above is the signal transmission line according to the present Invention is not limited to use on a bus system that connects several semiconductor chips (LSI chips) together, but can also be applied to a signal line of various types circuit blocks connects with each other.

As described in detail above according to the device to transfer a second mode signal of the present invention in that the terminating resistor to a value higher than the typical impedance of the signal transmission line is set, the driver output resistance is increased or a damping resistor parallel to the signal transmission line added the signal power will be significantly reduced. Farther is according to the receiver circuit in the device according to the invention to transfer of a signal an intersymbol interference that occurs in the device to transfer of a signal occurs, predicted from the previous signal and eliminated, thereby ensuring accurate data acquisition (transmission) at high speed possible becomes.

Before describing a signal transmission device according to a third mode of the present invention, a known signal transmission device and the problems associated therewith will be discussed 25 explained.

25 Fig. 4 is a block diagram schematically showing another example device for transmitting a signal (Rambus channel) according to the prior art. In 25 are the reference numerals 901 and 902 Termination resistors, 903 is a signal transmission line (bus), 904 is a clock line terminator, 905 is a clock generator and 906 is a clock line. Furthermore, the reference number 9-0 a controller (DRAM controller) and 9-1 to 9-n are components (DRAM chips). In some arrangements, the DRAM chips can 9-1 to 9-n formed as components within a single chip or constructed as DRAM modules such as DIMMs (dual inline memory modules) on which a plurality of DRAM chips are attached.

As in 25 the DRAM controllers are shown in the Rambus channel 9-0 and the multiple DRAM chips 9-1 . 9-2 , ..., 9-n connected to each other by a common signal transmission line (bus).

For the transmission and reception of high-speed signals, an exact clocking between the signal transmitter and the receiver must be created. For this purpose, a clock CLK (CLKs, CLKr) is on the folded clock line in the Rambus channel 906 sent out, and the DRAM controller 9-0 decreases the beat at a point (P902) near the refolding point. The DRAM controller determines based on this clock 9-0 the timing for receiving and sending signals.

On the other hand, each of the DRAM chips (DRAM modules) 9-1 to 9-n when there is a signal to the DRAM controller 9-0 sends out the clock (CLKs) on the section of the folded clock line 906 that runs in the direction of the DRAM controller and generates a signal transfer clock in synchronism with the clock. If a signal from the DRAM controller 9-0 is received, each of the DRAM modules (DRAMs) generates 9-1 to 9-n a receive clock by decreasing the clock (CLKr) that comes from the direction of the DRAM controller.

In a specific example, consider a case where data is for transmission to the DRAM controller 9-0 can be read from a DRAM chip. In the case of the DRAM chip 9-1 becomes the clock CLKs by the clock generator 905 on the clock line 906 is output at a point P912 on the clock line 906 and the readout data is sent to the DRAM controller 9-0 using points P911 and P901 on the signal transmission line 903 transfer. In the case of the DRAM chip 9-2 the clock CLKs at point P922 on the clock line 906 is removed and the readout data is sent to the DRAM controller 9-0 using points P921 and P901 on the signal transmission line 903 transfer. Furthermore, in the case of the DRAM chip 9-n the clock CLKs at point P9n2 on the clock line 906 is removed, and the readout data are obtained by means of points P9n1 and P901 on the signal transmission line 903 to the DRAM controller 9-0 transfer.

Thereby are subject between the DRAM chip 9-1 and the DRAM controller 9-0 the CLKs have a time offset (delay) corresponding to the distance between point P912 and point P902 on the clock line 906 , but since this shift is due to the time shift (delay) corresponding to the distance between point P911 and point P901 on the signal transmission line 903 which occurs when the signal (readout data) from the DRAM chip 9-1 to the DRAM controller 9-0 is sent out, the DRAM controller 9-0 record the signal with an exact (synchronized) timing.

In the same way in the case of the DRAM chip 9-2 is the time offset corresponding to the distance between point P922 and point P902 on the clock line 906 by the time shift corresponding to the distance between point P921 and point P901 on the signal transmission line 903 shifted, and in the case of the DRAM chip 9-n is the time shift corresponding to the distance between point P9n2 and point P902 on the clock line 906 , by the time offset corresponding to the distance between point P9n1 and point P901 on the signal transmission line 903 shifted, causing the DRAM controller 9-0 the signal with an exactly syn can record chronized clocking.

On the other hand, if there is a signal from the DRAM controller 9-0 is transferred to a DRAM chip, the DRAM controller takes 9-0 the clock CLKr (CLKs) at point P902 on the clock line 906 and sends the signal to the signal transmission line via point P901 903 , In a specific example, when a signal (write data) to the DRAM chip 9-1 is given, the write data is increased by a time corresponding to the distance between point P901 and point P911 on the signal transmission line 903 postponed (delayed). Meanwhile, the clock CLKr that goes to the DRAM chip 9-1 is transmitted, also by a time corresponding to the distance between point P902 and point P913 on the clock line 906 is shifted, the shift of the signal (write data) is offset, so that the DRAM chip 9-1 can perform a write operation by recording the write data with an accurate (synchronized) timing.

In the same way in the case of the DRAM chip 9-2 the time shift of the write data corresponding to the distance between the point P901 and the point P921 on the signal transmission line 903 by the time shift of the clock CLKr according to the distance between the point P902 and the point P923 on the clock line 906 shifted, and in the case of the DRAM chip 9-n is the time shift of the write data corresponding to the distance between the point P901 and the point P9n1 on the signal transmission line 903 by the time shift of the clock CLKr according to the distance between the point P902 and the point P9n3 on the clock line 906 offset, allowing each DRAM chip to write with accurate timing.

In this way, in the device for transmitting a signal (Rambus channel) as in 25 shown an exact clocking for both reception and transmission can be created as long as the clock line 906 and the signal transmission line 903 are identical in terms of routing and electrical properties. That is, the in 25 The device shown for transmitting a signal requires the same routing and the same electrical properties of the clock line 906 and the signal transmission line 903 ,

However, the load characteristics of the clock line are inevitably different 906 and the signal transmission line (bus) 903 , The reason for this is that while the signal transmission line 903 the use of a latch circuit that operates in synchronism with the receive clock to provide highly sensitive reception enables the clock line 906 the use of a differential amplifier, etc. is required since a latch circuit cannot be used. Since the load characteristics of a latch circuit and a differential amplifier or the like are different, the electrical line characteristics (for example, the delay per unit length) of the clock line and the signal transmission line are inevitably different. Even if the load characteristics of the two were exactly the same, it would not be possible to route the clock line exactly along the same path as the signal transmission line if the actual wiring routing on the board is taken into account. As a result, it becomes increasingly difficult at higher frequencies to correctly clock in the 25 shown device for transmitting a signal.

It has also been used in currently distributed signal transmission devices, including that in FIG 25 shown, in applications in which the signal transmission source is constantly switched from one device to another on the bus (signal transmission line), it is necessary to create a gap (time margin) between the signals. This gap is provided to prevent the signals from overlapping which could result in incorrect reception. To eliminate or reduce this gap, extremely precise control of the transmit / receive timing is necessary, but this too becomes increasingly difficult at higher frequencies.

There is therefore a need for a device to transfer a signal that can generate clock signals without the need a symmetry between the clock line and the signal line (signal transmission line, Bus) and the gap can decrease when switching from a transmitter to executed another becomes.

The following is a brief description the features and characteristics of the third mode of the present Invention to which a detailed description of the device to transfer a signal according to the third Mode of the invention follows.

According to the third mode of the present invention, a common clocking is provided with a temporal accuracy that is sufficiently shorter (for example approximately 10%) than the maximum time that a signal takes to cross the signal transmission line and all components (LSI chips, etc .) are designed so that they are operated with this common timing. The common clocking is synthesized from clocks that run in different directions in the clock line. Furthermore, the receiver side is provided with a function for eliminating the intersymbol interference (using a PRD, etc., see. 4A . 4B . 12 . 13 . 14 and 15 ) provided, and all elements are constructed so that they are operated with a common timing.

The time period for a signal from a component to a receiving element (e.g. the Controller) varies according to the signal runtime. When switching from one transmission element to another transmission element is carried out, the intersymbol interference increases because the reception is carried out using the common clock but with the above-mentioned time difference. Meanwhile, using an intersymbol interference canceller on the receiving side, signals can be received from each transmission element (LSI chip, etc.) using the common timing, and furthermore, an inexpensive circuit can be used to set the transmission / reception timing for each element. since strict timing is not necessary when using the intersymbol interference (estimator) facility (PRD).

More specifically, the characteristics are of the third mode of the present invention that all components (chip components, DRAM chips or DRAM modules, etc.) a common reference time (in sometimes referred to as GMT: global mean time) as use common time reference that the aforementioned receiving system (the receiver circuit in the transmission device a signal according to the second Mode of the present invention) with its eliminating function the intersymbol interference is used for reception, and that a push-pull driver (a constant current or high output impedance push-pull driver) is used as a driver circuit. The result is a seamless transfer possible, when read / write devices in various components be about it in addition, the transfer property the data clock line (clock line), which is along the previously described Data line (transmission signal line) extends, are not made identical to that of the data line and the need for the control (Rambus channel, Vernier, etc.) of the transfer clock (CLKs) and the receive clock (CLKr) is eliminated.

26 Fig. 10 is a block diagram showing the basic functional arrangement of the signal transmission device according to the third mode of the present invention. In 26 denote the reference numerals 701 and 702 Termination resistors, 703 is a signal transmission line (bus), 704 is a clock line terminator, 705 is a clock generator and 706 is a clock line. Furthermore, the reference number 7-0 a controller (DRAM controller) and 7-1 and 7-n are components (DRAM chips). Alternatively, the DRAM chips 7-1 to 7-n be designed as circuits within a single chip or as DRAM modules such as DIMMs, on which a plurality of DRAM chips are attached, and the DRAMs can be replaced by EPROMs (erasable programmable read-only memories) or flash EEPROMs (electrically erasable programmable read- only memories). Furthermore, the controller 7-0 be formed from an ASIC (application-specific integrated circuit), a graphic controller or a microprocessor or the like.

27 is a schematic diagram (first part) for explaining the operation of the device for transmitting a signal from 26 ,

As in 26 and 27 the common reference time (common clocking) GMT for all DRAM controllers is shown 7-0 and DRAM chips 7-1 to 7-n that with the signal transmission line 703 are connected using the folded clock line 706 created. More specifically, in the third mode of the present invention, instead of using the transmit clock CLKs and the receive clock CLKr, the common clock GMT is determined by determining an intermediate clock between the forward and the backward clock of the folded clock line 706 created.

More specifically, the DRAM chip takes 7-1 the forward clock CLK and at point P712 on the clock line 706 and the backward clock CLK at point P713 on the clock line 706 ab, and generates the common reference time GMT as a common timing by determining an intermediate timing (intermediate phase) between these two clocks. In the same way, the DRAM chip takes 7-2 the clockwise CLK propagating forward and backward at point P722 and point P723 on the clock line 706 and generates the common reference time GMT as a common timing by determining its intermediate timing, and the DRAM chip 7-n takes the forward and backward clock CLK at the point P7n2 and the point P7n3 on the clock line, respectively 706 and generates the common reference time GMT as the common timing that determines its intermediate timing. In this way, the common clocking (common reference time GMT) for each cycle TT can be independent of the position of each DRAM chip on the clock line 706 be preserved.

In this case, the clock sections must have the clock line clock moving back and forth 706 be aligned exactly along the same path, but there is no problem even if the transmission characteristics of the clock line 706 itself significantly different from that of the signal transmission line (data line) 703 differ. Furthermore, the folded clock line 706 along a different path than the data line 703 be led. That is, the common timing GMT can be created by choosing only the intermediate phase between the clock moving forward and the clock backward. There is an upper limit on the lengths of the clock line 706 for the common reference time GMT, which can be determined unambiguously, but in practice since the limit for the length of the clock line 706 increases n times (e.g. four times) can be made by dividing the clock CLK by n (for example 4) and the resulting clock having four times the cycle (1/4 of the frequency), the common clocking GMT can be distributed over a distance which is not problematic in practice. In this case, the DRAM controller 7-0 and the DRAM chips 7-1 to 7-n each provided with a PLL circuit or a DLL circuit which carries out a multiplication process by n (for example a four-fold multiplication process for multiplying the frequency by 4) by the original clock, the cycle of which has been increased by a factor n (for example 4), regain.

In this way, the common clocking can be done using the folded clock line 706 and creating a signal with a phase midway between the forward and backward clocks, but it should be noted that it is only necessary that the signals travel in different directions along the clock route and that the clock line does not must necessarily be folded back. For example, as will be described later, the forward and backward clocks can be arranged simultaneously on a single clock line (this state is equivalent to generating a standing wave along the clock line). A clock with the same phase can always be obtained at any point on a standing wave if the length of the clock line is half the wavelength. This shows that the common timing can also be distributed using a standing wave.

Next is a receiver circuit that exemplifies the previously described detector for temporal signal components (PRD) (see FIG. 4A . 4B . 12 . 13 . 14 and 15 ) is used as a circuit for receiving the signals. There is a limit to the length L of the data line (bus) 703 regarding the use of the PRD. In the example shown, the condition imposed is that the time it takes a shaft to complete a round trip (the round trip time) should not exceed the signal bit time T. In practice, this condition can be relaxed somewhat.

28A and 28B are schematic representations (second part) for explaining the operation of the device for transmitting a signal from 26 : 28A shows a unit pulse signal that the DRAM chips 7-1 to 7-n transferred, and 28B shows waveforms when the transmitted signals from the DRAM chips 7-1 to 7-n through the DRAM controller 7-0 be received.

As in 28B shown when the signals with the common clocking (t = TT) at the receiving end (the DRAM controller 7-0 ) are received by eliminating the intersymbol interference, and if an upper limit on the delay of each device (DRAM chip) is determined so that each device can generate a sufficient signal strength, all devices can transmit and receive using the common timing , Here, each device sends a new signal in synchronism with the beginning of the bit time and receives a signal in synchronism with the end of the bit time. The transmit and receive clocks can each be shifted slightly forward or backward to optimize the signal strength, but the time reference is always the common clocking TT.

Each driver circuit is a push-pull driver built (a constant current or a high impedance output push-pull driver). A high impedance output driver is a driver that is one Output impedance that is greater than the typical impedance the signal line, even if it is not as high as one Constant current driver. More specifically, such a driver is, for example, by a suitable one size reduction an output transistor built in a CMOS driver.

With this arrangement, if any of the driver circuits (the DRAM controller 7-0 and the DRAM chips 7-1 to 7-n ) the bus 703 drives (or if none of the driver circuits drives the bus), the time constant (more precisely the response function) of the bus is independent of the time constant. That is, the system is a "linear time invariant system" and therefore the received signal is obtained as a superposition of unit impulse responses h (t).

If h (t) is obtained in the worst condition, ie if the round-trip time is exactly equal to the signal bit time T, then h (nt) normalized by the final value of the step response is 0, 1 - s ² , (1 - s ² ) S ² , (1 - s ² ) S ⁴ ... for n = 0, 1, 2, ....

S is a coefficient of voltage reflection at one end of the line, assuming that both ends of the lines are terminated with the same resistance. If exp (-T / τ) = s ² , it is nothing more than an exponential answer.

It can be seen that when S ^{2 is set} to approximately 0.5, the signal can be obtained using the PRD without any problem. This reflection coefficient, if it is included in the value of the terminating resistor R _T ( 701 . 702 ) is implemented, is 5.8 times the typical impedance. This value is equivalent to a termination resistance of 290 Ω in a 50 Ω system, which means that reception can be facilitated if the termination resistance is slightly reduced since the intersymbol interference then decreases.

Next, if the value of the drive current is taken as io = 3.5 mA as an example, the final value of the step response is io × R _T / 2, which is approximately equal to 500 mV. Multiplying this value by 1 - s ² gives a net signal amplitude of 250 mV. This shows that reception by the PRD is possible even if the worst condition. Accordingly, even if the signal source moves from one chip to another ( 7-1 to 7-n ) switches and the amplitude of the transition voltage wave on the bus decreases by a factor of s ² per T, the intersymbol interference can be eliminated by the PRD and reception is possible without any problem. Thus, seamless transmission can be obtained.

It should be noted that the reception possible in the worst condition is, all components (chips) must only the signals with the clocking of the common reference time Send or receive GMT. This means that there is no need to use it a Vernier or a PLL or DLL that is like in the Rambus channel are synchronized with the transmit and receive clocks.

In this way, the device for transmission a signal according to the third mode of the present invention because the intersymbol interference in the receiver circuit is eliminated, all components of the common clock with a given Use accuracy. This given accuracy is based on the Premise, the existence some degree of clock error is allowed as long as the error is not is so big that the makes it impossible to eliminate intersymbol interference, this means a time accuracy that is sufficiently smaller (for example approximately 10%) than the time it takes for the signal to propagate (run) the signal line is required. Still needed the generation of the common clock only the provision of clocks, which are in opposite directions (forward and backward) along the Spread the cycle path and there is no need for electrical Properties or the course of the clock line with that of the signal line match. This offers advantages in that none restrictions exist with regard to the arrangement or structure of the clock line.

Different embodiments of the device to transfer a signal according to the third Mode of the present invention will now be referred to accompanying drawings.

29 Fig. 4 is a block diagram of a first embodiment of the signal transmission apparatus according to the third mode of the present invention. In 29 are the reference numerals 701 and 702 Termination resistors, 703 is a signal transmission line (bus), 704 is a clock line terminator, 705 is a clock generator, 706 is a clock line, and 770 to 774 are dummy resistors. Furthermore, the reference number 7-0 a controller (DRAM controller) and 7-1 to 7-4 are components (DRAM chips).

How referring to 26 and 27 is the DRAM controller 7-0 and the DRAM chips 7-1 to 7-4 each constructed so that they are in the folded clock line 706 Take clocks running forwards or backwards and generate an interphase signal as a common clock (common reference time GMT). The DRAM controller 7-0 and the DRAM chips 7-1 to 7-4 perform signal transmission and reception in synchronism with the common clock (GMT). The termination resistors exist 701 and 702 for example each consisting of a 250 Ω resistor and the dummy resistors 770 to 774 are each formed, for example, from a 25 Ω resistor.

In this way, according to the first embodiment of the signal transmission apparatus in the third mode of the present invention, the common clock (GMT) can be used as an intermediate clock between the forward and the backward clock in the folded clock line 706 be preserved. That is, a common clock that creates accurate common clocking can be independent of the position of each DRAM chip on the clock line 706 be created.

30 FIG. 12 is a block diagram of a modified example of the device for transmitting a signal from 29 , This example shows a multiple processor system. In 30 denote the reference numerals 7-1 to 7-4 Processor components.

As in 30 the third mode of the present invention is not shown for application to a signal transmission device using a bus (signal transmission device) 703 limited as in 29 is shown, but it can also be applied to a multiple processor system in which processors are connected to each other.

31 Fig. 12 is a block diagram showing a structural example of an essential portion of each component in the signal transmission device according to the third mode of the present invention. In 31 is the reference symbol 781 a driver circuit 782 is a PRD (Past Signal Detector).

As in 31 the DRAM chip is shown 7-1 (each of the DRAM chips 7-2 to 7-4 or the DRAM controller 7-0 ) with the PRD 782 is provided to eliminate the effects of intersymbol interference, and is designed to receive data at the common timing TT by reducing the effects of intersymbol interference in the received waveforms, such as in 28B shown executes. So if the PRD 782 with a self-calibration comparator (see 5A and 16 to 18 ) is used as the receiver circuit, large intersymbol interference can be eliminated with a simple circuit.

32 FIG. 12 is a block diagram of another structural example of an essential portion of each component in the signal transmission apparatus according to the third mode of the present the invention. In 32 is the reference symbol 781 a driver circuit and 783 is an equalizer.

As in 32 the DRAM chip is shown 7-1 (each of the DRAM chips 7-2 to 7-4 or the DRAM controller 7-0 ) with the equalizer 783 to reduce the effects of intersymbol interference. That is, in the arrangement shown is the equalizer as the receiver circuit 783 instead of the PRD 782 of 31 is used, and data reception is performed with the common clock TT while reducing the effects of intersymbol interference in the received waveforms, such as in FIG 28B shown is executed.

33 Fig. 4 is a block diagram of a second embodiment of the signal transmission apparatus according to the third mode of the present invention.

As in 33 the length of the signal transmission line (signal line) is shown in the second exemplary embodiment of the third mode 703 limited to such a length that a signal can perform one or more round trips in the signal line within the bit time T. More specifically, when the wave propagation speed of the signal line 703 denoted by v ₀ , the length of the signal line 703 denoted by L and a bit time (a bit length) by T, a limit value is imposed which can be expressed by 2L / v ₀ ≤ T. This makes it easier to keep the intersymbol interference at a minimum value, and furthermore all components (the DRAM controller and the DRAM chips) can use the common clock (GMT) by creating a signal with a phase in the middle between the phases of the forward and generate the backward clock.

34 Fig. 10 is a block diagram of a third embodiment of the signal transmission apparatus according to the third mode of the present invention. In 34 are the reference numerals 701 . 701 ' and 702 Termination resistors, 703 and 703 ' are signal transmission lines (buses), 706 is a clock line, 7-0 is a controller (DRAM controller), 7-1 to 7-n and 7-1 ' , ... are components (DRAM chips) and 708 is a buffer.

As in 34 the buffer is shown in the third exemplary embodiment of the third mode 708 between the signal transmission line (signal lines), 703 and 703 ' inserted. That is, if the length of the signal line exceeds the above limit 2L / v ₀ ≤ T as an example, the buffer becomes 708 inserted as needed.

The buffer 708 has the function of delaying a signal, namely that of the signal line 703 transmitted signal by a time equal to an integer multiple of the bit time T and the retransmission of the signal. Since the buffer delay time is an integer multiple of T, the buffer and the components (DRAM chips, etc.) connected to it can be operated with the present common clock. Signal reception and transmission into the buffer 708 is of course carried out on the basis of the common clocking.

35 FIG. 12 is a block diagram showing a modified example of the device for transmitting a signal from 34 shows.

As in 35 shown this modified example differs from a third in 34 shown example in that the buffer 708 not just for those along the signal line 703 Transmitted signals is provided, but also for the clock that runs along the clock line 706 ( 706 ' ) is transmitted. More specifically, the buffer points 708 a device for passing on the clock to the other components (DRAM chips 7-1 ' , ...) on that with the buffer 708 are connected.

The provision of the buffer makes it possible to extend the signal transmission length, but if the clock distribution line becomes too long, the common clock can no longer be generated uniquely by simply generating a signal which has an intermediate phase between the forward and the backward clock. The modified example addresses this problem. That is, the buffer 708 creates a waveform that leads in phase by a certain angle with respect to the common clock and a waveform whose phase lags by the same angle using a DLL or PLL, as well as output signals of the resulting clocks, then the components (DRAM- crisps 7-1 ' , ...), which record the clocks, the same common clocking as the buffer 708 to have.

36 Fig. 4 is a block diagram of a fourth embodiment of the signal transmission apparatus according to the third mode of the present invention. In 36 are the reference numerals 780 to 78m Buffer, 703 is a bus (signal line) and 7-1 to 7-n are components (DRAM chips).

As in 36 each of the buffers is shown in the fourth embodiment of the third mode 780 to 78m with several bus line groups 703 connected. This arrangement of the buffers 780 to 78m enables the transmission of signals to and from a large number of components (DRAM chips 7-1 to 7-n ) in a tree-like structure. It can be seen that the topology of the signal lines 703 using the buffers 780 up to 78m is not limited to the tree-like structure, but that other topologies, such as a star-shaped or a ring-shaped topology, are also possible.

37 Fig. 10 is a circuit diagram of an example of the driver circuit in the signal transmission apparatus according to the third mode of the present invention. This figure relates, for example, to the driver circuit 781 as in 31 and 32 is shown.

As in 37 shown the driver scarf device that the signal line (signal transmission line 703 ) drives P-channel MOS transistors 7811 and 7812 , N-channel MOS transistors 7815 and 7816 , Power sources 7813 and 7817 as well as CMOS inverters 7814 and 7818 on. Here is the transistor 7812 with the transistor 7811 connected in a current mirror arrangement, and furthermore the transistor 7816 with the transistor 7815 connected in a current mirror arrangement. The driver circuit uses an arrangement so that the sources of the transistors 7812 and 7816 in the symmetrical current mirror constant current driver circuit by the CMOS inverters 7814 respectively. 7818 can be controlled, whereby the constant current is switched. That is, the driver circuit 781 , in the 37 is constructed as a symmetrical constant current driver push-pull circuit.

With this structure, the driver circuit a high output impedance, so that the response function of the signal line system independently from switching any drivers in a circuit block (DRAM chip, etc.) is constant, which is the efficiency of inter-symbol interference elimination elevated and thus a device for transmission of a signal with improved accuracy. Another Advantage is that even if there is a mistake between the common bars caused by the respective block circuits are generated, whatever a situation occurs gives where more than one driver circuit simultaneously the signal line controls the constant current control method the problem of flashover current avoids.

38 Fig. 12 is a block diagram of a fifth embodiment of the signal transmission apparatus according to the third mode of the present invention. In 38 is the reference symbol 711 a common clock generating circuit, 712 is a variable delay circuit, 713 is a phase comparator, 714 is a NAND gate, 715 is a driver circuit (actual driver), 716 is a dummy driver circuit (dummy driver). The variable delay circuit 712 and the phase comparator 713 together a DLL (delay locked) circuit. The dummy driver 716 is in terms of its structure with the actual driver 715 identical (both drivers have the same delay time), the arrangement being such that the output signal of the dummy driver 716 to the phase comparator 713 is attributed to the delay in the actual driver 715 to eliminate. An input of the NAND gate 714 is connected to the output data, so that the output data to the actual driver 715 according to the output signal (clock) of the variable delay circuit 712 are given.

That is, in the fifth embodiment of the third mode are the phase comparator 713 , the variable delay circuit 712 and the dummy driver 716 that work together to reduce the delay in the driver circuit (actual driver) 715 to eliminate, in addition to the generating circuit 711 for the common clocking that receives the clocks that propagate through the clock line folded between the front and rear rearward portions, as referring to FIG 27 and creates a common clock by determining a time midway between the rising edges of the forward and backward clocks. The delay value in the variable delay circuit 712 is controlled to have the delay and the changes in the delay in the real driver 715 compensated, thereby achieving signal transmission with increased accuracy. Similar control can be performed using, for example, a DLL, and can also be applied to control the input timing.

39A and 39B 14 are block diagrams of a sixth embodiment of the signal transmission apparatus according to the third mode of the present invention.

As in 39A the clock line is shown in the sixth embodiment of the third mode 706 constructed as a single clock line and not as a round trip clock line. By direct grounding from one end of the single clock line 706 , ie by omitting the clock line terminating resistor 704 as in 26 shown and by short-circuiting this end a standing wave (s. 29B ) along the clock line 706 generated and this standing wave is used as a common timing (GMT).

The sixth embodiment of the third mode thus uses the phenomenon that when there is a standing wave along the clock line 706 is generated, a voltage amplitude of the same phase is obtained along a range of a length equal to half the wavelength. Advantages of this method are that the clock line only needs half the length of the circulation type clock line, and that since the clock runs forward and backward along a single line, the property of the forward path completely coincides with that of the return path and thereby the Accuracy of common clocking increases.

40A and 40B 14 are block diagrams of a seventh embodiment of the signal transmission apparatus according to the third mode of the present invention. In 40A are reference numerals 761 and 762 active degrees and in 40B is the reference symbol 7611 a delay unit and 7612 a control power supply unit.

In the sixth in 39A and 39B The embodiment shown is one end of the clock line 706 are short-circuited and, on the other hand, are both in the seventh embodiment of the third mode Ends of the clock line 706 with the active degrees 761 and 762 completed. The active degrees 761 and 762 are controlled so as to obtain a situation equivalent to shorting the line at a point where a reflected wave generated at each termination end has traveled a distance equal to, for example, 1/16 of the wavelength measured from the termination end , The active conclusion 761 ( 762 ) has, for example, the delay unit 7611 and the control power supply unit 7612 on how in 40B and is monitored by monitoring the voltage at the termination end by generating an electrical current signal having a constant phase relationship with respect to the voltage and feeding it back to the termination end (from the control voltage supply unit 7612 ) reached. This active termination can be easily accomplished using a known PLL or DLL circuit and a constant current drive circuit, etc. The seventh embodiment of the third mode has the advantage that a standing wave along the clock line 706 can be generated and the amplitude of the clock along the clock line 706 is constant without the clock line length having to be exactly matched to the clock frequency.

41 Fig. 4 is a circuit diagram of an example of the signal generation circuit 711 for a common clock used in the signal transmission apparatus according to the third mode of the present invention. In 41 are the reference numerals 7111 and 7112 capacitors, 7113 and 7114 are P-channel MOS transistors, 7115 and 7116 are N-channel MOS transistors, 7117 is a resistance 7118 and 7119 are voltage sources and 7120 is a power source. A sinusoidal clock is used as clock CLK, which passes through the clock line 706 spreads.

The generation circuit 711 for a common beat that in 41 shown, uses the property that when a sinusoidal clock is used as clock CLK, the sum of a first sine wave (forward clock) s1 and a second sine wave (reverse clock) s2 produces a sine wave (common clock signal) s3, the phase of which is accurate lies between the two. Through the capacitive coupling of the two capacitors 7111 and 7112 the two clocks (s1 and s2) are given to a comparator of the differential amplifier type for generating the common clock (s3). This method has the advantage of reducing the common clock generation circuit.

42 Fig. 10 is a circuit diagram of another example of the common clock generation circuit used in the signal transmission apparatus according to the third mode of the present invention. In this circuit, a sinusoidal clock is also used as the clock CLK through the clock line 706 running.

The generation circuit 711 for a common measure points as in 42 shown two comparators 720 and 730 and two inverters 740 and 750 on. Here, the clock s 1 running forward and a clock s2, which is obtained, for example, by inverting the backward clock s2, are used as clocks associated with each comparator 720 ( 730 ) can be entered to generate the common s3 with a phase between the forward and backward clock.

43 FIG. 12 is a circuit diagram of an example of the comparator used in the common clock generating circuit of 42 Is used. As in 43 shown the comparator 720 ( 730 ) multiple P-channel MOS transistors 721 . 722 and 726 and several N-channel MOS transistors 723 . 724 . 725 and 727 on.

44 Fig. 10 is a circuit diagram of another example of the common clock generation circuit used in the signal transmission apparatus according to the third mode of the present invention.

In the 44 A common clock generating circuit shown is constructed from a known phase interpolator. Using the phase interpolator, the generating circuit can 711 be constructed for a common clock, which receives the forward and the backward clock on the folded clock line and generates a clock which has a phase in the middle between the forward and the backward clock.

As in 44 shown the phase interpolator (generating circuit for a common clock) 711 multiple P-channel MOS transistors 771 to 784 , several N-channel MOS transistors 785 to 791 , Capacitors 792 and 793 as well as a comparator 794 on.

The structure of the generation circuit 711 for a common clock from a phase interpolator as in 44 shown has the advantage that rectangular signals, which are driven by a known CMOS driver, can be used as a clock and the generator circuit can be constructed for a common clock with less circuit complexity than when using an ordinary DLL or a PLL becomes. Of course, different arrangements can deviate from that in 44 shown for the construction of the phase interpolator can be used.

45 Fig. 10 is a block diagram of an eighth embodiment of the signal transmission device according to the third mode of the present invention. In 45 are the reference numerals 790 to 793 DLL circuits.

As in 45 In the eighth exemplary embodiment of the third mode, a clock CLK 'with the n-fold (for example four-fold) cycle is shown of the ordinary clock CLK on the clock line 706 given.

More specifically, in the eighth embodiment of the third mode, the cycle time is increased (for example by a factor of 4) by the upper limit of the length of the clock line 706 to increase the common clock by creating a signal with a phase midway between the forward and backward clocks. In the method using the circulation type clock line (and also in the method using the standing wave clock) when the revolution delay becomes larger than the cycle time, there is a phase ambiguity of 180 ° in the common timing, but by increasing that Cycle time as in the eighth embodiment of the third mode, the length over which the ambiguity occurs can be increased.

As in 45 are shown in the DRAM controller 7-0 and the DRAM chips 7-1 to 7-3 the DLL circuit 790 to 793 provided that perform a multiplication process by n (in order to reduce the cycle or to increase the frequency by a factor n, for example by multiplying by 4), by the original clock, whose cycle time has been increased by a factor by n (for example 4), regain. PLL circuits can be used instead of DLL circuits 790 to 793 be used.

46 Fig. 11 is a circuit diagram of an example of the clock distribution transmission line used in the signal transmission apparatus according to the third mode of the present invention. In 46 is the reference symbol 7061 a shield and 7062 is a clock pair (twisted pair).

As in 46 the transmission line (clock line) is shown 706 to distribute the clock CLK using a differential pair (twisted pair) 7062 formed, which crosses at predetermined intervals and shielded from both sides by grounded protective elements ( 7061 ) is. Although the clock line 706 According to this structure, of course, has a different transmission characteristic than the signal line, this does not cause any problem because the system has different transmission characteristics of the signal line 703 and the clock line 706 tolerated. This has the advantage of reducing clock-induced noise by applying sufficient shielding to the clock line that is subject to constant current fluctuations. Since there is no problem when there is a large difference in the transmission characteristics between the clock system and the signal system, it is of course possible to construct the clock system only by a coaxial cable or an optical fiber, for example.

In this way, according to the device for transmission a third mode signal of the present invention Transfer device of a signal can be built, the greater design freedom offers in terms of the clock system and the signal system and light the time gap at execution a device switchover reduced and also has a lower energy consumption.

The signal transmission system is as described according to the present Invention is not limited to use on a bus system that has several Semiconductor chips (LSI chips) connects, but can also be applied to a signal line, which connects different types of circuit blocks.

According to the device for transmission a third mode signal of the present invention the clock can be generated without any symmetry between the Clock line and the signal line (signal transmission line) is required, and the time gap at execution a circuit between transmission devices be reduced.

Next, an apparatus for transmitting a signal according to a fourth mode of the present invention will be described in detail. First, the basic functional structure of the fourth mode of the invention will be referenced to FIG 47 and 48 described. In the previous third mode, the forward and backward clocks are transferred to the DRAM chips, etc. using the folded clock line ( 706 ) and in the fourth mode, the clocks are made using clock lines for the forward and backward clock (forward and backward clock lines 1001 and 1002 ) are provided separately and clock generation circuits are provided which are provided separately for the clock which runs forwards and backwards (generation circuit 1100 and 1200 for the forward or backward beat).

47 10 is a block diagram of the basic functional arrangement of the signal transmission apparatus according to the fourth mode of the present invention, and 48 Fig. 10 is a timing chart for explaining the operation of the signal transmission device of 47 , In 47 are the reference numerals 10-1 to 10-n Devices such as DRAM chips (DRAM modules) or DRAM controllers, 1100 is the generation circuit for the clock and 1200 is the generation circuit for the clock running backwards. 48 corresponds to 47 that was previously explained in connection with the third mode of the present invention.

In the signal transmission apparatus of the present invention, as in FIG 47 shown the generating circuit 1100 for the clock running forward and the generating circuit 1200 for the measure running backwards (one or several pairs of such circuits) for generating the forward and backward clock for a pair of signal lines (clock lines) 1001 and 1002 intended. The devices 10-1 and 10-n that transmit and transmit signals receive a forward clock ϕ1 from the forward clock generation circuit 1100 and a backward clock ϕ2 from the backward clock generation circuit 1200 , and by determining an intermediate timing between these two clocks ϕ1 and ϕ2 on their rising and falling edges, they generate an intermediate phase signal (common clock GMT, global middle time).

More specifically, as in 48 shown produces the device 10-1 the common clock GMT as a signal with an intermediate phase between the forward clock ϕ1-1, which by means of the clock line 1001 is provided, and the backward clock ϕ2-1, which by means of the clock line 1002 is provided, the device is generated in the same way 10-n the common clock GMT as a signal with an intermediate phase between the forward clock ϕ1-n, which is by means of the clock line 1001 is provided and the backward clock ϕ2-n, which is by means of the clock line 1002 provided.

The backward clock generation circuit must 1200 generate a clock (ϕ2) so that the intermediate (interphase) clocking between the forward clock ϕ1 and the backward clock ϕ2 can be clearly obtained. More specifically, the phase difference between the forward and backward moving clock on the signal lines (clock lines) 1001 and 1002 (More specifically, the phase difference between the edges of the forward and backward moving clock ϕ1 or ϕ2, which carry the clock information) selected so that it is within certain limits (within ± 180 ° maximum). Furthermore, it is desirable that the reverse clock generating circuit 1200 is designed so that it generates the backward moving clock ϕ2 so that the intermediate clock extraction can be carried out using the simplest possible circuit as explained later.

According to the device for transmitting a signal (signal transmission method) according to the invention, it is eliminated by eliminating the intersymbol interference at each receiver circuit (each of the devices 10-1 to 10-n ) enables all elements to share the common clock (GMT) with a predetermined degree of accuracy. The predetermined level of accuracy is derived from the convention that a timing error does not become so large as to make it impossible to eliminate the intersymbol interference, and in practice a timing accuracy that is sufficiently less (e.g., about 10%) than the time that it takes is sufficient Signal required to traverse the signal line. Furthermore, in order to generate the common clock GMT, only clocks ( 1001 and 1002 ), which propagate in different directions along the clock line path, and since the path and the electrical properties, in contrast to the previously described prior art (device for transmitting a signal from 25 ) the clock line and the data line (signal transmission line) do not have to be identical, there are no special restrictions with regard to the design and arrangement of the clock lines.

Embodiments of the device to transfer a signal according to the fourth Mode of the present invention will now be referred to accompanying drawings explained.

49 10 is a block diagram of a first embodiment of the signal transmission apparatus according to the present invention. In 49 is the reference symbol 10-0 a chip such as a DRAM controller, 10-1 to 10-4 are chips like DRAMs, 1100 is a forward clock and generation circuit 1200 is a reverse clock generating circuit.

Furthermore, the reference number 1001 a clock line for the forward moving clock ϕ1, 1002 is a clock line for the backward moving clock ϕ2, 1003 is a signal transmission path (consisting of several parallel signal lines, such as 16 data lines), and 1004 is a clock line for the reference clock CLK.

As in 49 the DRAM controller is shown 10-0 , Forward Moving Clock Generation Circuit 1100 , the reverse clock generating circuit 1200 constructed so that the reference clock (idle clock) CLK by means of connections P1010, P1100 and P1200 on the reference clock line 1004 record while the DRAM chips 10-1 to 10-4 are each constructed so that they move forward and backward clock ϕ1 and ϕ2 by means of the clock lines for forward and backward moving clock 1001 and 1002 record and generate interphase signals as a common clock GMT (global mean time). In 49 is shown that the DRAM controller 10-0 with the reference clock CLK by means of the connection P1010 on the reference clock line 1004 is provided, alternatively the DRAM controller 10-0 like the DRAM chips 10-1 to 10-4 be constructed so that it generates the common clock GMT by taking the forward clock ϕ1 and the backward clock ϕ2 and generating the interphase signal.

50 Fig. 4 is a block diagram of an example of a generation circuit 1300 for a common clock, which is for use in the device for transmitting a signal from 49 is usable. The generation circuit 1300 for the common clock is, for example, in each of the DRAM chips 10-1 to 10-4 intended. Furthermore, the reference symbol T denotes a cycle time and τ denotes a delay time (delay value).

As in 50 shown the generation circuit 1300 for a common clock, a first variable delay circuit 1301 on, which receives the advancing clock Takt1 and generates a delay + τ, a second variable delay circuit 1302 , which receives the backward moving clock ϕ2 and generates a delay of –τ, a phase comparator 1303 which the phases of the output signals of the first and the second variable delay circuit 1301 and 1302 compares and a control circuit 1304 , the delay values (+ τ and -τ) in the first and the second variable delay circuit 1301 and 1302 according to the result of the comparison from the phase comparator 1303 controls (so that the phase difference between the output signals of the first and second variable delay circuits 1301 and 1302 Becomes zero). The first and the second variable delay circuit 1301 and 1302 each composed of several delay stages (delay units) cascaded and constructed so that they create a delay value up to the delay stage by the control unit 1304 is referred to as will be explained later. The delay value τ by the control circuit 1304 is controlled, becomes the cycle time T in the first variable delay circuit 1301 (T + τ) is added and is determined by the cycle time T in the second variable delay circuit 1302 (T - τ) subtracted. The output signal (T + τ) from the first variable delay circuit 1302 is used as the common clock GMT.

The control circuit controls as described 1304 the control value τ (| τ | <T / 2), so that the phase difference between the output signals of the first and the second variable delay circuit 1301 and 1302 Becomes zero. Here, when the output signal (GMT) of the first variable delay circuit 1301 is referred to as t1 and the output signal of the second variable delay circuit 1302 is referred to as t2 t1 + (T + τ) = t2 + (T - τ) from the τ = (t2 - t1) / 2 is obtained.

It is t1 + (T + τ) = (t2 + t1) / 2 + T

The intermediate clocking can thus be obtained.

51 Fig. 4 is a block diagram of an example of the forward clock generating circuit 1100 which in the device for transmitting a signal from 49 can be used.

As in 51 the forward clock generating circuit may be shown 1100 ϕ1 from a driver 1101 can be constructed, which receives the reference clock (idle clock) CLK at its input, which is provided by means of the connection P1100.

52 and 53 FIG. 11 are block diagrams of another example of the common clock generating circuit used in the signal transmission device of 49 can be used: 52 shows the main DLL (digitally locked loop) section 1300a the generating circuit 1300 for a common beat and

53 shows the sub-DLL section 1300b the generating circuit 1300 for a common beat.

First, as in 52 shown the main DLL section 1300a the forward clock ϕ1 (or the backward clock ϕ2), and the phases of the forward clock ϕ1 itself and its delayed version by a variable delay circuit 1305 are output in a phase comparator 1306 compared, and then control by a control circuit 1307 is carried out so that the phase difference between the two signals becomes zero (ie a delay of one cycle time T is introduced). In this way, a delay T equal to a cycle time of a clock (ϕ1, ϕ2) is obtained.

Furthermore, using the delay T, a cycle time (the number of delay stages equals the equivalent of a cycle time T) that is applied to the main DLL section 1300a of 52 is obtained in the sub-DLL section 1300b the time τ is added or subtracted in order to bring the forward moving clock ϕ1 or the backward moving clock ϕ2 into phase with one another.

More specifically, as in 53 shown, adds the first variable delay circuit for the advancing clock ϕ1 1301 the delay τ the delay T of a cycle time (T + τ), and for the backward moving clock rück2 the second variable delay circuit 1302 subtracts the delay τ from the delay T of the one cycle time ( 7 - τ). Then, as with the generating circuit described above 1300 for a common beat of 50 compares the phase comparator 1303 the phases of the output signal (T + τ) of the first variable delay circuit 1301 and the output signal (T - τ) of the second variable delay circuit 1302 , and the delay circuit 1304 selects the appropriate delay stage so that the phase difference between these signals (T + τ and T - τ) becomes zero.

54 Fig. 3 is a block diagram of an example of the generating circuit 1200 for a backward moving clock, which in the device for over carry a signal from 49 is usable.

As in 54 shown the backward clock generating circuit 1200 ϕ2 from a delay circuit 1201 be constructed, which receives at its input the reference clock (idle clock) CLK, which is provided by means of the connection P1100, and ensures a predetermined delay value. You can do this by setting the delay value (delay time) caused by the delay circuit 1201 is pulled to an appropriate value, the phase difference between forward and backward moving clocks (ϕ1 and ϕ2) on the clock lines ( 1001 and 1002 ) within ± 90 ° (preferably ± 45 °).

55 Fig. 11 is a circuit diagram of an example of the phase comparator (the phase comparator 1303 of 50 and 53 and the phase comparator 1306 of 52 ) in the common clock generating circuit in the device for transmitting a signal from 49 can be used.

As in 55 shown the phase comparator 1303 For example, two frequency dividers to divide the frequencies of the first and second input signals (T + τ and T - τ) by 2, several P-channel MOS transistors, several N-channel MOS transistors, several inverters, multiple NAND gates and multiple NOR gates. The arrangement is such that an output signal (/ DOWN or / UP) according to the phase difference between the first input signal ϕ1 (T + τ) and the second input signal ϕ2 (T - τ) for controlling the delay time in the first and the second variable delay circuit 1301 and 1302 by means of the control circuit 1304 is generated to eliminate the phase difference between the first and second output signals.

56 Fig. 12 is a block diagram of an example of a control circuit (the control circuit 1304 in 50 and 53 and the control circuit 1307 of 52 ) in the common clock generating circuit in the device for transmitting a signal from 49 Is used.

As in 56 shown the control circuit 1304 for example an UP / DOWN counter (U / D counter) 1341 on the control signals (/ DOWN and / UP) from the phase comparator 1303 records, and a decoder 1342 which has an output signal from the U / D counter 1341 records, with the decoder 1342 the designated delay stage in the variable delay circuit of 57 as described below according to the control signals (/ DOWN and / UP) from the phase comparator 1303 chooses.

57 FIG. 12 is a circuit diagram of an example of the variable delay circuit (the first and second variable delay circuits 1301 and 1302 of 50 and 53 and the variable delay circuit 1305 of 52 ) in the common clock generating circuit in the device for transmitting a signal from 49 Is used.

As in 57 shown has the first variable delay circuit 1301 (the second variable delay circuit 1302 ) multiple delay stages (delay units) DU. Each delay unit DU consists of an inverter and two NAND gates, and is common to a delay line 1310 connected. The arrangement is such that the delay value selected by any delay unit DU is selected by the decoder 1342 is equal to the delay value created by the variable delay circuit. It will be appreciated that various known DLL circuit techniques can be used for the arrangements described above.

58 Fig. 10 is a block diagram of a second embodiment of the signal transmission apparatus according to the fourth mode of the present invention.

In the fourth mode of the present invention, the common clock GMT is generated by generating the intermediate clock between the forward and backward clocks (ϕ1 and ϕ2), whereby the phase difference between the forward and backward clocks must be brought within certain limits in order to to generate the common clock GMT clearly. However, if the clock lines ( 1001 and 1002 ) become very long, it becomes difficult to bring the phase difference between the forward and backward moving clocks within certain limits along the entire length of the clock lines. For this purpose, according to the second exemplary embodiment, which is described below, the clock lines for the forward and backward moving clock are each divided into shorter segments ( 1011 . 1021 ; 1012 . 1022 ) divided in such a length that a clear provision of the common clock GMT can be ensured so that the common clock GMT can be generated even if the total length of the signal line is long.

More specifically, in the second embodiment, as in 58 unlike the first in 49 Embodiment shown clock generation circuit / data buffer pairs 1120 . 1121 and 1122 at equal intervals to send forward-moving clocks ϕ11, ϕ21 and backward-moving clocks ϕ12, ϕ22 along the clock lines for the forward-moving clock 1011 . 1021 or clock lines for backward moving clock 1012 . 1022 and for the transmission of data with sufficient amplitude in the data lines 1031 and 1032 intended.

Here are the clock generation circuit / data buffer pairs 1120 . 1121 . 1122 each constructed so that they generate the common clock GMT based on the clock from one before earlier block is received, and generate the forward clock to the next block (and the backward block to the previous block) based on the common clock GMT.

59 Fig. 10 is a block diagram of a third embodiment of the signal transmission apparatus according to the fourth mode of the present invention.

In the third in 59 Embodiment shown are those in 58 Data lines shown are all connected point to point. In this case, the clock generating circuits are 1211 . 1212 and 1213 to generate the forward and backward moving clocks for each group of devices (for DRAM chips 10-11 . 10-21 and 10-31 ) and the other devices ( 10-1m . 10-2m , etc.) are constructed so that the signals send or receive by generating the common clock GMT from the forward clock ϕ11 or ϕ21 and the backward clock ϕ12 or ϕ22 provided by the corresponding clock circuits. Since the signal transmission path is not a bus, the third exemplary embodiment is reflection-free due to the signal branching and can therefore transmit signals at high speed.

60 FIG. 12 is a block diagram of an example of the forward clock generating circuit for use in the signal transmission system according to a fourth embodiment according to the fourth mode of the present invention. In 60 is the reference symbol 1102 a driver 1103 is a common clock generating circuit, 1104 is a phase comparator, 1105 is a controller and 1106 is a variable delay circuit.

As in 60 the generating circuit is shown in the fourth exemplary embodiment 1100 for the forward moving clock not from a single driver 1101 as in 51 built, but so that an output signal from the variable delay circuit 1106 which creates a predetermined delay by taking up the reference clock CLK as the advancing clock ϕ1 by the driver 1102 is sent out and the common clock (interphase signal) GMT is sent through the signal generating circuit 1103 for a common clock from the output signal (ϕ1) of the driver 1102 and the backward moving clock ϕ2, the phases of the common clock and the reference clock CLK then in the phase comparator 1104 for controlling the delay value (the number of delay stages) in the variable delay circuit 1106 by means of the control circuit 1105 be compared.

Thus, according to the fourth embodiment, feedback is carried out so that the common clock GMT is synchronized with the rise of the reference clock CLK, thereby ensuring that a backward moving clock ϕ2 with stable phase can be obtained when the characteristics of the clock driver 1102 or the variable delay circuit 1106 fluctuate due to manufacturing fluctuations, changes in ambient temperature, etc., and it is further ensured that the common clock GMT generated by a device (e.g. a DRAM chip on the signal line) has the same clocking as the reference clock CLK. The reference clock CLK is related on the clock going to a special chip (e.g. the DRAM controller 10-0 ) is given.

61 Fig. 12 is a block diagram of an example of the reverse clock generating circuit for use in the signal transmission apparatus according to a fifth embodiment according to the fourth mode of the present invention. In 61 is the reference symbol 1231 a variable delay circuit, 1232 is an operational amplifier, 1233 and 1234 are a resistor or a capacitor, 1235 is an inversion driver for inverting an input signal for output, 1236 is a phase comparator and 1237 is a control circuit.

As in 61 shown in the fifth embodiment, the generating circuits for the backward clock 1200 not from a single delay circuit 1201 constructed as in 54 shown, but constructed so that the backward moving clock ϕ2 as an output signal of the variable delay circuit 1203 is determined, which receives the reference clock CLK and creates a predetermined delay, and the phase of the output signal (ϕ2) of the variable delay circuit 1231 that by the operational amplifier 1232 and the inversion driver 1235 goes in the phase comparator 1236 compared to the phase of the advancing clock ϕ1. Then, based on the result of the phase comparison, the delay value (the number of delay stages) in the variable delay circuit 1231 by means of the control circuit 1237 controlled. In this way, the backward moving clock ϕ2 is output as a signal whose phase is shifted (leading) by 90 ° with respect to the phase of the forward moving clock beweg1.

Thus, according to the reverse clock generating circuit 1200 of the fifth embodiment, feedback control is carried out so that the phase difference between the received forward clock ϕ1 and the backward clock ϕ2 is kept at a constant value (ie, the backward clock ϕ2 is 90 ° in phase with respect to the forward clock ϕ1 before), from which it follows that a backward moving clock ϕ2 with stable phase can be obtained even if the characteristics of the clock driver (the inversion driver 1235 ) of the variable delay circuit 1231 etc. change due to manufacturing fluctuations, changes in ambient temperature, etc. The backward clock generating circuit 1200 that consist of analog circuits, such as in 16 is constructed, it is preferable if the variability range of the clock (ϕ2) is small because the circuit size can be reduced.

62 FIG. 12 is a block diagram of another example of the reverse clock generating circuit usable for use in the signal transmission apparatus according to a sixth embodiment according to the fourth mode of the present invention. In 62 are the reference numerals 1241 to 1244 variable delay circuits, 1245 is a phase comparator and 1246 is a control circuit. In 62 are the reference numerals 1241 to 1244 variable delay circuits, 1245 is a phase comparator, and 1246 is a control circuit. The four variable delay circuits 1241 to 1244 through the control circuit 1246 controlled to create the same delay value.

As in 62 shown in the sixth embodiment leads the phase comparator 45 a phase comparison between the forward clock ϕ1 and the signal by delaying the forward clock ϕ1 by the four variable delay circuits 1241 to 1244 is obtained because the four variable delay circuits 1241 to 1244 through the control circuit 1246 are controlled to provide the same delay value, a backward clock ϕ2 with a 270 ° (-90 °) phase shift with respect to the forward clock ϕ1, ie, which is 90 ° in phase with respect to the forward clock ϕ1, is thereby generated that the output signal of the third stage of the variable delay circuit 1243 is generated as a backward moving clock ϕ2. In this way, the backward moving clock ϕ2 is obtained, the phase of which is unaffected by manufacturing fluctuations, temperature changes, etc. The generation circuit 1200 for the backward moving clock, which from the DLL circuit as in 62 shown can also be used when the fluctuation width of the clock (ϕ2) is large.

63 shows a diagram for explaining the operation (function) of the generating circuit 1200 for the forward-moving clock suitable as the seventh embodiment according to the fourth mode of the present invention for use in the signal transmission apparatus. Here the vertical axis θ represents the phase difference and the horizontal axis x the position of the clock line ( 1001 . 1002 ). The reference symbol L denotes the total length of the clock line.

As in 63 is shown, in the seventh embodiment, the phase difference between the forward clock θ1 and the backward clock / θ2 (inverted signal of clock θ2) in each of the devices (DRAM chips 10-1 to 10-n ) that receive the clocks are held within ± 90 degrees. More specifically, in the present embodiment, the backward clock θ2 is generated by inverting the received forward clock θ1 after giving it a phase advance that is just sufficient, the phase delay along the clock line 1002 to compensate. This function can be accomplished, for example, by inverting the feedback loop output in the reverse clock generating circuit which is shown in FIG 61 is shown to be installed.

In this way, according to the seventh embodiment, since it is guaranteed that the Phase difference between the moving forward and the moving backward Clock θ1 and θ2 falls within predetermined limits, the common clock GMT are generated with high accuracy; furthermore, by receiving the moving forward and the moving backward Clock θ1 and θ2 the influence of phase noise through a differential receiving circuit be prevented.

64 Fig. 12 is a block diagram showing another example of the reverse clock generating circuit suitable as the eighth embodiment according to the fourth mode of the present invention for use in the signal transmission apparatus.

As in 64 is shown in the eighth embodiment is the generating circuit 1200 for the backward moving clock from an inverting driver 1205 to invert an input signal (the advancing clock θ1) to output it.

That is, in the case of a short signal line in which the phase delay of the clock (θ1, θ2) by the clock receiving circuit, the driver, the clock line, etc. is not a problem, the generating circuit can 1200 for the backward moving clock from the inverting driver 1205 be constructed. This simplifies the circuit structure of the backward clock generating circuit.

65 Fig. 12 is a block circuit diagram showing an example of a sine wave generating circuit suitable as a ninth embodiment according to the fourth mode of the present invention for use in the signal transmission system. The ninth embodiment uses a sine wave (pseudo sine wave) as a clock; ie the sine wave generating circuit 1400 generates a sinusoidal clock signal from a pulse-like (square wave) clock (reference clock signal) clk.

As in 65 is shown in the sine wave generating circuit 1400 a triangular wave clock generated from the square wave clock clk by a full-amplitude CMOS circuit made up of P-channel MOS transistors 1401 and 1402 and N-channel MOS transistors 1403 . 1404 and then the sinusoidal clock (pseudo-sinusoidal clock) by a non-linear amplifier 1405 generated.

Instead of a sine wave, a clock with a different waveform, such as. B. a triangular wave or a trapezoidal wave can be used, the rising and falling sides of which represent a significant part of the clock cycle. Such a clock waveform (sinusoidal clock waveform) has the advantage that it is possible to reduce mutual interference with other signal lines because it contains less harmonic components than the waveform of a square wave clock. Another advantage is that the common clock generation circuit 1300 in each device (DRAM chip or the like) can be constructed from a differential comparator, as in 67 is shown.

66 Fig. 10 is a circuit diagram showing an example of the nonlinear amplifier 1405 in the sine wave generating circuit of 65 shows.

As in 66 is shown, the nonlinear amplifier 1405 made of P-channel MOS transistors 1451 to 1453 and N-channel MOS transistors 1454 to 1456 be constructed. Here, each transistor is of a suitable size; z. B. it is advantageous that the gate length of the transistors 1451 and 1452 to approximately twice the gate length of the transistors 1454 respectively. 1455 is set, and the gate length of the transistors 1452 and 1455 larger than the gate length of the transistors 1451 respectively. 1454 is made. Furthermore, the transistors 1453 and 1456 selected according to the load to be driven and are usually constructed from large transistors.

67 Fig. 3 is a block diagram showing an example of the generating circuit 1300 for the common clock, which is suitable as a tenth embodiment according to the fourth mode of the present invention for use in the apparatus for transmitting a signal.

As described above, if a sinusoidal or the like waveform clock is used, for example, the generating circuit 1300 for the common clock provided in each device (DRAM chip or the like) 10 from a differential comparator 1308 be constructed to which the forward and backward clocks θ1 and θ2 (/ θ2) are supplied as input signals.

The reason why the common clock (intermediate clock) GMT from the difference comparator 1308 is the following point. If the forward clock θ1 and the backward clock / θ2 are expressed as θ1 = A sinθ1 and / θ2 = A · sinθ2, then θ1 - / θ2 = 2A · cos ((θ 1 - θ2) / 2) · Sin ((θ1 + θ2) / 2). It can be seen from this that if the value of (θ1 - θ2) / 2 is within ± 90 degrees, the common clock GMT (the signal corresponding to the intermediate phase (θ1 + θ2) / 2) by processing the above signals by the comparator can be derived.

68 Fig. 10 is a circuit diagram showing an example of the differential comparator 1308 in the common clock generating circuit of 67 shows.

As in 68 is shown includes the differential comparator 1308 : a first differential amplifier stage consisting of P-channel MOS transistors 1380 and 1381 and N-channel MOS transistors 1385 to 1387 consists of the N-channel transistors 1385 and 1386 work as their inputs; a second differential amplifier stage consisting of P-channel MOS transistors 1382 to 1384 and N-channel MOS transistors 1388 and 1389 exists, the P-channel transistors 1383 and 1384 work as their inputs; and a storage level 1390 , Here the storage level consists of inverters 1391 to 1393 connected in cascade.

In this way, the generating circuit 1300 for the common clock using the differential comparator 1308 can be constructed from a simple circuit without using a DLL circuit or the like, which requires a large amount of circuit elements.

69 Fig. 12 is a block diagram showing an example of a terminating resistor in the signal transmission apparatus as an eleventh embodiment according to the fourth mode of the present invention.

In the eleventh embodiment, in which the forward and backward clocks θ1 and θ2 with sinusoidal waveform are used, the terminating end of the clock line becomes 1001 which transmits the advancing clock θ1 from a terminating resistor 1501 completed, which has a resistance value (e.g. 200 ohms) that is greater than the characteristic impedance (e.g. 50 or 70 ohms) of this clock line, and similarly becomes the termination end of the clock line 1002 which transmits the reverse clock θ2 from a terminating resistor 1502 completed, which has a resistance value (e.g. 200 ohms) that is greater than the characteristic impedance (e.g. 50 or 70 ohms) of this clock line.

In the eleventh embodiment, the resistance value of the terminating resistors 1501 and 1502 made larger than the characteristic impedance of the respective clock lines 1001 and 1002 , but since the forward and backward clocks θ1 and θ2 are sinusoidal clocks, the clock waveform remains sinusoidal when the Ab circuit resistors 1501 and 1502 are significantly shifted from the characteristic impedance. Furthermore, the propagation characteristic of the wave (the forward and reverse clocks θ1 and θ2) as a result of reflections in the line becomes different from that of the signal line (clock lines 1001 and 1002 ) but this is not a problem if the intermediate clock (for the common clock GMT) between the forward moving and the backward moving partial signal is extracted. Furthermore, by setting the resistance value of the terminating resistors 1501 and 1502 greater than the characteristic impedance of the clock lines 1001 and 1002 that of the terminating resistors 1501 and 1502 consumed energy (energy consumption in the clock system) can be reduced.

70 Fig. 12 is a block diagram for explaining a method for supplying the front clock in the signal transmission apparatus as a twelfth embodiment according to the fourth mode of the present invention.

In the twelfth embodiment, lines for the front clock, which are called differential transmission lines ( 1001a and 1001b ) are used to transmit complementary forward clocks θ1 and / θ1, so that the generating circuit 1200 for the backward moving signal, the backward moving clock θ2 can generate by reducing the influence of the phase noise introduced in the forward moving clock. More specifically, the generation circuit exists 1200 for the backward moving signal from a differential comparator 1261 , to which the complementary forward clocks θ1 and / θ1 are input, and a generating device 1262 for the backward moving clock (plus a memory 1263 ).

Here, the generation circuit provided in each device (DRAM chip or the like) can be provided 1300 for the common clock from the difference comparator 1308 be constructed to generate the common clock GMT previously in 67 was shown. In this case, the difference comparator 1308 fed at its inputs one of the complementary forward clocks θ1 and / θ1 (the true signal θ1) and the backward clock θ2; the influence of phase noise can also be reduced in this case.

71 Fig. 12 is a block diagram showing, as a 13th embodiment according to the fourth mode of the present invention, an essential part of the apparatus for transmitting a signal to a printed circuit board.

As in 71 is shown, in the 13th embodiment, a plurality of signal generating circuits (generating circuit 1100 for the forward moving clock and generating circuit 1200 for the backward moving clock) 1270 attached to the printed circuit board and these signal generating circuits 1270 generate the forward clock θ1 and the backward clock θ2 by using the reference clock signal (free-running clock) clk that propagates on the printed circuit board. More specifically, each signal generating circuit includes 1270 a circuit 1273 for a variable delay of the advancing clock, a circuit 1272 for a variable delay of the backward clock and a control circuit 1270 , wherein the forward clock θ1 and the backward clock θ2 by delaying the reference clock signal clk by the respective circuits 1273 and 1272 for the variable delay under the control of the control circuit 1270 be generated.

When the clocks (θ1, θ2) in the previous stage are used to sequentially generate the clock for the next stage as in the previous one 58 shown second embodiment, the jitter increases through the delay stages as the number of stages increases; on the other hand, for the many signal generating circuits mounted on the printed circuit board 1270 a jitter accumulation by using the construction of the in 71 shown 13th embodiment can be prevented.

72 FIG. 12 is a block diagram showing, as a 14th embodiment according to the fourth mode of the present invention, an essential part of the signal transmission apparatus implemented in a semiconductor integrated circuit.

As in 72 is shown, in the semiconductor integrated circuit (semiconductor chip) implementation of the 14th embodiment, the signals (forward clock θ1 and backward clock θ2) are those of the signal generating circuit 1300 for the common clock to generate the common clock GMT, not directly from the output of the generating circuit (clock driver) 1100 tapped for the forward moving measure, but the one over the pad 1281 Output forwarding clock θ1 is via a pad 1282 into the generation circuit 1300 tapped for the common clock, which it then uses a PAD 1283 fed backward moving clock 82 compares, compensates for the phase shift added to the clock θ1 by the clock driver, PAD, etc., and generates the common clock GMT. Here, as for the node IPO, at which the via the pad 1281 issued forward moving clock 81 over the pad 1282 the clock θ1, which is on the clock line 1001 over the pad 1281 and is output via an external pin (housing pin) into the chip (the circuit) over another external pin and over the pad 1282 be taken over, but that requires a separate external pen specifically for this purpose; to avoid this, the node can be formed by using only wire soldering or the like so that the timing can be adopted without increasing the number of external pins.

As described above, can according to the device to transfer a fourth mode signal of the present invention Transfer device of a signal that a greater freedom in the construction of the clock system and signal system that delivers in a simple manner the gap can minimize when switching the device is performed and which has low energy consumption.

Next is a fifth mode of the present invention are described in detail, but before that who is on the fifth Prior art mode of the present invention and the Problems associated with the prior art with reference to drawings explained.

73 FIG. 12 is a block diagram schematically showing an example of a prior art semiconductor memory device related to the fifth mode of the present invention. In 73 is the reference symbol 2001 a memory cell arrangement, 2002 is a word decoder (word decoder arrangement), 2003 is a sense amplifier (sense amplifier arrangement), 2004 is a local data bus, 2005 is a global data bus, 2006 is a data bus amplifier, 2007 is a precharge circuit for the local data bus, 2008 is a precharge circuit for the global data bus, 2009 is a switch for the local bus, and 2010 is a write amplifier.

As in 73 is shown, the semiconductor memory device according to the prior art (memory cell arrangement section of a DRAM) comprises a plurality of memory arrangements 2001 , Word decoder (word decoder arrangements) 2002 , Sense amplifiers (sense amplifier arrangements) 2003 , local data buses 2004 and global data buses 2005 , The semiconductor memory according to the prior art further comprises data bus amplifiers 2006 to amplify data in the global data buses 2005 when reading out data, precharge circuits 2007 for the local data bus for precharging the local data buses 2004 , Precharge circuits 2008 for the global data bus for precharging the global data buses 2005 , 2009 local bus switches to control connections between global data buses 2005 and the local data buses 2004 and write amplifier 2010 for writing data into the memory cells.

74 Fig. 10 is a circuit diagram showing an example of the sense amplifier 2003 in the semiconductor memory circuit from 73 shows.

As in 74 is shown includes the sense amplifier 2003 a sense amplifier of the latch type (sense amplifier stage of the latch or latch type) 2031 , a column transfer gate 2032 , a bit line short / precharge circuit 2033 and a bit line transmission gate 2034 , Here, reference numerals BL and / BL denote the bit lines and CL denotes the column selection line.

75 Fig. 4 is a circuit diagram showing an example of the data bus amplifier 2006 in the semiconductor memory circuit from 73 shows, and 76 Fig. 10 is a circuit diagram showing an example of the data bus short / precharge circuit (precharge circuit 2008 for the global data buses and precharge circuit 2007 for the local data buses) in the semiconductor memory circuit from 73 shows.

As in the 75 and 76 shown are the data bus amplifiers 2006 and the precharge circuit 2008 for the global data buses (precharge circuit 2007 for the local data buses) each made up of several P-channel MOS transistors and M-channel MOS transistors. Here, the reference symbols DB and / DB identify the data buses, PRE and / PRE the precharge control signals, Vbr the precharge reference voltage and ES the activation signal.

77 FIG. 11 is a waveform diagram for explaining an example of a data read (burst read) series in the semiconductor memory device of FIG 73 , 77 shows the case in which the output is set to a high level "H" when the data bus amplifier 2006 is deactivated. The burst reading series here is a scheme that e.g. B. is used for synchronous DRAM (SDRAM), in which data in the memory cells, which are connected to the same word line, are read out simultaneously without a pause.

As in 77 is shown, when a burst read operation is performed in the prior art semiconductor memory device, in the case of the complementary data buses DB, / DB and the complementary bit lines BL, / BL (BL0, / BL0 to BL3, / BL3) , for example the bit lines BL, / BL and the data buses DB, / DB first precharged to a predetermined level (precharge reference voltage Vpr); more specifically, each complementary bit line or data bus is precharged to the same potential as the other complementary pair.

Furthermore, as in the 74 and 77 is shown, in a data read operation, when data appears on the bit line pair BL, / BL (BL0, / BL0 to BL3, / BL3), a differential potential on the bit line pair BL, / BL that is initially precharged to the same potential and after amplifying this differential potential to a certain level by the sense amplifier (sense amplifier stage 2031 lock type) becomes the column transfer gate 2032 that corresponds to the selected column address. That is, by sequentially supplying column selection signals CL0 to CL3, the potential of each of the bit line pairs BL0, / BL0 to BL3, / BL3 is transferred to the local data bus pair DB, / DB which was initially precharged to the same potential. This differential potential is then switched on 2009 for the local data buses to the global data bus pair DB, / DB 2005, which was initially charged to the same potential, is replaced by the global data bus amplifier (data bus amplifier 2006 ) amplified and output as readout data (read data) via a memory, a further amplifier, etc.

When reading the next data, the sense amplifier 2003 remains active, the local data bus (pair) 2004 and the global data bus (pair) 2005 preloaded to initialize the system; then the column transfer gate 2032 opened and the resulting differential potential becomes your local data bus 2004 and the global data bus 2005 is transmitted through the global data bus amplifier 2006 amplified and output as readout data in the same manner as described above.

Here, in the memory (semiconductor memory device) operation, the bus precharge operation, that is, the initialization operation, must be performed for each data read operation as in FIG 77 is shown. However, when data is output in synchronism with the clock, the buses usually have a large capacity and it takes time to precharge them; for example, the precharge period is approximately half the clock cycle.

The fifth mode of the present Invention eliminates precharge time and increases data transfer rate by more than double. If the data transfer speed thereby be increased should that focus only on the development of device processing technology leaves, lasts it several years just to increase the clock speed; the fifth In contrast, mode of the present invention aims Increase the data transfer rate by eliminating the precharge time in the conventional one System indispensable was.

Thus, the fifth mode improves the present invention, the device for transmitting a signal (including the Data bus drive method, amplifier system for the global Data bus, etc.) in a semiconductor memory device, and thereby changed fundamentally the readout order of the semiconductor memory device and increases the Data transfer rate by eliminating the bus precharge time from the read cycle. Farther allowed while the prior art strictly required that column transmission gate selection times Completely were separated from each other, the fifth mode of the present Invention the overlap the selection times of the column transfer gates. With these improvements, the precharge time is reduced to zero, what, linked with the overlapping Part of the column transfer gates a drastic increase the memory data reading speed.

For the previously described PRD (detection of temporal previous signal parts) method for the data transfer used in the data bus. For the PRD is referred to H. Tamura, M. Saito, K. Gotoh, S. Wakayama, J. Ogawa, Y. Kato, M. Taguchi, "Partial Response Detection Technique for Driver Power Reduction in High-Speed Memory-to-Processor Communications " ISSCC 97, Digest of Technical Papers, pages 342-343, which is an interface system for one High-speed data transmission between chips describes.

Here, if an attempt is made, a Signal with a bandwidth larger than that of the transmission line is on a bandwidth limited transmission line transferred to, the signal because of the inter-symbol interference component of the signal to be interrupted. The PRD process is a recovery technique of the original Signals from the interrupted signal by eliminating the intersymbol interference component. Because the PRD method is not just the intersymbol interference component eliminated, but also a reference level itself during the Process of Inter-symbol interference elimination produces data without precharging the transmission line transferred to, which is the hidden feature of the PRD process. Thus the Property that a data transfer without Preloading allows used to increase the data bus precharge time from the data read cycle eliminate.

Furthermore, if the PRD procedure is used when data in the previous cycle on the transmission line remain, a certain amount of data overlap admitted as long as the next Data arrive at the receiving end after the previous data arrive. This means, if this property for a memory bus is used is a certain amount of overlap the column transfer gate selection also admitted. Furthermore reduces the PRD process the bus amplitude and can theoretically eliminate the need for precharging (though the preload need does not necessarily have to be eliminated), as a result of which energy consumption due to the loading and unloading of the bus can also be reduced can. additionally it becomes possible with the PRD process to increase the data rate by suitably building the circuit, and no big ones Modifications need on the core elements (sense amplifiers, memory cell arrangements, Word decoders, etc.) of the conventional Storage can be made.

78 is a block diagram showing the on construction of a first principle of the device for transmitting a signal according to the fifth mode of the present invention, and 79 Fig. 11 is a waveform diagram for explaining the operation of the signal transmission device of 78 , 78 shows here a device for transmitting a signal that uses PRD and requires precharging.

In 78 indicates the reference symbol 2100 a driver, 2200 is a floating bus (signal transmission line) and 2300 is a PRD-type bus amplifier (PRD-type data bus amplifier). With the PRD method, since the bus 2200 does not have to be operated at its full amplitude, the drive capacity of the drive device 2100 are made sufficiently small, and in the case of the first principle (the first principle of the fifth mode), the signal waveforms are as in FIG 79 shown. In 79 reference character A denotes the waveform of an output signal from the driver 2100 , B is the waveform of an input signal from the bus amplifier 2300 of the PRD type and C is the waveform of an output signal from the bus amplifier 2300 of the PRD type.

As in 79 shown, the input waveform (B) of the PRD type is broken because of the driving capacity of the driver 2100 was made small, but there in the bus amplifier 2300 of the PRD type using the PRD method, the restored output waveform (C) represents the output waveform (A) of the drive device 2100 in the correct way.

Thus, according to the first principle, it is shown that without the data output from the driver 2100 must be swung out to its full amplitude, the data correctly from the bus amplifier 2300 PRD type can be reproduced even if that is at the receiving end (of the bus amplifier 2300 of the PRD type) received signal has no transitions to a high or a low level with respect to a certain threshold value. In the first principle, since no precharge circuit is provided, the state at the end of the last data transfer is maintained until the next data transfer (signal transfer) starts, and after the data transfer becomes the level of the bus 2200 kept in the state at the end of data transmission.

80 Fig. 10 is a block diagram showing the construction of a second principle of the signal transmission apparatus according to the fifth mode of the present invention, and 81 Fig. 11 is a waveform diagram for explaining the operation of the signal transmission device of 80 , This in 80 Second principle shown differs from the device for transmitting a signal of the in 78 first principle shown by an additional precharge circuit 2400 ,

As previously mentioned, precharging does not need to be done in the PRD process, but there are cases where it is beneficial to use the bus 2200 to hold onto a certain level instead of leaving it at an indefinite level, for example when the bus is 2200 is not in operation. Accordingly, in the second principle, the precharge circuit 2400 provided to the bus 2200 to set to a certain level (precharge level) when the bus 2200 is not in operation before it starts operating or after it ends, as in 81 is shown.

82 FIG. 11 is a block diagram showing the construction of a third principle of the signal transmission apparatus according to the fifth mode of the present invention, and FIG 83 and 84 FIG. 14 are waveform diagrams for explaining the operation of the signal transmission device of FIG 82 , This in 82 Third principle shown differs from the device for transmitting a signal of the in 80 shown second principle by an additional load 2500 ,

In the third principle is the burden 2500 provided to prevent the level of the bus 2200 shifts steadily to the low level "L" side or the high level "H" side during operation, for example, when the output drive capacity of the driver is not symmetrical between the high level "H" and the low level "L", or from any one other reason.

83 shows the waveform when the load 2500 is not provided and if the level of the bus 2200 (the level of the input signal B of the bus amplifier 2300 of the PRD type) has shifted to the low level "L" side, and 84 shows the waveform when the shift by providing the load 2500 is suppressed according to the third principle.

When using the PRD method, there is no practical problem in reading data even if the signal has shifted towards a certain level and remains fixed at that level, but by adding the load 2500 As in the third principle, it enables the operating margin of the bus amplifier 2300 of the PRD type increase when the bus 2200 has been set to a certain level.

85 11 is a block diagram schematically showing an example of a semiconductor memory device to which the signal transmission device according to the fifth mode of the present invention is applied. In 85 denotes the reference symbol 2001 a memory cell arrangement, 2002 is a word decoder (word decoder arrangement), 2100 is a sense amplifier (sense amplifier arrangement), 2201 is a local data bus, 2202 is a global data bus, 2300 is a data bus amplifier of the PRD type, 2401 is a precharge circuit for the local data bus, 2402 is a precharge circuit for the global data bus, 2009 is a switch for the local bus, 2010 is a Write amplifier and 2500 is a burden.

As in 85 is shown, the semiconductor memory device (memory cell array portion of a DRAM) to which the fifth mode of the present invention is applied includes a plurality of memory cell arrays 2001 , Word decoder (word decoder arrangements) 2002 , Sense amplifiers (sense amplifier arrangements) 2100 , local data buses 2201 and global data buses 2202 , The semiconductor memory device further includes data bus amplifiers 2300 of the PRD type for amplifying data in the global data buses 2202 when reading out data, a precharge circuit 2401 for the local data buses for precharging the local data buses 2201 , a precharge circuit 2402 for the global data buses for precharging the global data buses 2202 , Switch 2009 for the local data buses to control the connections between the global data buses 2202 and the local data buses 2201 , Write amplifier 2010 for writing data into the memory cells and loads 2500 , The local data bus 2201 and the global data bus 2202 , in the 85 shown correspond to the local data bus 2004 and the global data bus 2005 that previously in 73 were shown, and the precharge circuit 2401 for the local data buses and the precharge circuit 2402 for the global data buses that are in 85 shown correspond to the precharge circuit 2007 for the local data buses and the precharge circuit 2008 for the global data buses previously in 73 were shown. Furthermore, in the semiconductor memory device of 85 the data bus amplifier 2006 in 73 as a data bus amplifier 2300 of the PRD type, and the load 2500 is the global data bus 2202 added.

In 85 works in comparison to the previously described principles of the fifth mode ( 78 . 80 and 82 ) the sense amplifier 2100 than the driver, the local data bus 2201 and the global data bus 2202 correspond to the bus and the global data bus amplifier (data bus amplifier of the PRD type) 2300 corresponds to the bus amplifier of the PRD type. In this description ( 85 etc.) the bus is divided into the local data bus and the global data bus, but it should be noted that labeling the bus with different names is not an essential feature of the present invention. In 85 are the precharge circuits (the precharge circuit 2401 for the local data bus and the precharge circuit 2402 for the global data bus) and the load 2500 according to the in 82 third principle shown provided.

With this structure, the semiconductor memory device data can be read out be during which the readout cycle does not require precharging, as previously described has been.

86 Fig. 11 is a block diagram showing in schematic form an essential part of a first embodiment of the signal transmission apparatus according to the fifth mode of the present invention. This embodiment corresponds to the structure of the first principle, which was previously in 78 was shown (in which neither the precharge circuit nor the load is provided).

In 86 indicates the reference symbol 2100 a driver (which is in the sense amplifier in 85 corresponds to), 2200 is a single bus (signal transmission line), and 2300 is a PRD-type bus amplifier (which corresponds to the PRD-type data bus amplifier in 85 corresponds). Furthermore, in 86 the reference symbol A is the waveform of an output signal from the drive device 2100 , B the waveform of an input signal of the bus amplifier 2300 of the PRD type and C the waveform of an output signal from the bus amplifier 2300 of the PRD type.

The 87A and 87B are circuit diagrams showing examples of the structure of the driver 2100 in the device for transmitting a signal from 86 show and 87C shows an example of the circuit of the bus amplifier (bus amplifier 2300 of the PRD type) in the device for transmitting a signal from 86 ,

The driver 2100 can be constructed from a simple inverter for inverting and amplifying input data (Din), as in 87A is shown, but it is also possible to construct it as a circuit that represents a high impedance (high-Z state) state using an activation signal (/ EN), as in FIG 87B is shown.

As in 87C the PRD-type bus amplifier (pseudo-PRD-type bus amplifier) 2300 several transmission gates, the switching steps of which are controlled by control signals (ϕ1, / ϕ1; ϕ2, / ϕ2; ϕ1 ', ϕ1'; ϕ1 '', / ϕ1 ''; ϕ2 ', / ϕ2'; ϕ2 '', / ϕ2 '') several inverters and several capacities (C1a, C2a; C1b, C2b). More specifically, the bus amplifier 2300 of the PRD type of 87C of the type that works in a nesting manner using a pair of blocks and includes two PRD blocks 2300A and 2300B ,

88 FIG. 12 is a diagram illustrating an example of the signal waveform for operating the bus amplifier of FIG 87C shows, and 89 FIG. 12 is a diagram showing an example of the operating waveform of the bus in the device for transmitting a signal from 86 shows.

The bus amplifier 2300 of the PRD type of 87C is represented by signals like that in 88 shown driven. Here, the control signals ϕ1 ', ϕ1''andϕ2', ϕ2 '' have essentially the same waveform as the control signals ϕ1 and ϕ2, respectively, and are output synchronized to the clock at alternating times (the rise and fall times of the clock signal CLK) to the PRD blocks 2300A and 2300B to drive in a nested way. That means the structure is tight stalt that during a PRD block (e.g. 2300A ) Performs calculations to eliminate (calculate) an intersymbol interference component for the data in the next clock cycle, the other PRD block (e.g. 2300B ) Receives data and delivers an output signal. This operation is carried out alternately to reproduce data at a high speed.

In the operation waveform diagram of the first embodiment (the first embodiment of the fifth mode) shown in 89 are the output signal (A) from the drive device 2100 that from the bus amplifier 2300 of the PRD type received signal (B) and that from the bus amplifier 2300 of the PRD-type signal (C) shown. In particular, the diagram shows an example of data transmission at 500 Mbps. As can be seen, according to the first exemplary embodiment, data can be used using the bus amplifier 2300 can be reproduced correctly without the data output from the driver 2100 must be swung out to its full amplitude. In the first embodiment, since the data bus ( 2200 ) is not precharged, the data bus is at a random level when it is not transmitting any data; nevertheless, data transmission at high speed is possible. Furthermore, since data can be transmitted by reducing the amount of bus level variation per bit of data, the bus actually behaves as a low amplitude bus so that the bus power consumption can be reduced.

90 Fig. 12 is a block diagram showing, in schematic form, an essential part of a second embodiment of the signal transmission apparatus according to the fifth mode of the present invention. This embodiment differs from that in 86 first embodiment shown by the inclusion of a precharge circuit 2400 and corresponds to the structure of the previously in 80 shown second principle (in which the precharge circuit is provided).

In the in 90 shown second embodiment, if no data transmission is carried out, a precharge from the precharge circuit 2400 carried out. In the second exemplary embodiment shown here, no precharging is carried out during data transmission, but it can be constructed such that precharging is carried out by the precharging circuit 2400 by temporarily stopping the data transfer when there is enough time to perform the precharge. However, precharging for each bit, as in the prior art, is not advantageous from the standpoint of data transfer efficiency.

In the second embodiment, since data transfer starts at the precharge level and ends at the precharge level, the start level of the bus is 2200 is known so that if there is a construction problem in any other section of the system, the problem can be easily analyzed. Furthermore, in cases where the total level of the bus 2200 moves steadily to a certain level, since the level at the end of the data transfer is reset to the precharge level, the probability that the bus level is fixed to the certain level is reduced. The reduced likelihood here means that there is a likelihood that the bus level will fix to a certain level even if a data read operation lasts for a very long time, and in a conventional read operation this is rarely a problem. Furthermore, if the bus 2200 is fixed at a certain level, data transmission can be performed as in the previous first embodiment.

91 Fig. 11 is a circuit diagram showing an example of the precharge circuit in the device for transmitting a signal from 90 shows. The same driver 2100 and a bus amplifier 2300 of the PRD type like those used in the first embodiment can also be used here.

As in 91 is shown is the precharge circuit 2500 built from a transmission gate that the bus 2200 charges by applying a precharge level (Vpr) according to the precharge control signals pre and / pre.

92 FIG. 12 is a diagram showing an example of the signal waveform for driving the bus and the bus amplifier in the device for transmitting a signal from 90 shows. Here shows in the signal waveform diagram of 92 reference numeral (I) a method in which the bus 2200 is charged when it is not transmitting data, and (II) shows a method in which the bus 2200 is only charged at the beginning and end of a data transfer. This means, 92 (I) shows the sequence in which charging is maintained when no data transfer is being performed, and 92 (II) shows the sequence in which charging is performed only at the start and end of a data transfer, and during periods other than the data transfer and charging period, the bus becomes 2200 brought into a changeable state.

93 FIG. 12 is a diagram showing an example of the operating waveform of the bus in the device for transmitting a signal from 90 shows. As in 93 is shown, according to the second embodiment, the level of the bus 2200 For example, reset to the charging level (Vpr) at the beginning and at the end of a data transmission.

94 Fig. 10 is a block diagram showing in schematic form an essential part of a third embodiment of the signal transmission apparatus according to the fifth mode of the present invention.

As from the comparison between the 94 and 86 can be seen is in the third embodiment example the single bus 2200 in the in 86 shown first embodiment of complementary buses 2200 ' (bus, / bus), and the device for transmitting a signal is using a driver 2100 ' and a bus amplifier of the PRD type (complementary differential bus amplifier of the PRD type) 2300 ' built up with the complementary buses 2200 ' are compatible.

The 95A and 95B show circuit examples of the drive device ( 2100 ' ) in the device for transmitting a signal from 94 , and 95C shows a circuit example of the PRD-type bus amplifier (the complementary differential bus amplifier 2300 ' of the PRD type) in the device for transmitting a signal from 94 ,

The drive device 2100 ' can be constructed from a simple pair of inverters for inverting and amplifying complementary input data (Din, / Din), as in 95A , but it is also possible to construct it as a circuit that generates complementary output signals A and / A from the input signal (positive logic input signal), as in FIG 95B is shown.

As in 95C is shown, the complementary differential bus amplifier of the PRD type (complementary differential bus amplifier of the pseudo-PRD type) comprises 2300 ' first and second PRD amplifiers 2310 and 2320 and an amplifier 2330 of the lock type. The first PRD amplifier 2310 receives a positive logic input signal B and carries an output signal D to the amplifier 2330 of the memory device and the second PRD amplifier 2320 receives a negative logic input signal / B and carries an output signal E to the amplifier 2330 of the memory module.

96A Fig. 10 is a circuit diagram showing an example of the PRD amplifier (the first and second PRD amplifiers 2310 and 2320 ) in the bus amplifier (complementary differential bus amplifier of the PRD type) from 95C shows, and 96B shows a circuit diagram of the amplifier ( 2330 ) of the memory module in the bus amplifier of 95C ,

As from the comparison between the 96A and 87C can be seen, the first PRD amplifier 2310 (the second PRD amplifier 2320 ) the same structure as the bus amplifier 2300 of the PRD type of 87C for the single bus. Furthermore, as in 96B is shown the amplifier 2330 of the memory device is configured to receive the output signals D and E from the first and second PRD amplifiers 2310 and 2320 receives and outputs complementary signals C and / C. By constructing the data transmission system in a complementary manner, it becomes possible to detect even smaller signal variations by reducing the influence of the phase noise. However, this structure increases the circuit scope of the complementary bus amplifier 2300 ' of the PRD type etc.

The drive device circuits described above 2100 ' and the complementary differential bus amplifier 2300 ' of the PRD type are only examples and it should be noted that other different circuits can also be used as long as they can generate complementary signals.

97 FIG. 12 is a diagram illustrating an example of the signal waveform for operating the bus amplifier of FIG 95C shows, and 98 FIG. 12 is a diagram showing an example of the operating waveform of the bus and the bus amplifier in the device for transmitting a signal from 94 shows.

As in 97 is shown, the control signals ϕ1 and ϕ2 (ϕ1 'and ϕ2'; ϕ1 '' and ϕ2 '') are output at alternate times in synchronization with the clock CLK to the PRD blocks 2300A and 2300B to drive in a nested manner, as shown in the previous one 88 ,

Then, as in 98 is shown in the third embodiment, the output signals (A, / A) of the drive device 2100 ' , the signals (B, / B) from the complementary differential bus amplifier 2300 ' of the PRD type, and that from the complementary differential bus amplifier 2300 ' of the PRD type output signals (C, / C) obtained, the complementary equivalents of the signal waveforms of the in 89 are shown first embodiment. As can be seen, according to the third embodiment, the data can be used using the complementary differential bus amplifier 2300 ' of the PRD type can be correctly reproduced without the data output from the drive device 2100 ' must be swung out to its full amplitude.

99 Fig. 12 is a block diagram showing in schematic form an essential part of a fourth embodiment of the signal transmission apparatus according to the fifth mode of the present invention.

This in 99 The fourth embodiment shown differs from that in FIG 94 shown third embodiment in that a precharge circuit 2400 ' is added, and that the complementary differential bus amplifier 2300 '' of the PRD type is constructed so that it only outputs the positive logic signal (C).

100A shows a circuit example of the precharge circuit ( 2400 ' ) in the device for transmitting a signal from 99 , and 100B shows a circuit example of the bus amplifier (the complementary differential bus amplifier 2200 " of the PRD type) in the device for transmitting a signal from 99 ,

As in 100A is shown is the precharge circuit 2500 ' composed of several transistors, and constructed in such a way that the complementary buses bus and / bus ( 2200 ' ) using precharge control signals PRE, / PRE shorts and a preload depegel (Vpr).

As in 100B is shown, the complementary differential bus amplifier of the PRD type (the complementary differential bus amplifier of the pseudo-PRD type) comprises a first and a second PRD amplifier 2310 and 2320 and a current mirror amplifier 2340 , The first PRD amplifier 2310 receives a positive logic input signal B and carries an output signal D to the current mirror amplifier 2340 too, and the second PRD amplifier 2320 receives a negative logic input signal / B and carries an output signal E to the current mirror amplifier 2340 to.

101A shows a circuit example of the PRD amplifier (the first and the second PRD amplifier 2310 and 2320 ) in the bus amplifier (the complementary differential bus amplifier of the PRD type) from 100B , and 101B shows a circuit example of the current mirror amplifier ( 2340 ) in the bus amplifier from 100B ,

As from the comparison between the 101A and 87C can be seen, the first PRD amplifier 2310 (the second PRD amplifier 2320 ) an identical structure to the bus amplifier 2300 of the PRD type of 87C for the single bus. Furthermore, as in 101B is shown, the current mirror amplifier 2340 constructed to receive the output signals D and E from the first and second PRD amplifiers 2310 and 2320 receives and outputs the signal (positive logic signal) C.

Here activation signals (en, / en) are sent to the control transistors in the current mirror amplifier 2340 created.

By using the complementary current mirror amplifier 2340 it becomes possible to detect even smaller signal variations by reducing the influence of phase noise. In this case, however, the circuit size of the current mirror amplifier increases 2340 ,

102 FIG. 10 shows an example of the signal waveform for operating the plus amplifier of FIG 100B ,

As in 102 is shown, the control signals ϕ1 and ϕ2 (ϕ1 'and ϕ2'; ϕ2 'and ϕ22') are output at alternate times in synchronization with the clock CLK to the blocks 2300A and 2300B to drive in a nested manner, as in the one shown previously 88 , During periods other than that during which the bus 2200 ' is in operation (data is being transferred), the precharge control signal PRE is held at a high level "H" (/ PRE is held at a low level "L") around the bus 2200 ' charge. Furthermore, this becomes the current mirror amplifier during the data transmission period 2340 applied activation signal is kept at a high level "H" (is kept at a low level "L") around the current mirror amplifier 2340 to activate, which thus outputs data (C).

103 Fig. 10 is a diagram showing an example of the operating waveform of the bus and the bus amplifier in the device for transmitting a signal from 99 shows.

As in 103 is shown, according to the fourth embodiment, the complementary signals (A / A), which are from the drive device or the driver 2100 ' are issued along the complementary buses 2200 ' transferred and the complementary differential bus amplifier 2300 ' of the PRD type receives the complementary signals (B, / B) and outputs the signal (positive logic signal) C. In the fourth embodiment, since the precharge circuit 2400 ' is provided, the input signals (B, / B) of the complementary bus amplifier 2300 ' of the PRD type is kept at a predetermined level (precharge level Vpr) before and after data transmission.

The fourth embodiment (the fourth embodiment of the fifth mode) consumes more energy than the previous third embodiment, but enables operation at a higher speed. Further, in the third and fourth embodiments, since the intersymbol interference component is eliminated by storing in the PRD type single amplifiers and a certain amount of amplification is still performed, an input offset which is a disadvantage of a complementary amplifier is not added a problem. The differential current mirror amplifier with the complementary inputs is not on the in 101B The structure shown is limited, but various other structures can be used as long as they are able to amplify differential inputs.

104 Fig. 11 is a block diagram showing in schematic form an essential part of a fifth embodiment of the signal transmission apparatus according to the fifth mode of the present invention. The basic structure is the same as that of the previous fourth embodiment, the only difference being the structure of the complementary differential bus amplifier 2302 ' of the PRD type that characterizes the fifth embodiment.

105 Fig. 10 is a block circuit diagram showing an essential part of an example of the bus amplifier in the device for transmitting a signal from 104 shows. A circuit example of the complementary differential bus amplifier 2302 ' of the PRD type is shown here.

In the complementary differential bus amplifier 2300 ' in the previous third and fourth exemplary embodiments, the inputs are first fed to the single bus amplifiers of the PRD type, the outputs of which are then fed as inputs to the complementary amplifier; on the other hand, the complementary differential bus amplifier comprises 2302 ' of the PRD type a differential amplifier 2303 and an amplifier precharge circuit 2302 for precharging the input nodes of the differential amplifier 2303 , in front of which a PRD functional block 2301 is arranged, which comprises capacitors (capacitors C10a, C20a; C10b, C20b). This complementary differential bus amplifier 2302 ' of the PRD type continues to perform data reproduction and amplification at a high speed by switching between two amplifier sections (that means here two main amplifier sections).

Here, if the value of the capacitors C10a and C10b is labeled C10 and the value of the capacitors C20a and C20b is labeled C20, the intersymbol interference can theoretically be completely eliminated if these capacitance values C10 and C20 are set to be in accordance with the equation C10 / (C10 + C20) = (1 + exp (–T / τ)) / 2 are sufficient. That this was in an ideal state, but in practice, because of the presence of parasitic capacitances, etc., the capacitance values are selected to provide a capacitance ratio that is close to the values that satisfy the above equation. In the equation, τ is the time constant of the bus 2200 ' and T is the cycle of a bit or the time during which the "1" level appears on the bus.

The 106A to 106C are waveform diagrams showing the relationship between the time constant of the bus and the "1" level: 106A is a graph showing the original waveform (data 1-1-0), 106B is a diagram for explaining the time T during the "1" level on the bus 2200 ' appear and 106C Fig. 12 is a graph showing "1" level (T).

When transmitting the original waveform (data 1-1-0 ), like the one in 106A As shown, the period of a high impedance state (high Z state) can be provided after the "1" level on the bus 2200 ' appear as in 106B shown, or the data can be transmitted throughout the "1" level T, as in 106C is shown. That is, one of the waveforms 106B or 106C can the in 106A original data shown by the PRD-type bus amplifier (the complementary differential bus amplifier 2300 '' of the PRD type) are correctly detected.

The 107A and 107B are diagrams for explaining the operation of the bus amplifier from 105 ,

The differential bus amplifier leads by controlling the control signals ϕ1 and ϕ2 2302 ' of the PRD type used in the 107A and 107B operating steps shown alternately.

That is, when the control signal ϕ1 is at a high level "H" (/ ϕ1 is at a low level "L") and the control signal ϕ2 is at a low level "L" (/ ϕ2 is at a high level Level "H"), an operating step for determining an intersymbol interference component is carried out, as in 107A and when the control signal ϕ1 is at a low level "L" and the control signal ϕ2 is at a high level "H", a signal determination operation is performed as in FIG 107B is shown. The amplifier precharge circuit charges here 2302 the input node differential bus amplifier 2303 during the period of determination of the intersymbol interference component.

In the previous third and fourth embodiments, the bus amplifier (the complementary differential bus amplifier 2300 ' PRD type) first the signals from the complementary bus 2200 ' by the PRD method and then amplifies their differential voltage instead of receiving the weak complementary signals in complementary form; this only means that the intersymbol interference components in the complementary signals are roughly eliminated, although the sensitivity is increased compared to a simple case of a line. In this case, incorrect operation can occur depending on the size of the signal.

In contrast to this is the complementary differential bus amplifier 2302 ' of the PRD type of the fifth embodiment, a bus amplifier of the PRD type for complementary signals in the true sense of the word, and ideally can completely eliminate inter-symbol interference components from complementary signals. Thus, compared to the third and fourth embodiments (pseudo PRD type bus amplifiers), the sensitivity can be greatly increased, in other words, the operating margin can be increased dramatically.

108 FIG. 11 is a diagram showing another example of the bus amplifier in the device for transmitting a signal from 104 shows, 109 FIG. 10 is a circuit diagram showing an example of the PRD amplifier structure in the bus amplifier of FIG 108 shows, and 110 FIG. 10 is a circuit diagram showing an example of a multiplexer in the bus amplifier of FIG 108 shows.

The bus amplifier (the complementary differential bus amplifier 2300A of the PRD type) comprises a first and a second PRD amplifier 2310a and 2320a which have a similar structure to the bus amplifier (the complementary differential bus amplifier 2302 ' of the PRD type) by 105 and a multiplexer (MUX) 2330A , The in 108 The bus amplifier shown achieves high-speed data transmission by performing interleaving operations such that a PRD amplifier (the first PRD amplifier 2310a ) determines (eliminates) the intersymbol interference, while the other PRD amplifier (the second PRD amplifier 2320a ) makes a determination of data, and at the next point in time the one PRD amplifier (the first PRD amplifier 2310a ) a determination of data by while the other PRD amplifier (the second PRD amplifier 2320a ) determines the intersymbol interference.

Here, the same PRD amplifier is precharged at the same time in the PRD amplifier that performs the inter-symbol interference determination operation. Since this precharge is performed in the background during the interleaving data read period, the precharge time does not affect the data transfer cycle. There are also capacities for PRD between the buses 2200 ' and the input node of the main section of the bus amplifier (the complementary differential bus amplifier 2300A of the PRD type: amplifier) so that the buses are isolated from the input nodes of the amplifier main section, and further, since the potential difference between the buses and the input nodes of the amplifier is not particularly limited in the PRD method, the levels of the input nodes at the beginning of amplifier operation by precharging at those points which increase the sensitivity of the complementary amplifier most. This can greatly increase the sensitivity even if the same complementary amplifier is used in the main section.

In the circuit described above, complementary transmission gates are used as the switches, but other devices with switching functions can also be used; for example, the switches can only be constructed using NMOS transistors (NMOS transfer gates) or PMOS transfer gates. In the fifth embodiment, the differential amplifier 2303 constructed as an NMOS gate receive amplifier, but whether it is constructed as an NMOS or PMOS gate receive amplifier depends on the technology etc. and which one is favorably selected. Furthermore, in the fifth exemplary embodiment, a gate-receiving jack or lock for the differential amplifier 2303 used, but the differential amplifier is not limited to this particular type. The differential amplifier 2303 , which is used in the fifth embodiment, is constructed so that by using the activation signals en and / en, its operation can be stopped when no data transmission is performed.

As in 109 is shown, the first PRD amplifier 2310a (the second PRD amplifier 2320a ) a structure similar to that in 105 Complementary differential bus amplifier shown 2302 ' of the PRD type and includes the PRD functional block 2301 who have favourited Amplifier Precharge Circuit 2302 and the differential amplifier 2303 , Here is the differential amplifier 2303 constructed as a gate receiving latch type differential amplifier. Furthermore, the precharge operation of the amplifier precharge circuit 2302 controlled by the control signal ϕ1 (/ ϕ1) during the operation of the differential amplifier 2303 is controlled by the activation signal en (/ en).

As in 110 is shown, the MUX (Muliplexer) 2330A the output signal (D) of the first PRD amplifier 2310a or the output signal (E) of the second PRD amplifier 2320a according to the control signals ϕ1 '(/ ϕ1') and ϕ2 '(ϕ2') and outputs the selected signal as the output signal (C) of the bus amplifier (the complementary differential bus amplifier 2300A of the PRD type).

111 FIG. 12 is a diagram illustrating an example of the signal waveform for operating the bus amplifier of FIG 108 shows, and 112 FIG. 12 is a diagram showing an example of the operating waveform of the bus and the bus amplifier in the device for transmitting a signal from 104 shows.

By using the control signals ϕ1 and ϕ2, as in 111 interleaving operations are performed such that a PRD amplifier (the first PRD amplifier 2310a ) determines the intersymbol interference while the other PRD amplifier (the second PRD amplifier 2320a ) performs a data determination, and at the next point in time one PRD amplifier carries out a data determination while the other PRD amplifier determines the intersymbol interference. Here, precharging is also carried out simultaneously in the PRD amplifier which carries out the intersymbol interference estimation operating step.

As in 112 is shown, according to the fifth embodiment, the complementary signals (A, / A) which are generated by the drive device 2100 ' are issued along the complementary buses 2200 ' transferred and the complementary differential bus amplifier 2302 ' receives the complementary signals (B, / B) and outputs the signal (positive logic signal) C.

113 Fig. 12 is a diagram showing an example of a bus amplifier in the signal transmission device as a sixth embodiment of the signal transmission device according to the fifth mode of the present invention. The sixth embodiment also relates to the example of the complementary bus and the block diagram itself is the same as that previously described 108 ,

More specifically, the bus amplifier comprises (the complementary differential bus amplifier 2300B of the PRD type) a first and a second PRD amplifier 2310b and 2320b and a multiplexer (MUX) 2330b , as in 113 is shown.

114 Fig. 10 is a circuit diagram showing an example of the PRD amplifier structure (the first and second PRD amplifiers 2310b and 2320b ) in the bus amplifier 113 shows.

As from the comparison between the 114 and 109 can be seen, the PRD amplifier differs ( 2310b . 2320b ) in the sixth embodiment from the PRD amplifier ( 2310a . 2320a ) in the in 109 fifth embodiment shown in the construction of the differential amplifier 2303a ,

As in 114 is shown, the differential amplifier differs 2303a of the sixth embodiment of the differential amplifier 2303 of 109 by incorporating a NAND gate 2331 and an AND gate 2332 , More specifically, while in the differential amplifier 2303 of 109 the activation signals (s, / s) are fed directly to the gates of the control transistors, in differential amplifiers 2300A of the sixth embodiment, which in 114 is shown, the activation signal en and the control signal ϕ1 the NAND gate 2331 and the AND gate 2332 entered for logical operations, and the outputs of these gates 2331 and 2332 are used to control the switching of the control transistors. In this way the differential amplifier 2300A turned on (activated) for a minimum required time to reduce energy consumption.

In the sixth embodiment, as in the previous fifth embodiment, is the differential amplifier 2300A constructed as a gate receiving latch type amplifier. The differential amplifier 2300A in the sixth embodiment, the NMOS gate receiving type amplifier is constructed, but whether it is constructed as the NMOS or PMOS gate receiving type amplifier depends on the technology, etc., and which one is favorably selected , The order of operation is the same as that for the in 111 fifth embodiment shown.

In 114 when the bus amplifier is precharged, the nodes N1a and N1b of the differential amplifier 2330A charged to the high level "H"; thus, by adopting the NMOS gate receiving structure as in the sixth embodiment, the operating speed of the amplifier can be increased. In the sixth embodiment, as in the in 108 shown structure, high-speed data transmission by performing interleaving operations using the control signals ϕ1 and ϕ2 such that a PRD amplifier (the first PRD amplifier 2310b ) determines the intersymbol interference while the other PRD amplifier (the second PRD amplifier 2320b ) makes a decision about data, and the next time one PRD amplifier makes a decision about data while the other PRD amplifier eliminates the intersymbol interference.

115 FIG. 10 is a circuit diagram showing another example of the PRD amplifier structure in the bus amplifier of FIG 113 shows.

The in 115 Differential amplifier shown 2303B is under inclusion of the NAND gate 2331 and AND gates 2332 into the differential amplifier ( 2303c ) built up, which is described in the following 119 is shown. In differential amplifier 2303B of 115 as in the differential amplifier 2303a of 114 , the activation signal en and the control signal ϕ1 the NAND gate 2331 the AND gate 2332 entered for logical operations, and the outputs of these gates 2331 and 2332 are used to control the switching of the control transistors. In this way the differential amplifier 2303B activated for a minimum required time to reduce energy consumption.

116 FIG. 10 is a circuit diagram showing an example of the multiplexer in the bus amplifier of FIG 113 shows.

As in 116 the MUX (multiplexer) 2330b either the output signal (D) of the first PRD amplifier 2310b or the output signal (E) of the second PRD amplifier 2320b in accordance with the control signals ϕ1 '(/ ϕ1') and ϕ2 '(/ ϕ2') and outputs the selected signal as the output signal (C) of the bus amplifier (the complementary differential bus amplifier 2330b of the PRD type) after being inverted by an inverter to maintain logical integrity. The in 116 shown MUX 2330b is with the in 114 shown PRD amplifier (differential amplifier 2303a ) to use. If the in 115 shown PRD amplifier (differential amplifier 2303B ) is used, the in 110 shown MUX 2330A be used. It is not necessary to say that the signal logic can be changed according to the needs.

117 12 is a diagram showing an example of the operation waveform of the bus and the bus amplifier in the sixth embodiment of the signal transmission apparatus according to the fifth mode of the present invention.

As in 117 is shown, according to the sixth embodiment, the complementary signals (A, / A) which are generated by the drive device 2100 ' are issued along the complementary buses 2200 ' transmitted and the complementary differential bus amplifier 2300B of the PRD type receives the complementary signals (B, / B) and outputs the signal (positive logic signal) C. In 117 are the output signal D of the first PRD amplifier 2310b and the output signal E of the second PRD amplifier 2320b also shown.

118 12 is a diagram showing an example of the bus amplifier in the signal transmission device as a seventh embodiment of the signal transmission device according to the fifth mode of the present invention. The seventh embodiment also relates to the complementary bus example, and the block diagram itself is the same as that described above 108 and 113 ,

More specifically, as included in 118 is shown, the bus amplifier (the complementary differential bus amplifier 2300c of the PRD type) a first and a second PRD amplifier 2310C and 2320c and a multiplexer (MUX) 2330c ,

119 FIG. 10 is a circuit diagram showing an example of the PRD amplifier structure in the bus amplifier of FIG 118 shows.

As described above, the differential amplifier differs 2303c in the PRD amplifier 2310C ( 2320c ) of 119 from the differential amplifier 2303B who in 115 is shown by omitting the NAND gate 2331 and the AND gate 2332 ,

As in 119 is shown is the differential amplifier 2303c of the seventh embodiment constructed as a current mirror amplifier. This type of amplifier has a higher sensitivity and enables operation at a higher speed than, for example, a differential amplifier of the lock type. However, since the dynamic range of a current mirror amplifier is generally small, it is advantageous to optimize the input level so that maximum use is made of the properties of the differential current mirror amplifier 2303c can be made. Thus, although this amplifier is a complementary amplifier, the sensitivity can be increased dramatically compared to, for example, the fifth embodiment. As in the previous embodiments, the seventh embodiment also enables high-speed data transmission through interleaving operations.

120 FIG. 10 is a circuit diagram showing an example of the multiplexer in the bus amplifier of FIG 118 shows.

As in 120 is shown, the MUX (multiplexer) 2330c an identical structure to that in 116 shown MUX 2330b on. That is, the MUX 2330c either selects the output signal (D) of the first PRD amplifier 2310C or the output signal (E) of the second PRD amplifier 2320c according to the control signals ϕ1 '(/ ϕ 1') and ϕ2 '(/ ϕ2') and outputs the selected signal as the output signal (C) of the bus amplifier (the complementary differential bus amplifier 2330c of the PRD type) after being inverted by an inverter to maintain logical integrity.

121 FIG. 12 is a diagram illustrating an example of the signal waveform for operating the bus amplifier of FIG 118 shows, and 122 12 is a diagram showing an example of the operation waveform of the bus and the bus amplifier in the seventh embodiment of the signal transmission apparatus according to the fifth mode of the present invention.

As from the comparison between the 121 and 122 and the 111 and 112 can be seen, the mode of operation of the bus amplifier (the differential bus amplifier 2330c ) and the device for transmitting a signal in the seventh embodiment are the same as those described in the fifth embodiment.

123 Fig. 12 is a diagram showing an example of the bus amplifier in the signal transmission device as an eighth embodiment of the signal transmission device according to the fifth mode of the present invention. The eighth embodiment also relates to the example of the complementary bus, and the block diagram itself is the same as that described above 108 Etc.

The eighth embodiment relates to a structure for compensating the input offset of the differential amplifier stage, which can become a problem, for example, in the fifth to seventh embodiment. That is, the eighth embodiment is directed to compensating for the input offset of the differential amplifier. More specifically, the differential amplifier 2303d the function of compensating the input offset of the eighth embodiment.

124 FIG. 10 is a circuit diagram showing an example of the PRD amplifier structure in the bus amplifier of FIG 123 shows.

As from the comparison between the 124 and 119 can be seen, is the precharge circuit in the eighth embodiment 2302d only for one input of the differential current mirror amplifier 2303d provided and the other input is connected to the output by means of a transmission gate, the switching of which is controlled by the control signal ϕ1 (/ ϕ1).

The 125A and 125B are diagrams for explaining the operation of the bus amplifier from 124 : 125A shows preparation for intersymbol interference elimination and self-calibration operation, and 125B shows a signal decision operation.

First, as in 125A an operation step for estimating the intersymbol interference is carried out at time 1, while at the same time the operation step for eliminating the input offset of the differential amplifier itself by electrically short-circuiting an input and the output of the differential amplifier 2303d is carried out. At the same time, the other input of the differential amplifier 2303d through the precharge circuit 2302d charged to a level (Vpr) which increases the sensitivity of the differential amplifier.

Next, as in 125B is shown, the operating step for data decision is carried out at a time 2. At this time there is a short circuit between the input and the output of the differential amplifier 2303d open and the precharge by the precharge circuit 2302d is also stopped.

As has been described, the eighth embodiment a function (self-calibration function) for eliminating the input offset added which is a disadvantage of the complementary differential amplifier is. Furthermore, the PRD functional block has an identical structure like that of the seventh embodiment on and unlike the third and fourth embodiments, the intersymbol interference component can ideally Completely be eliminated. That is, that third embodiment can eliminate the input offset through the self-calibration function of the complementary amplifier and by eliminating the input offset it becomes possible to get even weaker signals to detect, reproduce and amplify.

Usually requires using a complementary amplifier a self-calibration function a capacity for input offset compensation, but in the eighth embodiment exists because the offset is stored in the capacity required for Determination of the inter-symbol interference component is used no need a separate capacity to be provided for offset compensation. As a result, the self-calibration function without increase the area added become.

In the eighth embodiment, the two PRD amplifiers (bus amplifiers) 2310d and 2320d operated in a nested manner and alternately perform signal reproduction and amplification, whereby high-speed signal transmission is achieved.

126 Fig. 4 is a circuit diagram showing an example of the multiplexer (MUX) 2330d in the bus amplifier from 123 shows. The structure is the same as that of the MUX 2330c in the seventh embodiment, which in 120 is shown.

127 FIG. 12 is a diagram illustrating an example of the signal waveform for operating the bus amplifier of FIG 123 shows, and 128 11 is a diagram showing an example of the operation waveform of the bus and the bus amplifier in the eighth embodiment of the signal transmission device according to the fifth mode of the present invention.

As in 127 in the eighth embodiment, high-speed data transmission is achieved by performing interleaving operations using the control signals ϕ1 and ϕ2 such that a PRD amplifier (the first PRD amplifier 2310d ) eliminates the intersymbol interference while the other PRD amplifier (the second PRD amplifier 2320d ) makes a decision about data, and the next time one PRD amplifier makes a decision about data while the other PRD amplifier eliminates the intersymbol interference. In the amplifier that performs the intersymbol interference determination step, the input offset elimination (self-calibration step) and the amplifier precharge are performed simultaneously as described above (compare the position shown in FIG 128 are marked by arrows). In this way, in the eighth exemplary embodiment, since the bus amplifier (the differential bus amplifier 2300D of the PRD type) is provided with a self-calibration function, even a slight variation in the potential can be detected.

Here, since the self-calibration and precharge operations are performed in the background during the interleave data read period, these operations do not affect the data transfer cycle (which therefore does not require additional time). Thus, as in 127 is shown, the activation signal en2 (/ en2) that of the second PRD amplifier 2320d is outputted at a time delayed by one bit from the activation signal en1 (/ en1) that the first PRD amplifier 2310d to prevent an unwanted signal from the MUX 2330d is issued.

In other respects, the structure of the eighth embodiment is the same as that of the other embodiments described so far. That is, capacities for PRD are between the buses and the input nodes of the main section of the bus amplifier (the differential bus amplifier 2300D of the PRD type) so that the buses are isolated from the input nodes of the amplifier main section, and further, since the potential difference between the buses and the input nodes of the amplifier is not particularly limited in the PRD method, the levels of the input nodes at the beginning of the amplifier operation can be set by precharging at points which increase the sensitivity of the complementary amplifier most. This can greatly increase the sensitivity even if the same complementary amplifier is used in the main section.

Furthermore, complementary transmission gates are used as the switches in the circuit described above, but other devices with switching functions can also be used; for example, the switches can only be constructed using NMOS transistors (NMOS transfer gates) or only PMOS transfer gates. In the eighth embodiment, the differential amplifier 2303d constructed as an NMOS gate receiving type amplifier, but whether it should be constructed as an NMOS or PMOS gate receiving type amplifier depends on the technology, etc., and which one is favorably selected. The differential amplifier used in the eighth embodiment 2303d is constructed in such a way that its operation can be stopped by the activation signals en1 and / en1 (en2 and / en2) when no data transmission is being carried out.

129 FIG. 12 is a diagram showing an example of a bus amplifier as a ninth embodiment of the signal transmission apparatus according to the fifth mode of the present invention 2300e in the device for transmitting a signal, and 130 Fig. 10 is a circuit diagram showing an example of the structure of a PRD amplifier 2310e in the bus amplifier from 129 shows. The ninth embodiment also relates to the example of the complementary bus, but unlike that in FIG 123 The eighth exemplary embodiment shown is, for example, the complementary differential bus amplifier 2300e of the PRD type using a single PRD amplifier 2310e and a latch or a lock 2340e built up. Here the in 130 PRD amplifier shown 2310e the same structure as the one previously in 124 PRD amplifier shown 2310d ( 2320d ) on.

That is, in the ninth embodiment, instead of using two PRD amplifiers in a nested manner, one PRD amplifier is used 2310e used to reduce (by almost half) the area occupied by the bus amplifier, with some sacrifices in terms of data transfer rate. In this case, since there is no need to precharge the bus, data can be transferred at a higher speed than if bus precharge is performed for each bit. The reason is that since the CR (clock rate) of the section that needs to be loaded to eliminate intersymbol interference in the amplifier is much less than the CR of the bus, the preparation time for eliminating the intersymbol interference is less than the bus precharge time is.

131 Fig. 3 is a circuit diagram showing an example of the latch 2340e in the bus amplifier 2300e of 129 shows.

As in 131 is shown includes the pawl or lock 2340e a first latch section whose data latch operation is controlled by the control signals ϕ1 and / ϕ1, and a second latch section whose data latch operation is controlled by the control signals ϕ2 and / ϕ2. Alternatively, the latch or lock 2340e only be constructed from one or the other of the locking sections.

132 FIG. 10 is a diagram illustrating an example of the signal waveform for operating the bus amplifier of FIG 129 shows, and 133 FIG. 12 is a diagram showing an example of the operation waveform of the bus and the bus amplifier in the ninth embodiment of the signal transmission device according to the fifth mode of the present invention.

The ninth embodiment is for applications suitable where the high transmission rate, by using two PRD amplifiers in a nested manner is achieved is not required, but it is desired that Reduce bus amplifier area. Also in the ninth embodiment is an operation with a higher Speed possible than in the prior art method that precharges each image required, and furthermore, due to the provision of the complementary self-calibration function much higher Sensitivity achieved as usual is used for complementary bus amplifiers. There are also capacities for PRD between the buses and the input nodes of the main section of the complementary amplifier inserted, So that the Buses isolated from the input nodes of the main amplifier section are, and since the potential difference between the buses and the Input node of the amplifier in the PRD method is not particularly limited, the levels of the input nodes at the beginning of amplifier operation such points can be set that the sensitivity of the complementary amplifier increase most. Accordingly, the Sensitivity can be greatly increased even if the same complementary amplifier is used in the main section.

That is, in the ninth embodiment, the area of the bus amplifier is reduced by not using the interleaving bus amplifier structure of the eighth embodiment (by using only one PRD amplifier); this effect of reducing the bus amplifier area by using only one PRD amplifier can be widely applied to various other bus amplifiers. Furthermore, in the ninth embodiment, complementary transmission gates are used as the switches, but other devices with switching functions can also be used. E.g. the switches can only be constructed using NMOS transistors (NMOS transfer gates) or PMOS transfer gates. In the ninth embodiment, the differential amplifier 2303e constructed as an NMOS gate received type amplifier, but whether it is constructed as an NMOS or PMOS gate received type amplifier depends on the technology, etc., and which one is favorably selected. The differential amplifier in the ninth embodiment 2303e is designed so that its operation can be stopped by the activation signals en and / en when no data transmission is being carried out.

134 FIG. 12 is a diagram showing an example of a bus amplifier in the signal transmission device as a tenth embodiment of the signal transmission device according to the fifth mode of the present invention. This exemplary embodiment relates to a bus amplifier of the pseudo-PRD type. Hereafter is the block diagram of 134 the same as that for that in 123 shown eighth embodiment.

As in 134 the bus amplifier (the differential bus amplifier 2300f of the PRD type) a first and a second PRD amplifier 2310f and 2320f and a multiplexer (MUX) 2330f ,

135A FIG. 10 is a circuit diagram showing an example of the PRD amplifier structure in the bus amplifier of FIG 134 shows, 135B FIG. 10 is a circuit diagram showing another example of the PRD amplifier structure in the bus amplifier in FIG 134 shows, and 136 FIG. 10 is a circuit diagram showing yet another example of the PRD amplifier structure in the bus amplifier of FIG 134 shows.

In the PRD amplifier 2310f ( 2320f ) of the tenth embodiment are, as from the structure of the in 135A PRD functional block shown 2301f it can be seen the capacitors used to change the connection to the other bus when the amplifier is precharged from the PRD functional block 2301 in the PRD amplifier 2310d of in 124 shown eighth embodiment omitted. The precharge circuit 2302f and the differential amplifier 2303f are the same as the one in the 124 shown eighth embodiment.

In the PRD amplifier 2310f ' ( 2320f ' ) who in 135B is shown in 135A PRD functional block shown 2301f into a PRD functional block 2301f ' modified, in which the switching of the capacitors C30a and C30b is controlled by a logic circuit (OR and AND gates) which receives the control signals ϕ1, ϕ2 (ϕ1, / ϕ2).

In the in 136 shown PRD amplifier 2310f '' ( 2320f '' ) are, as from the structure of the in 136 PRD functional block shown 2301f '' can be seen, the transmission gates for controlling the connections between the buses (B, / B) and the capacitances (C30a, C30b) from the in 135A PRD amplifier shown omitted. If the time constant of the bus is small or if the time during which data is output on the bus is less than the cycle time per picture, the bus level can change as before in 106B was shown; if the data bus is of such a stable level, the transmission gates for controlling the connections between the buses (B, / B) and the capacitors (C30a, C30b) can be omitted, as in FIG 136 is shown.

The above PRD amplifier is so constructed that be Operation can be stopped by the activation signal en (/ en) can if no data is transferred become.

In the PRD method (pseudo PRD method) used in the tenth embodiment, unlike the real PRD method, a bit decision "0" or "1" is made about the current bit with respect to the value of one picture met before. Thus, the operating margin is small compared to the eighth embodiment. Instead, the bus amplifier (the complementary differential bus amplifier 2300f of the PRD type) occupied area can be reduced. In the tenth embodiment, as in the fifth embodiment, for example, complementary buses are used, and the data transmission speed is controlled by operating the two PRD amplifiers 2310f and 2320f increased in a nested manner.

137 Fig. 3 is a circuit diagram showing an example of the multiplexer 2330f in the in 134 shown amplifier shows.

As in 137 is shown, the multiplexer (MUX) 2330f the same structure as for example that in 116 shown MUX 2330b of the sixth embodiment, and is constructed so that it alternately outputs the PRD amplifier 2310f and 2320f in accordance with the control signals ϕ1 'and ϕ2' (ϕ1 'and / ϕ2') as the output.

Here in the PRD process to to eliminate the intersymbol interference, the scan cycle an inter-symbol interference component alternating with the cycle be executed to correctly sample the data; thus by Operating a pair of PRD amplifiers in a nested manner a data transfer carried out without interruption become. Furthermore, in the cases of the first to fourth embodiments and the eighth and ninth embodiments according to the fifth mode of present invention the amplifier sensitivity through the additional Carry out the amplifier self-calibration operation during the Scan cycle (estimate) an intersymbol interference component is increased. Also in the tenth embodiment by using the two PRD amplifiers as a pair, a pseudo-symbol interference component (corresponding the data from one bit before) and the amplifier self-calibration cycle is alternated with the cycle for correct sampling of the data.

138 FIG. 12 is a diagram illustrating an example of the signal waveform for operating the bus amplifier of FIG 134 shows, and 139 FIG. 12 is a diagram showing an example of the operation waveform of the bus and the bus amplifier in the tenth embodiment of the signal transmission apparatus according to the fifth mode of the present invention.

Also in the tenth embodiment, by using the two PRD amplifiers 2310f and 2320f the cycle for sampling a pseudo-inter-symbol interference component (corresponding to the data from a picture before) and for precharging the amplifier alternately with the cycle for correctly sampling the data leads. Since the precharge is performed in the background during the interleaving data reading period, the precharge time does not affect the data transfer cycle. In the tenth embodiment, the two PRD amplifiers are connected in pairs and operated in an interleaved manner in order to achieve high-speed data transmission, but the structure can be such that only one PRD amplifier is used and no interleaving is carried out as in that Structure of the new embodiment. In this case the transmission rate is reduced, but the area occupied by the bus amplifier can be reduced further.

Furthermore, as in 138 is shown, the second PRD amplifier 2320f supplied activation signal en2 (/ en2) is output at a time that is one bit of that by the first PRD amplifier 2310f supplied activation signal en1 (/ en1) is delayed in order to prevent an unwanted signal from the MUX 2330f is issued.

140 12 is a block diagram showing, as an eleventh embodiment, in schematic form an example of a semiconductor memory device to which the signal transmission device according to the fifth mode of the present invention is applied. In 140 denotes the reference symbol 2001 a memory cell arrangement, 2002 is a word decoder (word decoder arrangement), 2100 is a sense amplifier (sense amplifier arrangement), 2201 is a local data bus, 2202 is a global data bus, 2300g is a data bus amplifier of the PRD type (complementary global data bus amplifier of the PRD type), 2401 is a precharge circuit for the local data buses, 2402 is a precharge circuit for the global data buses, 2009 is a switch for the local data buses, 2010 is a write amplifier, 2011 is a sense amplifier drive device, and 2012 is a column decoder (column decoder arrangement).

As in 140 is shown, the semiconductor memory device (memory cell array portion of a DRAM) of the first embodiment includes a plurality of memory cell arrays 2001 , Word decoder 2002 , Sense amplifier 2100 , local data buses 2201 and global data buses 2202 , The semiconductor memory device of the eleventh embodiment further includes data bus amplifiers 2300g of the PRD type for amplifying data on the global data buses 2202 when reading out data, precharging circuits 2401 for the local data buses for precharging the local data buses 2201 , Precharge circuits 2402 for the global data buses for precharging the global data buses 2202 , Switch 2009 for the local data buses to control the connections between the global data buses 2202 and the local data buses 2201 and write amplifier 2010 for writing data into the memory cells. Furthermore, the semiconductor memory device of the eleventh embodiment includes column decoders 2012 for selecting column transfer gates, as discussed below, and sense amplifier drive devices 2011 to drive the sense amplifiers 2100 , Here are the switches 2009 for the local data buses, for example, each made up of a complementary NMOS or PMOS transmission gate.

141 FIG. 12 is a diagram showing an example of the bus amplifier in the semiconductor memory device of FIG 140 shows. The local data bus corresponds here 2201 and the global data bus 2202 in 140 the complementary breasts 2200 ' (B, / B) in 141 ,

As in 141 is shown is the bus amplifier (the data bus amplifier 2300g of the PRD type) of the eleventh embodiment is constructed as a complementary differential bus amplifier and comprises a first and a second PRD amplifier 2310g and 2320g and a multiplexer (MUX) 2330g ,

142 FIG. 10 is a circuit diagram showing an example of the PRD amplifier structure in the bus amplifier of FIG 141 shows and 143 FIG. 10 is a circuit diagram showing an example of the multiplexer in the bus amplifier of FIG 141 shows.

As from the comparison between the 142 and the eighth embodiment described above 124 can be seen, the PRD amplifier (the first and the second PRD amplifier 2310g and 2320g ) in the eleventh embodiment has substantially the same construction as the PRD amplifiers in the eighth embodiment, except that the sources of the PMOS transistors (P-channel MOS transistors) controlled by the activation signal (s) are on one predetermined potential Vpr 'can be maintained, not at a supply current Vcc (Vii) at a high level.

Furthermore, as can be seen from the comparison between the 143 and the eighth embodiment described above 126 can be seen, the MUX 2330g in the eleventh embodiment, the same structure as the MUX 2330g in the eighth embodiment and is constructed so that it either outputs D from the first PRD amplifier 2310g or the output signal E of the second PRD amplifier 2320g according to the control signals ϕ1 '(/ ϕ1') and ϕ2 '(/ ϕ2) and the selected signal as the output signal C of the bus amplifier (the complementary differential bus amplifier 2300g of the PRD type. Here, the control signals ϕ1 '(/ ϕ1') and ϕ2 '(/ ϕ2') are essentially the same as the control signals ϕ1 (/ ϕ1) and ϕ2 (/ ϕ2), although the timing is slightly different.

144 FIG. 11 is a circuit diagram showing an example of the sense amplifier in the semiconductor memory device of FIG 140 shows.

The sense amplifier 2100 used in the semiconductor memory device of the eleventh embodiment is the same as the sense amplifier, for example 2003 who in the in 74 shown semiconductor memory device of the prior art, and comprises a sense amplifier of the latch type (complementary PMOS / NMOS sense amplifier stage of the latch type) 2101 , a column transfer gate 2101 , which is made up of an NMOS transistor to output the data amplified by the sense amplifier to the local data bus, a bit line shortening / precharge circuit 2103 for shortening and precharging the bit lines, and a bit line transmission gate 2104 made up of NMOS transistors to support a shared sense amplifier method. Here, reference numerals BL and / BL denote the bit lines and CL denotes the column selection line.

The column transfer gate 2102 is from the column decoder 2012 in 140 selected and data from the selected sense amplifier 2100 are on the data buses ( 2001 . 2202 ; 2200 ' ) issued. I.e. the basic structure apart from the data bus amplifier 2300g of the PRD type is the same as that of an ordinary DRAM and is not specifically shown here, it is obvious that this method can be applied to similar DRAMs. Examples include a DRAM in which the data buses ( 2200 ' ) not specifically between the local data bus 2201 and the global data bus 2202 are divided.

145 FIG. 12 is a diagram showing an example of the operating waveform of the bus and the bus amplifier in the semiconductor memory device of FIG 140 shows. An example of a read operation with a burst length 8th (in blocks of eight bits: CL0 to CL7) is shown here.

As in 145 is shown, by sequentially outputting the column selection signals CL0 to CL7, read data as an output of the MUX 2330g (the output C of the data bus amplifier) obtained, the PRD amplifier 2310g and 2320g are operated in a nested manner by the control signals ϕ1 and ϕ2 (ϕ1 'and ϕ2').

In the eleventh embodiment, when there is no data on the data buses bus and / bus, the data buses are precharged, but it should be noted that a structure in which bus charging is not performed under any circumstances is as possible as in the first embodiment; in this case the shortening / pre-charging switch ( 2009 ) of the local data buses, the shortening / precharge switch of the global data buses, etc. can be omitted. It is also possible to selectively pre-load; z. For example, if the next reading is expected to start immediately, no precharge is performed, or precharge is performed by supplying an external bus precharge command, or precharge is performed only before a write operation to ensure correct operation of the write amplifier 2100 to ensure.

Furthermore, since the bus amplifier 2300g (the PRD amplifier 2310g and 2320g ) of the eleventh embodiment has a self-calibration function, data is detected and amplified even if the voltage change appearing on the data line is extremely small. In addition, as capacitors between the buses and the inputs of the current mirror amplifier ( 2303g ) are inserted in the bus amplifier, the inputs of the amplifier are set to levels which increase the sensitivity of the current mirror amplifier the most. This makes it possible to amplify even smaller changes in voltage. Here, if the buses were connected directly to the inputs, the inputs would always be kept at the bus potential and the amplifier could not always be operated in an area in which the current mirror amplifier has a high sensitivity. In the eleventh embodiment, substantially the same bus amplifier used in the eighth embodiment as the data bus amplifier ( 2300g ) are used, but instead the bus and bus amplifier structures described in each of the previously described embodiments (including the single bus case) can be used in the eleventh embodiment.

146 Fig. 12 is a block diagram showing, as a twelfth embodiment, in schematic form an example of a semiconductor memory device using the signal transmission device according to the fifth mode of the present invention.

The semiconductor memory device of the twelfth embodiment shown in 146 is substantially the same as the semiconductor memory device of FIG 140 shown eleventh embodiment, the only difference in the structure of the column decoder (column decoder arrangement) 2120 lies. The column decoder 2012 in the semiconductor memory device described above, just like in normal DRAMs, it is constructed so that it does not select the column transfer gates in an overlapping manner.

More specifically, a column transfer gate on a bus is selected and turned on and data from the sense amplifier 2100 are on the local data bus 2201 and the global data bus 2202 output and from the data bus amplifier 2300g strengthened. Bus precharging is then performed, but all column transfer gates must be closed before this time. The reason is that the bus is preloaded ( 2202 ) requires a finite time, the data in the sense amplifier 2100 be destroyed if the column transfer gates during precharge period are not closed.

However, when using the PRD method, there is no need to provide a period of time during which all column transfer gates are closed because the precharge period itself is eliminated. Furthermore, the nature of the PRD method allows the previous data to overlap with the next data; thus, before the transfer gate is closed in the previous cycle, the next transfer gate can be opened to output the next data on the data bus, without requiring the column transfer gate to be closed for one bit beforehand. In the twelfth embodiment, the above advantage becomes complete in the construction of the column decoder 2120 used.

147 FIG. 12 is a block diagram showing a structural example of the column decoder system in the semiconductor memory device of FIG 146 shows, and 148 FIG. 10 is a diagram illustrating an example of the operating waveform of the bus and the bus amplifier in the semiconductor memory device of FIG 146 shows.

In 147 denote the reference numerals 2120a and 2120b Column decoder (A and B) for two groups of columns (even and odd columns), 2121A and 2121b are column precoders (A and B) for the two groups of columns and 2122a and 2122b are column select line control pulse generators (CL pulse generators A and B) for the two groups of columns. The reference number 2123 identifies a clock signal generator (former).

As in 147 the column decoder system (the column decoder arrangement 2120 ) of the twelfth embodiment driven by two clocks (CLK and / CLK) and the first number of column decoders A ( 2120a ) driven by the positive logic clock CLK and the second number of column decoders B ( 2120b ), which are driven by the inverted logic clock / CLK, for example, are interleaved by the column precoders 2121A and 2121b driven to drive the column transfer gates at high speed while allowing a certain amount of overlap from one transfer gate to the next. Here is the column precoder 2121A a column address signal and a clock signal CLK for the even columns are supplied during the column precoder 2121b a column address signal and a clock / CLK for the odd columns are supplied. In the in 147 shown example, the complementary clock CLK and / CLK are fed directly from the outside; however if, for example, the clock generator 2123 using a PLL or the like, as shown by the dotted lines, by generating internally much more precise clocks CLK and / CLK from the clock CLK ', higher speed operation can be achieved.

By allowing the selection of the column transfer gates on overlapping Way, as described above, it becomes possible from a column transfer gate to the next within a shorter Switch time interval, which has the consequence that a data transmission with a much higher one Speed can be realized as if just the precharge time is eliminated. Furthermore, if the system is not specific is constructed so that it the overlap of sections of the column transfer gates allowed, since the PRD method inherently allows overlapping without problems, the System with a larger margin of time for the Columns transmission selection signal (CL).

As in 148 is shown, by sequentially outputting the column selection signals CL0 to CL7, read data as an output of the MUX 2330g (the output C of the data bus amplifier) received while the PRD amplifier 2310g and 2320g are driven in a nested manner by the control signals ϕ1 and ϕ2 (ϕ1 'and ϕ2').

Here, in the twelfth embodiment, if the time during which each column transfer gate is opened is made longer, that on the data buses ( 2201 and 2202 ) appearing potential to be increased in order to increase the operating margin. If the time during which the column transfer gate is opened is set approximately equal to that in the previous eleventh embodiment, the high-speed data transfer can be further increased.

149 Fig. 12 is a block diagram showing, as a thirteenth embodiment, in schematic form an example of a semiconductor memory device using the signal transmission device according to the fifth mode of the present invention.

The semiconductor memory device of the thirteenth embodiment shown in 149 shown has substantially the same structure as the semiconductor memory device of FIG 146 shown twelfth embodiment, except that in the thirteenth embodiment, a PMOS (P-channel MOS transistor) load 2413 for the global data bus ( 2202 ) is provided. More specifically, a PMOS transistor pulled to the high supply voltage (Vcc) side is for each of the complementary buses bus and / bus (the global data bus 2202 ) intended. Here, a predetermined load control signal V1L is applied to the gate of each PMOS transistor so that the load is only turned on when the data bus is used.

The thirteenth embodiment deals with the case where, if nothing is done, the entire bus potential (for both of the complementary buses) falls to the low level side, for example due to the properties of the NMOS transistor tors of the column transmission gate or because the push capability of the sense amplifier 2100 to the high level side is low. That is, in the case of a conventional bus system, since precharging is performed for each bit when the entire bus potential falls to the low level side, the potential is immediately returned to the precharging level (intermediate level); in the PRD method, on the other hand, since bus precharging is not performed for every bit, the entire bus potential falls on the low level side, for example. While it is true with the PRD method that data can be reconstructed if, for example, the bus is kept at the low level, the operating margin is nevertheless somewhat reduced.

150 FIG. 10 is a diagram for explaining how the data bus waveform depends on the presence or absence of the load in the semiconductor memory device of FIG 149 changes. The top part of the figure shows the waveform of the data bus ( 2202 ) when no load is provided and the other part shows the waveform of the data bus when the load 2413 is provided.

How out 150 can be seen, if the load is not provided, the entire potential of the bus (the global data bus 2202 ) to the low level side, but when the load 2413 the entire level of the bus (the global data bus 2202 ) kept at the intermediate level.

Here shows the burden 2413 for example approximately the same size as the PMOS transistor (P-channel MOS transistor) that is in the latch or latch ( 2101 ) in the sense amplifier 2100 (see 144 ) is used, and leads to a negligible increase in area. In this way, the provision of the load serves 2413 the operating scope of the bus amplifier 2300g ( 2300 ) to increase.

The 151A to 151i 14 are diagrams showing various examples of the load in the semiconductor memory device of FIG 149 demonstrate. As can be seen, not only loads of the PMOS type, but various other structures, such as those in the 151A to 151i , for the load 2413 be used.

The 151A relates to a structure in which as a load 2413 NMOS transistors pulled to the side (Vcc) of the supply voltage with a high level for the complementary buses bus and / bus (the global data bus 2202 ) are provided, and a predetermined load voltage (high level voltage) V2L is applied to the gate of each NMOS transistor. 151B shows a structure in which as the load 2413 Resistors connected to the high level supply voltage for which buses bus and / bus are provided while 151C represents a structure in which a PMOS transistor, the gate of which the activation signal / s is supplied, between the in 151B shown resistors and the supply voltage is inserted at the high level.

More specifically are in the structure of 151A the NMOS transistors pulled to the side (Vcc) of the supply voltage with the high level as the load 2413 for the complementary buses bus and / bus (the global data bus 2202 ) is provided and the predetermined load control signal (activation signal) V2L is applied to the gate of each NMOS transistor so that the load is turned on (connected) only when the data bus is used. In the in 151B The structures shown are the resistors associated with the high level supply voltage as the load 2413 provided for the buses bus and / bus while in the construction of 151C the PMOS transistor, the gate of which the activation signal / s is supplied, between the in 151B shown resistors and the supply voltage is inserted at the high level. That is, if PMOS or NMOS transistors as the load 2413 used, the load can be designed so that it is only switched on when the data bus is used; on the other hand, if resistors are used, a transistor (PMOS in the example shown) whose switching is controlled by a control signal should be provided, as in FIG 151C is shown.

The 151D to 151F relate to the case where the total bus potential (for both complementary buses) rises toward the high level side when nothing is done. In 151D are NMOS transistors pulled to the side (Vss) of the supply voltage at a lower level than the load 2413 is provided for the complementary buses bus and / bus, and a predetermined load control signal (activation signal) V3L is applied to the gate of each NMOS transistor, so that the load is switched on (connected) only when the data bus is used. In 151E are resistors connected to the supply voltage with the low level as a load 2413 intended for the buses bus and / bus while in 151F the NMOS transistors in 151D are replaced by PMOS transistors. Here, a predetermined load control signal (activation signal) V4L is applied to the gate of each PMOS transistor.

The 151G to 151i show examples in which the load is pulled to a potential (Vtt) different from the supply voltage with the high level and the supply voltage with the low level. In 151G are PMOS transistors pulled to the above-mentioned potential (Vtt) as the load 2413 intended for the complementary buses bus and / bus; in 151H NMOS transistors are provided; and in 151i transmission gates composed of PMOS and NMOS transistors are provided. Here V5L to V7L (/ V7L) identify control signals (activation signals) by which the load is only switched on (connected) when the data bus is used.

The 152 to 154 FIG. 14 show examples of the mounting positions of the load in the semiconductor memory device of the thirteenth embodiment using the signal transmission system according to the fifth mode of the present invention.

In addition to the in 149 shown construction, where only one load ( 2413 ) for each global data bus 2202 various other structures are possible; that is, several such loads can be spaced apart along the global data bus 2202 (see 152 ) can be provided, or can be on the side of the local data bus 2201 (see 153 ) can be provided, or the loads can be for the global data bus 2202 and the local data bus 2201 (see 154 ) be provided.

155 Fig. 12 is a block diagram showing, as a fourteenth embodiment, in schematic form an example of a semiconductor memory device in which the signal transmission device according to the fifth mode of the present invention is used. The fourteenth embodiment is substantially the same as the previous thirteenth embodiment except that the load 2413 is formed from a pair of PMOS transistors that are cross-connected with respect to the buses.

If the load 2413 is formed from a pair of PMOS transistors cross-connected with respect to the complementary buses bus and / bus, as in 155 is shown, in the complementary buses, the amount of movement toward the high level becomes larger than when a simple load is used, as in the thirteenth embodiment. Furthermore, in the case of the thirteenth embodiment ( 149 the bus potential, whether at a high level or at a low level, toward the high potential (high level) at a steady speed, but in the case of the fourteenth embodiment, the amount of movement toward the high level is reduced as the data bus moves in the direction of the low potential (low level). Specifically, the fourteenth embodiment not only prevents the data bus ( 2202 ) is held at a certain potential, but continues to provide an amplification effect to the bus drive capability of the sense amplifier ( 2100 ) to support. Accordingly, the operating margin can be increased further.

156 Fig. 12 is a diagram showing a comparison of the data bus waveforms when the load is provided according to the thirteenth and fourteenth embodiments using the signal transmission device according to the fifth mode of the present invention.

As from the comparison of the waveform of the thirteenth embodiment which is in the top part of 156 and the waveform of the fifteenth embodiment shown in the other part can be seen, the fourteenth embodiment can further increase the operating margin of the bus amplifier (the data bus amplifier 2300 of the PRD type).

In the in 155 Example shown it should be noted that an additional PMOS transistor, the gate of which an activation signal / s is provided, is provided to the load 2413 switch off when the data bus is not in use.

157 FIG. 12 is a diagram showing a modified example of the load to be used in the semiconductor memory device of FIG 155 suitable is.

In the fourteenth embodiment, if the data bus tends to shift to the high potential (high level) side, the cross-connected PMOS pair that the load in 155 is to be replaced by a cross-connected NMOS pair and the cross-connected NMOS pair should be pulled to the low potential (low level) side, as in 157 is shown. In the modified example of 157 it should also be noted that an additional NMOS transistor, the gate of which the activation signal en is supplied, is provided so that the load 2413 is switched off (is excluded) if the data bus is not used.

Regarding the mounting position of the load 2413 can also only one such load for the global data bus in the fourteenth embodiment 2202 or multiple such loads may be spaced along the global data bus 2202 be provided; alternatively, the load or loads can only be on the local data bus side 2201 for the global data bus 2202 and the local data bus 2201 be provided as before with reference to the 152 to 154 has been described.

158 Fig. 12 is a block diagram showing in schematic form, as a fifteenth embodiment, an example of a semiconductor memory device using the signal transmission device according to the fifth mode of the present invention. The semiconductor memory device of the fifteenth embodiment is substantially the same as that of the thirteenth embodiment shown in FIG 149 is shown, or of in 153 shown fourteenth embodiment, the only difference in the structure of the sense amplifier 2100 consists. The sense amplifier is more precisely said in the fifteenth embodiment 2100 built as a direct sense amplifier (gate receiving sense amplifier) which directly amplifies the levels of the bit lines and outputs them on two data buses (RDB, / RDB).

159 FIG. 11 is a circuit diagram showing an example of the sense amplifier used for the semiconductor memory device of FIG 158 suitable is. In 159 indicates the reference symbol 2103 a bit line precharge circuit, 2104 is a bit line transmission gate, 2105 is a read control circuit (sense amplifier stage), 2106 is a write control circuit, and 2107 is an interlock circuit. Furthermore, the reference symbol BTE denotes a bit line transmission activation signal, RDB and / RDB are read data buses, WDB and / WDB are write data buses, WE is a write activation signal, PLE and NLE are PMOS and NMOS lock activation signals, Vpr is a bit line Precharge level and PRE is a bit line precharge signal.

In the in 159 In contrast to the conventional locking type (for example that shown in 144 shown), the read control circuit 2105 Read data from the gates and outputs the data directly on the read data buses RDB and / RDB. With this arrangement, the data access time can be further reduced. There is no difference from the conventional gate-receiving sense amplifier in that the data access time is reduced, but it should be noted here that a further reduction in access time by using the gate-receiving read type sense amplifier stage (the read control circuit 2105 ), not the conventional lock-type sense amplifier (for example, that shown in 144 shown), can be achieved in combination with the bus of the PRD type.

In the bus system in which the PRD process is used exists when the potentials of the complementary buses yourself completely at a high level "H" and a low one Level "L" if the data in the sense amplifier and the data on the buses are opposite to each other, at worst If there is a risk that the Data in the sense amplifier inverted (destroyed) be when the time while the column transmission device is open, longer as a certain time. That puts a limit on the time while which is the column transfer system open can be if the conventional amplifier of the lock type is used. It is of course possible to solve this problem in the Avoid locking type by optimizing the structure, however if the sense amplifier of the gate-receiving read type (direct sense amplifier) is used, as in the fifteenth Embodiment, can, since the data in the sense amplifier by the potentials of the Data buses (RDB, / RDB) remain relatively unaffected, not just one higher Speed can be achieved, but also the operating and Construction leeway can be improved dramatically. For An example of a direct sense amplifier becomes reference, for example taken on G. Kitsukawa et. al., "A 23-ns 1-Mb BiCMOS DRAM", IEEE Journal of Solid State Circuits, Vol. 25, No. October 5, 1990.

160 FIG. 11 is a waveform diagram for explaining an example of the operation of the semiconductor memory device of FIG 158 ,

The waveform diagram of 160 relates to a read operation with a burst length 8th (in blocks of eight bits: CL0 to CL7) showing the case where the precharge level (Vpr) of the bus (RDB, / RDB) is set to a high level "H" (Vcc). By increasing the bus precharge level, as shown, the bus drive capability of the gate receiving NMOS sense amplifier can be increased. In this case it is advantageous to use a lower load.

161 FIG. 11 is a waveform diagram for explaining another example of the operation of the semiconductor memory device of FIG 158 ,

The waveform diagram of 161 relates to a read operation with a burst length 16 (in blocks of sixteen bits: CL0 to CL7) showing the case where the bus precharge level is set to an intermediate level between the high level "H" and a low level "H" but closer to the high level. In this case the load capacity is compared to the case of 160 elevated.

In the fifteenth embodiment uses a gate receiving NMOS sense amplifier, but instead a gate receiving PMOS sense amplifier can be used.

162 Fig. 12 is a circuit diagram showing the structure of an essential part of a semiconductor memory device to which the signal transmission device according to the fifth mode of the present invention is applied as a sixteenth embodiment.

As in 162 is shown, in the sixteenth embodiment, the gate receiving NMOS sense amplifier stage (the read control circuit 2105 ) of the fifteenth embodiment, which in 159 is shown by a gate receiving sense amplifier stage (read control circuit 2105 ' ) replaced. Otherwise, the structure is the same as that of the fifteenth embodiment. When the direct sense amplifier is used in combination with the PRD method, the CMOS structure is for the read control circuit 2105 ' preferable from the operational point of view, although the circuit area required is increased.

163 Fig. 12 is a block diagram showing, as a seventeenth embodiment, in schematic form an example of a semiconductor memory device using the signal transmission device according to the fifth mode of the present invention.

The seventeenth embodiment has substantially the same structure as the previously described fourteenth embodiment of FIG 155 , except that unlike the fourteenth Embodiment not the buses between the local data bus 2201 and the global data bus 2202 are divided and the write amplifier 2010 and the bus amplifier (data bus amplifier of the PRD type) 2300 for every data bus 2200 are provided. Furthermore, the burden 2413 and the data bus precharge circuit 2402 also for every data bus 2200 intended.

More specifically, each data bus amplifier receives and amplifies 2300 of the PRD type directly data transmitted from the column transfer gates. The data bus amplifier used here 2300 of the PRD type is the same as that used in the fourteenth embodiment.

164 FIG. 10 is a diagram illustrating an example of the operating waveform of the bus and the bus amplifier in the semiconductor memory device of FIG 163 shows, and 165 FIG. 12 is a diagram showing another example of the operating waveform of the bus and the bus amplifier in the semiconductor memory device of FIG 163 shows.

As in 164 can be shown in the seventeenth embodiment since the data bus 2200 not as a long bus, such as local and global data buses ( 2201 and 2202 ) is formed, that is, since the length of the data bus 2200 is lower, the bus amplitude is made higher and the operating margin is thus increased. That is, when the column selection cycle time is reduced and the bus amplitude level is set approximately equal to that in the fourteenth embodiment shown in FIG 165 is shown, even a higher transmission rate can be achieved.

This effect of the seventeenth embodiment is not obtained because the buses that are between the local data bus ( 2201 ) and the global data bus ( 2202 ) were divided into a data bus 2200 are combined. However, it should be noted that even in the case where data buses are organized in a hierarchical manner, for example, a similar effect can be obtained if the total bus length is reduced to reduce the bus time constant.

Generally, in a semiconductor memory device, whether it is of the PRD type or another type, data from sense amplifiers the local data bus and the local data bus (in some configurations there are no local data buses) and fed into the data bus amplifier, arranged at the end of the memory array (memory cell array) is amplified to become. If the unit size of the memory array is great the difference in the distance between the sense amplifier and the bus amplifier becomes dependent on the position of the sense amplifier considerably. As a result, there is a difference in the time between the Moment when the column transfer gate open will pass until the data arrives at the bus amplifier. More specifically, in an establishment where the difference in the time it takes for the data to arrive at the data bus amplifier, big in Regarding the data transfer rate is, in the case of the PRD process, the risk of a faulty Operation takes place because the bus amplifier is operated by the clock becomes. Thus, if the data time shift is due to the sense amplifier position can be eliminated, the high achieved by the PRD process Operating frequency further increased become. In this regard, this relates to what is described below eighteenth embodiment the structure and mode of operation of a memory arrangement (semiconductor memory arrangement), which compensates for the data step shift.

166 Fig. 12 is a block diagram showing, as the eighteenth embodiment, in schematic form the construction of an essential part of a semiconductor memory device to which the signal transmission device according to the fifth mode of the present invention is applied. In 166 denotes the reference symbol 2002a a main word decoder, 2002b is a subword decoder, 2100 is a sense amplifier arrangement, 2201 is a local data bus pair, 2202 is a global data bus pair, and 2300 is a data bus amplifier (data bus amplifier of the PRD type).

In the 166 The semiconductor memory device shown is part of a 32 Mbit memory cell arrangement (a 16 Mbit (16M) block that forms half of the memory cell arrangement is shown). The 16M block is divided into eight smaller blocks (2M per block) in the row direction (X direction: vertical direction). Here, each 2M block includes memory cell arrays 2001 , Subword decoder arrangements 2002b , Read-only memory arrangements 2100 , local data buses 2201 , global data buses 2202 etc. and a bus amplifier 2300 is for every global data bus 2202 intended. Every data bus ( 2201 . 2202 ) is a bus of the PRD type and the data bus amplifier 2300 is also a PRD-type bus amplifier.

167 FIG. 12 is a diagram showing an example of the bus amplifier in the semiconductor memory device of FIG 166 shows, 168 FIG. 10 is a circuit diagram showing an example of the PRD amplifier structure in the bus amplifier of FIG 167 shows, and 169 FIG. 10 is a circuit diagram showing an example of a multiplexer in the bus amplifier of FIG 167 shows. Here they correspond 167 to 169 those previously shown in connection with the eleventh embodiment 141 to 143 ,

170 Fig. 12 is a block diagram showing a structural example of a column decoder system in the semiconductor memory device of the eighteenth embodiment, in which the signal transmission device according to the fifth mode of the present invention is used.

In 170 denote the reference numerals 2120a and 2120b Column decoder (A and B) for two groups of columns (even and odd columns), 2121A and 2121b are column precoders (A and B) for the two groups of columns, and 2122a ' and 2122b ' are column select line control pulse generation circuits with a delay setting function (CL pulse generation circuits A and B with a delay setting function) for the two groups of columns. The reference number 2123 identifies a clock signal generator (shaper).

As in 170 the column decoder system (the column decoder arrangement 2120 ) of the eighteenth embodiment driven by two clocks (CLK, and / CLK), and the first number of column decoders A ( 2120a ), which is driven by the positive logic clock CLK and the second number of column decoders B ( 2120b ), which are driven by the inverted logic clock / CLK, for example, are interleaved by the column precoders 2121A and 2121b driven to drive the column transfer gates at high speed while allowing a certain amount of overlap from one column transfer gate to the next. Here is the column precoder 2121A a column address signal and a clock CLK for the even columns are supplied during the column precoder 2121b a column address signal and a clock / CLK for the odd columns are supplied.

More specifically, a signal with decoded column addresses and a column pulse signal are sent to the column decoders 2120a and 2120b and after an address is established, a column pulse (column select line control pulse CL) is supplied with which the column transfer gate operates in synchronism. On the other hand, the clock (CLK) and a row address of the RAS type (precoded address signal) are given to the CL pulse generating circuits with a delay setting function, 2122a ' and 2122b ' , fed. The precoded address signal is a row address signal (3 bits) for specifying one of the eight blocks. In the example shown, a 3-bit pre-encoded signal is input as the row address signal, but the row address signal is not limited to this particular type; the only requirement is to input a RAS type address signal that can select a block.

In the in 170 shown example, the complementary clocks CLK and / CLK are fed directly from the outside; if, for example, the clock generator 2123 using a PLL or the like, as shown by the dotted lines, higher-speed operation can be achieved by internally generating much sharper clocks CLK and / CLK from the clock CLK '.

171 FIG. 12 is a diagram showing an example of the CL pulse generation circuit (CL pulse generation circuits with a delay setting function, 2122a ' and 2122b ' ) in 170 shows.

As in 171 is shown, the CL pulse generation circuit with a delay setting circuit, 2122a ' ( 2122b ' ) of the eighth embodiment is constructed so that the capacitance of the capacitor provided on the side of each source of each NMOS is varied according to the precoded RAS address (C0>C1>...> C7) to add a column pulse (column select line control pulse CL) generate so that the pulse rises earlier than the distance from the data bus amplifier ( 2300 ) increases. That is, the CL pulse generation circuit 2122a ' generates the column pulse CL so that a column transfer gate farther away from the data bus amplifier is activated earlier, in other words, the time to transfer data from the sense amplifier 2100 on the data bus ( 2201 . 2202 ) is pushed forward when the distance from the arrangement 2001 to the data bus amplifier 2300 elevated.

Here if the CL pulse generation circuit is constructed so that it the CL pulse at the same time regardless of the distance from the CL pulse generating circuit and the data bus amplifier generates the control signals used in the data bus amplifier (ϕ1, ϕ2) for Sense amplifier, the closer to the column selection signal generating circuit and the data bus amplifier are to an earlier one Point in time, and for Sense amplifier, which are further away from the column selection signal generation circuit and the data bus amplifier are arranged to a later Point in time are generated, and the control signals can too an appropriate time to be determined when the incoming Data take effect (for example, on a rear section of the Bit time).

172 FIG. 12 is a diagram for explaining the operation of the CL pulse generation circuit (CL pulse generation circuit with a delay setting function) shown in FIG 171 is shown.

Data (read data) move along the local data bus 2201 and the global data bus 2202 and come to the data bus amplifier 2300 ( 2300g ) on. The time required for that from an array (memory cell array 2001 ) read data to the data bus amplifier 2300 arriving increases as the distance from the device to the data bus amplifier increases.

Thus, the CL pulse generation circuit generates 2122a ' ( 2122b ' ) such a column pulse CL, which is used for memory arrangements which are further away from the data bus amplifier 2300 are arranged as in 172 shown increases earlier, thereby ensuring that data read from any arrangement is at the same time in the data bus amplifier 2300 arrive. Genauerge is said in the CL pulse generation circuits with a delay setting function, 2122a ' and 2122b ' , the pulse rise time is controlled such that the sum of the delay by the data bus and the delay by the signal line driving the column transfer gate is shifted. This enables data to always be sent to the data bus amplifier at the same time 2300 arrive and thus a constant data decision period can always be maintained. Since the PRD-type bus amplifier is operated by the clock, erroneous operation of the amplifier in a high-speed operation can be prevented by ensuring that data always arrive at the same time. With this method, the memory bus of the PRD type can be operated at a higher speed at a higher level.

In the example above is the 32M block in eight blocks divided in the row direction, but of course the number of blocks does not have to necessarily be limited to that particular number, nor is the storage capacity to any certain capacity limited. Furthermore, the rise time of the column pulse signal (CL) can be used as an alternative method. according to the distance of the line block from the data bus amplifier or be delayed when the distance of the block from the data bus amplifier decreases. In the example above, each local data bus is on one Length set, that he there is no time difference on the local data bus.

173 FIG. 10 is a diagram showing another example of the bus amplifier in the semiconductor memory device of FIG 166 shows, 174 FIG. 10 is a circuit diagram showing an example of the PRD amplifier structure in the bus amplifier of FIG 173 shows and 175 FIG. 10 is a circuit diagram showing an example of latching in the bus amplifier of FIG 173 shows. Here they correspond 173 to 175 those previously shown in connection with the ninth embodiment 129 to 131 ,

When the structure of the previously described ninth embodiment is applied, data transfer at a higher speed than that of the prior art semiconductor memory device can also be achieved, although the transfer rate is lower than that in the above 167 to 169 shown bus amplifier. On the other hand, if the structure of the bus amplifier (the data bus amplifier 2300e of the PRD type), which in the 173 to 175 is applied, the advantage that the circuit area compared to that in 167 to 169 shown bus amplifier ( 2300g ) can be reduced.

176 Fig. 12 is a block diagram showing another structural example of the column decoder system in the semiconductor memory device of the eighteenth embodiment to which the signal transmission device according to the fifth mode of the present invention is applied.

As from the comparison between the 176 and 170 can be seen, indicates in 176 shown column decoder system no nesting, but the column decoder 2120 is operated by the clock (the positive logic clock CLK). As already explained in the 170 mentioned, the clock generator can be made using a PLL or the like as shown by the dotted lines in FIG 176 shown, can be provided, in which case an even sharper clock CLK can be generated internally from the clock CLK '.

177 FIG. 12 is a block diagram showing in schematic form the structure of an essential portion of a semiconductor memory device to which the signal transmission device according to the fifth mode of the present invention is applied as a nineteenth embodiment, and FIG 178 FIG. 12 is a diagram showing an example of the CL pulse generation circuit used for the semiconductor memory device of FIG 177 suitable is. Here they correspond 177 and 178 the 166 and 171 illustrating the eighteenth embodiment described above.

As in 177 is shown, in the nineteenth embodiment, the 16M memory cell array (memory array) block is divided into four smaller blocks in the row direction (X direction: vertical direction). Otherwise, the structure is the same as that of the eighteenth embodiment.

However, as in 178 is shown, the delay values in the CL pulse generating circuit (CL pulse generating circuits with a delay setting function, 2122a ' and 2122b ' ), not by varying the capacitance of the capacitor provided on the source side of each NMOS transistor, but by the number of cascaded delay stages (NAND gate / inverter delay units) which are arranged to have a column pulse (column select line Control pulse CL) in such a way that the pulse for memory arrangements which are further away from the data bus amplifier ( 2300 ) are arranged, rises earlier. It is needless to say that the delay stage structure can be modified in various ways.

Although each embodiment is in the fifth mode of the present invention applied to a semiconductor memory device (DRAM) it has been described that the application of the device to transfer one Signal to the present invention is not limited to a DRAM.

Claims (75)

Device for transmitting a signal between several circuit blocks ( 7-0 . 7-1 . 7-2 . 7-3 . 7-4 to r ) via a signal transmission line ( 703 ), characterized in that the device for transmitting a signal comprises a clock distribution unit ( 707 ) to distribute a reference clock (clk) to each circuit block ( 7-0 . 7-1 . 7-2 . 7-4 to 7-n ) via a clock line ( 706 ), a generation unit ( 611 . 621 ; 711 ; 1300 ) to create a common clock (GMT) based on the reference clock (clk) for each of the circuit blocks ( 7-0 . 7-1 . 7-2 . 7-3 . 7-4 to 7-n ) with a clock accuracy (GMT) that is shorter than the time it takes the signal to cross the lines between the circuit blocks ( 7-0 . 7-1 . 7-2 . 7-3 . 7-4 to 7-n ) and one unit ( 612 . 613 . 614 . 622 . 623 . 624 ; 710 ) for sending and receiving the signal in synchronization with the common clock. Device for transmitting a signal according to claim 1, characterized in that each of the circuit blocks ( 7-0 . 7-1 . 7-2 . 7-3 . 7-4 to 7-n ) is an integrated circuit module, an integrated circuit chip or a subcircuit within a single chip. Device for transmitting a signal according to claim 1, characterized in that the maximum length of the signal transmission line ( 703 ) is not greater than the distance that the signal has along the signal transmission line in a bit time period (TT) ( 703 ) covered. Device for transmitting a signal according to claim 3, characterized in that the maximum length of the signal transmission line ( 703 ) is not greater than half the distance that the signal has along the signal transmission line in a bit time period (TT) ( 703 ) back. Device for transmitting a signal according to claim 3, characterized in that in the signal transmission line ( 703 ) a memory ( 708 ) is inserted to delay the signal with a time period equal to an integer multiple of a bit time period (TT) of the signal and to retransmit the delayed signal, whereby the memory ( 708 ) allows the signal to be transmitted over a distance that is the maximum length of the signal transmission line ( 703 ) exceeds. Device for transmitting a signal according to claim 5, characterized in that the memory ( 708 ) to other circuit blocks ( 7-1 ' . 7-2 ' . 7-3 ' . 7-4 ' to 7-n ' ) with the memory ( 708 ) outputs a reference clock (clk) that the other circuit blocks ( 7-1 ' . 7-2 ' . 7-3 ' . 7-4 ' to 7-n ' ) to generate a common clock (GMT). Device for transmitting a signal according to claim 1, characterized in that the signal transmission line ( 703 ) is a bus of the conventional signal line type and has a terminating resistor at one end or at both ends of the bus ( 701 . 702 ) is provided, which has a resistance that is approximately equal to or greater than the characteristic impedance of the bus. Device for transmitting a signal according to claim 1, characterized in that a driver circuit ( 781 ) to control the signal transmission line ( 703 ) has an output impedance that is greater than the characteristic impedance of the signal transmission line ( 703 ) is. Device for transmitting a signal according to claim 8th , characterized in that the driver circuit ( 781 ) generates a DC driver output signal. Device for transmitting a signal according to claim 1, characterized in that the generating unit ( 611 . 621 ; 711 ; 1300 ) for the common clock (GMT) takes clocks (ϕ1, ϕ2) along a clock line ( 706 ) running between a clock line section ( 706a ) for a forward moving clock (ϕ1) and a clock line section ( 706b ) is folded for a backward moving clock (ϕ2), and generates a common clock (GMT) by determining a time between the rising edges of the forward moving clock (ϕ1) and the backward moving clock (ϕ2), which from each circuit block ( 7-0 . 7-1 . 7-2 . 7-3 . 7-4 to 7-n ) Will be received. Device for transmitting a signal according to claim 10, characterized in that the generating unit ( 711 ) for the common clock (GMT) a linear sum generation unit ( 720 . 730 ) for generating a linear sum of sinusoidal clocks in the clock line section ( 706a ) for the forward moving clock (ϕ1) and in the clock line section ( 706b ) for the backward moving clock (ϕ2) of the folded clock line ( 706 ) and a waveform shaping unit ( 740 . 750 ) for waveform shaping of the sinusoidal signals generated by the linear sum generating unit ( 720 . 730 ) are obtained. Device for transmitting a signal according to claim 10, characterized in that the generating unit ( 711 ) for the common clock (GMT) a phase interpolator ( 711a ) for recording the moving clock (ϕ1) and the backward moving clock (ϕ2) on the folded clock line ( 706 ) and to generate a clock (GMT) which has a phase between the forward and the backward moving clock. Device for transmitting a signal according to claim 1, characterized in that a generating unit ( 705 ) for the reference clock (clk) a standing wave along the clock line ( 706 ) and each of the circuit blocks ( 7-0 . 7-1 . 7-2 . 7-3 . 7-4 to 7-n ) takes the reference clock (clk) from the standing wave that runs along the clock line ( 706 ) is produced. Device for transmitting a signal according to claim 13, characterized in that a generating unit ( 760 ) to generate the standing wave along the clock line ( 706 ) an educational unit ( 761 . 762 ) in order to actively receive a reflected signal of the reference clock (clk) either in a clock control circuit ( 761 ) or in a clock termination circuit ( 762 ) or in both, creating an electrical length of the clock line ( 706 ) is set. Device for transmitting a signal according to Claim 1, characterized in that the cycle time (T) of the clock (Clk) used to generate the common clock (GMT) is greater than twice the length of a bit period (TT) of the signal sent along the signal transmission line ( 703 ) is transmitted. Device for transmitting a signal according to claim 1, characterized in that the clock line ( 706 ) has a transmission characteristic that is substantially different from that of the signal transmission line ( 703 ), and with increased electrical shielding ( 7061 ) against an external environment in comparison to the signal transmission line ( 703 ) is provided. Device for transmitting a signal according to claim 1, characterized in that at least one of the circuit blocks ( 7-0 . 7-1 . 7-2 . 7-3 . 7-4 to 7-n ) on a receiving side with a receiver circuit ( 613 . 622 . 623 ) for eliminating intersymbol interference components from the signal and this is provided via the signal transmission line ( 703 ) receives the transmitted signal. Device for transmitting a signal according to claim 17, characterized in that the receiver circuit ( 613 . 622 . 623 ) a circuit ( 40 ; 500 ) for signal correction of past signal components and a signal logic decision circuit ( 42 ) to make a logical decision regarding the circuit ( 40 ; 500 ) apply to the signal processing processed signal. Device for transmitting a signal according to claim 18, characterized in that the circuit ( 40 ; 500 ) an intersymbol interference estimation unit for signal cleaning ( 50 ; 540 ) for estimating inter-symbol interference components on the basis of the signal received in the past and a subtracting unit ( 41 ; 541 ) for subtracting the estimated intersymbol interference component from a signal currently received. Device for transmitting a signal according to claim 19, characterized in that the intermediate symbol reference estimation unit ( 50 ; 540 ) is constructed in such a way that it determines a sum of linear weightings from previous decision values. Device for transmitting a signal according to claim 10, characterized in that the inter-symbol interference estimation unit ( 50 ; 540 ) a shift register ( 43 ; 543 ) for holding previous bit information and a weighting unit ( 45 ; 45 '; 55 ' ) for weighting in the shift register ( 43 ; 543 ) data held. Device for transmitting a signal according to claim 21, characterized in that the weighting unit ( 45 ) from several resistors ( 451 . 452 . 453 . 454 ) is constructed. Device for transmitting a signal according to claim 21, characterized in that the weighting unit ( 43 ; 55 ' ) from several capacitors ( 451 ' . 452 ' . 453 ' . 454 '; 551 . 552 . 553 . 554 ) and switches ( 461 . 462 . 463 . 464 ) is constructed. Device for transmitting a signal according to claim 19, characterized in that the inter-symbol interference estimation unit ( 50 . 540 ) is constructed in such a way that it determines non-linear weightings from previous decision values. Device for transmitting a signal according to claim 24, characterized in that the inter-symbol interference estimation unit ( 50 ) a shift register ( 43 ) for holding previous bit information and a storage unit ( 48 ) to store estimates that are in the shift register ( 43 ) correspond to held data. A device for transmitting a signal according to claim 23, characterized in that the intersymbol interference estimation unit is an accumulation unit for accumulating a Analog value of the received signal in the past and an inter-symbol interference generating unit for generating an inter-symbol interference component from the analog value. Transfer device of a signal according to claim 26, characterized in that the Inter-symbol interference estimator is constructed to be a linearly weighted sum of an analog value a signal that was received a sampling time earlier, and a fixed analog reference value is calculated. Transfer device of a signal according to claim 27, characterized in that the Inter-symbol interference estimator provided with several switch units and capacitor units is. Device for transmitting a signal according to claim 1, characterized in that the generating unit ( 611 . 621 ; 711 ; 1300 ) for the common clock receives a forward-moving clock (ϕ1) and a backward-moving clock (ϕ2) which run along a clock line section ( 706a ) for a forward moving clock and a clock line section ( 706b ) run for a backward-moving clock, and the common clock (GMT) by recording a time between the rising and falling edges of the forward-moving clock (ϕ1) and the backward-moving clock (ϕ2) generated by each circuit block ( 7-0 . 7-1 . 7-2 . 7-3 . 7-4 , to 7-n ) is recorded. A device for transmitting a signal according to claim 29, characterized in that at least one pair of clock generating circuits ( 1100 . 1200 ) including a generating circuit ( 1100 ) for a forward moving clock (ϕ1) and a generating circuit ( 1200 ) for a backward moving clock (ϕ2) for each pair of clock line sections ( 706a . 706b ) including the clock line section ( 706a ) for the forward moving clock (ϕ1) and the clock line section ( 706b ) are provided for the backward moving clock (ϕ2) and the clock line section ( 706a ) for the advancing clock (ϕ1) and the clock line section ( 706b ) for the backward clock (ϕ2), the phases of only the rising and falling edges of the forward and backward clocks (ϕ1, ϕ2) are set to set the phases to a predetermined value. Device for transmitting a signal according to claim 30, characterized in that the generating circuit ( 1100 ) one unit for the forward moving clock (ϕ1) ( 1106 ) for synchronizing the clock of an intermediate phase signal (ϕ _M ), which is obtained by defining a between the rising or falling edges of the forward moving clock (ϕ1) and the backward moving clock (ϕ2), with the rising and falling edge of a reference clock (clk), one unit ( 1104 ) to detect a phase difference (δclk) between the interphase signal (ϕ _M ) and the reference clock (clk) and one unit ( 1105 ) for setting the phase of the forward-moving clock (ϕ1) so that the detected phase difference (δclk) becomes zero. Device for transmitting a signal according to claim 30, characterized in that a plurality of clock generation circuits ( 1211 . 1212 . 1213 to 121n ) for each pair of clock line sections ( 706a . 706b ; 1011 . 1021 . 1012 . 1022 to 101n . 102n ) are provided for the forward moving clock (ϕ1) and for the backward moving clock (ϕ2) and the clock generating circuit ( 1211 . 121n ) located at each end of the pair of clock line sections ( 706a ; 1011 . 1012 to 101n) for the advancing clock (ϕ1) and clock line sections ( 706b ; 1021 . 1022 to 102n ) for the backward moving clock (ϕ2), only one generation circuit ( 1100 ) for a forward moving clock (ϕ1) or a generating circuit ( 1200 ) for a backward moving clock (ϕ2) and each clock generating circuit ( 1212 to 121 (n-1) ) located at intermediate positions along the clock line section ( 706a ; 1011 . 1012 to 101n ) for the advancing clock (ϕ1) and the clock line section ( 706b ; 1021 . 1022 to 102n ) for the backward moving clock (ϕ2), a generation circuit ( 1200 ) for a backward clock (ϕ2) that generates a backward clock (ϕ2) based on a forward clock (ϕ1) that is generated by the clock generation circuit ( 1211 to 121 (n-2) ) of the previous stage, and a generating circuit ( 1100 ) for a advancing clock (ϕ1) which includes a new advancing clock (ϕ1) for the clock generating circuit ( 1213 to 121n ) generated in the next stage. Device for transmitting a signal according to claim 32, characterized in that each of the clock generating circuits ( 1120 . 1121 . 1122 ) a memory for controlling a signal line ( 1030 . 1031 . 1032 ) signal supplied. Device for transmitting a signal according to claim 32, characterized in that the signal line ( 1031 ) which the circuit blocks ( 10-11 to 10-1m to 10-21 to 10-2m to 10-31 ) connects, is a point-to-point connection and that Clock generation circuits ( 1211 . 1212 . 1213 ) each for one or more of the circuit blocks ( 10-11 to 10-1m to 10-21 to 10-2m to 10-31 ) are provided. Device for transmitting a signal according to claim 30, characterized in that the generating circuit ( 1200 ) for the backward moving clock (ϕ2) from a feedback loop ( 1238 ; 1247 ) is constructed, which performs a phase adjustment in order to maintain a constant phase difference (δ empf) between the received forward clock (ϕ1) and backward clock (ϕ2). Device for transmitting a signal according to claim 30, characterized in that the generating circuit ( 1200 ) for the backward moving clock (ϕ2) from a variable delay unit ( 1240 ), a feedback loop ( 1247 ) for synchronizing a delay quantity (τ) in the variable delay unit ( 1240 ) with one cycle clock (T) and one unit ( 1246 ) for transferring a delay quantity (τ), which is proportional to the cycle clock (T), to the advancing clock (ϕ1) by a delay unit ( 1240 ) subordinate to the feedback loop ( 1247 ) is controlled. Device for transmitting a signal according to claim 36, characterized in that the variable delay unit ( 1240 ) several variable delay circuits ( 1241 . 1242 . 1243 . 1244 ) in cascade, with the feedback loop ( 1247 ) the delay quantity (τ) in each of the variable delay circuits ( 1241 . 1242 . 1243 . 1244 ) controls with the same value and the backward moving clock (ϕ2) from a certain node along the variable delay circuits ( 1241 . 1242 . 1243 . 1244 ) is removed. A signal transmission device according to claim 29, characterized in that the phase of the backward clock (ϕ2) is controlled such that the phase difference (δϕ) between the forward clock (ϕ1) and an inverted version of the backward clock Clock (ϕ2) in each of the circuit blocks ( 7-0 . 7-1 . 7-2 . 7-3 . 7-4 to 7-n ) that receive the forward-moving clock (ϕ1) and the backward-moving clock (ϕ2) is within ± 180 degrees. A signal transmission device according to claim 38, characterized in that the phase of the reverse clock (ϕ2) is controlled such that the phase difference (δϕ) between the forward clock (ϕ1) and an inverted version of the reverse clock Clock (ϕ2) in each of the circuit blocks ( 7-0 . 7-1 . 7-2 . 7-3 . 7-4 to 7-n ) receiving the forward clock (ϕ1) and the backward clock (ϕ2) is within ± 90 degrees. Transfer device of a signal according to claim 29, characterized in that the moving backwards Clock (ϕ2) an inverted version of the moving forward Is (ϕ1). Transfer device of a signal according to claim 29, characterized in that the yourself forward moving clock (ϕ1) and the backwards moving clock (ϕ2) each have a waveform, the rising and falling edges of which represent a significant range of the clock cycle (T). Transfer device of a signal according to claim 41, characterized in that the yourself forward moving clock (ϕ1) and the backwards moving clock (ϕ2) each a sinusoidal, triangular or trapezoidal Have a waveform. Device for transmitting a signal according to claim 41, characterized in that the generating circuit ( 1300 ) a differential comparator for the common clock (GMT) ( 1308 ) to which the forward-moving clock (ϕ1) and the backward-moving clock (ϕ2) are supplied as differential inputs. Device for transmitting a signal according to claim 29, characterized in that the terminating ends of the clock line sections ( 706a ; 1001 ) for the forward moving clock (ϕ1) and the clock line sections ( 706b ; 1002 ) for the backward moving clock (ϕ2) each with an impedance ( 1501 . 1502 ) which are greater than the characteristic impedance of the clock line section ( 706a ; 1001 ) for the advancing clock (ϕ1) and the clock line section ( 706b ; 1002 ) for the backward moving clock (ϕ2). Transfer device of a signal according to claim 29, characterized in that at least the forward moving clock (ϕ1) or the backwards moving clock (ϕ2) transmitted using a differential signal transmission method becomes. Device for transmitting a signal according to claim 45, characterized in that the forward moving clock (ϕ1) is transmitted as a complementary signal and the backward moving clock (ϕ2) is generated from a signal, which is generated by differential amplification of the complementary, forward-moving clock (ϕ1). Device for transmitting a signal according to claim 29, characterized in that the advancing clock (ϕ1) and the backward moving clock (ϕ2) by introducing a delay quantity (τ) which is different from that caused by a feedback loop ( 1247 ) controlled variable delay circuit ( 1240 ) is generated, generated in a reference clock (clk) in a free-running state. Device for transmitting a signal according to claim 29 , characterized in that when the forward-moving clock (ϕ1) and the backward-moving clock (ϕ2) are recorded, a signal which has already been output outside of a chip is again input into the chip as the forward-moving clock (ϕ1) and the common clock (GMT) is generated from it. Device for transmitting a signal with a signal transmission line ( 2200 ) that transmits data without precharge for each bit by eliminating an intersymbol interference component introduced from data received in the past, and a unit ( 2300 ) for eliminating an intersymbol interference component of a signal which is transmitted by means of the signal transmission line ( 2200 ) is transmitted. Device for transmitting a signal according to claim 49, characterized in that the signal transmission line ( 2200 ) as a single signal line ( 2200 ) is designed. Device for transmitting a signal according to claim 49, characterized in that the signal transmission line ( 2200 ) as a complementary signal bus ( 2200 ' ) and the device for transmitting a signal is a complementary signal bus driver ( 2100 ' ) and a complementary signal bus amplifier ( 2300 ' ) having. Device for transmitting a signal according to claim 51, characterized in that the device for transmitting a signal further comprises a precharge circuit ( 2400 ) which the signal transmission line ( 2200 ) does not charge for each bit during a data transmission period and which the signal transmission line ( 2200 ) charges to a certain potential level except during the data transmission period. Device for transmitting a signal according to claim 52, characterized in that the precharge circuit ( 2400 ) the signal transmission line ( 2200 ) charges only during a predetermined period before and after the data transfer period. Device for transmitting a signal according to claim 52, characterized in that the precharge circuit ( 2400 ) the signal transmission line ( 2200 ) charges during all periods except the data transfer period. Device for transmitting a signal according to claim 52, characterized in that the precharge circuit ( 2400 ) the signal transmission line ( 2200 ) charges arbitrarily from the outside. Device for transmitting a signal according to claim 51, characterized in that the complementary signal bus amplifier ( 2300 ' ) one amplifier each ( 2310 . 2320 ) with an intersymbol interference elimination function for a single signal line ( 2200 ), each one of the two complementary signals of the complementary signal bus ( 2200 ' ) are assigned, and a complementary signal differential amplifier ( 2330 ), the downstream of the two amplifiers ( 2310 . 2320 ) is provided with the intersymbol interference eliminating function. Device for transmitting a signal according to claim 56, characterized in that the complementary signal differential amplifier ( 2300 ' ) as differential amplifier with memory function ( 2330 ) is executed. Device for transmitting a signal according to claim 57, characterized in that the differential amplifier with memory function ( 2330 ) is designed as a gate-receiving differential amplifier. Device for transmitting a signal according to claim 56, characterized in that the complementary signal differential amplifier ( 2300 ' ) as a current mirror differential amplifier ( 2340 ) is executed. Device for transmitting a signal according to claim 51, characterized in that the complementary signal bus amplifier ( 2300 ' ) a differential amplifier ( 2303 ) with a first and second gate receiving amplifier input, an amplifier precharge circuit ( 2302 ) connected to each of the first and second inputs of the differential amplifier ( 2303 ) is provided to the differential amplifier ( 2303 ) in order to increase his sensitivity, and two sentences ( 2310a . 2310b ) of first capacitors (C10a, C10b) and second capacitors (C20a, C20b), which are connected to the first and second inputs of the differential amplifier ( 2303 ) are provided the first and second inputs of the differential amplifier with the complementary signal bus ( 2200 ' ) is coupled via the first capacitor (C10a, C10b) and second capacitor (C20a, C20b) and in each set ( 2310a . 2310b ) of capacitors the first capacitor (C10a, C10b) at any time with one of the complementary signals of the complementary signal bus ( 2200 ' ), whereas the second capacitor (C20a, C20b) is selectively connected to one of the other complementary signals of the complementary signal bus (S10a, S10b, S20a, S20b) by a switch unit (S10a, S10b, S20a, S20b). 2200 ' ) is coupled. Device for transmitting a signal according to Claim 60, characterized in that in each set of capacitors ( 2301a . 2301b ) the second capacitor (C20a, C20b) during a phase of the intersymbol interference estimation with the complement signal of the complement signal bus ( 2200 ' ) coupled to the compliment signal of the compliment signal bus ( 2200 ' ), which is coupled to the first capacitor (C10a, C10b) connected to the same differential input, and during a phase of the level determination with the same complementary signal of the complementary signal bus ( 2200 ' ), which is coupled to the first capacitor (C10a, C10b) connected to the same differential input, whereby the elimination of complementary intersymbol interference components is achieved. Device for transmitting a signal according to Claim 60, characterized in that the value of the first capacitor (C10a, C10b) is identified by C10 and the value of the second capacitor (C20a, C20b) is identified by C20, the values of the first capacitor (C10a, C10b) and the second capacitor (C20a, C20b) are selected so that they essentially satisfy the equation C10 / (C10 + C20) = (1 + exp (-T / τ)) / 2, where τ is the Time constant of the complementary signal bus ( 2200 ' ), and T is the cycle time of a bit or the time during which the data at "1" level on the complement signal bus ( 2200 ' ) appear. Device for transmitting a signal according to claim 60, characterized in that the differential amplifier ( 2303 ) as differential amplifier with memory function ( 2330 ) is listed. Device for transmitting a signal according to claim 63, characterized in that, except during a data reading period, the differential amplifier ( 2303 ) sets its output node to a high level if a data receiving transistor is a transistor (T10, T20) of the N-channel type, or to a low level if the data receiving transistor (T10, T20) is a transistor of the P Channel type, which increases the operating speed. Device for transmitting a signal according to claim 63, characterized in that during a phase of the input node precharging of the differential amplifier ( 2303 ) and a phase of the inter-symbol interference estimate within a data reading period and except during a data transmission period of the differential amplifier ( 2303 ) sets its output node to a high level if a data receiving transistor is a transistor (T10, T20) of the N-channel type, or to a low level if the data receiving transistor is a transistor (T10, T20) of the P Channel type, which increases the operating speed. Device for transmitting a signal according to claim 60, characterized in that the differential amplifier ( 2303 ) as a current mirror differential amplifier ( 2340 ) is executed. Device for transmitting a signal according to claim 60, characterized in that the differential amplifier ( 2303 ) is constructed so that it does not work except during a data transmission period. Device for transmitting a signal according to claim 51, characterized in that the complementary signal bus amplifier ( 2300A ) a first amplifier block ( 2310a ) and second amplifier block ( 2320a ), which each have an intersymbol interference elimination function and are constructed in such a way that the second amplifier block ( 2320a ) performs a level determination while the first amplifier block ( 2310a ) performs an inter-symbol interference estimate, and performs an inter-symbol interference estimate at the next sampling time, while the first amplifier block ( 2310a ) performs a level determination, and wherein the first amplifier block ( 2310a ) and the second amplifier block ( 2320a ) one differential amplifier each ( 2303 ) with a first and a second gate-receiving complementary signal input, an amplifier precharge circuit ( 2302 ), which at the first input of the differential amplifier ( 2303 ) is provided in order to precharge in a way that increases the sensitivity of the differential amplifier ( 2303 ) increased, a self-calibration circuit ( 2304 ) to control the electrical conductivity between the second input of the differential amplifier ( 2303 ) and an output of the differential amplifier ( 2303 ), and two sentences ( 2301a . 2301b ) of first and second capacitors connected to the first and second inputs of the differential amplifier ( 2303 ) are provided, the first and the second input of the differential amplifier ( 2303 ) with the complementary signal buses ( 2200 ' ) are coupled via the first capacitor (C10a, C10b) and the second capacitor (C20a, C20b) and in each set ( 2301a . 2301b ) of capacitors the first capacitor (C10a, C10b) at any time with one of the complementary signal buses ( 2200 ' ) is coupled, whereas the second capacitor (C20a, C20b) is selectively connected to one or the other of the complementary signal buses (S10a, S10b, S20a, S20b) by means of a switch unit (S10a, S10b, S20a, S20b). 2200 ' ) is coupled. Device for transmitting a signal to. Claim 68, characterized in that in each sentence ( 2301a . 2301b ) of capacitors the second capacitor (C20a, C20b) during a phase of the intersymbol interference estimation with the complementary signal bus ( 2200 ' ) which is connected to the complementary signal bus ( 2200 ' ), which is coupled to the first capacitor (C10a, C10b) connected to the same differential input, and during a phase of level determination with the same complementary signal bus ( 2200 ' ) which is coupled to the first capacitor (C10a, C10b) connected to the same differential input, as a result of which the elimination of complementary signal intermediate symbol interference components is achieved. Device for transmitting a signal according to Claim 68, characterized in that when the value of the first capacitor (C10a, C10b) is labeled C10 and the value of the second capacitor (C20a, C20b) is labeled C20, the values of the first and second capacitors (C10a, C10b, C20a, C20b) are selected so that they essentially satisfy the equation C10 / (C10 + C20) = 1 + exp (-T / τ)) / 2, where τ is the time constant of the complementary signal Busses ( 2200 ' ) and T is the cycle time of a bit or the time during which data is at "1 -" level on the complementary signal bus ( 2200 " ) appear. Device for transmitting a signal according to claim 68, characterized in that the differential amplifier ( 2303 ) as differential amplifier with memory function ( 2303 ; 2303a ) is expanded. Device for transmitting a signal according to Claim 71, characterized in that, except during a data reading period, the differential amplifier ( 2303 ) sets an output node to a high level if a data receiving transistor (T10, T20) is an N-channel type transistor, or to a low level if the data receiving transistor (T10, T20) is a transistor of P Channel type, which increases the operating speed. Device for transmitting a signal according to claim 71, characterized in that during a phase of the input node precharging of the differential amplifier ( 2303 ) and a phase of the inter-symbol interference component estimation within a data reading period and outside a data transmission period of the differential amplifier ( 2303 ) sets its output node to a high level if a data receiving transistor (T10, T20) is an N-channel type transistor, or to a low level if the data receiving transistor (T10, T20) is a transistor of P Channel type, which increases the operating speed. Device for transmitting a signal according to claim 68, characterized in that the differential amplifier ( 2303 ) as a current mirror differential amplifier ( 2303B ; 2303c ; 2303d ; 2303e ; 2303f ; 2303g ) is constructed. Device for transmitting a signal according to claim 68, characterized in that the differential amplifier ( 2303 ) is constructed so that it does not work except during a data transmission period.