US4775931A - Dynamically configured computing device - Google Patents

Dynamically configured computing device Download PDF

Info

Publication number
US4775931A
US4775931A US07035248 US3524887A US4775931A US 4775931 A US4775931 A US 4775931A US 07035248 US07035248 US 07035248 US 3524887 A US3524887 A US 3524887A US 4775931 A US4775931 A US 4775931A
Authority
US
Grant status
Grant
Patent type
Prior art keywords
peripheral
device
cpu
configuration
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US07035248
Inventor
James P. Dickie
David M. Rabinowitz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
HP Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44Arrangements for executing specific programs
    • G06F9/4401Bootstrapping
    • G06F9/4411Configuring for operating with peripheral devices; Loading of device drivers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • G06F12/0653Configuration or reconfiguration with centralised address assignment
    • G06F12/0661Configuration or reconfiguration with centralised address assignment and decentralised selection

Abstract

A computing system is presented which has a central processing unit (CPU) and peripheral devices. Identification registers associated with each peripheral device may be accessed by the CPU to identify characteristics of individual peripheral devices. Additionally, configuration registers within each peripheral device allow a particular peripheral device to determine whether instructions from the CPU are addressing that particular peripheral device.

Description

This application is a continuation of application Ser. No. 609,376, filed 5/11/84, now abandoned.

BACKGROUND

In typical computer systems, configuration of various system components is fixed. In a typical prior art static configuration scheme for a computing system, as shown in FIG. 1, a central processing unit (CPU) 50 is coupled to peripheral devices 51, 52, 53, and 54. Each device of peripheral devices 51-54 may be, for example, a memory device such as a random access memory (RAM) or a read only memory (ROM), or a non-memory device such as a display, printer, or communication controller, Peripheral devices 51-54 are coupled to CPU 50 through a bus 65. Each of peripheral devices 51-54 has assigned to it a fixed address. CPU 50 may independently interact with each of peripheral devices 51-54 by utilizing its fixed address. Peripheral devices 51-54 are each coupled to an associated address compare register 61-64 and an address select circuit 71-74. When CPU 50 or another device sends an instruction on bus 65, address compare registers 61-64 and address select circuits 71-74 screen the instruction so that each of the peripheral devices 51-54 responds only to instruction which include the fixed address assigned to that peripheral device.

The use of static configuration schemes, as that described above, inherently limits flexibility. Adding or removing devices becomes difficult, as some physical change in the system is required to allow a new device to be accessed or to indicate that a removed device is no longer present.

SUMMARY OF THE INVENTION

In accordance with the preferred embodiment of the present invention a computing system is presented which has a central processing unit (CPU) and peripheral devices which are dynamically configured by the CPU. Each peripheral device has a built-in identification code that identifies the characteristics of the peripheral device. The CPU can read the identification code to discover the peripheral device type (e.g., whether the peripheral device consists of a ROM, RAM, controller, or etc.) and other pertinent information about the peripheral device (e.g., memory size of a memory device).

Each peripheral device also contains a configuration register. The number of bits in each of the configuration registers is less than or equal to the number of bits used by the computer system for a full memory address. Each peripheral device also has a one-bit register referred to as a configuration flag. The state of the configuration flat in a particular peripheral device indicates whether that peripheral device has been configured by the CPU and thus whether the contents of the configuration register are valid.

After the CPU utilizes the identification code to determine the characteristics of a particular peripheral device, it uses this information to allocate address space to that peripheral device. The CPU then configures the peripheral device by writing one or more bits into the configuration register and setting the configuration flag of the peripheral device. Similarly, the CPU "unconfigures" or removes a peripheral device from configuration by clearing that peripheral device's configuration flag. In this way the CPU is able to dynamically adjust the configuration of the computer system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of a prior art configuration scheme for a computing device.

FIG. 2 is a schematic of a central processing unit (CPU) coupled to a series of peripheral devices in accordance to the preferred embodiment of the present invention.

FIG. 3 is a schematic of a peripheral device in accordance with the preferred embodiment of the present invention.

FIG. 4 is a block diagram of registers within a peripheral device in accordance with the preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In FIG. 2 a central processing unit (CPU) 201 is coupled to a series of peripheral devices 101, 111, 121, 131, 141, and 151. Each peripheral device 101, 111, 121, 131, 141 and 151 has an associated bus labeled 109, 119, 129, 139, 149, and 159 respectively. Busses 109, 119, 129, 139, 149, and 159 are coupled in parallel to a bus 202 which is in turn coupled to CPU 201.

CPU 201 sends commands and data to perhiperal devices 101, 111, 121, 131, 141, and 151 on its bus 202 which is coupled to busses 109, 119, 129, 139, 149, and 159. CPU 201 receives data from peripheral devices 101, 111, 121, 131, 141, and 151 through their respective busses 109, 119, 129, 139, 149, and 159 coupled to CPU 201's bus 202.

Each bus 109, 119, 129, 139, 149, and 159 is identical to each of the other busses 109, 119, 129, 139, 149, and 159. The structure of bus 109 is seen in FIG. 3. Each bus has several lines consisting of a ground line 106, a power line 105, a command line 104, a strobe line 103, and a collection of data lines 102. In the present embodiment there are four data lines in data lines 102. Ground line 106 is held at a constant voltage of 0.0 volts. Power line 105 is held at a constant voltage different from 0.0 volts, for example +4.5 volts. Command line 104 is normally driven by CPU 201 but may occasionally be driven by one or more of peripheral devices 101, 111, 121, 131, 141, or 151. Strobe line 103 is driven exclusively by CPU 201, and data lines 102 are driven by either CPU 201 or by one of peripheral devices 101, 111, 121, 131, 141, or 151. A line is at logic 0 when it is held at the same voltage as ground line 106 and is at logic 1 when it is held at the same voltage as power line 105. Strobe line 103 is asserted when it is held at logic 0 and is unasserted when it is held at logic 1. Command line 104 is asserted when it is held at logic 0 and is unasserted when it is held at logic 1. Information on data lines is data when command line is unasserted and is a command when command line is asserted. Information on data lines 102 is valid immediately prior to and during the transition of strobe line 103 from a state of assertion to a state of unassertion.

In FIG. 2, peripheral devices 101, 111, 121, and 131 are replaceable modules while peripheral devices 141 and 151 are permanent. Each of replaceable peripheral devices 101, 111, 121, and 131 is coupled to a daisy-chain 203 or a daisy-chain 204. In the present embodiment peripheral devices 101, 111, and 121 are coupled to daisy-chain 203 commencing at CPU 201 while peripheral device 131 is coupled to another daisy-chain 204 also commencing at CPU 201. Daisy-chain 203 commences at CPU 201, enters peripheral device 101 at daisy-chain input 107 and exits at daisy-chain output 108, enters peripheral device 111 at daisy-chain input 117 and exits at daisy-chain output 118, and enters peripheral device 121 at daisy-chain input 127 and exits at daisy-chain output 128 at which daisy-chain 203 terminates. Daisy-chain 204 commences at the CPU 201 and enters peripheral device 131 at daisy-chain input 137 and exits at daisy-chain output 138 at which daisy-chain 203 terminates. Daisy-chains 203 and 204 are driven by CPU 201, and are considered to be asserted when held at logic 1 and unasserted when held at logic 0.

In FIG. 4, registers within peripheral device 101 are shown. Identification code register (ID) 251, 20 bits long in the preferred embodiment, contains information identifying characteristics of peripheral device 101. CPU 201 can read ID 251 to determine the function of peripheral device 101 (e.g., whether the peripheral device 101 contains a ROM, RAM, controller, memory-mapped I/O device) and to discover other pertinent information about peripheral device 101 (e.g., the memory size). Only replaceable peripheral devices 101, 111, 121, and 131 need have an ID. Permanent peripheral devices 141 and 151 do not need to have an ID.

Peripheral device 101 also has a configuration register 252. Configuration register 252 contains fewer bits than the number of bits required by CPU 201 to access its entire memory space (the number of bits required by CPU 201 to access its entire memory space is hereinafter referred to as CPU address length, e.g., in the present embodiment CPU address length is 20 bits). Configuration register 252, for example, may be 12 bits long, while peripheral devices 111, 121, 131, 141, and 151 may have configuration registers containing more or fewer bits depending upon the memory size of each particular peripheral devices. The contents of configuration register 252 indicates to peripheral 101 the memory address(es) peripheral device 101 has been assigned by CPU 201.

A configuration flag 253 is a one-bit register which is set when CPU 201 has assigned memory address(es) to peripheral device 101 (i.e. peripheral device 101 is configured). Configuration flag 253 is reset when CPU 201 has not yet assigned memory address(es) or when CPU 201 has explicitly unassigned (i.e. unconfigured) memory addresses priorly assigned to peripheral device 101.

Peripheral device 101 also contains a command register 256 which contains a number of bits equivalent to the number of data lines in data lines 102, e.g., four bits in the present embodiment. Command register 256 is used to store a current command sent by CPU 201 (see Table I). Each peripheral device 111, 121, 131, 141, and 151 contains a command register.

Peripheral device 101 also contains a data pointer register (DP) 254 and a program counter register (PC) 255. DP 254 and PC 255 each contain a number of bits equal to the CPU address length. Each peripheral device 111, 121, 131, 141, and 151 contains a DP and may contain a PC depending upon its function.

If peripheral device 101 is unconfigured, CPU 201 may configure it as follows. CPU 201 assigns to peripheral device a range of one or more addresses which can be directly addressed by CPU 201. In order to do this CPU 201 first asserts daisy-chain input 107. Then CPU 201 examines ID 251 to determine the characteristics of peripheral device 101. CPU 201 issues a "CONFIGURE" command (i.e. sends a binary code corresponding to a CONFIGURE command, see Table I) and then transfers a configuration address, in this case 20 bits of data, to peripheral device 101. Peripheral device 101 copies the 12 high-order bits into configuration register 252 and sets flag 253, indicating that it is configured.

CPU 201 may also unassign (unconfigure) the memory address(es) of peripheral device 101. In order to do so CPU 201 issues a "Load DP" command (see Table I) and then transfers over data bus 201 a 20 bit address corresponding to the configuration address assigned to peripheral device 101. Each peripheral device 101, 111, 121, 131, 141, 151 then places this address into its DP. CPU 201 then sends an "UNCONFIGURE" command (see Table I). Each peripheral device compares the contents of its configuration register with a corresponding number of high order bits within its DP register. Since in this case the address contained in the DP registers corresponds to the configuration address assigned to peripheral device 101, peripheral device 101 will reset configuration flag 253.

In the same way as it configures and unconfigures peripheral device 101, CPU may configure and unconfigure the other peripheral devices. When configured each peripheral device has a unique configuration address, thereby allowing CPU 201 to address each of peripheral devices 101, 111, 121, 131, 141, and 151 individually.

When a peripheral device's configuration flag is reset, that peripheral device holds its daisy-chain output line unasserted. Thus when peripheral device 101 is unconfigured its daisy-chain output line 108 is held unasserted regardless of the value of its daisy-chain input line 107. When a peripheral device's configuration flag is set that peripheral device holds its daisy-chain output line at the same value as its daisy-chain input line. Thus when peripheral device 101 is configured (configuration flag 253 is set) its daisy-chain output line 108 is held at the same logic level as its daisy-chain input line 107.

Once configured, peripheral device 101 utilizes the contents of configuration register 252 to evaluate whether commands issued by CPU 201 are addressing it. For instance, when a PC READ is issued, peripheral device 101 will compare the contents of PC 255 with the contents of configuration register 252 to determine whether CPU 201 is addressing memory space within peripheral device 101. In the same way, upon the receipt of a PC READ each peripheral device 111, 121, 131, 141, and 151 will also compare the contents of its PC with the contents of its configuration register to determine whether CPU 201 is addressing it. Only the peripheral device addressed by CPU 201 will respond to commands issued by CPU 201.

The PC of each peripheral device 101, 111, 121, 131, 141, and 151 at any particular time all contain the same value. When CPU 201 issues a LOAD PC instruction, each peripheral device 101, 111, 121, 131, 141, and 151 simultaneously loads a new value into its PC. Similarly, the DP of each peripheral device 101, 111, 121, 131, 141, and 151 at any particular time all contain the same value.

Except when there is a nibble transfer across data lines 102, CPU 201 holds strobe line 102 unasserted. When making a nibble transfer across data lines 102, CPU 201 strobes (i.e. asserts then unasserts strobe line 103) as described in Table I.

Except when transfering command codes (i.e. binary codes, see Table I) to peripheral devices 101, 111, 121, 131, 141, and 151, CPU 201 holds command line 104 unasserted. To send a command code CPU 201 places on data lines 102 logic levels (i.e. logic 0s and logic 1s) corresponding to the command code of each command (see Table I). CPU 201 then asserts command line 104 and strobes (asserts and then unasserts) strobe line 103. Each peripheral device 101, 111, 121, 131, 141, and 151 copies the command code into its command register (e.g. command register 256 of peripheral device 101) as strobe line 103 is unasserted by CPU 201. CPU 201 then unasserts command line 104. The contents of the command register of each peripheral device 101, 111, 121, 131, 141 and 151 is interpreted by that peripheral device and will indicate how each peripheral device will respond to subsequent data on data lines 102, or whether it will apply data to data lines 102.

The following table gives a list of commands, their binary codes and a summary of the action take by peripheral devices 101, 111, 121, 131, 141, and 151.

                                  TABLE I__________________________________________________________________________Binary Code  Command   Summary of action__________________________________________________________________________0000   NOP       All peripheral devices ignore strobe            (strobes are received by each peripheral            device on strobe line 103) until next            control code is sent.0001   ID        An unconfigured peripheral device which            sees its daisy-chain input at logic 1            sends its ID nibbles on following            strobes starting with the low-order            nibble.0010   PC READ   BUS→(PC). The peripheral device            addressed by the high-order bits of the            program counter sends data pointed to by            its PC register on each following strobe            and all peripheral devices increment            their PC registers after each strobe. A            dummy strobe will immediately follow the            issuance of PC READ.0011   DP READ   BUS→(DP). The peripheral device            addressed by the high-order bits of the            data pointer sends data pointed to by            its DP register on each following strobe            and all peripheral devices increment            their DP registers after each strobe. A            dummy strobe will immediately follow the            issuance of a DP READ.0100   PC WRITE  (PC)→BUS. The peripheral device            addressed by the high-order bits of the            program counter loads data on following            strobes into a location pointed to by            its PC register and all peripheral            devices increment their PC registers            after each strobe.0101   DP WRITE  (DP)→BUS The peripheral device            addressed by the high-order bits of the            data pointer loads data on following            strobes into the a location pointed to            by its DP register and all peripheral            devices increment their DP register            after each strobe.0110   LOAD PC   BUS→PC. All peripheral devices load            the data on following strobes into their            PC registers starting with the low-order            nibble. After all 5 nibbles are trans-            ferred the command code is automically            changed to a PC READ (0010).0111   LOAD DP   BUS→DP. All peripheral devices load            the data on following strobes into their            DP registers starting with the low-order            nibble. After all 5 nibbles are trans-            ferred the command code is automically            changed to a DP READ (0011).1000   CONFIGURE The unconfigured peripheral device that            sees its DAISY-CHAIN input high loads            the following five data nibbles into its            configuration register starting with the            low-order nibble.1001   UNCONFIGURE            The peripheral device currently addres-            sed by its data pointer will unconfigure            itself. The device will then respond to            CONFIGURE and ID bus commands only. The            local DP must be loaded immediately            preceding an UNCONFIGURE command.1010   POLL      All peripheral devices that require            service pull one data line high during            the next strobe low.1011   Reserved1100   BUSCC     The peripheral device currently addres-            sed by its local DP will perform a            specialized operation as defined by the            individual peripheral device1101   Reserved1110   SHUTDOWN  Each peripheral device responds to this            command based on its own specialized            requirements.1111   RESET     All peripheral devices perform local            reset, including resetting their            configuration flags if they are replace-            able peripheral devices__________________________________________________________________________

Claims (4)

We claim:
1. A computing device comprising:
CPU means for processing data;
a first peripheral device coupled to the CPU means, the first peripheral device including a first plurality of memory locations which serve as directly addressable memory for the CPU means, and first configuration register means, coupled to the first plurality of memory locations, for storing bits which serve as high order bits of addresses for the memory locations within the first plurality of memory locations;
identification register means coupled to the first peripheral device for storing data identifying characteristics of the first peripheral device, wherein the first peripheral device provides the CPU means with data from the identification register means in order to identify to the CPU means the amount of memory locations within the first plurality of memory locations;
a second peripheral device coupled to the CPU means, the second peripheral device comprising a second plurality of memory locations which serve as directly addressable memory for the CPU, and second configuration register means coupled to the second plurality of memory locations for storing bits which serve as high order bits of addresses for the memory locations within the second plurality of memory locations; and,
daisy-chain means coupled to the CPU, the first peripheral device, and the second peripheral device for allowing the CPU to separately initialize the first configuration register means and the second configuration register means, the second peripheral device having a daisy-chain input line connected to a daisy-chain output line of the first peripheral device, and a daisy-chain input line of the first peripheral device being connected to the CPU means, wherein the first peripheral device includes flag means responsive to command from said CPU means for indicating that the first peripheral device is configured and wherein the first peripheral device includes means for changing a signal on the daisy-chain output line of the first peripheral device based on a signal on the daisy-chain input line of the first peripheral device.
2. A computing device as in claim 1 wherein the high order bits stored in the first configuration register means in the first peripheral device define a first address space, wherein the high order bits stored in the second configuration means in the second peripheral device define a second address space, and wherein the first address space is not equal to the second address space.
3. A computing device as in claim 2 wherein the first peripheral device additionally comprises:
data pointer register means for storing a third address to which the CPU means requests access, wherein the first peripheral device compares contents of the first configuration register means with high order bits from the third address to determine whether the address addresses memory within the first address space.
4. In a computing system having a central processing unit, a first peripheral device having a first plurality of memory locations directly addressable by the central processing device and a second peripheral device having a second plurality of memory locations directly addressable by the central processing device, wherein the second peripheral device has a daisy-chain input line connected to a daisy-chain output line of the first peripheral device and a daisy-chain input line of the first peripheral device is connected to the central processing unit, a method by which the central processing unit assigns addresses to the first plurality of memory locations within the first peripheral device and the second peripheral device, the method comprising:
examining contents of an identification register within the first peripheral device by the central processing unit to determine the amount of memory locations within the first peripheral device;
transferring to the first peripheral device a first configuration address which indicates the address of the first peripheral device in the computing system address space;
storing high order bits of the first configuration address to identify the high order bits of the address of each memory location in the first plurality of memory locations;
examining contents of an identification register within the second peripheral device by the central processing unit to determine the amount of memory locations within the second peripheral device;
transferring to the second peripheral device a second configuration address which indicates the address of the second peripheral device in the computing system address space;
storing high order bits of the second configuration address to identify the high order bits of the address of each memory location in the second plurality of memory locations;
indicating with a flag that the first peripheral device has been configured; and
changing a signal on the daisy-chain output line of the first peripheral device based on a signal on the daisy-chain input line of the first peripheral device.
US07035248 1984-05-11 1987-04-02 Dynamically configured computing device Expired - Lifetime US4775931A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US60937684 true 1984-05-11 1984-05-11
US07035248 US4775931A (en) 1984-05-11 1987-04-02 Dynamically configured computing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07035248 US4775931A (en) 1984-05-11 1987-04-02 Dynamically configured computing device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US60937684 Continuation 1984-05-11 1984-05-11

Publications (1)

Publication Number Publication Date
US4775931A true US4775931A (en) 1988-10-04

Family

ID=26711929

Family Applications (1)

Application Number Title Priority Date Filing Date
US07035248 Expired - Lifetime US4775931A (en) 1984-05-11 1987-04-02 Dynamically configured computing device

Country Status (1)

Country Link
US (1) US4775931A (en)

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4875158A (en) * 1985-08-14 1989-10-17 Apple Computer, Inc. Method for requesting service by a device which generates a service request signal successively until it is serviced
US4910655A (en) * 1985-08-14 1990-03-20 Apple Computer, Inc. Apparatus for transferring signals and data under the control of a host computer
US4912627A (en) * 1985-08-14 1990-03-27 Apple Computer, Inc. Method for storing a second number as a command address of a first peripheral device and a third number as a command address of a second peripheral device
US4918598A (en) * 1985-08-14 1990-04-17 Apple Computer, Inc. Method for selectively activating and deactivating devices having same first address and different extended addresses
EP0375981A2 (en) * 1988-12-30 1990-07-04 International Business Machines Corporation Method and apparatus for applying electric power to electronic components
US5075841A (en) * 1988-01-18 1991-12-24 Citizen Watch Co., Ltd. Printer control with automatic intialization of stored control data
US5077660A (en) * 1989-03-23 1991-12-31 F.M.E. Corporation Remote meter configuration
US5121500A (en) * 1988-12-30 1992-06-09 International Business Machines Corporation Preliminary polling for identification and location of removable/replaceable computer components prior to power-up
US5125095A (en) * 1987-04-20 1992-06-23 Hitachi Microcomputer Engineering Ltd. System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus
US5168555A (en) * 1989-09-06 1992-12-01 Unisys Corporation Initial program load control
US5170472A (en) * 1991-03-28 1992-12-08 International Business Machines Corp. Dynamically changing a system i/o configuration definition
WO1993000637A1 (en) * 1991-06-21 1993-01-07 Cad Forms Technology Inc. Method and apparatus for transferring data between a host device and a plurality of portable computers
US5191655A (en) * 1987-10-13 1993-03-02 Standard Microsystems Corporation Interface arrangement for facilitating data communication between a computer and peripherals
US5220654A (en) * 1991-03-28 1993-06-15 International Business Machines Corp. Method and system for managing an operating system definition of a dynamically modifiable i/o configuration
GB2262825A (en) * 1991-12-27 1993-06-30 Intel Corp Device driver configuration in a computer system
US5296936A (en) * 1991-07-22 1994-03-22 International Business Machines Corporation Communication apparatus and method for transferring image data from a source to one or more receivers
US5301276A (en) * 1990-06-29 1994-04-05 Sanyo Electric Co., Ltd. Method and device for assigning I/O address in data processing apparatus
US5301346A (en) * 1991-06-21 1994-04-05 Cad Forms Technology Inc. Method and apparatus for transferring data between a host device and plurality of portable computers
US5369401A (en) * 1989-03-23 1994-11-29 F.M.E. Corporation Remote meter operation
US5371892A (en) * 1989-12-19 1994-12-06 3Com Corporation Method for configuring a computer bus adapter circuit board without the use of jumpers or switches
US5420987A (en) * 1993-07-19 1995-05-30 3 Com Corporation Method and apparatus for configuring a selected adapter unit on a common bus in the presence of other adapter units
US5426767A (en) * 1987-08-03 1995-06-20 Compaq Computer Corporation Method for distinguishing between a 286-type central processing unit and a 386-type central processing unit
US5434982A (en) * 1990-06-12 1995-07-18 Sgs-Thomson Microelectronics, S.A. Electronically configurable connection device
US5452424A (en) * 1990-08-31 1995-09-19 Ncr Corporation Work station and method for serially providing configuration data to functional units contained therein
US5465364A (en) * 1989-09-22 1995-11-07 International Business Machines, Inc. Method and system for providing device driver support which is independent of changeable characteristics of devices and operating systems
US5493683A (en) * 1992-12-29 1996-02-20 Intel Corporation Register for identifying processor characteristics
US5499385A (en) * 1990-04-18 1996-03-12 Rambus, Inc. Method for accessing and transmitting data to/from a memory in packets
WO1996007971A1 (en) * 1994-09-09 1996-03-14 Medialink Technologies Corporation Method and apparatus for automatically configuring an interface
US5561813A (en) * 1993-08-27 1996-10-01 Advanced System Products, Inc. Circuit for resolving I/O port address conflicts
EP0734597A1 (en) * 1993-12-07 1996-10-02 3Com Corporation Circuit card with low profile detachable interface
US5594873A (en) * 1994-12-08 1997-01-14 Dell Usa, L.P. System and method for identifying expansion devices in a computer system
US5594874A (en) * 1993-09-30 1997-01-14 Cirrus Logic, Inc. Automatic bus setting, sensing and switching interface unit
US5608877A (en) * 1995-03-24 1997-03-04 Cirrus Logic, Inc. Reset based computer bus identification method and circuit resilient to power transience
WO1997014133A2 (en) * 1995-09-27 1997-04-17 Cirrus Logic, Inc. Display control system with subsystems corresponding to different display regions
US5666557A (en) * 1994-06-16 1997-09-09 Cassidy; Bruce Michael Method and apparatus for automatically assigning device identifiers on a parallel data bus
US5727184A (en) * 1994-06-27 1998-03-10 Cirrus Logic, Inc. Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
US5794014A (en) * 1994-06-27 1998-08-11 Cirrus Logic, Inc. Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
US5850573A (en) * 1990-08-16 1998-12-15 Canon Kabushiki Kaisha Control method for peripheral device in host computer connectable to a plurality of peripheral devices
EP0899655A1 (en) * 1997-08-26 1999-03-03 Canon Kabushiki Kaisha Information communicating apparatus, method and system
US5909592A (en) * 1994-09-07 1999-06-01 Intel Corporation Method in a basic input-output system (BIOS) of detecting and configuring integrated device electronics (IDE) devices
US5999743A (en) * 1997-09-09 1999-12-07 Compaq Computer Corporation System and method for dynamically allocating accelerated graphics port memory space
US6094053A (en) * 1995-11-06 2000-07-25 Ford Global Technologies, Inc. Method and apparatus for identifying electronic circuits in a distributed electronic system
US6101319A (en) * 1997-01-02 2000-08-08 Intel Corporation Method and apparatus for the automatic configuration of strapping options on a circuit board assembly
US6134605A (en) * 1998-04-15 2000-10-17 Diamond Multimedia Systems, Inc. Redefinable signal processing subsystem
EP1083487A2 (en) * 1999-09-10 2001-03-14 Texas Instruments Incorporated Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor
US6205522B1 (en) 1998-04-15 2001-03-20 Diamond Multimedia Systems, Inc. DSP code swapping with continuous DSP execution
US6230216B1 (en) * 1999-01-28 2001-05-08 Vlsi Technology, Inc. Method for eliminating dual address cycles in a peripheral component interconnect environment
US6256723B1 (en) 1998-04-15 2001-07-03 Diamond Multimedia Systems, Inc. Signal processing system with distributed uniform memory
US6260086B1 (en) * 1998-12-22 2001-07-10 Motorola, Inc. Controller circuit for transferring a set of peripheral data words
US6311165B1 (en) * 1998-04-29 2001-10-30 Ncr Corporation Transaction processing systems
US20020103989A1 (en) * 2001-01-31 2002-08-01 International Business Machines Corporation Method and apparatus to determine the availability of some instruction subsets within a processor architecture
US6948006B1 (en) * 1990-12-12 2005-09-20 Canon Kabushiki Kaisha Host system that provides device driver for connected external peripheral if device driver type is available or device driver is downloaded from memory of external peripheral to host system
US20050223388A1 (en) * 2004-04-01 2005-10-06 Lsi Logic Corporation System and method for implementing multiple instantiated configurable peripherals in a circuit design
US20060136609A1 (en) * 2004-07-28 2006-06-22 Gaidukov Vladimir Control system having main controller and peripheral controllers, and bus connection method
US20090327540A1 (en) * 2008-06-30 2009-12-31 Lg Chem, Ltd. System and Method for Determining a Bus Address for a Controller Within a Network
US20100257303A1 (en) * 2007-12-17 2010-10-07 Atlab Inc. Serial communication system and id grant method thereof
US20120239844A1 (en) * 2011-03-17 2012-09-20 American Megatrends, Inc. Data storage system for managing serial interface configuration based on detected activity
US8582570B2 (en) 2000-03-27 2013-11-12 Tri-County Excelsior Foundation Automatic attachment and detachment for hub and peripheral devices
US8904049B2 (en) 2012-08-23 2014-12-02 Lg Chem, Ltd. Battery pack monitoring system and method for assigning a binary ID to a microprocessor in the battery pack monitoring system

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902162A (en) * 1972-11-24 1975-08-26 Honeywell Inf Systems Data communication system incorporating programmable front end processor having multiple peripheral units
US4124887A (en) * 1977-04-04 1978-11-07 Universal Instruments Corporation Real time computer control system for automatic machines
US4268901A (en) * 1974-09-18 1981-05-19 Ing. C. Olivetti & C., S.P.A. Variable configuration accounting machine with automatic identification of the number and type of connected peripheral units
US4303993A (en) * 1979-10-10 1981-12-01 Honeywell Information Systems Inc. Memory present apparatus
US4373181A (en) * 1980-07-30 1983-02-08 Chisholm Douglas R Dynamic device address assignment mechanism for a data processing system
US4556953A (en) * 1982-02-24 1985-12-03 Caprio A Ronald Interchangeable interface circuitry arrangements for use with a data processing system
US4562535A (en) * 1982-04-05 1985-12-31 Texas Instruments Incorporated Self-configuring digital processor system with global system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902162A (en) * 1972-11-24 1975-08-26 Honeywell Inf Systems Data communication system incorporating programmable front end processor having multiple peripheral units
US4268901A (en) * 1974-09-18 1981-05-19 Ing. C. Olivetti & C., S.P.A. Variable configuration accounting machine with automatic identification of the number and type of connected peripheral units
US4124887A (en) * 1977-04-04 1978-11-07 Universal Instruments Corporation Real time computer control system for automatic machines
US4303993A (en) * 1979-10-10 1981-12-01 Honeywell Information Systems Inc. Memory present apparatus
US4373181A (en) * 1980-07-30 1983-02-08 Chisholm Douglas R Dynamic device address assignment mechanism for a data processing system
US4556953A (en) * 1982-02-24 1985-12-03 Caprio A Ronald Interchangeable interface circuitry arrangements for use with a data processing system
US4562535A (en) * 1982-04-05 1985-12-31 Texas Instruments Incorporated Self-configuring digital processor system with global system

Cited By (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4875158A (en) * 1985-08-14 1989-10-17 Apple Computer, Inc. Method for requesting service by a device which generates a service request signal successively until it is serviced
US4910655A (en) * 1985-08-14 1990-03-20 Apple Computer, Inc. Apparatus for transferring signals and data under the control of a host computer
US4912627A (en) * 1985-08-14 1990-03-27 Apple Computer, Inc. Method for storing a second number as a command address of a first peripheral device and a third number as a command address of a second peripheral device
US4918598A (en) * 1985-08-14 1990-04-17 Apple Computer, Inc. Method for selectively activating and deactivating devices having same first address and different extended addresses
US5125095A (en) * 1987-04-20 1992-06-23 Hitachi Microcomputer Engineering Ltd. System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus
US5426767A (en) * 1987-08-03 1995-06-20 Compaq Computer Corporation Method for distinguishing between a 286-type central processing unit and a 386-type central processing unit
US5490267A (en) * 1987-08-03 1996-02-06 Compaq Computer Corporation Method for distinguishing between a 386-type central processing unit and A 286-type central processing unit
US5191655A (en) * 1987-10-13 1993-03-02 Standard Microsystems Corporation Interface arrangement for facilitating data communication between a computer and peripherals
US5075841A (en) * 1988-01-18 1991-12-24 Citizen Watch Co., Ltd. Printer control with automatic intialization of stored control data
US5121500A (en) * 1988-12-30 1992-06-09 International Business Machines Corporation Preliminary polling for identification and location of removable/replaceable computer components prior to power-up
EP0375981A2 (en) * 1988-12-30 1990-07-04 International Business Machines Corporation Method and apparatus for applying electric power to electronic components
EP0375981A3 (en) * 1988-12-30 1991-03-06 International Business Machines Corporation Method and apparatus for applying electric power to electronic components
US5612884A (en) * 1989-03-23 1997-03-18 F.M.E. Corporation Remote meter operation
US5077660A (en) * 1989-03-23 1991-12-31 F.M.E. Corporation Remote meter configuration
US5369401A (en) * 1989-03-23 1994-11-29 F.M.E. Corporation Remote meter operation
US5168555A (en) * 1989-09-06 1992-12-01 Unisys Corporation Initial program load control
US5465364A (en) * 1989-09-22 1995-11-07 International Business Machines, Inc. Method and system for providing device driver support which is independent of changeable characteristics of devices and operating systems
US5371892A (en) * 1989-12-19 1994-12-06 3Com Corporation Method for configuring a computer bus adapter circuit board without the use of jumpers or switches
US5954804A (en) * 1990-04-18 1999-09-21 Rambus Inc. Synchronous memory device having an internal register
US5928343A (en) * 1990-04-18 1999-07-27 Rambus Inc. Memory module having memory devices containing internal device ID registers and method of initializing same
US5499385A (en) * 1990-04-18 1996-03-12 Rambus, Inc. Method for accessing and transmitting data to/from a memory in packets
US5983320A (en) * 1990-04-18 1999-11-09 Rambus, Inc. Method and apparatus for externally configuring and modifying the transaction request response characteristics of a semiconductor device coupled to a bus
US5915105A (en) * 1990-04-18 1999-06-22 Rambus Inc. Integrated circuit I/O using a high performance bus interface
US5638334A (en) * 1990-04-18 1997-06-10 Rambus Inc. Integrated circuit I/O using a high performance bus interface
US5809263A (en) * 1990-04-18 1998-09-15 Rambus Inc. Integrated circuit I/O using a high performance bus interface
US6070222A (en) * 1990-04-18 2000-05-30 Rambus Inc. Synchronous memory device having identification register
US6085284A (en) * 1990-04-18 2000-07-04 Rambus Inc. Method of operating a memory device having a variable data output length and an identification register
US5841580A (en) * 1990-04-18 1998-11-24 Rambus, Inc. Integrated circuit I/O using a high performance bus interface
US5606717A (en) * 1990-04-18 1997-02-25 Rambus, Inc. Memory circuitry having bus interface for receiving information in packets and access time registers
US5434982A (en) * 1990-06-12 1995-07-18 Sgs-Thomson Microelectronics, S.A. Electronically configurable connection device
US5727169A (en) * 1990-06-12 1998-03-10 Sgs-Thomson Microelectronics, S.A. Electronically configurable connection device
US5301276A (en) * 1990-06-29 1994-04-05 Sanyo Electric Co., Ltd. Method and device for assigning I/O address in data processing apparatus
US5850573A (en) * 1990-08-16 1998-12-15 Canon Kabushiki Kaisha Control method for peripheral device in host computer connectable to a plurality of peripheral devices
US5452424A (en) * 1990-08-31 1995-09-19 Ncr Corporation Work station and method for serially providing configuration data to functional units contained therein
US6948006B1 (en) * 1990-12-12 2005-09-20 Canon Kabushiki Kaisha Host system that provides device driver for connected external peripheral if device driver type is available or device driver is downloaded from memory of external peripheral to host system
US7266618B2 (en) 1990-12-12 2007-09-04 Canon Kabushiki Kaisha Host system that provides device driver for connected external peripheral if device driver type is available or device driver is downloaded from memory of external peripheral to host system
US20050266705A1 (en) * 1990-12-12 2005-12-01 Canon Kabushiki Kaisha Electronic apparatus having connecting means
US5170472A (en) * 1991-03-28 1992-12-08 International Business Machines Corp. Dynamically changing a system i/o configuration definition
US5220654A (en) * 1991-03-28 1993-06-15 International Business Machines Corp. Method and system for managing an operating system definition of a dynamically modifiable i/o configuration
US5461717A (en) * 1991-06-21 1995-10-24 Cad Forms Technology Inc. Apparatus for transferring data between a host device and portable computers of various sizes and for recharging the batteries of same
US5301346A (en) * 1991-06-21 1994-04-05 Cad Forms Technology Inc. Method and apparatus for transferring data between a host device and plurality of portable computers
WO1993000637A1 (en) * 1991-06-21 1993-01-07 Cad Forms Technology Inc. Method and apparatus for transferring data between a host device and a plurality of portable computers
US5621890A (en) * 1991-06-21 1997-04-15 John Notarianni Method and apparatus for transferring data between a host device and a plurality of portable computers
US5296936A (en) * 1991-07-22 1994-03-22 International Business Machines Corporation Communication apparatus and method for transferring image data from a source to one or more receivers
GB2262825B (en) * 1991-12-27 1995-05-24 Intel Corp Device driver configuration in a computer system
GB2262825A (en) * 1991-12-27 1993-06-30 Intel Corp Device driver configuration in a computer system
US5319751A (en) * 1991-12-27 1994-06-07 Intel Corporation Device driver configuration in a computer system
US5493683A (en) * 1992-12-29 1996-02-20 Intel Corporation Register for identifying processor characteristics
US5420987A (en) * 1993-07-19 1995-05-30 3 Com Corporation Method and apparatus for configuring a selected adapter unit on a common bus in the presence of other adapter units
US5561813A (en) * 1993-08-27 1996-10-01 Advanced System Products, Inc. Circuit for resolving I/O port address conflicts
US5594874A (en) * 1993-09-30 1997-01-14 Cirrus Logic, Inc. Automatic bus setting, sensing and switching interface unit
EP0734597A1 (en) * 1993-12-07 1996-10-02 3Com Corporation Circuit card with low profile detachable interface
US5666557A (en) * 1994-06-16 1997-09-09 Cassidy; Bruce Michael Method and apparatus for automatically assigning device identifiers on a parallel data bus
US5905885A (en) * 1994-06-27 1999-05-18 Cirrus Logic, Inc. Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
US5794014A (en) * 1994-06-27 1998-08-11 Cirrus Logic, Inc. Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
US5727184A (en) * 1994-06-27 1998-03-10 Cirrus Logic, Inc. Method and apparatus for interfacing between peripherals of multiple formats and a single system bus
US5909592A (en) * 1994-09-07 1999-06-01 Intel Corporation Method in a basic input-output system (BIOS) of detecting and configuring integrated device electronics (IDE) devices
WO1996007971A1 (en) * 1994-09-09 1996-03-14 Medialink Technologies Corporation Method and apparatus for automatically configuring an interface
US5594873A (en) * 1994-12-08 1997-01-14 Dell Usa, L.P. System and method for identifying expansion devices in a computer system
US5608877A (en) * 1995-03-24 1997-03-04 Cirrus Logic, Inc. Reset based computer bus identification method and circuit resilient to power transience
WO1997014133A2 (en) * 1995-09-27 1997-04-17 Cirrus Logic, Inc. Display control system with subsystems corresponding to different display regions
US6025840A (en) * 1995-09-27 2000-02-15 Cirrus Logic, Inc. Circuits, systems and methods for memory mapping and display control systems using the same
US6058464A (en) * 1995-09-27 2000-05-02 Cirrus Logic, Inc. Circuits, systems and method for address mapping
WO1997014133A3 (en) * 1995-09-27 1997-08-28 Cirrus Logic Inc Display control system with subsystems corresponding to different display regions
US6094053A (en) * 1995-11-06 2000-07-25 Ford Global Technologies, Inc. Method and apparatus for identifying electronic circuits in a distributed electronic system
US6434632B1 (en) 1997-01-02 2002-08-13 Intel Corporation Method and apparatus for the automatic configuration of strapping options on a circuit board assembly
US6101319A (en) * 1997-01-02 2000-08-08 Intel Corporation Method and apparatus for the automatic configuration of strapping options on a circuit board assembly
US20030160869A1 (en) * 1997-08-26 2003-08-28 Shinichi Koyama Information communicating apparatus, method and system
US7071972B2 (en) * 1997-08-26 2006-07-04 Canon Kabushiki Kaisha Detecting device information including information about a device
EP0899655A1 (en) * 1997-08-26 1999-03-03 Canon Kabushiki Kaisha Information communicating apparatus, method and system
CN100541457C (en) 1997-08-26 2009-09-16 佳能株式会社 Method and equipment for detecting information comprising information related to a selection device
US5999743A (en) * 1997-09-09 1999-12-07 Compaq Computer Corporation System and method for dynamically allocating accelerated graphics port memory space
US6256723B1 (en) 1998-04-15 2001-07-03 Diamond Multimedia Systems, Inc. Signal processing system with distributed uniform memory
US6205522B1 (en) 1998-04-15 2001-03-20 Diamond Multimedia Systems, Inc. DSP code swapping with continuous DSP execution
US6134605A (en) * 1998-04-15 2000-10-17 Diamond Multimedia Systems, Inc. Redefinable signal processing subsystem
US6311165B1 (en) * 1998-04-29 2001-10-30 Ncr Corporation Transaction processing systems
US20020099634A1 (en) * 1998-04-29 2002-07-25 Ncr Corporation Transaction processing systems
US7912914B2 (en) 1998-04-29 2011-03-22 Ncr Corporation Transaction processing systems
US6260086B1 (en) * 1998-12-22 2001-07-10 Motorola, Inc. Controller circuit for transferring a set of peripheral data words
US6230216B1 (en) * 1999-01-28 2001-05-08 Vlsi Technology, Inc. Method for eliminating dual address cycles in a peripheral component interconnect environment
EP1083487A3 (en) * 1999-09-10 2002-01-23 Texas Instruments Incorporated Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor
EP1083487A2 (en) * 1999-09-10 2001-03-14 Texas Instruments Incorporated Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor
US6694385B1 (en) 1999-09-10 2004-02-17 Texas Instruments Incorporated Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor
US8588231B2 (en) 2000-03-27 2013-11-19 Tri-County Excelsior Foundation Personal area network apparatus
US8675590B2 (en) 2000-03-27 2014-03-18 Tri-County Excelsior Foundation Personal area network with automatic attachment and detachment
US8588196B2 (en) 2000-03-27 2013-11-19 Tri-County Excelsior Foundation Automatic attachment and detachment for hub and peripheral devices
US8582570B2 (en) 2000-03-27 2013-11-12 Tri-County Excelsior Foundation Automatic attachment and detachment for hub and peripheral devices
US8582571B2 (en) 2000-03-27 2013-11-12 Tri-County Excelsior Foundation Personal area network apparatus
US20020103989A1 (en) * 2001-01-31 2002-08-01 International Business Machines Corporation Method and apparatus to determine the availability of some instruction subsets within a processor architecture
US6728864B2 (en) * 2001-01-31 2004-04-27 International Business Machines Corporation Identifying architecture and bit specification of processor implementation using bits in identification register
US20050223388A1 (en) * 2004-04-01 2005-10-06 Lsi Logic Corporation System and method for implementing multiple instantiated configurable peripherals in a circuit design
US7620743B2 (en) * 2004-04-01 2009-11-17 Lsi Corporation System and method for implementing multiple instantiated configurable peripherals in a circuit design
US7555583B2 (en) 2004-07-28 2009-06-30 Samsung Electronics Co., Ltd. Control system having main controller and peripheral controllers, and bus connection method
US20060136609A1 (en) * 2004-07-28 2006-06-22 Gaidukov Vladimir Control system having main controller and peripheral controllers, and bus connection method
US20100257303A1 (en) * 2007-12-17 2010-10-07 Atlab Inc. Serial communication system and id grant method thereof
US20090327540A1 (en) * 2008-06-30 2009-12-31 Lg Chem, Ltd. System and Method for Determining a Bus Address for a Controller Within a Network
US7962661B2 (en) * 2008-06-30 2011-06-14 Lg Chem, Ltd. System and method for determining a bus address for a controller within a network
US20120239844A1 (en) * 2011-03-17 2012-09-20 American Megatrends, Inc. Data storage system for managing serial interface configuration based on detected activity
US8996775B2 (en) * 2011-03-17 2015-03-31 American Megatrends, Inc. Backplane controller for managing serial interface configuration based on detected activity
US8938566B2 (en) * 2011-03-17 2015-01-20 American Megatrends, Inc. Data storage system for managing serial interface configuration based on detected activity
US20120239845A1 (en) * 2011-03-17 2012-09-20 American Megatrends, Inc. Backplane controller for managing serial interface configuration based on detected activity
US8904049B2 (en) 2012-08-23 2014-12-02 Lg Chem, Ltd. Battery pack monitoring system and method for assigning a binary ID to a microprocessor in the battery pack monitoring system

Similar Documents

Publication Publication Date Title
US5802269A (en) Method and apparatus for power management of distributed direct memory access (DDMA) devices
US6216191B1 (en) Field programmable gate array having a dedicated processor interface
US6185654B1 (en) Phantom resource memory address mapping system
US4908789A (en) Method and system for automatically assigning memory modules of different predetermined capacities to contiguous segments of a linear address range
US4361868A (en) Device for increasing the length of a logic computer address
US5006982A (en) Method of increasing the bandwidth of a packet bus by reordering reply packets
US4006466A (en) Programmable interface apparatus and method
US5684973A (en) Expandable memory system and method for interleaving addresses among memory banks of different speeds and sizes
US3828325A (en) Universal interface system using a controller to adapt to any connecting peripheral device
US4004283A (en) Multiple interrupt microprocessor system
US4349870A (en) Microcomputer with programmable multi-function port
US4050096A (en) Pulse expanding system for microprocessor systems with slow memory
US5535368A (en) Automatically-configuring memory subsystem
US5278801A (en) Flexible addressing for drams
US5768598A (en) Method and apparatus for sharing hardward resources in a computer system
US5966727A (en) Combination flash memory and dram memory board interleave-bypass memory access method, and memory access device incorporating both the same
US5247629A (en) Multiprocessor system with global data replication and two levels of address translation units
US5088023A (en) Integrated circuit having processor coupled by common bus to programmable read only memory for processor operation and processor uncoupled from common bus when programming read only memory from external device
US20070130397A1 (en) System and method for encoding packet header to enable higher bandwidth efficiency across PCIe links
US4860252A (en) Self-adaptive computer memory address allocation system
US4291371A (en) I/O Request interrupt mechanism
US6640262B1 (en) Method and apparatus for automatically configuring a configurable integrated circuit
US5530895A (en) System and method for computer interface board identification by serially comparing identification address bits and asserting complementary logic patterns for each match
US4156932A (en) Programmable communications controller
US6771526B2 (en) Method and apparatus for data transfer

Legal Events

Date Code Title Description
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: HEWLETT-PACKARD COMPANY, COLORADO

Free format text: MERGER;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:011523/0469

Effective date: 19980520