JPS5682961U - - Google Patents
Info
- Publication number
- JPS5682961U JPS5682961U JP16673279U JP16673279U JPS5682961U JP S5682961 U JPS5682961 U JP S5682961U JP 16673279 U JP16673279 U JP 16673279U JP 16673279 U JP16673279 U JP 16673279U JP S5682961 U JPS5682961 U JP S5682961U
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16673279U JPS5682961U (en) | 1979-12-01 | 1979-12-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16673279U JPS5682961U (en) | 1979-12-01 | 1979-12-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5682961U true JPS5682961U (en) | 1981-07-04 |
Family
ID=29677612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16673279U Pending JPS5682961U (en) | 1979-12-01 | 1979-12-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5682961U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6304937B1 (en) | 1990-04-18 | 2001-10-16 | Rambus Inc. | Method of operation of a memory controller |
| US6324120B2 (en) | 1990-04-18 | 2001-11-27 | Rambus Inc. | Memory device having a variable data output length |
| US6684285B2 (en) | 1990-04-18 | 2004-01-27 | Rambus Inc. | Synchronous integrated circuit device |
-
1979
- 1979-12-01 JP JP16673279U patent/JPS5682961U/ja active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6304937B1 (en) | 1990-04-18 | 2001-10-16 | Rambus Inc. | Method of operation of a memory controller |
| US6324120B2 (en) | 1990-04-18 | 2001-11-27 | Rambus Inc. | Memory device having a variable data output length |
| US6452863B2 (en) | 1990-04-18 | 2002-09-17 | Rambus Inc. | Method of operating a memory device having a variable data input length |
| US6546446B2 (en) | 1990-04-18 | 2003-04-08 | Rambus Inc. | Synchronous memory device having automatic precharge |
| US6564281B2 (en) | 1990-04-18 | 2003-05-13 | Rambus Inc. | Synchronous memory device having automatic precharge |
| US6684285B2 (en) | 1990-04-18 | 2004-01-27 | Rambus Inc. | Synchronous integrated circuit device |
| US6697295B2 (en) | 1990-04-18 | 2004-02-24 | Rambus Inc. | Memory device having a programmable register |
| US6715020B2 (en) | 1990-04-18 | 2004-03-30 | Rambus Inc. | Synchronous integrated circuit device |
| US6751696B2 (en) | 1990-04-18 | 2004-06-15 | Rambus Inc. | Memory device having a programmable register |