JPS61107453A - Module address setting circuit - Google Patents

Abstract

PURPOSE:To permit setting of a module address automatically and electrically without providing individual module switch or jumper by setting the module address in a register via a bus. CONSTITUTION:A control circuit 1 outputs the module address, which is to be set in the beginning of a module 21, on an address bus signal conductor 3, and drives an address set control signal conductor 5. A identifying circuit 10 writes the module address which is output on an address bus 3 to an address register 7. Then, the control circuit 1 outputs the module address, which is to be set in the second module, on an address bus signal conductor 3, and drives an address set control signal conductor 5, since the first module is already set, the circuit 10 relays an address set signal directly to the address control signal conductor 6, and sets it to the address register of the second module 22.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an address setting circuit that economically sets module addresses for modules connected in parallel or in cascade via a bus.

(Prior art) Conventionally, in order to identify modules connected in parallel or cascade via a bus, the address information on the address signal line and the self-address of each module were compared to detect a match between the two. . In this type of address identification system, each module is provided with a switch or jumper for address setting, and the address is set using an electronic circuit by manually setting this switch or jumper.

(Problems to be Solved by the Invention) Therefore, the above configuration has the disadvantage that each address must be manually set one by one, as already explained, and the reliability of the switch is reduced. In addition to being a problem, there was also the drawback that addresses could not be changed without human intervention.

An object of the present invention is to provide each module with an address register for storing its own address and an identification circuit for identifying whether or not an address has already been set in this address register. The control signals for setting are connected in a daisy chain manner between each module, and when the address set control signal becomes active, each module will transmit the address set control signal if the address has already been set in the address register. The above drawback can be eliminated by relaying to the next module and setting the address data on the address signal line at that time to the address register without relaying it if it has not been set yet. Instead, it is an object of the present invention to provide an address setting circuit configured to electrically automatically set a module address.

, l (Means for Solving the Problems) The address setting circuit according to the present invention uses a module address setting method in which each of a plurality of modules connected in parallel or cascade to a bus is identified by a module address on an address signal line. It is installed inside the module used in.

In the present invention, the module address setting circuit includes an address register, an address comparator, and an identification circuit.

The address register is for storing its own address.

The address comparator is for comparing its own address and the module address.

The identification circuit connects a control signal to be set in an address register between a plurality of modules in a daisy chain manner, and sequentially identifies module addresses based on its own address and the control signal.

(Example) 1': Next, an example of the present invention will be described with reference to the drawings.
'Explain in detail.

FIG. 1 is a block diagram showing one embodiment of a module address setting circuit according to the present invention. FIG. 2 is a block diagram showing the circuit configuration of the internal address setting portion of each module.

In FIG. 1, 1 is a control circuit, and 21 to 24 are modules, respectively. On the other hand, in FIG. 2, T is an address register, 8 is an address comparator, and 10 is an identification circuit.

In FIG. 1, address bus signal lines 3 and data/control bus signal lines 4 input and output to a control circuit 1 are connected to each module 21 to 24 to form a bus. Address set control signal lines 5.6 connect each module in a daisy chain. When the internal details of each module 21 to 24 are shown in FIG. 2,
The trace bus signal line 3 is connected to the address register 7 and the 'b' side of the address comparator 8. The output of the address register T is connected to the @b' side input terminal of the address comparator 8. When the address setting has been completed, a signal indicating that one of the modules 21 to 24 has been selected is sent from the control circuit 1 to the address bus signal line 3 connected to the control circuit 1 as a module selection signal. It is sent out on line 9. The address set control signal on the signal line 5 is sent out onto the signal line 6 via the identification circuit 10.
This is the address set control signal for the next module.

Further, the 1 identification circuit 10 identifies whether or not an address is set in the address register 7, and controls writing of the address to the address register 7.

The operation of the present invention is such that in the initial state, each module 21 to
All 24 address registers 7 have no addresses set. The control circuit 1 outputs the module address to be set to the first module 21 onto the address bus signal line 3, and also drives the address set control signal line 5. Module 21 at the beginning of 5 signal lines
The address register 7 inside the module is not set at this time. Therefore, the identification circuit 1° does not output the address set control signal on the signal line 6, but writes the module address output on the address bus signal line 3 into the address register T.

Next, the control circuit 1 outputs the module address to be set in the second module onto the address bus signal line 3 and drives the 1-address set control signal line 5. In this case, the first module 2 already has address register 7.
Since the module address is set in , the identification circuit 10 directly relays the address set signal on the address set control signal line 5 to the address control signal line 6. This address set signal is input to the second module 22. Since the module address has not yet been set in the second module 22, the address bus signal line 3
The contents of the second 7 joule 22 address register (
(not shown).

Thereafter, in the same manner, the control circuit 1 sequentially drives the address j' bus signal line 3 and the address set control signal line 5 to sequentially set the module address of each module 21 to 24 starting from the first 7 joules 21. can be set. After configuring all modules,
Address bus signal line 3 and data/control bus signal line 4
By using υ, each module can be selected and controlled.

(Effects of the Invention) As explained above, in the present invention, since the module address is set in the register via the bus, there is no need to provide switches or jumpers for each module, and the module address is automatically set electrically. This makes it possible to set the system manually, which has the effect of reducing operational labor, increasing system reliability, and making the configuration more flexible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a module address setting circuit according to the present invention. FIG. 2 is a block diagram showing the internal details of each module shown in FIG. 1. 1
Para 1...Control circuit 21-24...Module 7...Address register 8...Address comparator 10...Identification circuit 3-6.9...Signal line

Claims (1)

[Claims] An address setting circuit inside a module used in a module address setting method in which multiple modules connected in parallel or cascade via a bus are each identified by a module address on an address signal line, and stores its own address. , an address register for comparing the self address with the module address, and a control signal for setting an address in the address register are connected in a daisy chain manner between the plurality of modules. A module address setting circuit comprising: an identification circuit for sequentially identifying the module address based on the own address and the control signal.