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JPS61107453A - Module address setting circuit - Google Patents

Module address setting circuit

Info

Publication number
JPS61107453A
JPS61107453A JP22854384A JP22854384A JPS61107453A JP S61107453 A JPS61107453 A JP S61107453A JP 22854384 A JP22854384 A JP 22854384A JP 22854384 A JP22854384 A JP 22854384A JP S61107453 A JPS61107453 A JP S61107453A
Authority
JP
JAPAN
Prior art keywords
address
module
set
signal conductor
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22854384A
Inventor
Koichi Sano
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP22854384A priority Critical patent/JPS61107453A/en
Publication of JPS61107453A publication Critical patent/JPS61107453A/en
Application status is Pending legal-status Critical

Links

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/10Plc systems
    • G05B2219/11Plc I-O input output
    • G05B2219/1113Address setting

Abstract

PURPOSE: To permit setting of a module address automatically and electrically without providing individual module switch or jumper by setting the module address in a register via a bus.
CONSTITUTION: A control circuit 1 outputs the module address, which is to be set in the beginning of a module 21, on an address bus signal conductor 3, and drives an address set control signal conductor 5. A identifying circuit 10 writes the module address which is output on an address bus 3 to an address register 7. Then, the control circuit 1 outputs the module address, which is to be set in the second module, on an address bus signal conductor 3, and drives an address set control signal conductor 5, since the first module is already set, the circuit 10 relays an address set signal directly to the address control signal conductor 6, and sets it to the address register of the second module 22.
COPYRIGHT: (C)1986,JPO&Japio
JP22854384A 1984-10-30 1984-10-30 Module address setting circuit Pending JPS61107453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22854384A JPS61107453A (en) 1984-10-30 1984-10-30 Module address setting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22854384A JPS61107453A (en) 1984-10-30 1984-10-30 Module address setting circuit

Publications (1)

Publication Number Publication Date
JPS61107453A true JPS61107453A (en) 1986-05-26

Family

ID=16878034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22854384A Pending JPS61107453A (en) 1984-10-30 1984-10-30 Module address setting circuit

Country Status (1)

Country Link
JP (1) JPS61107453A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6266285B1 (en) 1990-04-18 2001-07-24 Rambus Inc. Method of operating a memory device having write latency
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6591353B1 (en) 1995-10-19 2003-07-08 Rambus Inc. Protocol for communication with dynamic memory
JP2006133996A (en) * 2004-11-04 2006-05-25 Canon Inc System and method for serial communication
US9647857B2 (en) 1997-06-20 2017-05-09 Massachusetts Institute Of Technology Digital transmitter

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6266285B1 (en) 1990-04-18 2001-07-24 Rambus Inc. Method of operating a memory device having write latency
US6314051B1 (en) 1990-04-18 2001-11-06 Rambus Inc. Memory device having write latency
US6378020B2 (en) 1990-04-18 2002-04-23 Rambus Inc. System having double data transfer rate and intergrated circuit therefor
US6415339B1 (en) 1990-04-18 2002-07-02 Rambus Inc. Memory device having a plurality of programmable internal registers and a delay time register
US6470405B2 (en) 1995-10-19 2002-10-22 Rambus Inc. Protocol for communication with dynamic memory
US6591353B1 (en) 1995-10-19 2003-07-08 Rambus Inc. Protocol for communication with dynamic memory
US6810449B1 (en) 1995-10-19 2004-10-26 Rambus, Inc. Protocol for communication with dynamic memory
US6931467B2 (en) 1995-10-19 2005-08-16 Rambus Inc. Memory integrated circuit device which samples data upon detection of a strobe signal
US9647857B2 (en) 1997-06-20 2017-05-09 Massachusetts Institute Of Technology Digital transmitter
JP2006133996A (en) * 2004-11-04 2006-05-25 Canon Inc System and method for serial communication

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