SU1451712A1 - Adaptive data processing device - Google Patents

Abstract

The invention relates to computing and can be used in measuring and computing complexes and automated control systems based on multiprocessor computing systems. The aim of the invention is to increase the system capacity in the processing of interdependent applications by reducing the time of just processors in a sequential system operation mode. This goal is achieved by introducing N bidirectional switches into the system, where N is determined by the number of processors in the system, and an AND element, a demultiplexer, and a buffer memory block are introduced into each processor. 18 il. (L

Description

4 O1

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The invention relates to computing technology and can be used in measuring and computing complexes and automated control systems based on multiprocessor computing systems.

The purpose of the invention is to increase the system capacity in the processing of interdependent orders by reducing the time of just processors in a sequential system operation mode.

FIG. 1 is a block diagram of the system; in fig. 2 - block diagram of operations; in fig. 3 - command system; in fig. A - diagram of the switching unit; in fig. 5 is a block diagram of bidirectional switches; in fig. 6 shows diagrams of a buffer memory block and a logic block; in fig. 7 is a diagram of an arithmetic logic unit; in fig. 8 - time diagram; .on FIG. 9 - system of microinstructions; in fig. 10 is a block exchange diagram; in fig. 11 - his time chart; in fig. 12 - system of microinstructions; in fig. 13 shows the switching elements included in the arithmetic logic unit and the exchange unit; in fig. 14 is a circuit of a switching element; in fig. 15 is a block diagram of a memory unit; in fig. 16 is a block connection diagram of a highway; in fig. 17, 18 - block diagrams of the algorithms of the processors in the system. The adaptive data processing system contains a block 1 of the memory of the processor, processors 2, each of which contains a switching unit 3, a unit 4 for performing operations, an OR 5 element, an AND 6 element, a demultiplexer 7, a block. 8 buffer memory, signal transmission line 9 divided into sections through blocks of 10 bidirectional switches and containing address bus 11, data bus 12, delivery highway 13, reception highway 14, request highway 15, busy highway 16, capture request 17 and line 18 response output; mode setting highway 19, resolution output 20, request input 21, first request communication 22, second request communication 23, write communication 24, first launch connection 25, second start communication 26, call communication 27, connection 28 polling, signal link 29 Empty, signal link 30 Filled.

The operation unit 4 comprises a memory unit 31, a command counter 32, a decoder 33, a first control connection 3, a second control connection 35, a third control connection 36, a fourth control connection 37, a control connection 38, the OR element 39 arithmetic logic unit 40, exchange unit 41, trunk connection unit 42, command bus 43, communication 44, 45 execution, address communication 46, informational communication 47 issuance, reception communication 48, capture communication 49 50 capture resolution.

Switching unit 3 contains elements AND 51-55, element OR 56.

 Block 10 bidirectional switches contains bi-directional switches 57-63.

Logic block 7 contains two elements 64 and 65, and block 8 of buffer memory contains a write address counter 66, a write address decoder 67, a fill counter 68, a read address counter 69, a read address decoder 70, input register 71, memory block 72 output register 73.

The arithmetic logic unit 40 comprises a reception-transmission unit 74, a register 75, a general-purpose register unit 76, an adder 77, a shifter 78, a state register 79, a switching element 80, a micro-command decoder 81, a register 82. micro-instructions, a sync pulse generator 83 .

The exchange unit 41 comprises a reception unit 84, a reception-transmission unit 85, 86, switching elements 87, 88, register 89, switch 90, micro-command decoder 91, clock generator 92, AND 93 element, micro-register 94, OR element 95.

The switching element 80 contains elements AND 96, 97, the element OR 98; switching element 87 - elements AND 99, 100, element OR 101; switching element 88 - elements And 102, 103, key elements 104, 105, element OR 106.

Memory unit 31 contains address registers 107, 108, memory node 109. The line connection unit 42 contains elements And 110-113, trigger 114, key elements 115, 116.

The system operates in one of two processing modes: parallel or sequential. The mode of processing depends on the value of the signal on the mode setting highway 19. Depending on the specified mode, the system proceeds as follows.

Parallel processing mode for wok.

Initial state: all processors 2 are free, block 8 of the buffer memory is empty, the signal value on the mode setting highway 19 is equal to 1.

In this case, each processor 2 issues a request signal, which is generated by block 4 of performing operations every time after the completion of the sample processing algorithm. From the polling code of the operation block 4, this signal passes through communication 28 to the first input of the element 64 of the demultiplexer 7, then to its output (since the signal is empty to communication 29 is 1) and is received via the second communication 23 of the request on the second input element OR 5. The first input element OR 5 in the parallel processing mode receives a signal from the switching unit 3, which is formed from the request of subsequent processors. The signal on the first communication 22 of the request (output of the AND 6 element) in this mode is always equal to O, since the first inverse input of the AND 6 element is given the value of the signal 1.

Combined through the elements OR 5, all requests are sent to the input 21 of the request of the memory 1 block of the request. According to the request signal, block 1, if it has a request, from the address and information outputs to the signal transmission highway 9, the channel number code and the sample code, respectively, which are installed on address bus 11 and data bus 12. Output 20 of the resolution of the storage unit 1 gives an enable signal.

All bidirectional switches 57-63 blocks of 10 bidirectional switches closed under the action of a single signal on the line 19. Therefore, the individual sections of the line form a single system highway 9 signal transmission.

In parallel mode, the resolution signal passes sequentially through the switching units 3 of processor 2 and switches the last processor into operation. Turn on the processor

ten

15

20

thirty

is a signal on the first launch connection 25 to the first trigger input of the operation execution unit 4. At the same time, in block 4, the codes for the channel number and the sample from buses 11 and 12, respectively, are read. At the same time, the interrogation signal coming over communication 28 from block 4 (the request of this processor is canceled) is blocked, which serves as a resolution to enable the previous processor to work. Signals on links 26 and 24 are always equal to O, therefore the state of block 8 of the buffer memory does not change and this block is not used in parallel processing mode. Thus, the topological priority of the processors is created as they are removed from the storage unit 1 of the memory.

The number of the channel read in block 4 of the operations is determined by the application processing program. Since the duration of treatment in general is random, 25 then. the sequence of switching on the processors 2 into operation as they are released is arbitrary. This ensures the continuity of work of all processors and the absence of downtime in their work.

The algorithm for operating the system in the parallel processing mode of the application is shown in FIG. 17

Sequential processing mode

Initial state: all processors 2 are free, block 8 of buffer memory is empty (the signal value at output 29 is 1, and at output 30 is O), the signal value at line 19 of the mode setting is O.

, In this mode, bidirectional switches 57-63 blocks of 10 bidirectional switches are open. Therefore, the signal transmission line 9 is divided into electrically unconnected sections. At the same time, independent transmission-reception communications are organized in the system between pairs of neighboring processors via buses 12 of the trunk sections data.

At the initial time, in each processor 2, two request signals are simultaneously generated 5. First, the free operation unit 4 outputs a signal from the polling output, coming over communication 28 via demultiplexer 7 to the second input of the element.

35

0

five

0

or 5 by communication 23 as a signal of the first request. Secondly, the signal of the second request is formed at the output of the AND 6 element (since the value of the signal Filled at link 1, 30 equals O), arriving via communication 22 at the third input of the element OR 5 and at the information input of the switching unit 3. The signal of the second request, when operating in sequential mode, is continuously supplied through the OR 5 element to the request input of the switching unit 3 of the previous processor 2 until the buffer storage unit 8 is filled.

When a request signal is received on request 21, the storage unit 1 outputs from output 20 a resolution signal to the first processor and passes the application code to the data bus 12 of the first trunk section. In this mode, all applications from block 1 are successively received only by the first processor 2, since the zero value of the signal on the mode setting highway 19 prevents the permission signal from passing through them. In this case, the processing algorithm is uniquely determined by the order number therefore the address bus does not operate.

The appearance of the permission signal at the resolution input of the switching unit 3 of the first processor 2 initiates the output from the recording output of unit 3 via communication 24 of a recording signal, which writes the sample code from the bus 12 of the first trunk section to the buffer storage unit 8. Since block 8 is no longer empty, the request signal, coming from the polling output of block 4 via link 28 to logic block 7, generates a signal to link 26 that triggers block 4 and also sends to it from block 8 a sample that 4 begins to process the appropriate partial processing algorithm. In this case, the signal from the polling output of block 4 is removed.

While block 4 executes the first part of the application processing algorithm, the signal of the first processor request is saved, therefore block 1 of the application memory continues to issue applications that are written to the node 8 of the buffer memory of this processor 2 wok ends

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17126

at full filling of the buffer 8 of the buffer memory.

The unit 4 of performing the operations of the first processor 2, having executed the first part of the application processing algorithm, outputs the callback signal in the switching unit 3 from the output of the communication via communication 27. If, at the same time, at the input of the request of block 3 10 there is a request signal from the second processor 2, then the block 3 outputs from the resolution output a signal arriving at the resolution input of the block 3 of the second processor 2,

15 In the second processor 2, the switching unit 3 transfers the result of partial processing of the request (made by the first processor) to the block 8 of the buffer memory of this processor via bus 24 via the data bus 12 of the second trunk section, where it came from first processor. The signal from the polling output of the operation execution unit 4 received via communication 28, the demultiplexer 7 generates a control signal via communication 26, which is fed to the second trigger input of the operation execution unit 4, and also transmits data from the control unit 30 8 to block 4 for further processing, t, e. to perform the second part of the algorithm. Similarly, the remaining processors are activated 2.

Since in this mode, the formation of the request signal and. receiving information in block 8 of the buffer memory of processors 2 is not associated with the end of the execution of a part of the algorithm, then su. 40, processor idle 2 is significantly reduced due to the uneven lengths of the parts of the algorithms. By properly selecting the memory capacity of block 8, it is possible to eliminate almost completely the downtime in the system. Moreover, the reception of information to the block 8 of processors 2 and the output of information from the processors in this mode are performed independently due to the separation of the signal transmission line 9 into unrelated sections, which further reduces the downtime of the processors in the system,

The algorithm of operation of the system processors 2 55 in the sequential processing mode of the application is shown in FIG. 18.

The logic of forming the signals that control the operation of the processors 2 in the system in the desired mode is implemented

45

50

7

in block 3 switching, the element And 6, the demultiplexer 7.

Claims (1)

Invention Formula An adaptive data processing system containing a storage unit and N processors, each of which contains an operation execution unit, a switching unit and an OR element, and the request input of the storage unit is connected to the output of the OR element of the first processor, the resolution input of the memory unit The gateway is connected to the enable input of the switching unit of the first processor, the first input of the OR element of each processor is connected to the output of the switching unit request of the same processor, the output of the switching unit i-ro (i 1, 1Т) of the processor is connected to input By enabling the switching unit (1 + 1) processor, the first trigger input of the operation unit of each processor is connected to the trigger input of the switching unit of the same processor, the output of the operation unit is connected in each processor to the input of the switching unit, the request input of the switching unit The i-ro of the processor is connected to the output of the OR element (itl) -ro of the processor, the inputs for setting the mode of the switching unit of each processor are interconnected and are the same input of the system, characterized in that Increasing the system capacity when processing interdependent applications by reducing the time of just processors in the sequential mode of the system, N bidirectional switches are entered into it, the system mode setting input is connected to the mode setting input of each of the bidirectional switches, The wok is connected to the output address of the bidirectional switch, the input / output data of the memory block for the wok is connected to the input-output data of the first bidirectional switch and the first o712; 8 processor, request output of the first bidirectional switch is connected to the input Response of the first bidirectional switch, inputs-inputs of the output data, reception, request address, i-ro bidirectional switch are connected to the corresponding inputs-outputs of the 1st processor and (itl) - ro bidirectional switch, output Request to capture the i-ro bidirectional switch connected to the input Request to capture the i-ro processor, output Answer the i-rn processor connected to the input of the OTsei (1 + 1) -th bidirectional switch, and in each quarrels entered the And element, demultiplexer, buffer memory block, the demultiplexer information input is connected to the polling output of the operation block, and the demultiplexer control input is connected to the Start output of the buffer memory block, the first output of the demultiplexer is connected to the second trigger input of the operation block and to The readout input of the buffer memory block, the second output of the demultiplexer is connected to the second input of the OR element, the first input of the 11T element AND is connected to the fill output of the buffer memory block, the second input is The AND input is connected to the system mode setting input, and its output is connected to the third input of the OR element and to the first input of the switching unit request, the output of the recording attribute of which is connected to the input of the recording attribute of the buffer memory block whose information output is connected to the information input of the operation execution unitJ the input / output data of the buffer storage block is the input / output of the processor data, the input / output of the address, data, output, receive, request and busyness of the operation block are the corresponding input / output E processor, input and output capture request response block performing the corresponding operations are the input and output processor. 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